Searched refs:getSubClassWithSubReg (Results 1 - 19 of 19) sorted by relevance
| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 66 getSubClassWithSubReg(const TargetRegisterClass *RC,
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| H A D | X86RegisterInfo.cpp | 83 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, function in class:X86RegisterInfo
91 return X86GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
100 A = X86GenRegisterInfo::getSubClassWithSubReg(A, X86::sub_8bit_hi);
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| H A D | X86InstructionSelector.cpp | 757 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
1174 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubIdx);
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 65 getSubClassWithSubReg(const TargetRegisterClass *RC,
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| H A D | AArch64RegisterInfo.cpp | 173 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
182 return AArch64GenRegisterInfo::getSubClassWithSubReg(RC, Idx);
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 451 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
464 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT, isDivergent), SubIdx);
571 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx);
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| H A D | FastISel.cpp | 2106 MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx));
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| /netbsd-current/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 611 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 532 if (getSubClassWithSubReg(RC, Idx) != RC)
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| H A D | PeepholeOptimizer.cpp | 478 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx);
488 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr;
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| H A D | MachineInstr.cpp | 960 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
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| H A D | MachineVerifier.cpp | 1992 TRI->getSubClassWithSubReg(RC, SubIdx);
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| /netbsd-current/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 381 // getSubClassWithSubReg - Returns the largest sub-class where all
384 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { function in class:llvm::CodeGenRegisterClass
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| H A D | CodeGenRegisters.cpp | 1007 CodeGenRegisterClass *BiggestSuperRegRC = getSubClassWithSubReg(SubIdx);
1547 if (RegClass.getSubClassWithSubReg(&SubRegIndex) == nullptr)
2171 // Synthesize missing sub-classes for getSubClassWithSubReg().
2237 if (RC->getSubClassWithSubReg(&SubIdx) != RC)
2308 // Synthesize answers for getSubClassWithSubReg().
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| H A D | CodeGenTarget.cpp | 353 CodeGenRegisterClass *SubClassWithSubReg = RC.getSubClassWithSubReg(SubIdx);
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| H A D | RegisterInfoEmitter.cpp | 1163 << " const TargetRegisterClass *getSubClassWithSubReg"
1498 // Emit getSubClassWithSubReg.
1501 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
1515 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
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| /netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 489 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubReg);
573 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);
739 Src0RC = TRI.getSubClassWithSubReg(Src0RC, SubReg);
1936 = TRI.getSubClassWithSubReg(SrcRC, SubRegIdx);
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| H A D | AMDGPUISelDAGToDAG.cpp | 590 return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
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| H A D | SIInstrInfo.cpp | 5091 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg(
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