Searched refs:VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT (Results 1 - 11 of 11) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gmc/
H A Dgmc_7_0_sh_mask.h5282 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
H A Dgmc_8_2_sh_mask.h6404 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
H A Dgmc_7_1_sh_mask.h5924 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
H A Dgmc_6_0_sh_mask.h11847 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x0000000a macro
H A Dgmc_8_1_sh_mask.h6526 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_0_sh_mask.h7748 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
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H A Dmmhub_9_1_sh_mask.h7411 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
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H A Dmmhub_9_3_0_sh_mask.h7838 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
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/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h6676 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
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H A Dgc_9_1_sh_mask.h6490 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
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H A Dgc_9_2_1_sh_mask.h6313 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa macro
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