1/* $NetBSD: mmhub_9_1_sh_mask.h,v 1.2 2021/12/18 23:45:16 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef _mmhub_9_1_SH_MASK_HEADER 24#define _mmhub_9_1_SH_MASK_HEADER 25 26 27// addressBlock: mmhub_dagbdec 28//DAGB0_RDCLI0 29#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 30#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 32#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 33#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 35#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 36#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 37#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 39#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 40#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 41#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 42#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 43#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 44#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 45#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 46#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 47#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 48#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 49//DAGB0_RDCLI1 50#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 51#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 52#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 53#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 54#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 55#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 56#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 57#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 58#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 59#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 60#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 61#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 62#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 63#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 64#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 65#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 66#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 67#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 68#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 69#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 70//DAGB0_RDCLI2 71#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 72#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 73#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 74#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 75#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 76#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 77#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 78#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 79#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 80#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 81#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 82#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 83#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 84#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 85#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 86#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 87#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 88#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 89#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 90#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 91//DAGB0_RDCLI3 92#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 93#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 94#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 95#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 96#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 97#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 98#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 99#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 100#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 101#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 102#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 103#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 104#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 105#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 106#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 107#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 108#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 109#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 110#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 111#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 112//DAGB0_RDCLI4 113#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 114#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 115#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 116#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 117#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 118#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 119#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 120#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 121#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 123#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 124#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 125#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 126#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 127#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 128#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 129#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 130#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 131#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 132#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 133//DAGB0_RDCLI5 134#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 135#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 136#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 137#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 138#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 139#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 140#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 141#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 142#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 143#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 144#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 145#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 146#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 147#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 148#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 149#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 150#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 151#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 152#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 153#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 154//DAGB0_RDCLI6 155#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 156#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 157#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 158#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 159#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 160#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 161#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 162#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 163#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 164#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 165#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 166#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 167#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 168#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 169#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 170#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 171#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 172#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 173#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 174#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 175//DAGB0_RDCLI7 176#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 177#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 178#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 179#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 180#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 181#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 182#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 183#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 184#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 185#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 186#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 187#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 188#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 189#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 190#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 191#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 192#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 193#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 194#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 195#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 196//DAGB0_RDCLI8 197#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 198#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 199#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 200#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 201#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 202#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 203#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 204#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 205#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 206#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 207#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 208#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 209#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 210#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 211#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 212#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 213#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 214#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 215#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 216#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 217//DAGB0_RDCLI9 218#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 219#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 220#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 221#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 222#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 223#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 224#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 225#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 226#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 227#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 228#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 229#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 230#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 231#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 232#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 233#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 234#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 235#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 236#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 237#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 238//DAGB0_RDCLI10 239#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 240#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 241#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 242#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 243#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 244#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 245#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 246#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 247#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 248#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 249#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 250#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 251#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 252#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 253#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 254#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 255#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 256#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 257#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 258#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 259//DAGB0_RDCLI11 260#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 261#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 262#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 263#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 264#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 265#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 266#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 267#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 268#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 269#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 270#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 271#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 272#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 273#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 274#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 275#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 276#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 277#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 278#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 279#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 280//DAGB0_RDCLI12 281#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 282#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 283#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 284#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 285#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 286#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 287#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 288#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 289#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 290#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 291#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 292#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 293#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 294#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 295#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 296#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 297#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 298#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 299#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 300#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 301//DAGB0_RDCLI13 302#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 303#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 304#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 305#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 306#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 307#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 308#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 309#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 310#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 311#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 312#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 313#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 314#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 315#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 316#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 317#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 318#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 319#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 320#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 321#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 322//DAGB0_RDCLI14 323#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 324#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 325#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 326#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 327#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 328#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 329#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 330#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 331#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 332#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 333#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 334#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 335#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 336#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 337#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 338#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 339#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 340#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 341#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 342#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 343//DAGB0_RDCLI15 344#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 345#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 346#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 347#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 348#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 349#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 350#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 351#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 352#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 353#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 354#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 355#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 356#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 357#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 358#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 359#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 360#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 361#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 362#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 363#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 364//DAGB0_RDCLI16 365#define DAGB0_RDCLI16__VIRT_CHAN__SHIFT 0x0 366#define DAGB0_RDCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 367#define DAGB0_RDCLI16__URG_HIGH__SHIFT 0x4 368#define DAGB0_RDCLI16__URG_LOW__SHIFT 0x8 369#define DAGB0_RDCLI16__MAX_BW_ENABLE__SHIFT 0xc 370#define DAGB0_RDCLI16__MAX_BW__SHIFT 0xd 371#define DAGB0_RDCLI16__MIN_BW_ENABLE__SHIFT 0x15 372#define DAGB0_RDCLI16__MIN_BW__SHIFT 0x16 373#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 374#define DAGB0_RDCLI16__MAX_OSD__SHIFT 0x1a 375#define DAGB0_RDCLI16__VIRT_CHAN_MASK 0x00000007L 376#define DAGB0_RDCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 377#define DAGB0_RDCLI16__URG_HIGH_MASK 0x000000F0L 378#define DAGB0_RDCLI16__URG_LOW_MASK 0x00000F00L 379#define DAGB0_RDCLI16__MAX_BW_ENABLE_MASK 0x00001000L 380#define DAGB0_RDCLI16__MAX_BW_MASK 0x001FE000L 381#define DAGB0_RDCLI16__MIN_BW_ENABLE_MASK 0x00200000L 382#define DAGB0_RDCLI16__MIN_BW_MASK 0x01C00000L 383#define DAGB0_RDCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 384#define DAGB0_RDCLI16__MAX_OSD_MASK 0xFC000000L 385//DAGB0_RDCLI17 386#define DAGB0_RDCLI17__VIRT_CHAN__SHIFT 0x0 387#define DAGB0_RDCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 388#define DAGB0_RDCLI17__URG_HIGH__SHIFT 0x4 389#define DAGB0_RDCLI17__URG_LOW__SHIFT 0x8 390#define DAGB0_RDCLI17__MAX_BW_ENABLE__SHIFT 0xc 391#define DAGB0_RDCLI17__MAX_BW__SHIFT 0xd 392#define DAGB0_RDCLI17__MIN_BW_ENABLE__SHIFT 0x15 393#define DAGB0_RDCLI17__MIN_BW__SHIFT 0x16 394#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 395#define DAGB0_RDCLI17__MAX_OSD__SHIFT 0x1a 396#define DAGB0_RDCLI17__VIRT_CHAN_MASK 0x00000007L 397#define DAGB0_RDCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 398#define DAGB0_RDCLI17__URG_HIGH_MASK 0x000000F0L 399#define DAGB0_RDCLI17__URG_LOW_MASK 0x00000F00L 400#define DAGB0_RDCLI17__MAX_BW_ENABLE_MASK 0x00001000L 401#define DAGB0_RDCLI17__MAX_BW_MASK 0x001FE000L 402#define DAGB0_RDCLI17__MIN_BW_ENABLE_MASK 0x00200000L 403#define DAGB0_RDCLI17__MIN_BW_MASK 0x01C00000L 404#define DAGB0_RDCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 405#define DAGB0_RDCLI17__MAX_OSD_MASK 0xFC000000L 406//DAGB0_RDCLI18 407#define DAGB0_RDCLI18__VIRT_CHAN__SHIFT 0x0 408#define DAGB0_RDCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 409#define DAGB0_RDCLI18__URG_HIGH__SHIFT 0x4 410#define DAGB0_RDCLI18__URG_LOW__SHIFT 0x8 411#define DAGB0_RDCLI18__MAX_BW_ENABLE__SHIFT 0xc 412#define DAGB0_RDCLI18__MAX_BW__SHIFT 0xd 413#define DAGB0_RDCLI18__MIN_BW_ENABLE__SHIFT 0x15 414#define DAGB0_RDCLI18__MIN_BW__SHIFT 0x16 415#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 416#define DAGB0_RDCLI18__MAX_OSD__SHIFT 0x1a 417#define DAGB0_RDCLI18__VIRT_CHAN_MASK 0x00000007L 418#define DAGB0_RDCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 419#define DAGB0_RDCLI18__URG_HIGH_MASK 0x000000F0L 420#define DAGB0_RDCLI18__URG_LOW_MASK 0x00000F00L 421#define DAGB0_RDCLI18__MAX_BW_ENABLE_MASK 0x00001000L 422#define DAGB0_RDCLI18__MAX_BW_MASK 0x001FE000L 423#define DAGB0_RDCLI18__MIN_BW_ENABLE_MASK 0x00200000L 424#define DAGB0_RDCLI18__MIN_BW_MASK 0x01C00000L 425#define DAGB0_RDCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 426#define DAGB0_RDCLI18__MAX_OSD_MASK 0xFC000000L 427//DAGB0_RDCLI19 428#define DAGB0_RDCLI19__VIRT_CHAN__SHIFT 0x0 429#define DAGB0_RDCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 430#define DAGB0_RDCLI19__URG_HIGH__SHIFT 0x4 431#define DAGB0_RDCLI19__URG_LOW__SHIFT 0x8 432#define DAGB0_RDCLI19__MAX_BW_ENABLE__SHIFT 0xc 433#define DAGB0_RDCLI19__MAX_BW__SHIFT 0xd 434#define DAGB0_RDCLI19__MIN_BW_ENABLE__SHIFT 0x15 435#define DAGB0_RDCLI19__MIN_BW__SHIFT 0x16 436#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 437#define DAGB0_RDCLI19__MAX_OSD__SHIFT 0x1a 438#define DAGB0_RDCLI19__VIRT_CHAN_MASK 0x00000007L 439#define DAGB0_RDCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 440#define DAGB0_RDCLI19__URG_HIGH_MASK 0x000000F0L 441#define DAGB0_RDCLI19__URG_LOW_MASK 0x00000F00L 442#define DAGB0_RDCLI19__MAX_BW_ENABLE_MASK 0x00001000L 443#define DAGB0_RDCLI19__MAX_BW_MASK 0x001FE000L 444#define DAGB0_RDCLI19__MIN_BW_ENABLE_MASK 0x00200000L 445#define DAGB0_RDCLI19__MIN_BW_MASK 0x01C00000L 446#define DAGB0_RDCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 447#define DAGB0_RDCLI19__MAX_OSD_MASK 0xFC000000L 448//DAGB0_RDCLI20 449#define DAGB0_RDCLI20__VIRT_CHAN__SHIFT 0x0 450#define DAGB0_RDCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 451#define DAGB0_RDCLI20__URG_HIGH__SHIFT 0x4 452#define DAGB0_RDCLI20__URG_LOW__SHIFT 0x8 453#define DAGB0_RDCLI20__MAX_BW_ENABLE__SHIFT 0xc 454#define DAGB0_RDCLI20__MAX_BW__SHIFT 0xd 455#define DAGB0_RDCLI20__MIN_BW_ENABLE__SHIFT 0x15 456#define DAGB0_RDCLI20__MIN_BW__SHIFT 0x16 457#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 458#define DAGB0_RDCLI20__MAX_OSD__SHIFT 0x1a 459#define DAGB0_RDCLI20__VIRT_CHAN_MASK 0x00000007L 460#define DAGB0_RDCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 461#define DAGB0_RDCLI20__URG_HIGH_MASK 0x000000F0L 462#define DAGB0_RDCLI20__URG_LOW_MASK 0x00000F00L 463#define DAGB0_RDCLI20__MAX_BW_ENABLE_MASK 0x00001000L 464#define DAGB0_RDCLI20__MAX_BW_MASK 0x001FE000L 465#define DAGB0_RDCLI20__MIN_BW_ENABLE_MASK 0x00200000L 466#define DAGB0_RDCLI20__MIN_BW_MASK 0x01C00000L 467#define DAGB0_RDCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 468#define DAGB0_RDCLI20__MAX_OSD_MASK 0xFC000000L 469//DAGB0_RDCLI21 470#define DAGB0_RDCLI21__VIRT_CHAN__SHIFT 0x0 471#define DAGB0_RDCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 472#define DAGB0_RDCLI21__URG_HIGH__SHIFT 0x4 473#define DAGB0_RDCLI21__URG_LOW__SHIFT 0x8 474#define DAGB0_RDCLI21__MAX_BW_ENABLE__SHIFT 0xc 475#define DAGB0_RDCLI21__MAX_BW__SHIFT 0xd 476#define DAGB0_RDCLI21__MIN_BW_ENABLE__SHIFT 0x15 477#define DAGB0_RDCLI21__MIN_BW__SHIFT 0x16 478#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 479#define DAGB0_RDCLI21__MAX_OSD__SHIFT 0x1a 480#define DAGB0_RDCLI21__VIRT_CHAN_MASK 0x00000007L 481#define DAGB0_RDCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 482#define DAGB0_RDCLI21__URG_HIGH_MASK 0x000000F0L 483#define DAGB0_RDCLI21__URG_LOW_MASK 0x00000F00L 484#define DAGB0_RDCLI21__MAX_BW_ENABLE_MASK 0x00001000L 485#define DAGB0_RDCLI21__MAX_BW_MASK 0x001FE000L 486#define DAGB0_RDCLI21__MIN_BW_ENABLE_MASK 0x00200000L 487#define DAGB0_RDCLI21__MIN_BW_MASK 0x01C00000L 488#define DAGB0_RDCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 489#define DAGB0_RDCLI21__MAX_OSD_MASK 0xFC000000L 490//DAGB0_RDCLI22 491#define DAGB0_RDCLI22__VIRT_CHAN__SHIFT 0x0 492#define DAGB0_RDCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 493#define DAGB0_RDCLI22__URG_HIGH__SHIFT 0x4 494#define DAGB0_RDCLI22__URG_LOW__SHIFT 0x8 495#define DAGB0_RDCLI22__MAX_BW_ENABLE__SHIFT 0xc 496#define DAGB0_RDCLI22__MAX_BW__SHIFT 0xd 497#define DAGB0_RDCLI22__MIN_BW_ENABLE__SHIFT 0x15 498#define DAGB0_RDCLI22__MIN_BW__SHIFT 0x16 499#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 500#define DAGB0_RDCLI22__MAX_OSD__SHIFT 0x1a 501#define DAGB0_RDCLI22__VIRT_CHAN_MASK 0x00000007L 502#define DAGB0_RDCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 503#define DAGB0_RDCLI22__URG_HIGH_MASK 0x000000F0L 504#define DAGB0_RDCLI22__URG_LOW_MASK 0x00000F00L 505#define DAGB0_RDCLI22__MAX_BW_ENABLE_MASK 0x00001000L 506#define DAGB0_RDCLI22__MAX_BW_MASK 0x001FE000L 507#define DAGB0_RDCLI22__MIN_BW_ENABLE_MASK 0x00200000L 508#define DAGB0_RDCLI22__MIN_BW_MASK 0x01C00000L 509#define DAGB0_RDCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 510#define DAGB0_RDCLI22__MAX_OSD_MASK 0xFC000000L 511//DAGB0_RDCLI23 512#define DAGB0_RDCLI23__VIRT_CHAN__SHIFT 0x0 513#define DAGB0_RDCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 514#define DAGB0_RDCLI23__URG_HIGH__SHIFT 0x4 515#define DAGB0_RDCLI23__URG_LOW__SHIFT 0x8 516#define DAGB0_RDCLI23__MAX_BW_ENABLE__SHIFT 0xc 517#define DAGB0_RDCLI23__MAX_BW__SHIFT 0xd 518#define DAGB0_RDCLI23__MIN_BW_ENABLE__SHIFT 0x15 519#define DAGB0_RDCLI23__MIN_BW__SHIFT 0x16 520#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 521#define DAGB0_RDCLI23__MAX_OSD__SHIFT 0x1a 522#define DAGB0_RDCLI23__VIRT_CHAN_MASK 0x00000007L 523#define DAGB0_RDCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 524#define DAGB0_RDCLI23__URG_HIGH_MASK 0x000000F0L 525#define DAGB0_RDCLI23__URG_LOW_MASK 0x00000F00L 526#define DAGB0_RDCLI23__MAX_BW_ENABLE_MASK 0x00001000L 527#define DAGB0_RDCLI23__MAX_BW_MASK 0x001FE000L 528#define DAGB0_RDCLI23__MIN_BW_ENABLE_MASK 0x00200000L 529#define DAGB0_RDCLI23__MIN_BW_MASK 0x01C00000L 530#define DAGB0_RDCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 531#define DAGB0_RDCLI23__MAX_OSD_MASK 0xFC000000L 532//DAGB0_RDCLI24 533#define DAGB0_RDCLI24__VIRT_CHAN__SHIFT 0x0 534#define DAGB0_RDCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 535#define DAGB0_RDCLI24__URG_HIGH__SHIFT 0x4 536#define DAGB0_RDCLI24__URG_LOW__SHIFT 0x8 537#define DAGB0_RDCLI24__MAX_BW_ENABLE__SHIFT 0xc 538#define DAGB0_RDCLI24__MAX_BW__SHIFT 0xd 539#define DAGB0_RDCLI24__MIN_BW_ENABLE__SHIFT 0x15 540#define DAGB0_RDCLI24__MIN_BW__SHIFT 0x16 541#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 542#define DAGB0_RDCLI24__MAX_OSD__SHIFT 0x1a 543#define DAGB0_RDCLI24__VIRT_CHAN_MASK 0x00000007L 544#define DAGB0_RDCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 545#define DAGB0_RDCLI24__URG_HIGH_MASK 0x000000F0L 546#define DAGB0_RDCLI24__URG_LOW_MASK 0x00000F00L 547#define DAGB0_RDCLI24__MAX_BW_ENABLE_MASK 0x00001000L 548#define DAGB0_RDCLI24__MAX_BW_MASK 0x001FE000L 549#define DAGB0_RDCLI24__MIN_BW_ENABLE_MASK 0x00200000L 550#define DAGB0_RDCLI24__MIN_BW_MASK 0x01C00000L 551#define DAGB0_RDCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 552#define DAGB0_RDCLI24__MAX_OSD_MASK 0xFC000000L 553//DAGB0_RDCLI25 554#define DAGB0_RDCLI25__VIRT_CHAN__SHIFT 0x0 555#define DAGB0_RDCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 556#define DAGB0_RDCLI25__URG_HIGH__SHIFT 0x4 557#define DAGB0_RDCLI25__URG_LOW__SHIFT 0x8 558#define DAGB0_RDCLI25__MAX_BW_ENABLE__SHIFT 0xc 559#define DAGB0_RDCLI25__MAX_BW__SHIFT 0xd 560#define DAGB0_RDCLI25__MIN_BW_ENABLE__SHIFT 0x15 561#define DAGB0_RDCLI25__MIN_BW__SHIFT 0x16 562#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 563#define DAGB0_RDCLI25__MAX_OSD__SHIFT 0x1a 564#define DAGB0_RDCLI25__VIRT_CHAN_MASK 0x00000007L 565#define DAGB0_RDCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 566#define DAGB0_RDCLI25__URG_HIGH_MASK 0x000000F0L 567#define DAGB0_RDCLI25__URG_LOW_MASK 0x00000F00L 568#define DAGB0_RDCLI25__MAX_BW_ENABLE_MASK 0x00001000L 569#define DAGB0_RDCLI25__MAX_BW_MASK 0x001FE000L 570#define DAGB0_RDCLI25__MIN_BW_ENABLE_MASK 0x00200000L 571#define DAGB0_RDCLI25__MIN_BW_MASK 0x01C00000L 572#define DAGB0_RDCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 573#define DAGB0_RDCLI25__MAX_OSD_MASK 0xFC000000L 574//DAGB0_RDCLI26 575#define DAGB0_RDCLI26__VIRT_CHAN__SHIFT 0x0 576#define DAGB0_RDCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 577#define DAGB0_RDCLI26__URG_HIGH__SHIFT 0x4 578#define DAGB0_RDCLI26__URG_LOW__SHIFT 0x8 579#define DAGB0_RDCLI26__MAX_BW_ENABLE__SHIFT 0xc 580#define DAGB0_RDCLI26__MAX_BW__SHIFT 0xd 581#define DAGB0_RDCLI26__MIN_BW_ENABLE__SHIFT 0x15 582#define DAGB0_RDCLI26__MIN_BW__SHIFT 0x16 583#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 584#define DAGB0_RDCLI26__MAX_OSD__SHIFT 0x1a 585#define DAGB0_RDCLI26__VIRT_CHAN_MASK 0x00000007L 586#define DAGB0_RDCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 587#define DAGB0_RDCLI26__URG_HIGH_MASK 0x000000F0L 588#define DAGB0_RDCLI26__URG_LOW_MASK 0x00000F00L 589#define DAGB0_RDCLI26__MAX_BW_ENABLE_MASK 0x00001000L 590#define DAGB0_RDCLI26__MAX_BW_MASK 0x001FE000L 591#define DAGB0_RDCLI26__MIN_BW_ENABLE_MASK 0x00200000L 592#define DAGB0_RDCLI26__MIN_BW_MASK 0x01C00000L 593#define DAGB0_RDCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 594#define DAGB0_RDCLI26__MAX_OSD_MASK 0xFC000000L 595//DAGB0_RDCLI27 596#define DAGB0_RDCLI27__VIRT_CHAN__SHIFT 0x0 597#define DAGB0_RDCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 598#define DAGB0_RDCLI27__URG_HIGH__SHIFT 0x4 599#define DAGB0_RDCLI27__URG_LOW__SHIFT 0x8 600#define DAGB0_RDCLI27__MAX_BW_ENABLE__SHIFT 0xc 601#define DAGB0_RDCLI27__MAX_BW__SHIFT 0xd 602#define DAGB0_RDCLI27__MIN_BW_ENABLE__SHIFT 0x15 603#define DAGB0_RDCLI27__MIN_BW__SHIFT 0x16 604#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 605#define DAGB0_RDCLI27__MAX_OSD__SHIFT 0x1a 606#define DAGB0_RDCLI27__VIRT_CHAN_MASK 0x00000007L 607#define DAGB0_RDCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 608#define DAGB0_RDCLI27__URG_HIGH_MASK 0x000000F0L 609#define DAGB0_RDCLI27__URG_LOW_MASK 0x00000F00L 610#define DAGB0_RDCLI27__MAX_BW_ENABLE_MASK 0x00001000L 611#define DAGB0_RDCLI27__MAX_BW_MASK 0x001FE000L 612#define DAGB0_RDCLI27__MIN_BW_ENABLE_MASK 0x00200000L 613#define DAGB0_RDCLI27__MIN_BW_MASK 0x01C00000L 614#define DAGB0_RDCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 615#define DAGB0_RDCLI27__MAX_OSD_MASK 0xFC000000L 616//DAGB0_RDCLI28 617#define DAGB0_RDCLI28__VIRT_CHAN__SHIFT 0x0 618#define DAGB0_RDCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 619#define DAGB0_RDCLI28__URG_HIGH__SHIFT 0x4 620#define DAGB0_RDCLI28__URG_LOW__SHIFT 0x8 621#define DAGB0_RDCLI28__MAX_BW_ENABLE__SHIFT 0xc 622#define DAGB0_RDCLI28__MAX_BW__SHIFT 0xd 623#define DAGB0_RDCLI28__MIN_BW_ENABLE__SHIFT 0x15 624#define DAGB0_RDCLI28__MIN_BW__SHIFT 0x16 625#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 626#define DAGB0_RDCLI28__MAX_OSD__SHIFT 0x1a 627#define DAGB0_RDCLI28__VIRT_CHAN_MASK 0x00000007L 628#define DAGB0_RDCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 629#define DAGB0_RDCLI28__URG_HIGH_MASK 0x000000F0L 630#define DAGB0_RDCLI28__URG_LOW_MASK 0x00000F00L 631#define DAGB0_RDCLI28__MAX_BW_ENABLE_MASK 0x00001000L 632#define DAGB0_RDCLI28__MAX_BW_MASK 0x001FE000L 633#define DAGB0_RDCLI28__MIN_BW_ENABLE_MASK 0x00200000L 634#define DAGB0_RDCLI28__MIN_BW_MASK 0x01C00000L 635#define DAGB0_RDCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 636#define DAGB0_RDCLI28__MAX_OSD_MASK 0xFC000000L 637//DAGB0_RDCLI29 638#define DAGB0_RDCLI29__VIRT_CHAN__SHIFT 0x0 639#define DAGB0_RDCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 640#define DAGB0_RDCLI29__URG_HIGH__SHIFT 0x4 641#define DAGB0_RDCLI29__URG_LOW__SHIFT 0x8 642#define DAGB0_RDCLI29__MAX_BW_ENABLE__SHIFT 0xc 643#define DAGB0_RDCLI29__MAX_BW__SHIFT 0xd 644#define DAGB0_RDCLI29__MIN_BW_ENABLE__SHIFT 0x15 645#define DAGB0_RDCLI29__MIN_BW__SHIFT 0x16 646#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 647#define DAGB0_RDCLI29__MAX_OSD__SHIFT 0x1a 648#define DAGB0_RDCLI29__VIRT_CHAN_MASK 0x00000007L 649#define DAGB0_RDCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 650#define DAGB0_RDCLI29__URG_HIGH_MASK 0x000000F0L 651#define DAGB0_RDCLI29__URG_LOW_MASK 0x00000F00L 652#define DAGB0_RDCLI29__MAX_BW_ENABLE_MASK 0x00001000L 653#define DAGB0_RDCLI29__MAX_BW_MASK 0x001FE000L 654#define DAGB0_RDCLI29__MIN_BW_ENABLE_MASK 0x00200000L 655#define DAGB0_RDCLI29__MIN_BW_MASK 0x01C00000L 656#define DAGB0_RDCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 657#define DAGB0_RDCLI29__MAX_OSD_MASK 0xFC000000L 658//DAGB0_RDCLI30 659#define DAGB0_RDCLI30__VIRT_CHAN__SHIFT 0x0 660#define DAGB0_RDCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 661#define DAGB0_RDCLI30__URG_HIGH__SHIFT 0x4 662#define DAGB0_RDCLI30__URG_LOW__SHIFT 0x8 663#define DAGB0_RDCLI30__MAX_BW_ENABLE__SHIFT 0xc 664#define DAGB0_RDCLI30__MAX_BW__SHIFT 0xd 665#define DAGB0_RDCLI30__MIN_BW_ENABLE__SHIFT 0x15 666#define DAGB0_RDCLI30__MIN_BW__SHIFT 0x16 667#define DAGB0_RDCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 668#define DAGB0_RDCLI30__MAX_OSD__SHIFT 0x1a 669#define DAGB0_RDCLI30__VIRT_CHAN_MASK 0x00000007L 670#define DAGB0_RDCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L 671#define DAGB0_RDCLI30__URG_HIGH_MASK 0x000000F0L 672#define DAGB0_RDCLI30__URG_LOW_MASK 0x00000F00L 673#define DAGB0_RDCLI30__MAX_BW_ENABLE_MASK 0x00001000L 674#define DAGB0_RDCLI30__MAX_BW_MASK 0x001FE000L 675#define DAGB0_RDCLI30__MIN_BW_ENABLE_MASK 0x00200000L 676#define DAGB0_RDCLI30__MIN_BW_MASK 0x01C00000L 677#define DAGB0_RDCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L 678#define DAGB0_RDCLI30__MAX_OSD_MASK 0xFC000000L 679//DAGB0_RDCLI31 680#define DAGB0_RDCLI31__VIRT_CHAN__SHIFT 0x0 681#define DAGB0_RDCLI31__CHECK_TLB_CREDIT__SHIFT 0x3 682#define DAGB0_RDCLI31__URG_HIGH__SHIFT 0x4 683#define DAGB0_RDCLI31__URG_LOW__SHIFT 0x8 684#define DAGB0_RDCLI31__MAX_BW_ENABLE__SHIFT 0xc 685#define DAGB0_RDCLI31__MAX_BW__SHIFT 0xd 686#define DAGB0_RDCLI31__MIN_BW_ENABLE__SHIFT 0x15 687#define DAGB0_RDCLI31__MIN_BW__SHIFT 0x16 688#define DAGB0_RDCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19 689#define DAGB0_RDCLI31__MAX_OSD__SHIFT 0x1a 690#define DAGB0_RDCLI31__VIRT_CHAN_MASK 0x00000007L 691#define DAGB0_RDCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L 692#define DAGB0_RDCLI31__URG_HIGH_MASK 0x000000F0L 693#define DAGB0_RDCLI31__URG_LOW_MASK 0x00000F00L 694#define DAGB0_RDCLI31__MAX_BW_ENABLE_MASK 0x00001000L 695#define DAGB0_RDCLI31__MAX_BW_MASK 0x001FE000L 696#define DAGB0_RDCLI31__MIN_BW_ENABLE_MASK 0x00200000L 697#define DAGB0_RDCLI31__MIN_BW_MASK 0x01C00000L 698#define DAGB0_RDCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L 699#define DAGB0_RDCLI31__MAX_OSD_MASK 0xFC000000L 700//DAGB0_RD_CNTL 701#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 702#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 703#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 704#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 705#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 706#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 707#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 708#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 709#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 710#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 711#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 712#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 713#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 714#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 715//DAGB0_RD_GMI_CNTL 716#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 717#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 718#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 719#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 720#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 721#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 722#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 723#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 724//DAGB0_RD_ADDR_DAGB 725#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 726#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 727#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 728#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 729#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 730#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 731#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 732#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 733//DAGB0_RD_OUTPUT_DAGB_MAX_BURST 734#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 735#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 736#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 737#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 738#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 739#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 740#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 741#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 742#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 743#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 744#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 745#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 746#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 747#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 748#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 749#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 750//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 751#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 752#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 753#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 754#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 755#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 756#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 757#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 758#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 759#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 760#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 761#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 762#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 763#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 764#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 765#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 766#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 767//DAGB0_RD_CGTT_CLK_CTRL 768#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 769#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 770#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 771#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 772#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 773#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 774#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 775#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 776#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 777#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 778#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 779#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 780#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 781#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 782#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 783#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 784//DAGB0_L1TLB_RD_CGTT_CLK_CTRL 785#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 786#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 787#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 788#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 789#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 790#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 791#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 792#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 793#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 794#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 795#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 796#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 797#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 798#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 799#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 800#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 801//DAGB0_ATCVM_RD_CGTT_CLK_CTRL 802#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 803#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 804#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 805#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 806#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 807#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 808#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 809#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 810#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 811#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 812#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 813#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 814#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 815#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 816#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 817#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 818//DAGB0_RD_ADDR_DAGB_MAX_BURST0 819#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 820#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 821#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 822#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 823#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 824#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 825#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 826#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 827#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 828#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 829#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 830#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 831#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 832#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 833#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 834#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 835//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 836#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 837#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 838#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 839#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 840#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 841#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 842#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 843#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 844#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 845#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 846#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 847#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 848#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 849#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 850#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 851#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 852//DAGB0_RD_ADDR_DAGB_MAX_BURST1 853#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 854#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 855#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 856#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 857#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 858#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 859#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 860#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 861#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 862#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 863#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 864#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 865#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 866#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 867#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 868#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 869//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 870#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 871#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 872#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 873#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 874#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 875#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 876#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 877#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 878#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 879#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 880#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 881#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 882#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 883#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 884#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 885#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 886//DAGB0_RD_ADDR_DAGB_MAX_BURST2 887#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 888#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 889#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 890#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 891#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 892#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 893#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 894#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 895#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 896#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 897#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 898#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 899#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 900#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 901#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 902#define DAGB0_RD_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 903//DAGB0_RD_ADDR_DAGB_LAZY_TIMER2 904#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 905#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 906#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 907#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 908#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 909#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 910#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 911#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 912#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 913#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 914#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 915#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 916#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 917#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 918#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 919#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 920//DAGB0_RD_ADDR_DAGB_MAX_BURST3 921#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 922#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 923#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 924#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 925#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 926#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 927#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 928#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 929#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 930#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 931#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 932#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 933#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 934#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 935#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 936#define DAGB0_RD_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 937//DAGB0_RD_ADDR_DAGB_LAZY_TIMER3 938#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 939#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 940#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 941#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 942#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 943#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 944#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 945#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 946#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 947#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 948#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 949#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 950#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 951#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 952#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 953#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 954//DAGB0_RD_VC0_CNTL 955#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 956#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 957#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 958#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 959#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 960#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 961#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 962#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 963#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 964#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 965#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 966#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 967#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 968#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 969#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 970#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 971//DAGB0_RD_VC1_CNTL 972#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 973#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 974#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 975#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 976#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 977#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 978#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 979#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 980#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 981#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 982#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 983#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 984#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 985#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 986#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 987#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 988//DAGB0_RD_VC2_CNTL 989#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 990#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 991#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 992#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 993#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 994#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 995#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 996#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 997#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 998#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 999#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1000#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1001#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1002#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1003#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1004#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1005//DAGB0_RD_VC3_CNTL 1006#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1007#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 1008#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1009#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 1010#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1011#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 1012#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1013#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 1014#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1015#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 1016#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1017#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1018#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1019#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1020#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1021#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1022//DAGB0_RD_VC4_CNTL 1023#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1024#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 1025#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1026#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 1027#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1028#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 1029#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1030#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 1031#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1032#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 1033#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1034#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1035#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1036#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1037#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1038#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1039//DAGB0_RD_VC5_CNTL 1040#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1041#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 1042#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1043#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 1044#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1045#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 1046#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1047#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 1048#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1049#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 1050#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1051#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1052#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1053#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1054#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1055#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1056//DAGB0_RD_VC6_CNTL 1057#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 1058#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 1059#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1060#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 1061#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1062#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 1063#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1064#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 1065#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 1066#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 1067#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1068#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 1069#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1070#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 1071#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1072#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 1073//DAGB0_RD_VC7_CNTL 1074#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 1075#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 1076#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1077#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 1078#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1079#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 1080#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1081#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 1082#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 1083#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 1084#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1085#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 1086#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1087#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 1088#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1089#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 1090//DAGB0_RD_CNTL_MISC 1091#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1092#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 1093#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 1094#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 1095#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 1096#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 1097#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1098#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 1099#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 1100#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 1101#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 1102#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 1103//DAGB0_RD_TLB_CREDIT 1104#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 1105#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 1106#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 1107#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 1108#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 1109#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 1110#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 1111#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 1112#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 1113#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 1114#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 1115#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 1116//DAGB0_RDCLI_ASK_PENDING 1117#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 1118#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1119//DAGB0_RDCLI_GO_PENDING 1120#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 1121#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1122//DAGB0_RDCLI_GBLSEND_PENDING 1123#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1124#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1125//DAGB0_RDCLI_TLB_PENDING 1126#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 1127#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1128//DAGB0_RDCLI_OARB_PENDING 1129#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 1130#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1131//DAGB0_RDCLI_OSD_PENDING 1132#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 1133#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1134//DAGB0_WRCLI0 1135#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 1136#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 1137#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 1138#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 1139#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 1140#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 1141#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 1142#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 1143#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 1144#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 1145#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 1146#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 1147#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 1148#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 1149#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 1150#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 1151#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 1152#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 1153#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 1154#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 1155//DAGB0_WRCLI1 1156#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 1157#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 1158#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 1159#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 1160#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 1161#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 1162#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 1163#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 1164#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 1165#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 1166#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 1167#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 1168#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 1169#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 1170#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 1171#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 1172#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 1173#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 1174#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 1175#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 1176//DAGB0_WRCLI2 1177#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 1178#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 1179#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 1180#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 1181#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 1182#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 1183#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 1184#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 1185#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 1186#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 1187#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 1188#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 1189#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 1190#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 1191#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 1192#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 1193#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 1194#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 1195#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 1196#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 1197//DAGB0_WRCLI3 1198#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 1199#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 1200#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 1201#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 1202#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 1203#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 1204#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 1205#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 1206#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 1207#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 1208#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 1209#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 1210#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 1211#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 1212#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 1213#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 1214#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 1215#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 1216#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 1217#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 1218//DAGB0_WRCLI4 1219#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 1220#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 1221#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 1222#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 1223#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 1224#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 1225#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 1226#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 1227#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 1228#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 1229#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 1230#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 1231#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 1232#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 1233#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 1234#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 1235#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 1236#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 1237#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 1238#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 1239//DAGB0_WRCLI5 1240#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 1241#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1242#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 1243#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 1244#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 1245#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 1246#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 1247#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 1248#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1249#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 1250#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 1251#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1252#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 1253#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 1254#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1255#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 1256#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1257#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 1258#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1259#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 1260//DAGB0_WRCLI6 1261#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 1262#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1263#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 1264#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 1265#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 1266#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 1267#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 1268#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 1269#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1270#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 1271#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 1272#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1273#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 1274#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 1275#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1276#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 1277#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1278#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 1279#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1280#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 1281//DAGB0_WRCLI7 1282#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 1283#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1284#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 1285#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 1286#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 1287#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 1288#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 1289#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 1290#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1291#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 1292#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 1293#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1294#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 1295#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 1296#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1297#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 1298#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1299#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 1300#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1301#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 1302//DAGB0_WRCLI8 1303#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 1304#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1305#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 1306#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 1307#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 1308#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 1309#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 1310#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 1311#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1312#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 1313#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 1314#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1315#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 1316#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 1317#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1318#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 1319#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1320#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 1321#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1322#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 1323//DAGB0_WRCLI9 1324#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 1325#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1326#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 1327#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 1328#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 1329#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 1330#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 1331#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 1332#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1333#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 1334#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 1335#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1336#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 1337#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 1338#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1339#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 1340#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1341#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 1342#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1343#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 1344//DAGB0_WRCLI10 1345#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 1346#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1347#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 1348#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 1349#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 1350#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 1351#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 1352#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 1353#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1354#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 1355#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 1356#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1357#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 1358#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 1359#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1360#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 1361#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1362#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 1363#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1364#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 1365//DAGB0_WRCLI11 1366#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 1367#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1368#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 1369#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 1370#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 1371#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 1372#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 1373#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 1374#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1375#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1376#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1377#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1378#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1379#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1380#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1381#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1382#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1383#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1384#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1385#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1386//DAGB0_WRCLI12 1387#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1388#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1389#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1390#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1391#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1392#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1393#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1394#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1395#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1396#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1397#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1398#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1399#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1400#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1401#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1402#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1403#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1404#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1405#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1406#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1407//DAGB0_WRCLI13 1408#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1409#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1410#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1411#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1412#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1413#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1414#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1415#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1416#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1417#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1418#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1419#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1420#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1421#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1422#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1423#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1424#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1425#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1426#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1427#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1428//DAGB0_WRCLI14 1429#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1430#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1431#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1432#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1433#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1434#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1435#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1436#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1437#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1438#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1439#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1440#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1441#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1442#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1443#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1444#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1445#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1446#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1447#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1448#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1449//DAGB0_WRCLI15 1450#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1451#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1452#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1453#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1454#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1455#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1456#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1457#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1458#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1459#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1460#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1461#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1462#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1463#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1464#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1465#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1466#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1467#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1468#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1469#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1470//DAGB0_WRCLI16 1471#define DAGB0_WRCLI16__VIRT_CHAN__SHIFT 0x0 1472#define DAGB0_WRCLI16__CHECK_TLB_CREDIT__SHIFT 0x3 1473#define DAGB0_WRCLI16__URG_HIGH__SHIFT 0x4 1474#define DAGB0_WRCLI16__URG_LOW__SHIFT 0x8 1475#define DAGB0_WRCLI16__MAX_BW_ENABLE__SHIFT 0xc 1476#define DAGB0_WRCLI16__MAX_BW__SHIFT 0xd 1477#define DAGB0_WRCLI16__MIN_BW_ENABLE__SHIFT 0x15 1478#define DAGB0_WRCLI16__MIN_BW__SHIFT 0x16 1479#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE__SHIFT 0x19 1480#define DAGB0_WRCLI16__MAX_OSD__SHIFT 0x1a 1481#define DAGB0_WRCLI16__VIRT_CHAN_MASK 0x00000007L 1482#define DAGB0_WRCLI16__CHECK_TLB_CREDIT_MASK 0x00000008L 1483#define DAGB0_WRCLI16__URG_HIGH_MASK 0x000000F0L 1484#define DAGB0_WRCLI16__URG_LOW_MASK 0x00000F00L 1485#define DAGB0_WRCLI16__MAX_BW_ENABLE_MASK 0x00001000L 1486#define DAGB0_WRCLI16__MAX_BW_MASK 0x001FE000L 1487#define DAGB0_WRCLI16__MIN_BW_ENABLE_MASK 0x00200000L 1488#define DAGB0_WRCLI16__MIN_BW_MASK 0x01C00000L 1489#define DAGB0_WRCLI16__OSD_LIMITER_ENABLE_MASK 0x02000000L 1490#define DAGB0_WRCLI16__MAX_OSD_MASK 0xFC000000L 1491//DAGB0_WRCLI17 1492#define DAGB0_WRCLI17__VIRT_CHAN__SHIFT 0x0 1493#define DAGB0_WRCLI17__CHECK_TLB_CREDIT__SHIFT 0x3 1494#define DAGB0_WRCLI17__URG_HIGH__SHIFT 0x4 1495#define DAGB0_WRCLI17__URG_LOW__SHIFT 0x8 1496#define DAGB0_WRCLI17__MAX_BW_ENABLE__SHIFT 0xc 1497#define DAGB0_WRCLI17__MAX_BW__SHIFT 0xd 1498#define DAGB0_WRCLI17__MIN_BW_ENABLE__SHIFT 0x15 1499#define DAGB0_WRCLI17__MIN_BW__SHIFT 0x16 1500#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE__SHIFT 0x19 1501#define DAGB0_WRCLI17__MAX_OSD__SHIFT 0x1a 1502#define DAGB0_WRCLI17__VIRT_CHAN_MASK 0x00000007L 1503#define DAGB0_WRCLI17__CHECK_TLB_CREDIT_MASK 0x00000008L 1504#define DAGB0_WRCLI17__URG_HIGH_MASK 0x000000F0L 1505#define DAGB0_WRCLI17__URG_LOW_MASK 0x00000F00L 1506#define DAGB0_WRCLI17__MAX_BW_ENABLE_MASK 0x00001000L 1507#define DAGB0_WRCLI17__MAX_BW_MASK 0x001FE000L 1508#define DAGB0_WRCLI17__MIN_BW_ENABLE_MASK 0x00200000L 1509#define DAGB0_WRCLI17__MIN_BW_MASK 0x01C00000L 1510#define DAGB0_WRCLI17__OSD_LIMITER_ENABLE_MASK 0x02000000L 1511#define DAGB0_WRCLI17__MAX_OSD_MASK 0xFC000000L 1512//DAGB0_WRCLI18 1513#define DAGB0_WRCLI18__VIRT_CHAN__SHIFT 0x0 1514#define DAGB0_WRCLI18__CHECK_TLB_CREDIT__SHIFT 0x3 1515#define DAGB0_WRCLI18__URG_HIGH__SHIFT 0x4 1516#define DAGB0_WRCLI18__URG_LOW__SHIFT 0x8 1517#define DAGB0_WRCLI18__MAX_BW_ENABLE__SHIFT 0xc 1518#define DAGB0_WRCLI18__MAX_BW__SHIFT 0xd 1519#define DAGB0_WRCLI18__MIN_BW_ENABLE__SHIFT 0x15 1520#define DAGB0_WRCLI18__MIN_BW__SHIFT 0x16 1521#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE__SHIFT 0x19 1522#define DAGB0_WRCLI18__MAX_OSD__SHIFT 0x1a 1523#define DAGB0_WRCLI18__VIRT_CHAN_MASK 0x00000007L 1524#define DAGB0_WRCLI18__CHECK_TLB_CREDIT_MASK 0x00000008L 1525#define DAGB0_WRCLI18__URG_HIGH_MASK 0x000000F0L 1526#define DAGB0_WRCLI18__URG_LOW_MASK 0x00000F00L 1527#define DAGB0_WRCLI18__MAX_BW_ENABLE_MASK 0x00001000L 1528#define DAGB0_WRCLI18__MAX_BW_MASK 0x001FE000L 1529#define DAGB0_WRCLI18__MIN_BW_ENABLE_MASK 0x00200000L 1530#define DAGB0_WRCLI18__MIN_BW_MASK 0x01C00000L 1531#define DAGB0_WRCLI18__OSD_LIMITER_ENABLE_MASK 0x02000000L 1532#define DAGB0_WRCLI18__MAX_OSD_MASK 0xFC000000L 1533//DAGB0_WRCLI19 1534#define DAGB0_WRCLI19__VIRT_CHAN__SHIFT 0x0 1535#define DAGB0_WRCLI19__CHECK_TLB_CREDIT__SHIFT 0x3 1536#define DAGB0_WRCLI19__URG_HIGH__SHIFT 0x4 1537#define DAGB0_WRCLI19__URG_LOW__SHIFT 0x8 1538#define DAGB0_WRCLI19__MAX_BW_ENABLE__SHIFT 0xc 1539#define DAGB0_WRCLI19__MAX_BW__SHIFT 0xd 1540#define DAGB0_WRCLI19__MIN_BW_ENABLE__SHIFT 0x15 1541#define DAGB0_WRCLI19__MIN_BW__SHIFT 0x16 1542#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE__SHIFT 0x19 1543#define DAGB0_WRCLI19__MAX_OSD__SHIFT 0x1a 1544#define DAGB0_WRCLI19__VIRT_CHAN_MASK 0x00000007L 1545#define DAGB0_WRCLI19__CHECK_TLB_CREDIT_MASK 0x00000008L 1546#define DAGB0_WRCLI19__URG_HIGH_MASK 0x000000F0L 1547#define DAGB0_WRCLI19__URG_LOW_MASK 0x00000F00L 1548#define DAGB0_WRCLI19__MAX_BW_ENABLE_MASK 0x00001000L 1549#define DAGB0_WRCLI19__MAX_BW_MASK 0x001FE000L 1550#define DAGB0_WRCLI19__MIN_BW_ENABLE_MASK 0x00200000L 1551#define DAGB0_WRCLI19__MIN_BW_MASK 0x01C00000L 1552#define DAGB0_WRCLI19__OSD_LIMITER_ENABLE_MASK 0x02000000L 1553#define DAGB0_WRCLI19__MAX_OSD_MASK 0xFC000000L 1554//DAGB0_WRCLI20 1555#define DAGB0_WRCLI20__VIRT_CHAN__SHIFT 0x0 1556#define DAGB0_WRCLI20__CHECK_TLB_CREDIT__SHIFT 0x3 1557#define DAGB0_WRCLI20__URG_HIGH__SHIFT 0x4 1558#define DAGB0_WRCLI20__URG_LOW__SHIFT 0x8 1559#define DAGB0_WRCLI20__MAX_BW_ENABLE__SHIFT 0xc 1560#define DAGB0_WRCLI20__MAX_BW__SHIFT 0xd 1561#define DAGB0_WRCLI20__MIN_BW_ENABLE__SHIFT 0x15 1562#define DAGB0_WRCLI20__MIN_BW__SHIFT 0x16 1563#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE__SHIFT 0x19 1564#define DAGB0_WRCLI20__MAX_OSD__SHIFT 0x1a 1565#define DAGB0_WRCLI20__VIRT_CHAN_MASK 0x00000007L 1566#define DAGB0_WRCLI20__CHECK_TLB_CREDIT_MASK 0x00000008L 1567#define DAGB0_WRCLI20__URG_HIGH_MASK 0x000000F0L 1568#define DAGB0_WRCLI20__URG_LOW_MASK 0x00000F00L 1569#define DAGB0_WRCLI20__MAX_BW_ENABLE_MASK 0x00001000L 1570#define DAGB0_WRCLI20__MAX_BW_MASK 0x001FE000L 1571#define DAGB0_WRCLI20__MIN_BW_ENABLE_MASK 0x00200000L 1572#define DAGB0_WRCLI20__MIN_BW_MASK 0x01C00000L 1573#define DAGB0_WRCLI20__OSD_LIMITER_ENABLE_MASK 0x02000000L 1574#define DAGB0_WRCLI20__MAX_OSD_MASK 0xFC000000L 1575//DAGB0_WRCLI21 1576#define DAGB0_WRCLI21__VIRT_CHAN__SHIFT 0x0 1577#define DAGB0_WRCLI21__CHECK_TLB_CREDIT__SHIFT 0x3 1578#define DAGB0_WRCLI21__URG_HIGH__SHIFT 0x4 1579#define DAGB0_WRCLI21__URG_LOW__SHIFT 0x8 1580#define DAGB0_WRCLI21__MAX_BW_ENABLE__SHIFT 0xc 1581#define DAGB0_WRCLI21__MAX_BW__SHIFT 0xd 1582#define DAGB0_WRCLI21__MIN_BW_ENABLE__SHIFT 0x15 1583#define DAGB0_WRCLI21__MIN_BW__SHIFT 0x16 1584#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE__SHIFT 0x19 1585#define DAGB0_WRCLI21__MAX_OSD__SHIFT 0x1a 1586#define DAGB0_WRCLI21__VIRT_CHAN_MASK 0x00000007L 1587#define DAGB0_WRCLI21__CHECK_TLB_CREDIT_MASK 0x00000008L 1588#define DAGB0_WRCLI21__URG_HIGH_MASK 0x000000F0L 1589#define DAGB0_WRCLI21__URG_LOW_MASK 0x00000F00L 1590#define DAGB0_WRCLI21__MAX_BW_ENABLE_MASK 0x00001000L 1591#define DAGB0_WRCLI21__MAX_BW_MASK 0x001FE000L 1592#define DAGB0_WRCLI21__MIN_BW_ENABLE_MASK 0x00200000L 1593#define DAGB0_WRCLI21__MIN_BW_MASK 0x01C00000L 1594#define DAGB0_WRCLI21__OSD_LIMITER_ENABLE_MASK 0x02000000L 1595#define DAGB0_WRCLI21__MAX_OSD_MASK 0xFC000000L 1596//DAGB0_WRCLI22 1597#define DAGB0_WRCLI22__VIRT_CHAN__SHIFT 0x0 1598#define DAGB0_WRCLI22__CHECK_TLB_CREDIT__SHIFT 0x3 1599#define DAGB0_WRCLI22__URG_HIGH__SHIFT 0x4 1600#define DAGB0_WRCLI22__URG_LOW__SHIFT 0x8 1601#define DAGB0_WRCLI22__MAX_BW_ENABLE__SHIFT 0xc 1602#define DAGB0_WRCLI22__MAX_BW__SHIFT 0xd 1603#define DAGB0_WRCLI22__MIN_BW_ENABLE__SHIFT 0x15 1604#define DAGB0_WRCLI22__MIN_BW__SHIFT 0x16 1605#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE__SHIFT 0x19 1606#define DAGB0_WRCLI22__MAX_OSD__SHIFT 0x1a 1607#define DAGB0_WRCLI22__VIRT_CHAN_MASK 0x00000007L 1608#define DAGB0_WRCLI22__CHECK_TLB_CREDIT_MASK 0x00000008L 1609#define DAGB0_WRCLI22__URG_HIGH_MASK 0x000000F0L 1610#define DAGB0_WRCLI22__URG_LOW_MASK 0x00000F00L 1611#define DAGB0_WRCLI22__MAX_BW_ENABLE_MASK 0x00001000L 1612#define DAGB0_WRCLI22__MAX_BW_MASK 0x001FE000L 1613#define DAGB0_WRCLI22__MIN_BW_ENABLE_MASK 0x00200000L 1614#define DAGB0_WRCLI22__MIN_BW_MASK 0x01C00000L 1615#define DAGB0_WRCLI22__OSD_LIMITER_ENABLE_MASK 0x02000000L 1616#define DAGB0_WRCLI22__MAX_OSD_MASK 0xFC000000L 1617//DAGB0_WRCLI23 1618#define DAGB0_WRCLI23__VIRT_CHAN__SHIFT 0x0 1619#define DAGB0_WRCLI23__CHECK_TLB_CREDIT__SHIFT 0x3 1620#define DAGB0_WRCLI23__URG_HIGH__SHIFT 0x4 1621#define DAGB0_WRCLI23__URG_LOW__SHIFT 0x8 1622#define DAGB0_WRCLI23__MAX_BW_ENABLE__SHIFT 0xc 1623#define DAGB0_WRCLI23__MAX_BW__SHIFT 0xd 1624#define DAGB0_WRCLI23__MIN_BW_ENABLE__SHIFT 0x15 1625#define DAGB0_WRCLI23__MIN_BW__SHIFT 0x16 1626#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE__SHIFT 0x19 1627#define DAGB0_WRCLI23__MAX_OSD__SHIFT 0x1a 1628#define DAGB0_WRCLI23__VIRT_CHAN_MASK 0x00000007L 1629#define DAGB0_WRCLI23__CHECK_TLB_CREDIT_MASK 0x00000008L 1630#define DAGB0_WRCLI23__URG_HIGH_MASK 0x000000F0L 1631#define DAGB0_WRCLI23__URG_LOW_MASK 0x00000F00L 1632#define DAGB0_WRCLI23__MAX_BW_ENABLE_MASK 0x00001000L 1633#define DAGB0_WRCLI23__MAX_BW_MASK 0x001FE000L 1634#define DAGB0_WRCLI23__MIN_BW_ENABLE_MASK 0x00200000L 1635#define DAGB0_WRCLI23__MIN_BW_MASK 0x01C00000L 1636#define DAGB0_WRCLI23__OSD_LIMITER_ENABLE_MASK 0x02000000L 1637#define DAGB0_WRCLI23__MAX_OSD_MASK 0xFC000000L 1638//DAGB0_WRCLI24 1639#define DAGB0_WRCLI24__VIRT_CHAN__SHIFT 0x0 1640#define DAGB0_WRCLI24__CHECK_TLB_CREDIT__SHIFT 0x3 1641#define DAGB0_WRCLI24__URG_HIGH__SHIFT 0x4 1642#define DAGB0_WRCLI24__URG_LOW__SHIFT 0x8 1643#define DAGB0_WRCLI24__MAX_BW_ENABLE__SHIFT 0xc 1644#define DAGB0_WRCLI24__MAX_BW__SHIFT 0xd 1645#define DAGB0_WRCLI24__MIN_BW_ENABLE__SHIFT 0x15 1646#define DAGB0_WRCLI24__MIN_BW__SHIFT 0x16 1647#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE__SHIFT 0x19 1648#define DAGB0_WRCLI24__MAX_OSD__SHIFT 0x1a 1649#define DAGB0_WRCLI24__VIRT_CHAN_MASK 0x00000007L 1650#define DAGB0_WRCLI24__CHECK_TLB_CREDIT_MASK 0x00000008L 1651#define DAGB0_WRCLI24__URG_HIGH_MASK 0x000000F0L 1652#define DAGB0_WRCLI24__URG_LOW_MASK 0x00000F00L 1653#define DAGB0_WRCLI24__MAX_BW_ENABLE_MASK 0x00001000L 1654#define DAGB0_WRCLI24__MAX_BW_MASK 0x001FE000L 1655#define DAGB0_WRCLI24__MIN_BW_ENABLE_MASK 0x00200000L 1656#define DAGB0_WRCLI24__MIN_BW_MASK 0x01C00000L 1657#define DAGB0_WRCLI24__OSD_LIMITER_ENABLE_MASK 0x02000000L 1658#define DAGB0_WRCLI24__MAX_OSD_MASK 0xFC000000L 1659//DAGB0_WRCLI25 1660#define DAGB0_WRCLI25__VIRT_CHAN__SHIFT 0x0 1661#define DAGB0_WRCLI25__CHECK_TLB_CREDIT__SHIFT 0x3 1662#define DAGB0_WRCLI25__URG_HIGH__SHIFT 0x4 1663#define DAGB0_WRCLI25__URG_LOW__SHIFT 0x8 1664#define DAGB0_WRCLI25__MAX_BW_ENABLE__SHIFT 0xc 1665#define DAGB0_WRCLI25__MAX_BW__SHIFT 0xd 1666#define DAGB0_WRCLI25__MIN_BW_ENABLE__SHIFT 0x15 1667#define DAGB0_WRCLI25__MIN_BW__SHIFT 0x16 1668#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE__SHIFT 0x19 1669#define DAGB0_WRCLI25__MAX_OSD__SHIFT 0x1a 1670#define DAGB0_WRCLI25__VIRT_CHAN_MASK 0x00000007L 1671#define DAGB0_WRCLI25__CHECK_TLB_CREDIT_MASK 0x00000008L 1672#define DAGB0_WRCLI25__URG_HIGH_MASK 0x000000F0L 1673#define DAGB0_WRCLI25__URG_LOW_MASK 0x00000F00L 1674#define DAGB0_WRCLI25__MAX_BW_ENABLE_MASK 0x00001000L 1675#define DAGB0_WRCLI25__MAX_BW_MASK 0x001FE000L 1676#define DAGB0_WRCLI25__MIN_BW_ENABLE_MASK 0x00200000L 1677#define DAGB0_WRCLI25__MIN_BW_MASK 0x01C00000L 1678#define DAGB0_WRCLI25__OSD_LIMITER_ENABLE_MASK 0x02000000L 1679#define DAGB0_WRCLI25__MAX_OSD_MASK 0xFC000000L 1680//DAGB0_WRCLI26 1681#define DAGB0_WRCLI26__VIRT_CHAN__SHIFT 0x0 1682#define DAGB0_WRCLI26__CHECK_TLB_CREDIT__SHIFT 0x3 1683#define DAGB0_WRCLI26__URG_HIGH__SHIFT 0x4 1684#define DAGB0_WRCLI26__URG_LOW__SHIFT 0x8 1685#define DAGB0_WRCLI26__MAX_BW_ENABLE__SHIFT 0xc 1686#define DAGB0_WRCLI26__MAX_BW__SHIFT 0xd 1687#define DAGB0_WRCLI26__MIN_BW_ENABLE__SHIFT 0x15 1688#define DAGB0_WRCLI26__MIN_BW__SHIFT 0x16 1689#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE__SHIFT 0x19 1690#define DAGB0_WRCLI26__MAX_OSD__SHIFT 0x1a 1691#define DAGB0_WRCLI26__VIRT_CHAN_MASK 0x00000007L 1692#define DAGB0_WRCLI26__CHECK_TLB_CREDIT_MASK 0x00000008L 1693#define DAGB0_WRCLI26__URG_HIGH_MASK 0x000000F0L 1694#define DAGB0_WRCLI26__URG_LOW_MASK 0x00000F00L 1695#define DAGB0_WRCLI26__MAX_BW_ENABLE_MASK 0x00001000L 1696#define DAGB0_WRCLI26__MAX_BW_MASK 0x001FE000L 1697#define DAGB0_WRCLI26__MIN_BW_ENABLE_MASK 0x00200000L 1698#define DAGB0_WRCLI26__MIN_BW_MASK 0x01C00000L 1699#define DAGB0_WRCLI26__OSD_LIMITER_ENABLE_MASK 0x02000000L 1700#define DAGB0_WRCLI26__MAX_OSD_MASK 0xFC000000L 1701//DAGB0_WRCLI27 1702#define DAGB0_WRCLI27__VIRT_CHAN__SHIFT 0x0 1703#define DAGB0_WRCLI27__CHECK_TLB_CREDIT__SHIFT 0x3 1704#define DAGB0_WRCLI27__URG_HIGH__SHIFT 0x4 1705#define DAGB0_WRCLI27__URG_LOW__SHIFT 0x8 1706#define DAGB0_WRCLI27__MAX_BW_ENABLE__SHIFT 0xc 1707#define DAGB0_WRCLI27__MAX_BW__SHIFT 0xd 1708#define DAGB0_WRCLI27__MIN_BW_ENABLE__SHIFT 0x15 1709#define DAGB0_WRCLI27__MIN_BW__SHIFT 0x16 1710#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE__SHIFT 0x19 1711#define DAGB0_WRCLI27__MAX_OSD__SHIFT 0x1a 1712#define DAGB0_WRCLI27__VIRT_CHAN_MASK 0x00000007L 1713#define DAGB0_WRCLI27__CHECK_TLB_CREDIT_MASK 0x00000008L 1714#define DAGB0_WRCLI27__URG_HIGH_MASK 0x000000F0L 1715#define DAGB0_WRCLI27__URG_LOW_MASK 0x00000F00L 1716#define DAGB0_WRCLI27__MAX_BW_ENABLE_MASK 0x00001000L 1717#define DAGB0_WRCLI27__MAX_BW_MASK 0x001FE000L 1718#define DAGB0_WRCLI27__MIN_BW_ENABLE_MASK 0x00200000L 1719#define DAGB0_WRCLI27__MIN_BW_MASK 0x01C00000L 1720#define DAGB0_WRCLI27__OSD_LIMITER_ENABLE_MASK 0x02000000L 1721#define DAGB0_WRCLI27__MAX_OSD_MASK 0xFC000000L 1722//DAGB0_WRCLI28 1723#define DAGB0_WRCLI28__VIRT_CHAN__SHIFT 0x0 1724#define DAGB0_WRCLI28__CHECK_TLB_CREDIT__SHIFT 0x3 1725#define DAGB0_WRCLI28__URG_HIGH__SHIFT 0x4 1726#define DAGB0_WRCLI28__URG_LOW__SHIFT 0x8 1727#define DAGB0_WRCLI28__MAX_BW_ENABLE__SHIFT 0xc 1728#define DAGB0_WRCLI28__MAX_BW__SHIFT 0xd 1729#define DAGB0_WRCLI28__MIN_BW_ENABLE__SHIFT 0x15 1730#define DAGB0_WRCLI28__MIN_BW__SHIFT 0x16 1731#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE__SHIFT 0x19 1732#define DAGB0_WRCLI28__MAX_OSD__SHIFT 0x1a 1733#define DAGB0_WRCLI28__VIRT_CHAN_MASK 0x00000007L 1734#define DAGB0_WRCLI28__CHECK_TLB_CREDIT_MASK 0x00000008L 1735#define DAGB0_WRCLI28__URG_HIGH_MASK 0x000000F0L 1736#define DAGB0_WRCLI28__URG_LOW_MASK 0x00000F00L 1737#define DAGB0_WRCLI28__MAX_BW_ENABLE_MASK 0x00001000L 1738#define DAGB0_WRCLI28__MAX_BW_MASK 0x001FE000L 1739#define DAGB0_WRCLI28__MIN_BW_ENABLE_MASK 0x00200000L 1740#define DAGB0_WRCLI28__MIN_BW_MASK 0x01C00000L 1741#define DAGB0_WRCLI28__OSD_LIMITER_ENABLE_MASK 0x02000000L 1742#define DAGB0_WRCLI28__MAX_OSD_MASK 0xFC000000L 1743//DAGB0_WRCLI29 1744#define DAGB0_WRCLI29__VIRT_CHAN__SHIFT 0x0 1745#define DAGB0_WRCLI29__CHECK_TLB_CREDIT__SHIFT 0x3 1746#define DAGB0_WRCLI29__URG_HIGH__SHIFT 0x4 1747#define DAGB0_WRCLI29__URG_LOW__SHIFT 0x8 1748#define DAGB0_WRCLI29__MAX_BW_ENABLE__SHIFT 0xc 1749#define DAGB0_WRCLI29__MAX_BW__SHIFT 0xd 1750#define DAGB0_WRCLI29__MIN_BW_ENABLE__SHIFT 0x15 1751#define DAGB0_WRCLI29__MIN_BW__SHIFT 0x16 1752#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE__SHIFT 0x19 1753#define DAGB0_WRCLI29__MAX_OSD__SHIFT 0x1a 1754#define DAGB0_WRCLI29__VIRT_CHAN_MASK 0x00000007L 1755#define DAGB0_WRCLI29__CHECK_TLB_CREDIT_MASK 0x00000008L 1756#define DAGB0_WRCLI29__URG_HIGH_MASK 0x000000F0L 1757#define DAGB0_WRCLI29__URG_LOW_MASK 0x00000F00L 1758#define DAGB0_WRCLI29__MAX_BW_ENABLE_MASK 0x00001000L 1759#define DAGB0_WRCLI29__MAX_BW_MASK 0x001FE000L 1760#define DAGB0_WRCLI29__MIN_BW_ENABLE_MASK 0x00200000L 1761#define DAGB0_WRCLI29__MIN_BW_MASK 0x01C00000L 1762#define DAGB0_WRCLI29__OSD_LIMITER_ENABLE_MASK 0x02000000L 1763#define DAGB0_WRCLI29__MAX_OSD_MASK 0xFC000000L 1764//DAGB0_WRCLI30 1765#define DAGB0_WRCLI30__VIRT_CHAN__SHIFT 0x0 1766#define DAGB0_WRCLI30__CHECK_TLB_CREDIT__SHIFT 0x3 1767#define DAGB0_WRCLI30__URG_HIGH__SHIFT 0x4 1768#define DAGB0_WRCLI30__URG_LOW__SHIFT 0x8 1769#define DAGB0_WRCLI30__MAX_BW_ENABLE__SHIFT 0xc 1770#define DAGB0_WRCLI30__MAX_BW__SHIFT 0xd 1771#define DAGB0_WRCLI30__MIN_BW_ENABLE__SHIFT 0x15 1772#define DAGB0_WRCLI30__MIN_BW__SHIFT 0x16 1773#define DAGB0_WRCLI30__OSD_LIMITER_ENABLE__SHIFT 0x19 1774#define DAGB0_WRCLI30__MAX_OSD__SHIFT 0x1a 1775#define DAGB0_WRCLI30__VIRT_CHAN_MASK 0x00000007L 1776#define DAGB0_WRCLI30__CHECK_TLB_CREDIT_MASK 0x00000008L 1777#define DAGB0_WRCLI30__URG_HIGH_MASK 0x000000F0L 1778#define DAGB0_WRCLI30__URG_LOW_MASK 0x00000F00L 1779#define DAGB0_WRCLI30__MAX_BW_ENABLE_MASK 0x00001000L 1780#define DAGB0_WRCLI30__MAX_BW_MASK 0x001FE000L 1781#define DAGB0_WRCLI30__MIN_BW_ENABLE_MASK 0x00200000L 1782#define DAGB0_WRCLI30__MIN_BW_MASK 0x01C00000L 1783#define DAGB0_WRCLI30__OSD_LIMITER_ENABLE_MASK 0x02000000L 1784#define DAGB0_WRCLI30__MAX_OSD_MASK 0xFC000000L 1785//DAGB0_WRCLI31 1786#define DAGB0_WRCLI31__VIRT_CHAN__SHIFT 0x0 1787#define DAGB0_WRCLI31__CHECK_TLB_CREDIT__SHIFT 0x3 1788#define DAGB0_WRCLI31__URG_HIGH__SHIFT 0x4 1789#define DAGB0_WRCLI31__URG_LOW__SHIFT 0x8 1790#define DAGB0_WRCLI31__MAX_BW_ENABLE__SHIFT 0xc 1791#define DAGB0_WRCLI31__MAX_BW__SHIFT 0xd 1792#define DAGB0_WRCLI31__MIN_BW_ENABLE__SHIFT 0x15 1793#define DAGB0_WRCLI31__MIN_BW__SHIFT 0x16 1794#define DAGB0_WRCLI31__OSD_LIMITER_ENABLE__SHIFT 0x19 1795#define DAGB0_WRCLI31__MAX_OSD__SHIFT 0x1a 1796#define DAGB0_WRCLI31__VIRT_CHAN_MASK 0x00000007L 1797#define DAGB0_WRCLI31__CHECK_TLB_CREDIT_MASK 0x00000008L 1798#define DAGB0_WRCLI31__URG_HIGH_MASK 0x000000F0L 1799#define DAGB0_WRCLI31__URG_LOW_MASK 0x00000F00L 1800#define DAGB0_WRCLI31__MAX_BW_ENABLE_MASK 0x00001000L 1801#define DAGB0_WRCLI31__MAX_BW_MASK 0x001FE000L 1802#define DAGB0_WRCLI31__MIN_BW_ENABLE_MASK 0x00200000L 1803#define DAGB0_WRCLI31__MIN_BW_MASK 0x01C00000L 1804#define DAGB0_WRCLI31__OSD_LIMITER_ENABLE_MASK 0x02000000L 1805#define DAGB0_WRCLI31__MAX_OSD_MASK 0xFC000000L 1806//DAGB0_WR_CNTL 1807#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 1808#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 1809#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 1810#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 1811#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 1812#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 1813#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 1814#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 1815#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 1816#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 1817#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 1818#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 1819#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 1820#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 1821//DAGB0_WR_GMI_CNTL 1822#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 1823#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 1824#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 1825#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 1826#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 1827#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 1828#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 1829#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 1830//DAGB0_WR_ADDR_DAGB 1831#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1832#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1833#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1834#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1835#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1836#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1837#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1838#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1839//DAGB0_WR_OUTPUT_DAGB_MAX_BURST 1840#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 1841#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 1842#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 1843#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 1844#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 1845#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 1846#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 1847#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 1848#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 1849#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 1850#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 1851#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 1852#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 1853#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 1854#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 1855#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 1856//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 1857#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 1858#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 1859#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 1860#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 1861#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 1862#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 1863#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 1864#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 1865#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 1866#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 1867#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 1868#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 1869#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 1870#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 1871#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 1872#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 1873//DAGB0_WR_CGTT_CLK_CTRL 1874#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1875#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1876#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1877#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1878#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1879#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1880#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1881#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1882#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1883#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1884#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1885#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1886#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1887#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1888#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1889#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1890//DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1891#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1892#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1893#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1894#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1895#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1896#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1897#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1898#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1899#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1900#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1901#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1902#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1903#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1904#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1905#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1906#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1907//DAGB0_ATCVM_WR_CGTT_CLK_CTRL 1908#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1909#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1910#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1911#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1912#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1913#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1914#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1915#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1916#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1917#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1918#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1919#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1920#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1921#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1922#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1923#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1924//DAGB0_WR_ADDR_DAGB_MAX_BURST0 1925#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1926#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1927#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1928#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1929#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1930#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1931#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1932#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1933#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1934#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1935#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1936#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1937#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1938#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1939#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1940#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1941//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1942#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1943#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1944#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1945#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1946#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1947#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1948#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1949#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1950#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1951#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1952#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1953#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1954#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1955#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1956#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1957#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1958//DAGB0_WR_ADDR_DAGB_MAX_BURST1 1959#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1960#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1961#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1962#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1963#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1964#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1965#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1966#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1967#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1968#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1969#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1970#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1971#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1972#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1973#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1974#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1975//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1976#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1977#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1978#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1979#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1980#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1981#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1982#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1983#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1984#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1985#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1986#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1987#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1988#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1989#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1990#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1991#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1992//DAGB0_WR_ADDR_DAGB_MAX_BURST2 1993#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 1994#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 1995#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 1996#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 1997#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 1998#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 1999#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 2000#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 2001#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 2002#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 2003#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 2004#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 2005#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 2006#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 2007#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 2008#define DAGB0_WR_ADDR_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 2009//DAGB0_WR_ADDR_DAGB_LAZY_TIMER2 2010#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 2011#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 2012#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 2013#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 2014#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 2015#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 2016#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 2017#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 2018#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 2019#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 2020#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 2021#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 2022#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 2023#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 2024#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 2025#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 2026//DAGB0_WR_ADDR_DAGB_MAX_BURST3 2027#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 2028#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 2029#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 2030#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 2031#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 2032#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 2033#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 2034#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 2035#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 2036#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 2037#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 2038#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 2039#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 2040#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 2041#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 2042#define DAGB0_WR_ADDR_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 2043//DAGB0_WR_ADDR_DAGB_LAZY_TIMER3 2044#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 2045#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 2046#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 2047#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 2048#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 2049#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 2050#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 2051#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 2052#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 2053#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 2054#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 2055#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 2056#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 2057#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 2058#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 2059#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 2060//DAGB0_WR_DATA_DAGB 2061#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 2062#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2063#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2064#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 2065#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 2066#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2067#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2068#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 2069//DAGB0_WR_DATA_DAGB_MAX_BURST0 2070#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2071#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2072#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2073#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2074#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2075#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2076#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2077#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2078#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2079#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2080#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2081#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2082#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2083#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2084#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2085#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2086//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 2087#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2088#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2089#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2090#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2091#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2092#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2093#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2094#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2095#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2096#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2097#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2098#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2099#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2100#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2101#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2102#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2103//DAGB0_WR_DATA_DAGB_MAX_BURST1 2104#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2105#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2106#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2107#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2108#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2109#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2110#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2111#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2112#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2113#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2114#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2115#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2116#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2117#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2118#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2119#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2120//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 2121#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2122#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2123#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2124#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2125#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2126#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2127#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2128#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2129#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2130#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2131#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2132#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2133#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2134#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2135#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2136#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2137//DAGB0_WR_DATA_DAGB_MAX_BURST2 2138#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16__SHIFT 0x0 2139#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17__SHIFT 0x4 2140#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18__SHIFT 0x8 2141#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19__SHIFT 0xc 2142#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20__SHIFT 0x10 2143#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21__SHIFT 0x14 2144#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22__SHIFT 0x18 2145#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23__SHIFT 0x1c 2146#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT16_MASK 0x0000000FL 2147#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT17_MASK 0x000000F0L 2148#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT18_MASK 0x00000F00L 2149#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT19_MASK 0x0000F000L 2150#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT20_MASK 0x000F0000L 2151#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT21_MASK 0x00F00000L 2152#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT22_MASK 0x0F000000L 2153#define DAGB0_WR_DATA_DAGB_MAX_BURST2__CLIENT23_MASK 0xF0000000L 2154//DAGB0_WR_DATA_DAGB_LAZY_TIMER2 2155#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16__SHIFT 0x0 2156#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17__SHIFT 0x4 2157#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18__SHIFT 0x8 2158#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19__SHIFT 0xc 2159#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20__SHIFT 0x10 2160#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21__SHIFT 0x14 2161#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22__SHIFT 0x18 2162#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23__SHIFT 0x1c 2163#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT16_MASK 0x0000000FL 2164#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT17_MASK 0x000000F0L 2165#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT18_MASK 0x00000F00L 2166#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT19_MASK 0x0000F000L 2167#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT20_MASK 0x000F0000L 2168#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT21_MASK 0x00F00000L 2169#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT22_MASK 0x0F000000L 2170#define DAGB0_WR_DATA_DAGB_LAZY_TIMER2__CLIENT23_MASK 0xF0000000L 2171//DAGB0_WR_DATA_DAGB_MAX_BURST3 2172#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24__SHIFT 0x0 2173#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25__SHIFT 0x4 2174#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26__SHIFT 0x8 2175#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27__SHIFT 0xc 2176#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28__SHIFT 0x10 2177#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29__SHIFT 0x14 2178#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30__SHIFT 0x18 2179#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31__SHIFT 0x1c 2180#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT24_MASK 0x0000000FL 2181#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT25_MASK 0x000000F0L 2182#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT26_MASK 0x00000F00L 2183#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT27_MASK 0x0000F000L 2184#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT28_MASK 0x000F0000L 2185#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT29_MASK 0x00F00000L 2186#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT30_MASK 0x0F000000L 2187#define DAGB0_WR_DATA_DAGB_MAX_BURST3__CLIENT31_MASK 0xF0000000L 2188//DAGB0_WR_DATA_DAGB_LAZY_TIMER3 2189#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24__SHIFT 0x0 2190#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25__SHIFT 0x4 2191#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26__SHIFT 0x8 2192#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27__SHIFT 0xc 2193#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28__SHIFT 0x10 2194#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29__SHIFT 0x14 2195#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30__SHIFT 0x18 2196#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31__SHIFT 0x1c 2197#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT24_MASK 0x0000000FL 2198#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT25_MASK 0x000000F0L 2199#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT26_MASK 0x00000F00L 2200#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT27_MASK 0x0000F000L 2201#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT28_MASK 0x000F0000L 2202#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT29_MASK 0x00F00000L 2203#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT30_MASK 0x0F000000L 2204#define DAGB0_WR_DATA_DAGB_LAZY_TIMER3__CLIENT31_MASK 0xF0000000L 2205//DAGB0_WR_VC0_CNTL 2206#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 2207#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 2208#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2209#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 2210#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2211#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 2212#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2213#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 2214#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 2215#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 2216#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2217#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 2218#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2219#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 2220#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2221#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 2222//DAGB0_WR_VC1_CNTL 2223#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 2224#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 2225#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2226#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 2227#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2228#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 2229#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2230#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 2231#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 2232#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 2233#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2234#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 2235#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2236#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 2237#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2238#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 2239//DAGB0_WR_VC2_CNTL 2240#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 2241#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 2242#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2243#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 2244#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2245#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 2246#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2247#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 2248#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 2249#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 2250#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2251#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 2252#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2253#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 2254#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2255#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 2256//DAGB0_WR_VC3_CNTL 2257#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 2258#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 2259#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2260#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 2261#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2262#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 2263#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2264#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 2265#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 2266#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 2267#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2268#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 2269#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2270#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 2271#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2272#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 2273//DAGB0_WR_VC4_CNTL 2274#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 2275#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 2276#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2277#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 2278#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2279#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 2280#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2281#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 2282#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 2283#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 2284#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2285#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 2286#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2287#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 2288#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2289#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 2290//DAGB0_WR_VC5_CNTL 2291#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 2292#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 2293#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2294#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 2295#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2296#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 2297#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2298#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 2299#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 2300#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 2301#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2302#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 2303#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2304#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 2305#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2306#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 2307//DAGB0_WR_VC6_CNTL 2308#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 2309#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 2310#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2311#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 2312#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2313#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 2314#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2315#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 2316#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 2317#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 2318#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2319#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 2320#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2321#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 2322#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2323#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 2324//DAGB0_WR_VC7_CNTL 2325#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 2326#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 2327#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2328#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 2329#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2330#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 2331#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2332#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 2333#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 2334#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 2335#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2336#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 2337#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2338#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 2339#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2340#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 2341//DAGB0_WR_CNTL_MISC 2342#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 2343#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 2344#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 2345#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 2346#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 2347#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 2348#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 2349#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 2350#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 2351#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 2352#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 2353#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 2354//DAGB0_WR_TLB_CREDIT 2355#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 2356#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 2357#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 2358#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 2359#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 2360#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 2361#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 2362#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 2363#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 2364#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 2365#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 2366#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 2367//DAGB0_WR_DATA_CREDIT 2368#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 2369#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 2370#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 2371#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 2372#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 2373#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 2374#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 2375#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 2376//DAGB0_WR_MISC_CREDIT 2377#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 2378#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 2379#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 2380#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 2381#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 2382#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 2383#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 2384#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 2385//DAGB0_WRCLI_ASK_PENDING 2386#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 2387#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2388//DAGB0_WRCLI_GO_PENDING 2389#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 2390#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2391//DAGB0_WRCLI_GBLSEND_PENDING 2392#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 2393#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 2394//DAGB0_WRCLI_TLB_PENDING 2395#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 2396#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 2397//DAGB0_WRCLI_OARB_PENDING 2398#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 2399#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2400//DAGB0_WRCLI_OSD_PENDING 2401#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 2402#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2403//DAGB0_WRCLI_DBUS_ASK_PENDING 2404#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 2405#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2406//DAGB0_WRCLI_DBUS_GO_PENDING 2407#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 2408#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2409//DAGB0_DAGB_DLY 2410#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 2411#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 2412#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 2413#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 2414#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 2415#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 2416//DAGB0_CNTL_MISC 2417#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 2418#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 2419#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 2420#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 2421#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 2422#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 2423#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 2424#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 2425#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 2426#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 2427#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 2428#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 2429#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 2430#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 2431#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 2432#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 2433#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 2434#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 2435#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 2436#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 2437//DAGB0_CNTL_MISC2 2438#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 2439#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 2440#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 2441#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 2442#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 2443#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 2444#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 2445#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 2446#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 2447#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 2448#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 2449#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 2450#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 2451#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 2452#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 2453#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 2454#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 2455#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 2456#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 2457#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 2458#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 2459#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 2460//DAGB0_FIFO_EMPTY 2461#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 2462#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 2463//DAGB0_FIFO_FULL 2464#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 2465#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL 2466//DAGB0_WR_CREDITS_FULL 2467#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 2468#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL 2469//DAGB0_RD_CREDITS_FULL 2470#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 2471#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 2472//DAGB0_PERFCOUNTER_LO 2473#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 2474#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 2475//DAGB0_PERFCOUNTER_HI 2476#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 2477#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 2478#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 2479#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 2480//DAGB0_PERFCOUNTER0_CFG 2481#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 2482#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 2483#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 2484#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 2485#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 2486#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 2487#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 2488#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 2489#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 2490#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 2491//DAGB0_PERFCOUNTER1_CFG 2492#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 2493#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 2494#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 2495#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 2496#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 2497#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 2498#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 2499#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 2500#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 2501#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 2502//DAGB0_PERFCOUNTER2_CFG 2503#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 2504#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 2505#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 2506#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 2507#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 2508#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 2509#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 2510#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 2511#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 2512#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 2513//DAGB0_PERFCOUNTER_RSLT_CNTL 2514#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 2515#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 2516#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 2517#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 2518#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 2519#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 2520#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 2521#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 2522#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 2523#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 2524#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 2525#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 2526//DAGB0_RESERVE0 2527#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 2528#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 2529//DAGB0_RESERVE1 2530#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 2531#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 2532//DAGB0_RESERVE2 2533#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 2534#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 2535//DAGB0_RESERVE3 2536#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 2537#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 2538//DAGB0_RESERVE4 2539#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 2540#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 2541//DAGB0_RESERVE5 2542#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 2543#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 2544//DAGB0_RESERVE6 2545#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 2546#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 2547//DAGB0_RESERVE7 2548#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 2549#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 2550//DAGB0_RESERVE8 2551#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 2552#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 2553//DAGB0_RESERVE9 2554#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 2555#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 2556//DAGB0_RESERVE10 2557#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 2558#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 2559//DAGB0_RESERVE11 2560#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 2561#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 2562//DAGB0_RESERVE12 2563#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 2564#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 2565//DAGB0_RESERVE13 2566#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 2567#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 2568//DAGB0_RESERVE14 2569#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 2570#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL 2571//DAGB0_RESERVE15 2572#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 2573#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL 2574//DAGB0_RESERVE16 2575#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 2576#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL 2577//DAGB0_RESERVE17 2578#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 2579#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL 2580//DAGB0_RESERVE18 2581#define DAGB0_RESERVE18__RESERVE__SHIFT 0x0 2582#define DAGB0_RESERVE18__RESERVE_MASK 0xFFFFFFFFL 2583//DAGB0_RESERVE19 2584#define DAGB0_RESERVE19__RESERVE__SHIFT 0x0 2585#define DAGB0_RESERVE19__RESERVE_MASK 0xFFFFFFFFL 2586//DAGB0_RESERVE20 2587#define DAGB0_RESERVE20__RESERVE__SHIFT 0x0 2588#define DAGB0_RESERVE20__RESERVE_MASK 0xFFFFFFFFL 2589//DAGB0_RESERVE21 2590#define DAGB0_RESERVE21__RESERVE__SHIFT 0x0 2591#define DAGB0_RESERVE21__RESERVE_MASK 0xFFFFFFFFL 2592//DAGB0_RESERVE22 2593#define DAGB0_RESERVE22__RESERVE__SHIFT 0x0 2594#define DAGB0_RESERVE22__RESERVE_MASK 0xFFFFFFFFL 2595//DAGB0_RESERVE23 2596#define DAGB0_RESERVE23__RESERVE__SHIFT 0x0 2597#define DAGB0_RESERVE23__RESERVE_MASK 0xFFFFFFFFL 2598//DAGB0_RESERVE24 2599#define DAGB0_RESERVE24__RESERVE__SHIFT 0x0 2600#define DAGB0_RESERVE24__RESERVE_MASK 0xFFFFFFFFL 2601//DAGB0_RESERVE25 2602#define DAGB0_RESERVE25__RESERVE__SHIFT 0x0 2603#define DAGB0_RESERVE25__RESERVE_MASK 0xFFFFFFFFL 2604//DAGB0_RESERVE26 2605#define DAGB0_RESERVE26__RESERVE__SHIFT 0x0 2606#define DAGB0_RESERVE26__RESERVE_MASK 0xFFFFFFFFL 2607//DAGB0_RESERVE27 2608#define DAGB0_RESERVE27__RESERVE__SHIFT 0x0 2609#define DAGB0_RESERVE27__RESERVE_MASK 0xFFFFFFFFL 2610//DAGB0_RESERVE28 2611#define DAGB0_RESERVE28__RESERVE__SHIFT 0x0 2612#define DAGB0_RESERVE28__RESERVE_MASK 0xFFFFFFFFL 2613//DAGB0_RESERVE29 2614#define DAGB0_RESERVE29__RESERVE__SHIFT 0x0 2615#define DAGB0_RESERVE29__RESERVE_MASK 0xFFFFFFFFL 2616//DAGB0_RESERVE30 2617#define DAGB0_RESERVE30__RESERVE__SHIFT 0x0 2618#define DAGB0_RESERVE30__RESERVE_MASK 0xFFFFFFFFL 2619//DAGB0_RESERVE31 2620#define DAGB0_RESERVE31__RESERVE__SHIFT 0x0 2621#define DAGB0_RESERVE31__RESERVE_MASK 0xFFFFFFFFL 2622//DAGB0_RESERVE32 2623#define DAGB0_RESERVE32__RESERVE__SHIFT 0x0 2624#define DAGB0_RESERVE32__RESERVE_MASK 0xFFFFFFFFL 2625//DAGB0_RESERVE33 2626#define DAGB0_RESERVE33__RESERVE__SHIFT 0x0 2627#define DAGB0_RESERVE33__RESERVE_MASK 0xFFFFFFFFL 2628//DAGB0_RESERVE34 2629#define DAGB0_RESERVE34__RESERVE__SHIFT 0x0 2630#define DAGB0_RESERVE34__RESERVE_MASK 0xFFFFFFFFL 2631//DAGB0_RESERVE35 2632#define DAGB0_RESERVE35__RESERVE__SHIFT 0x0 2633#define DAGB0_RESERVE35__RESERVE_MASK 0xFFFFFFFFL 2634//DAGB0_RESERVE36 2635#define DAGB0_RESERVE36__RESERVE__SHIFT 0x0 2636#define DAGB0_RESERVE36__RESERVE_MASK 0xFFFFFFFFL 2637//DAGB0_RESERVE37 2638#define DAGB0_RESERVE37__RESERVE__SHIFT 0x0 2639#define DAGB0_RESERVE37__RESERVE_MASK 0xFFFFFFFFL 2640//DAGB0_RESERVE38 2641#define DAGB0_RESERVE38__RESERVE__SHIFT 0x0 2642#define DAGB0_RESERVE38__RESERVE_MASK 0xFFFFFFFFL 2643//DAGB0_RESERVE39 2644#define DAGB0_RESERVE39__RESERVE__SHIFT 0x0 2645#define DAGB0_RESERVE39__RESERVE_MASK 0xFFFFFFFFL 2646//DAGB0_RESERVE40 2647#define DAGB0_RESERVE40__RESERVE__SHIFT 0x0 2648#define DAGB0_RESERVE40__RESERVE_MASK 0xFFFFFFFFL 2649//DAGB0_RESERVE41 2650#define DAGB0_RESERVE41__RESERVE__SHIFT 0x0 2651#define DAGB0_RESERVE41__RESERVE_MASK 0xFFFFFFFFL 2652//DAGB0_RESERVE42 2653#define DAGB0_RESERVE42__RESERVE__SHIFT 0x0 2654#define DAGB0_RESERVE42__RESERVE_MASK 0xFFFFFFFFL 2655//DAGB0_RESERVE43 2656#define DAGB0_RESERVE43__RESERVE__SHIFT 0x0 2657#define DAGB0_RESERVE43__RESERVE_MASK 0xFFFFFFFFL 2658//DAGB0_RESERVE44 2659#define DAGB0_RESERVE44__RESERVE__SHIFT 0x0 2660#define DAGB0_RESERVE44__RESERVE_MASK 0xFFFFFFFFL 2661//DAGB0_RESERVE45 2662#define DAGB0_RESERVE45__RESERVE__SHIFT 0x0 2663#define DAGB0_RESERVE45__RESERVE_MASK 0xFFFFFFFFL 2664//DAGB0_RESERVE46 2665#define DAGB0_RESERVE46__RESERVE__SHIFT 0x0 2666#define DAGB0_RESERVE46__RESERVE_MASK 0xFFFFFFFFL 2667//DAGB0_RESERVE47 2668#define DAGB0_RESERVE47__RESERVE__SHIFT 0x0 2669#define DAGB0_RESERVE47__RESERVE_MASK 0xFFFFFFFFL 2670//DAGB0_RESERVE48 2671#define DAGB0_RESERVE48__RESERVE__SHIFT 0x0 2672#define DAGB0_RESERVE48__RESERVE_MASK 0xFFFFFFFFL 2673//DAGB0_RESERVE49 2674#define DAGB0_RESERVE49__RESERVE__SHIFT 0x0 2675#define DAGB0_RESERVE49__RESERVE_MASK 0xFFFFFFFFL 2676//DAGB0_RESERVE50 2677#define DAGB0_RESERVE50__RESERVE__SHIFT 0x0 2678#define DAGB0_RESERVE50__RESERVE_MASK 0xFFFFFFFFL 2679//DAGB0_RESERVE51 2680#define DAGB0_RESERVE51__RESERVE__SHIFT 0x0 2681#define DAGB0_RESERVE51__RESERVE_MASK 0xFFFFFFFFL 2682//DAGB0_RESERVE52 2683#define DAGB0_RESERVE52__RESERVE__SHIFT 0x0 2684#define DAGB0_RESERVE52__RESERVE_MASK 0xFFFFFFFFL 2685//DAGB0_RESERVE53 2686#define DAGB0_RESERVE53__RESERVE__SHIFT 0x0 2687#define DAGB0_RESERVE53__RESERVE_MASK 0xFFFFFFFFL 2688//DAGB0_RESERVE54 2689#define DAGB0_RESERVE54__RESERVE__SHIFT 0x0 2690#define DAGB0_RESERVE54__RESERVE_MASK 0xFFFFFFFFL 2691//DAGB0_RESERVE55 2692#define DAGB0_RESERVE55__RESERVE__SHIFT 0x0 2693#define DAGB0_RESERVE55__RESERVE_MASK 0xFFFFFFFFL 2694//DAGB0_RESERVE56 2695#define DAGB0_RESERVE56__RESERVE__SHIFT 0x0 2696#define DAGB0_RESERVE56__RESERVE_MASK 0xFFFFFFFFL 2697//DAGB0_RESERVE57 2698#define DAGB0_RESERVE57__RESERVE__SHIFT 0x0 2699#define DAGB0_RESERVE57__RESERVE_MASK 0xFFFFFFFFL 2700//DAGB0_RESERVE58 2701#define DAGB0_RESERVE58__RESERVE__SHIFT 0x0 2702#define DAGB0_RESERVE58__RESERVE_MASK 0xFFFFFFFFL 2703//DAGB0_RESERVE59 2704#define DAGB0_RESERVE59__RESERVE__SHIFT 0x0 2705#define DAGB0_RESERVE59__RESERVE_MASK 0xFFFFFFFFL 2706//DAGB0_RESERVE60 2707#define DAGB0_RESERVE60__RESERVE__SHIFT 0x0 2708#define DAGB0_RESERVE60__RESERVE_MASK 0xFFFFFFFFL 2709//DAGB0_RESERVE61 2710#define DAGB0_RESERVE61__RESERVE__SHIFT 0x0 2711#define DAGB0_RESERVE61__RESERVE_MASK 0xFFFFFFFFL 2712//DAGB0_RESERVE62 2713#define DAGB0_RESERVE62__RESERVE__SHIFT 0x0 2714#define DAGB0_RESERVE62__RESERVE_MASK 0xFFFFFFFFL 2715//DAGB0_RESERVE63 2716#define DAGB0_RESERVE63__RESERVE__SHIFT 0x0 2717#define DAGB0_RESERVE63__RESERVE_MASK 0xFFFFFFFFL 2718//DAGB0_RESERVE64 2719#define DAGB0_RESERVE64__RESERVE__SHIFT 0x0 2720#define DAGB0_RESERVE64__RESERVE_MASK 0xFFFFFFFFL 2721//DAGB0_RESERVE65 2722#define DAGB0_RESERVE65__RESERVE__SHIFT 0x0 2723#define DAGB0_RESERVE65__RESERVE_MASK 0xFFFFFFFFL 2724//DAGB0_RESERVE66 2725#define DAGB0_RESERVE66__RESERVE__SHIFT 0x0 2726#define DAGB0_RESERVE66__RESERVE_MASK 0xFFFFFFFFL 2727//DAGB0_RESERVE67 2728#define DAGB0_RESERVE67__RESERVE__SHIFT 0x0 2729#define DAGB0_RESERVE67__RESERVE_MASK 0xFFFFFFFFL 2730//DAGB0_RESERVE68 2731#define DAGB0_RESERVE68__RESERVE__SHIFT 0x0 2732#define DAGB0_RESERVE68__RESERVE_MASK 0xFFFFFFFFL 2733//DAGB0_RESERVE69 2734#define DAGB0_RESERVE69__RESERVE__SHIFT 0x0 2735#define DAGB0_RESERVE69__RESERVE_MASK 0xFFFFFFFFL 2736//DAGB0_RESERVE70 2737#define DAGB0_RESERVE70__RESERVE__SHIFT 0x0 2738#define DAGB0_RESERVE70__RESERVE_MASK 0xFFFFFFFFL 2739//DAGB0_RESERVE71 2740#define DAGB0_RESERVE71__RESERVE__SHIFT 0x0 2741#define DAGB0_RESERVE71__RESERVE_MASK 0xFFFFFFFFL 2742//DAGB0_RESERVE72 2743#define DAGB0_RESERVE72__RESERVE__SHIFT 0x0 2744#define DAGB0_RESERVE72__RESERVE_MASK 0xFFFFFFFFL 2745//DAGB0_RESERVE73 2746#define DAGB0_RESERVE73__RESERVE__SHIFT 0x0 2747#define DAGB0_RESERVE73__RESERVE_MASK 0xFFFFFFFFL 2748//DAGB0_RESERVE74 2749#define DAGB0_RESERVE74__RESERVE__SHIFT 0x0 2750#define DAGB0_RESERVE74__RESERVE_MASK 0xFFFFFFFFL 2751//DAGB0_RESERVE75 2752#define DAGB0_RESERVE75__RESERVE__SHIFT 0x0 2753#define DAGB0_RESERVE75__RESERVE_MASK 0xFFFFFFFFL 2754//DAGB0_RESERVE76 2755#define DAGB0_RESERVE76__RESERVE__SHIFT 0x0 2756#define DAGB0_RESERVE76__RESERVE_MASK 0xFFFFFFFFL 2757//DAGB0_RESERVE77 2758#define DAGB0_RESERVE77__RESERVE__SHIFT 0x0 2759#define DAGB0_RESERVE77__RESERVE_MASK 0xFFFFFFFFL 2760//DAGB0_RESERVE78 2761#define DAGB0_RESERVE78__RESERVE__SHIFT 0x0 2762#define DAGB0_RESERVE78__RESERVE_MASK 0xFFFFFFFFL 2763//DAGB0_RESERVE79 2764#define DAGB0_RESERVE79__RESERVE__SHIFT 0x0 2765#define DAGB0_RESERVE79__RESERVE_MASK 0xFFFFFFFFL 2766//DAGB0_RESERVE80 2767#define DAGB0_RESERVE80__RESERVE__SHIFT 0x0 2768#define DAGB0_RESERVE80__RESERVE_MASK 0xFFFFFFFFL 2769//DAGB0_RESERVE81 2770#define DAGB0_RESERVE81__RESERVE__SHIFT 0x0 2771#define DAGB0_RESERVE81__RESERVE_MASK 0xFFFFFFFFL 2772//DAGB0_RESERVE82 2773#define DAGB0_RESERVE82__RESERVE__SHIFT 0x0 2774#define DAGB0_RESERVE82__RESERVE_MASK 0xFFFFFFFFL 2775//DAGB0_RESERVE83 2776#define DAGB0_RESERVE83__RESERVE__SHIFT 0x0 2777#define DAGB0_RESERVE83__RESERVE_MASK 0xFFFFFFFFL 2778//DAGB0_RESERVE84 2779#define DAGB0_RESERVE84__RESERVE__SHIFT 0x0 2780#define DAGB0_RESERVE84__RESERVE_MASK 0xFFFFFFFFL 2781//DAGB0_RESERVE85 2782#define DAGB0_RESERVE85__RESERVE__SHIFT 0x0 2783#define DAGB0_RESERVE85__RESERVE_MASK 0xFFFFFFFFL 2784//DAGB0_RESERVE86 2785#define DAGB0_RESERVE86__RESERVE__SHIFT 0x0 2786#define DAGB0_RESERVE86__RESERVE_MASK 0xFFFFFFFFL 2787//DAGB0_RESERVE87 2788#define DAGB0_RESERVE87__RESERVE__SHIFT 0x0 2789#define DAGB0_RESERVE87__RESERVE_MASK 0xFFFFFFFFL 2790//DAGB0_RESERVE88 2791#define DAGB0_RESERVE88__RESERVE__SHIFT 0x0 2792#define DAGB0_RESERVE88__RESERVE_MASK 0xFFFFFFFFL 2793//DAGB0_RESERVE89 2794#define DAGB0_RESERVE89__RESERVE__SHIFT 0x0 2795#define DAGB0_RESERVE89__RESERVE_MASK 0xFFFFFFFFL 2796//DAGB0_RESERVE90 2797#define DAGB0_RESERVE90__RESERVE__SHIFT 0x0 2798#define DAGB0_RESERVE90__RESERVE_MASK 0xFFFFFFFFL 2799//DAGB0_RESERVE91 2800#define DAGB0_RESERVE91__RESERVE__SHIFT 0x0 2801#define DAGB0_RESERVE91__RESERVE_MASK 0xFFFFFFFFL 2802//DAGB0_RESERVE92 2803#define DAGB0_RESERVE92__RESERVE__SHIFT 0x0 2804#define DAGB0_RESERVE92__RESERVE_MASK 0xFFFFFFFFL 2805//DAGB0_RESERVE93 2806#define DAGB0_RESERVE93__RESERVE__SHIFT 0x0 2807#define DAGB0_RESERVE93__RESERVE_MASK 0xFFFFFFFFL 2808//DAGB0_RESERVE94 2809#define DAGB0_RESERVE94__RESERVE__SHIFT 0x0 2810#define DAGB0_RESERVE94__RESERVE_MASK 0xFFFFFFFFL 2811//DAGB0_RESERVE95 2812#define DAGB0_RESERVE95__RESERVE__SHIFT 0x0 2813#define DAGB0_RESERVE95__RESERVE_MASK 0xFFFFFFFFL 2814//DAGB0_RESERVE96 2815#define DAGB0_RESERVE96__RESERVE__SHIFT 0x0 2816#define DAGB0_RESERVE96__RESERVE_MASK 0xFFFFFFFFL 2817//DAGB0_RESERVE97 2818#define DAGB0_RESERVE97__RESERVE__SHIFT 0x0 2819#define DAGB0_RESERVE97__RESERVE_MASK 0xFFFFFFFFL 2820//DAGB0_RESERVE98 2821#define DAGB0_RESERVE98__RESERVE__SHIFT 0x0 2822#define DAGB0_RESERVE98__RESERVE_MASK 0xFFFFFFFFL 2823//DAGB0_RESERVE99 2824#define DAGB0_RESERVE99__RESERVE__SHIFT 0x0 2825#define DAGB0_RESERVE99__RESERVE_MASK 0xFFFFFFFFL 2826//DAGB0_RESERVE100 2827#define DAGB0_RESERVE100__RESERVE__SHIFT 0x0 2828#define DAGB0_RESERVE100__RESERVE_MASK 0xFFFFFFFFL 2829//DAGB0_RESERVE101 2830#define DAGB0_RESERVE101__RESERVE__SHIFT 0x0 2831#define DAGB0_RESERVE101__RESERVE_MASK 0xFFFFFFFFL 2832 2833 2834// addressBlock: mmhub_ea_mmeadec 2835//MMEA0_DRAM_RD_CLI2GRP_MAP0 2836#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 2837#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 2838#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 2839#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 2840#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 2841#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 2842#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 2843#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 2844#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 2845#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 2846#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 2847#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 2848#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 2849#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 2850#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 2851#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 2852#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 2853#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 2854#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 2855#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 2856#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 2857#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 2858#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 2859#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 2860#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 2861#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 2862#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 2863#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 2864#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 2865#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 2866#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 2867#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 2868//MMEA0_DRAM_RD_CLI2GRP_MAP1 2869#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 2870#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 2871#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 2872#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 2873#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 2874#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 2875#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 2876#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 2877#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 2878#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 2879#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 2880#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 2881#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 2882#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 2883#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 2884#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 2885#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 2886#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 2887#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 2888#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 2889#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 2890#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 2891#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 2892#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 2893#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 2894#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 2895#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 2896#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 2897#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 2898#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 2899#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 2900#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 2901//MMEA0_DRAM_WR_CLI2GRP_MAP0 2902#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 2903#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 2904#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 2905#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 2906#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 2907#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 2908#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 2909#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 2910#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 2911#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 2912#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 2913#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 2914#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 2915#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 2916#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 2917#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 2918#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 2919#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 2920#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 2921#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 2922#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 2923#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 2924#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 2925#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 2926#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 2927#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 2928#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 2929#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 2930#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 2931#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 2932#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 2933#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 2934//MMEA0_DRAM_WR_CLI2GRP_MAP1 2935#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 2936#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 2937#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 2938#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 2939#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 2940#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 2941#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 2942#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 2943#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 2944#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 2945#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 2946#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 2947#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 2948#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 2949#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 2950#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 2951#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 2952#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 2953#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 2954#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 2955#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 2956#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 2957#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 2958#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 2959#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 2960#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 2961#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 2962#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 2963#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 2964#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 2965#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 2966#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 2967//MMEA0_DRAM_RD_GRP2VC_MAP 2968#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 2969#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 2970#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 2971#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 2972#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 2973#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 2974#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 2975#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 2976//MMEA0_DRAM_WR_GRP2VC_MAP 2977#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 2978#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 2979#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 2980#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 2981#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 2982#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 2983#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 2984#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 2985//MMEA0_DRAM_RD_LAZY 2986#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 2987#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 2988#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 2989#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 2990#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 2991#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 2992#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 2993#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 2994//MMEA0_DRAM_WR_LAZY 2995#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 2996#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 2997#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 2998#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 2999#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 3000#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 3001#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 3002#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 3003//MMEA0_DRAM_RD_CAM_CNTL 3004#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 3005#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 3006#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 3007#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 3008#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 3009#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 3010#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 3011#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 3012#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 3013#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 3014#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 3015#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 3016#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 3017#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 3018#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 3019#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 3020//MMEA0_DRAM_WR_CAM_CNTL 3021#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 3022#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 3023#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 3024#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 3025#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 3026#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 3027#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 3028#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 3029#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 3030#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 3031#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 3032#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 3033#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 3034#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 3035#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 3036#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 3037//MMEA0_DRAM_PAGE_BURST 3038#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 3039#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 3040#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 3041#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 3042#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 3043#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 3044#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 3045#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 3046//MMEA0_DRAM_RD_PRI_AGE 3047#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3048#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3049#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3050#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3051#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3052#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3053#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3054#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3055#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3056#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3057#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3058#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3059#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3060#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3061#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3062#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3063//MMEA0_DRAM_WR_PRI_AGE 3064#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3065#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3066#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3067#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3068#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3069#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3070#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3071#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3072#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3073#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3074#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3075#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3076#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3077#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3078#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3079#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3080//MMEA0_DRAM_RD_PRI_QUEUING 3081#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3082#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3083#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3084#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3085#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3086#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3087#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3088#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3089//MMEA0_DRAM_WR_PRI_QUEUING 3090#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3091#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3092#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3093#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3094#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3095#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3096#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3097#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3098//MMEA0_DRAM_RD_PRI_FIXED 3099#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3100#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3101#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3102#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3103#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3104#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3105#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3106#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3107//MMEA0_DRAM_WR_PRI_FIXED 3108#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3109#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3110#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3111#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3112#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3113#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3114#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3115#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3116//MMEA0_DRAM_RD_PRI_URGENCY 3117#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3118#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3119#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3120#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3121#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3122#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3123#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3124#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3125#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3126#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3127#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3128#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3129#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3130#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3131#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3132#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3133//MMEA0_DRAM_WR_PRI_URGENCY 3134#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3135#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3136#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3137#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3138#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3139#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3140#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3141#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3142#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3143#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3144#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3145#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3146#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3147#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3148#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3149#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3150//MMEA0_DRAM_RD_PRI_QUANT_PRI1 3151#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3152#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3153#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3154#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3155#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3156#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3157#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3158#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3159//MMEA0_DRAM_RD_PRI_QUANT_PRI2 3160#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3161#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3162#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3163#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3164#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3165#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3166#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3167#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3168//MMEA0_DRAM_RD_PRI_QUANT_PRI3 3169#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3170#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3171#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3172#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3173#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3174#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3175#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3176#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3177//MMEA0_DRAM_WR_PRI_QUANT_PRI1 3178#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3179#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3180#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3181#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3182#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3183#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3184#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3185#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3186//MMEA0_DRAM_WR_PRI_QUANT_PRI2 3187#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3188#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3189#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3190#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3191#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3192#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3193#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3194#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3195//MMEA0_DRAM_WR_PRI_QUANT_PRI3 3196#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3197#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3198#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3199#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3200#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3201#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3202#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3203#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3204//MMEA0_ADDRNORM_BASE_ADDR0 3205#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 3206#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 3207#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 3208#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 3209#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 3210#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 3211#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 3212#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L 3213#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L 3214#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 3215//MMEA0_ADDRNORM_LIMIT_ADDR0 3216#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 3217#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 3218#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa 3219#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 3220#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL 3221#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 3222#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L 3223#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 3224//MMEA0_ADDRNORM_BASE_ADDR1 3225#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 3226#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 3227#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 3228#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 3229#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 3230#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 3231#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 3232#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L 3233#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L 3234#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 3235//MMEA0_ADDRNORM_LIMIT_ADDR1 3236#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 3237#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 3238#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa 3239#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 3240#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL 3241#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 3242#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L 3243#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 3244//MMEA0_ADDRNORM_OFFSET_ADDR1 3245#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 3246#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 3247#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 3248#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 3249//MMEA0_ADDRNORM_HOLE_CNTL 3250#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 3251#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 3252#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 3253#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 3254//MMEA0_ADDRDEC_BANK_CFG 3255#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 3256#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 3257#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 3258#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 3259#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 3260#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 3261#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 3262#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 3263#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 3264#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 3265#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 3266#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 3267//MMEA0_ADDRDEC_MISC_CFG 3268#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 3269#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 3270#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 3271#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 3272#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 3273#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 3274#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 3275#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 3276#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 3277#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 3278#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 3279#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 3280#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b 3281#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 3282#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 3283#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 3284#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 3285#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 3286#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 3287#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 3288#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L 3289#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L 3290#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L 3291#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L 3292#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L 3293#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L 3294//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 3295#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 3296#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 3297#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 3298#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 3299#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 3300#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 3301//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 3302#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 3303#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 3304#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 3305#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 3306#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 3307#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 3308//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 3309#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 3310#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 3311#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 3312#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 3313#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 3314#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 3315//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 3316#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 3317#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 3318#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 3319#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 3320#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 3321#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 3322//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 3323#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 3324#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 3325#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 3326#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 3327#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 3328#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 3329//MMEA0_ADDRDECDRAM_ADDR_HASH_PC 3330#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 3331#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 3332#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 3333#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 3334#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 3335#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 3336//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 3337#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 3338#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 3339//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 3340#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 3341#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 3342#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 3343#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 3344//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 3345#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 3346#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 3347#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 3348#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 3349//MMEA0_ADDRDECDRAM_HARVEST_ENABLE 3350#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 3351#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 3352#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 3353#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 3354#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 3355#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 3356#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 3357#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 3358//MMEA0_ADDRDEC0_BASE_ADDR_CS0 3359#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 3360#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 3361#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 3362#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 3363//MMEA0_ADDRDEC0_BASE_ADDR_CS1 3364#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 3365#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 3366#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 3367#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 3368//MMEA0_ADDRDEC0_BASE_ADDR_CS2 3369#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 3370#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 3371#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 3372#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 3373//MMEA0_ADDRDEC0_BASE_ADDR_CS3 3374#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 3375#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 3376#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 3377#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 3378//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 3379#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 3380#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 3381#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 3382#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 3383//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 3384#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 3385#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 3386#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 3387#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 3388//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 3389#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 3390#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 3391#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 3392#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 3393//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 3394#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 3395#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 3396#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 3397#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 3398//MMEA0_ADDRDEC0_ADDR_MASK_CS01 3399#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 3400#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 3401//MMEA0_ADDRDEC0_ADDR_MASK_CS23 3402#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 3403#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 3404//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 3405#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 3406#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 3407//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 3408#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 3409#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 3410//MMEA0_ADDRDEC0_ADDR_CFG_CS01 3411#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 3412#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 3413#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 3414#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 3415#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 3416#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 3417#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 3418#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 3419#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 3420#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 3421#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 3422#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 3423//MMEA0_ADDRDEC0_ADDR_CFG_CS23 3424#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 3425#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 3426#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 3427#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 3428#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 3429#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 3430#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 3431#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 3432#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 3433#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 3434#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 3435#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 3436//MMEA0_ADDRDEC0_ADDR_SEL_CS01 3437#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 3438#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 3439#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 3440#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 3441#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 3442#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 3443#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 3444#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 3445#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 3446#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 3447#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 3448#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 3449#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 3450#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 3451//MMEA0_ADDRDEC0_ADDR_SEL_CS23 3452#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 3453#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 3454#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 3455#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 3456#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 3457#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 3458#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 3459#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 3460#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 3461#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 3462#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 3463#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 3464#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 3465#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 3466//MMEA0_ADDRDEC0_COL_SEL_LO_CS01 3467#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 3468#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 3469#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 3470#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 3471#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 3472#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 3473#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 3474#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 3475#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 3476#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 3477#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 3478#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 3479#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 3480#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 3481#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 3482#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 3483//MMEA0_ADDRDEC0_COL_SEL_LO_CS23 3484#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 3485#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 3486#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 3487#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 3488#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 3489#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 3490#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 3491#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 3492#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 3493#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 3494#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 3495#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 3496#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 3497#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 3498#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 3499#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 3500//MMEA0_ADDRDEC0_COL_SEL_HI_CS01 3501#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 3502#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 3503#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 3504#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 3505#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 3506#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 3507#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 3508#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 3509#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 3510#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 3511#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 3512#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 3513#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 3514#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 3515#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 3516#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 3517//MMEA0_ADDRDEC0_COL_SEL_HI_CS23 3518#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 3519#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 3520#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 3521#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 3522#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 3523#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 3524#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 3525#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 3526#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 3527#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 3528#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 3529#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 3530#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 3531#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 3532#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 3533#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 3534//MMEA0_ADDRDEC0_RM_SEL_CS01 3535#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 3536#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 3537#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 3538#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 3539#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3540#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3541#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 3542#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 3543#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 3544#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 3545#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3546#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3547//MMEA0_ADDRDEC0_RM_SEL_CS23 3548#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 3549#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 3550#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 3551#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 3552#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3553#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3554#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 3555#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 3556#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 3557#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 3558#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3559#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3560//MMEA0_ADDRDEC0_RM_SEL_SECCS01 3561#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 3562#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 3563#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 3564#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 3565#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3566#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3567#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 3568#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 3569#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 3570#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 3571#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3572#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3573//MMEA0_ADDRDEC0_RM_SEL_SECCS23 3574#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 3575#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 3576#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 3577#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 3578#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3579#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3580#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 3581#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 3582#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 3583#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 3584#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3585#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3586//MMEA0_ADDRDEC1_BASE_ADDR_CS0 3587#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 3588#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 3589#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 3590#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 3591//MMEA0_ADDRDEC1_BASE_ADDR_CS1 3592#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 3593#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 3594#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 3595#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 3596//MMEA0_ADDRDEC1_BASE_ADDR_CS2 3597#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 3598#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 3599#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 3600#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 3601//MMEA0_ADDRDEC1_BASE_ADDR_CS3 3602#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 3603#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 3604#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 3605#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 3606//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 3607#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 3608#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 3609#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 3610#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 3611//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 3612#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 3613#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 3614#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 3615#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 3616//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 3617#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 3618#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 3619#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 3620#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 3621//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 3622#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 3623#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 3624#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 3625#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 3626//MMEA0_ADDRDEC1_ADDR_MASK_CS01 3627#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 3628#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 3629//MMEA0_ADDRDEC1_ADDR_MASK_CS23 3630#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 3631#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 3632//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 3633#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 3634#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 3635//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 3636#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 3637#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 3638//MMEA0_ADDRDEC1_ADDR_CFG_CS01 3639#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 3640#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 3641#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 3642#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 3643#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 3644#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 3645#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 3646#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 3647#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 3648#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 3649#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 3650#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 3651//MMEA0_ADDRDEC1_ADDR_CFG_CS23 3652#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 3653#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 3654#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 3655#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 3656#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 3657#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 3658#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 3659#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 3660#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 3661#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 3662#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 3663#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 3664//MMEA0_ADDRDEC1_ADDR_SEL_CS01 3665#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 3666#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 3667#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 3668#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 3669#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 3670#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 3671#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 3672#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 3673#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 3674#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 3675#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 3676#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 3677#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 3678#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 3679//MMEA0_ADDRDEC1_ADDR_SEL_CS23 3680#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 3681#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 3682#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 3683#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 3684#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 3685#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 3686#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 3687#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 3688#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 3689#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 3690#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 3691#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 3692#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 3693#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 3694//MMEA0_ADDRDEC1_COL_SEL_LO_CS01 3695#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 3696#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 3697#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 3698#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 3699#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 3700#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 3701#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 3702#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 3703#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 3704#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 3705#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 3706#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 3707#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 3708#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 3709#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 3710#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 3711//MMEA0_ADDRDEC1_COL_SEL_LO_CS23 3712#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 3713#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 3714#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 3715#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 3716#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 3717#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 3718#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 3719#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 3720#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 3721#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 3722#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 3723#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 3724#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 3725#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 3726#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 3727#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 3728//MMEA0_ADDRDEC1_COL_SEL_HI_CS01 3729#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 3730#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 3731#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 3732#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 3733#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 3734#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 3735#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 3736#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 3737#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 3738#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 3739#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 3740#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 3741#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 3742#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 3743#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 3744#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 3745//MMEA0_ADDRDEC1_COL_SEL_HI_CS23 3746#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 3747#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 3748#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 3749#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 3750#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 3751#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 3752#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 3753#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 3754#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 3755#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 3756#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 3757#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 3758#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 3759#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 3760#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 3761#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 3762//MMEA0_ADDRDEC1_RM_SEL_CS01 3763#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 3764#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 3765#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 3766#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 3767#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3768#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3769#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 3770#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 3771#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 3772#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 3773#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3774#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3775//MMEA0_ADDRDEC1_RM_SEL_CS23 3776#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 3777#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 3778#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 3779#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 3780#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3781#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3782#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 3783#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 3784#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 3785#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 3786#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3787#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3788//MMEA0_ADDRDEC1_RM_SEL_SECCS01 3789#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 3790#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 3791#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 3792#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 3793#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3794#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3795#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 3796#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 3797#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 3798#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 3799#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3800#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3801//MMEA0_ADDRDEC1_RM_SEL_SECCS23 3802#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 3803#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 3804#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 3805#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 3806#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 3807#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 3808#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 3809#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 3810#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 3811#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 3812#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 3813#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 3814//MMEA0_IO_RD_CLI2GRP_MAP0 3815#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3816#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3817#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3818#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3819#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3820#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3821#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3822#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3823#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3824#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3825#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3826#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3827#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3828#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3829#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3830#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3831#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3832#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3833#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3834#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3835#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3836#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3837#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3838#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3839#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3840#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3841#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3842#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3843#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3844#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3845#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3846#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3847//MMEA0_IO_RD_CLI2GRP_MAP1 3848#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3849#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3850#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3851#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3852#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3853#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3854#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3855#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3856#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3857#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3858#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3859#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3860#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3861#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3862#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3863#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3864#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3865#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3866#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3867#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3868#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3869#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3870#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3871#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3872#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3873#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3874#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3875#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3876#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3877#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3878#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3879#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3880//MMEA0_IO_WR_CLI2GRP_MAP0 3881#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3882#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3883#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3884#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3885#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3886#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3887#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3888#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3889#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3890#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3891#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3892#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3893#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3894#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3895#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3896#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3897#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3898#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3899#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3900#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3901#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3902#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3903#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3904#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3905#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3906#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3907#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3908#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3909#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3910#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3911#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3912#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3913//MMEA0_IO_WR_CLI2GRP_MAP1 3914#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3915#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3916#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3917#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3918#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3919#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3920#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3921#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3922#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3923#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3924#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3925#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3926#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3927#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3928#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3929#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3930#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3931#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3932#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3933#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3934#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3935#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3936#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3937#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3938#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3939#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3940#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3941#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3942#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3943#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3944#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3945#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3946//MMEA0_IO_RD_COMBINE_FLUSH 3947#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 3948#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 3949#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 3950#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 3951#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 3952#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 3953#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 3954#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 3955//MMEA0_IO_WR_COMBINE_FLUSH 3956#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 3957#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 3958#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 3959#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 3960#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 3961#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 3962#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 3963#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 3964//MMEA0_IO_GROUP_BURST 3965#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 3966#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 3967#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 3968#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 3969#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 3970#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 3971#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 3972#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 3973//MMEA0_IO_RD_PRI_AGE 3974#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3975#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3976#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3977#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3978#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3979#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3980#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3981#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3982#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3983#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3984#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3985#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3986#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3987#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3988#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3989#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3990//MMEA0_IO_WR_PRI_AGE 3991#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3992#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3993#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3994#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3995#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3996#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3997#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3998#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3999#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 4000#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 4001#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 4002#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 4003#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 4004#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 4005#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 4006#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 4007//MMEA0_IO_RD_PRI_QUEUING 4008#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 4009#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 4010#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 4011#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 4012#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 4013#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 4014#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 4015#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 4016//MMEA0_IO_WR_PRI_QUEUING 4017#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 4018#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 4019#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 4020#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 4021#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 4022#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 4023#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 4024#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 4025//MMEA0_IO_RD_PRI_FIXED 4026#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 4027#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 4028#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 4029#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 4030#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 4031#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 4032#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 4033#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 4034//MMEA0_IO_WR_PRI_FIXED 4035#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 4036#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 4037#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 4038#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 4039#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 4040#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 4041#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 4042#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 4043//MMEA0_IO_RD_PRI_URGENCY 4044#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 4045#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 4046#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 4047#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 4048#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 4049#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 4050#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 4051#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 4052#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 4053#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 4054#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 4055#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 4056#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 4057#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 4058#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 4059#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 4060//MMEA0_IO_WR_PRI_URGENCY 4061#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 4062#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 4063#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 4064#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 4065#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 4066#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 4067#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 4068#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 4069#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 4070#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 4071#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 4072#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 4073#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 4074#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 4075#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 4076#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 4077//MMEA0_IO_RD_PRI_URGENCY_MASK 4078#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 4079#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 4080#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 4081#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 4082#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 4083#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 4084#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 4085#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 4086#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 4087#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 4088#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 4089#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 4090#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 4091#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 4092#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 4093#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 4094#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 4095#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 4096#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 4097#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 4098#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 4099#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 4100#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 4101#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 4102#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 4103#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 4104#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 4105#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 4106#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 4107#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 4108#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 4109#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 4110#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 4111#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 4112#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 4113#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 4114#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 4115#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 4116#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 4117#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 4118#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 4119#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 4120#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 4121#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 4122#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 4123#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 4124#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 4125#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 4126#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 4127#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 4128#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 4129#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 4130#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 4131#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 4132#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 4133#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 4134#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 4135#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 4136#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 4137#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 4138#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 4139#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 4140#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 4141#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 4142//MMEA0_IO_WR_PRI_URGENCY_MASK 4143#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 4144#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 4145#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 4146#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 4147#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 4148#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 4149#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 4150#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 4151#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 4152#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 4153#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 4154#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 4155#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 4156#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 4157#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 4158#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 4159#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 4160#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 4161#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 4162#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 4163#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 4164#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 4165#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 4166#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 4167#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 4168#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 4169#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 4170#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 4171#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 4172#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 4173#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 4174#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 4175#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 4176#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 4177#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 4178#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 4179#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 4180#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 4181#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 4182#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 4183#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 4184#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 4185#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 4186#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 4187#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 4188#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 4189#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 4190#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 4191#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 4192#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 4193#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 4194#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 4195#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 4196#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 4197#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 4198#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 4199#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 4200#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 4201#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 4202#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 4203#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 4204#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 4205#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 4206#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 4207//MMEA0_IO_RD_PRI_QUANT_PRI1 4208#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 4209#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 4210#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 4211#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 4212#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 4213#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 4214#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 4215#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 4216//MMEA0_IO_RD_PRI_QUANT_PRI2 4217#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 4218#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 4219#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 4220#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 4221#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 4222#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 4223#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 4224#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 4225//MMEA0_IO_RD_PRI_QUANT_PRI3 4226#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 4227#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 4228#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 4229#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 4230#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 4231#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 4232#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 4233#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 4234//MMEA0_IO_WR_PRI_QUANT_PRI1 4235#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 4236#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 4237#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 4238#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 4239#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 4240#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 4241#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 4242#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 4243//MMEA0_IO_WR_PRI_QUANT_PRI2 4244#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 4245#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 4246#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 4247#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 4248#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 4249#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 4250#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 4251#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 4252//MMEA0_IO_WR_PRI_QUANT_PRI3 4253#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 4254#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 4255#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 4256#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 4257#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 4258#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 4259#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 4260#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 4261//MMEA0_SDP_ARB_DRAM 4262#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 4263#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 4264#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 4265#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 4266#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 4267#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 4268#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 4269#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 4270#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 4271#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 4272#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 4273#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 4274#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 4275#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 4276//MMEA0_SDP_ARB_FINAL 4277#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 4278#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 4279#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 4280#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 4281#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 4282#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 4283#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 4284#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 4285#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 4286#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 4287#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 4288#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 4289#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 4290#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 4291#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 4292#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 4293#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 4294#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 4295#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 4296#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 4297#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 4298#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 4299#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 4300#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 4301#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 4302#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 4303#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 4304#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 4305//MMEA0_SDP_DRAM_PRIORITY 4306#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 4307#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 4308#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 4309#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 4310#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 4311#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 4312#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 4313#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 4314#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 4315#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 4316#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 4317#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 4318#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 4319#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 4320#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 4321#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 4322//MMEA0_SDP_IO_PRIORITY 4323#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 4324#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 4325#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 4326#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 4327#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 4328#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 4329#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 4330#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 4331#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 4332#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 4333#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 4334#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 4335#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 4336#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 4337#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 4338#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 4339//MMEA0_SDP_CREDITS 4340#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 4341#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 4342#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 4343#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 4344#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 4345#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 4346//MMEA0_SDP_TAG_RESERVE0 4347#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 4348#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 4349#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 4350#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 4351#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 4352#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 4353#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 4354#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 4355//MMEA0_SDP_TAG_RESERVE1 4356#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 4357#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 4358#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 4359#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 4360#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 4361#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 4362#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 4363#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 4364//MMEA0_SDP_VCC_RESERVE0 4365#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 4366#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 4367#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 4368#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 4369#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 4370#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 4371#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 4372#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 4373#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 4374#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 4375//MMEA0_SDP_VCC_RESERVE1 4376#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 4377#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 4378#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 4379#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 4380#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 4381#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 4382#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 4383#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 4384//MMEA0_SDP_VCD_RESERVE0 4385#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 4386#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 4387#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 4388#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 4389#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 4390#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 4391#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 4392#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 4393#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 4394#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 4395//MMEA0_SDP_VCD_RESERVE1 4396#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 4397#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 4398#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 4399#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 4400#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 4401#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 4402#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 4403#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 4404//MMEA0_SDP_REQ_CNTL 4405#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 4406#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 4407#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 4408#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 4409#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 4410#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 4411#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 4412#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 4413#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 4414#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 4415//MMEA0_MISC 4416#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 4417#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 4418#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 4419#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 4420#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 4421#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 4422#define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6 4423#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 4424#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 4425#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa 4426#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc 4427#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe 4428#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 4429#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 4430#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 4431#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 4432#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 4433#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 4434#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 4435#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 4436#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 4437#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 4438#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 4439#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 4440#define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L 4441#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L 4442#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L 4443#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L 4444#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L 4445#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L 4446#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L 4447#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L 4448#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L 4449#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L 4450#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L 4451#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L 4452//MMEA0_LATENCY_SAMPLING 4453#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 4454#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 4455#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 4456#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 4457#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 4458#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 4459#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 4460#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 4461#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 4462#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 4463#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 4464#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 4465#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 4466#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 4467#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 4468#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 4469#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 4470#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 4471#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 4472#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 4473#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 4474#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 4475#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 4476#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 4477#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 4478#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 4479#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 4480#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 4481#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 4482#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 4483#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 4484#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 4485//MMEA0_PERFCOUNTER_LO 4486#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 4487#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 4488//MMEA0_PERFCOUNTER_HI 4489#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 4490#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 4491#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 4492#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 4493//MMEA0_PERFCOUNTER0_CFG 4494#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 4495#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 4496#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 4497#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 4498#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 4499#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 4500#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 4501#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 4502#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 4503#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 4504//MMEA0_PERFCOUNTER1_CFG 4505#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 4506#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 4507#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 4508#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 4509#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 4510#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 4511#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 4512#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 4513#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 4514#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 4515//MMEA0_PERFCOUNTER_RSLT_CNTL 4516#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 4517#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 4518#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 4519#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 4520#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 4521#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 4522#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 4523#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 4524#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 4525#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 4526#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 4527#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 4528//MMEA0_EDC_CNT 4529#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 4530#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 4531#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 4532#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 4533#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 4534#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 4535#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 4536#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 4537#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 4538#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 4539#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 4540#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 4541#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 4542#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 4543#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 4544#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 4545#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 4546#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 4547#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 4548#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 4549#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 4550#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 4551#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 4552#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 4553#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 4554#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 4555#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 4556#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 4557#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 4558#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 4559//MMEA0_EDC_CNT2 4560#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 4561#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 4562#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 4563#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 4564#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 4565#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 4566#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 4567#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 4568#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 4569#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 4570#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 4571#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 4572#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 4573#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 4574#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 4575#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 4576//MMEA0_DSM_CNTL 4577#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 4578#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4579#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 4580#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 4581#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 4582#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4583#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 4584#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4585#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 4586#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 4587#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 4588#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 4589#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 4590#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 4591#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 4592#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 4593#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 4594#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4595#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 4596#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4597#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4598#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4599#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 4600#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4601#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 4602#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 4603#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 4604#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 4605#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 4606#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 4607#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 4608#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 4609//MMEA0_DSM_CNTLA 4610#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 4611#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 4612#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 4613#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 4614#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 4615#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 4616#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 4617#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 4618#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 4619#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 4620#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 4621#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 4622#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 4623#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 4624#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 4625#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 4626#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 4627#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 4628#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 4629#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 4630#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 4631#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 4632#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 4633#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 4634#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 4635#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 4636#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 4637#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 4638//MMEA0_DSM_CNTLB 4639//MMEA0_DSM_CNTL2 4640#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4641#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 4642#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 4643#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 4644#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 4645#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 4646#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 4647#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 4648#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 4649#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 4650#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 4651#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 4652#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 4653#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 4654#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 4655#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 4656#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 4657#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4658#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4659#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 4660#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 4661#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4662#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 4663#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4664#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 4665#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 4666#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 4667#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 4668#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 4669#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 4670#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 4671#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 4672#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 4673#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 4674//MMEA0_DSM_CNTL2A 4675#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 4676#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 4677#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 4678#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 4679#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 4680#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 4681#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 4682#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 4683#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 4684#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 4685#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 4686#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 4687#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 4688#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 4689#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 4690#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 4691#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 4692#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 4693#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 4694#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 4695#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 4696#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 4697#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 4698#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 4699#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 4700#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 4701#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 4702#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 4703//MMEA0_DSM_CNTL2B 4704//MMEA0_CGTT_CLK_CTRL 4705#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4706#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4707#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4708#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4709#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 4710#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 4711#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 4712#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 4713#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4714#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4715#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4716#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4717#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 4718#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 4719#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 4720#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 4721//MMEA0_EDC_MODE 4722#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 4723#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 4724#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 4725#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 4726#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 4727#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 4728#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 4729#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 4730#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 4731#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 4732//MMEA0_ERR_STATUS 4733#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 4734#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 4735#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 4736#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 4737#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa 4738#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 4739#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 4740#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L 4741#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L 4742#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L 4743//MMEA0_MISC2 4744#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 4745#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 4746#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 4747#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 4748#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 4749#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 4750#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 4751#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 4752//MMEA1_DRAM_RD_CLI2GRP_MAP0 4753#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 4754#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 4755#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 4756#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 4757#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 4758#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 4759#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 4760#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 4761#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 4762#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 4763#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 4764#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 4765#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 4766#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 4767#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 4768#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 4769#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 4770#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 4771#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 4772#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 4773#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 4774#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 4775#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 4776#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 4777#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 4778#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 4779#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 4780#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 4781#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 4782#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 4783#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 4784#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 4785//MMEA1_DRAM_RD_CLI2GRP_MAP1 4786#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 4787#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 4788#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 4789#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 4790#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 4791#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 4792#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 4793#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 4794#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 4795#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 4796#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 4797#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 4798#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 4799#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 4800#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 4801#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 4802#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 4803#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 4804#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 4805#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 4806#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 4807#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 4808#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 4809#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 4810#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 4811#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 4812#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 4813#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 4814#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 4815#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 4816#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 4817#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 4818//MMEA1_DRAM_WR_CLI2GRP_MAP0 4819#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 4820#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 4821#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 4822#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 4823#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 4824#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 4825#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 4826#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 4827#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 4828#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 4829#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 4830#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 4831#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 4832#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 4833#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 4834#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 4835#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 4836#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 4837#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 4838#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 4839#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 4840#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 4841#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 4842#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 4843#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 4844#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 4845#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 4846#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 4847#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 4848#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 4849#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 4850#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 4851//MMEA1_DRAM_WR_CLI2GRP_MAP1 4852#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 4853#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 4854#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 4855#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 4856#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 4857#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 4858#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 4859#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 4860#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 4861#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 4862#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 4863#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 4864#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 4865#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 4866#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 4867#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 4868#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 4869#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 4870#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 4871#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 4872#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 4873#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 4874#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 4875#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 4876#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 4877#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 4878#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 4879#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 4880#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 4881#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 4882#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 4883#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 4884//MMEA1_DRAM_RD_GRP2VC_MAP 4885#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 4886#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 4887#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 4888#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 4889#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 4890#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 4891#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 4892#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 4893//MMEA1_DRAM_WR_GRP2VC_MAP 4894#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 4895#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 4896#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 4897#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 4898#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 4899#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 4900#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 4901#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 4902//MMEA1_DRAM_RD_LAZY 4903#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 4904#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 4905#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 4906#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 4907#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 4908#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 4909#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 4910#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 4911//MMEA1_DRAM_WR_LAZY 4912#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 4913#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 4914#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 4915#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 4916#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 4917#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 4918#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 4919#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 4920//MMEA1_DRAM_RD_CAM_CNTL 4921#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 4922#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 4923#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 4924#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 4925#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 4926#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 4927#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 4928#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 4929#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 4930#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 4931#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 4932#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 4933#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 4934#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 4935#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 4936#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 4937//MMEA1_DRAM_WR_CAM_CNTL 4938#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 4939#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 4940#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 4941#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 4942#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 4943#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 4944#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 4945#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 4946#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 4947#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 4948#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 4949#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 4950#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 4951#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 4952#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 4953#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 4954//MMEA1_DRAM_PAGE_BURST 4955#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 4956#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 4957#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 4958#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 4959#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 4960#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 4961#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 4962#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 4963//MMEA1_DRAM_RD_PRI_AGE 4964#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 4965#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 4966#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 4967#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 4968#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 4969#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 4970#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 4971#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 4972#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 4973#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 4974#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 4975#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 4976#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 4977#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 4978#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 4979#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 4980//MMEA1_DRAM_WR_PRI_AGE 4981#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 4982#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 4983#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 4984#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 4985#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 4986#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 4987#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 4988#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 4989#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 4990#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 4991#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 4992#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 4993#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 4994#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 4995#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 4996#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 4997//MMEA1_DRAM_RD_PRI_QUEUING 4998#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 4999#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 5000#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 5001#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 5002#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 5003#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 5004#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 5005#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 5006//MMEA1_DRAM_WR_PRI_QUEUING 5007#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 5008#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 5009#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 5010#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 5011#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 5012#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 5013#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 5014#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 5015//MMEA1_DRAM_RD_PRI_FIXED 5016#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 5017#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 5018#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 5019#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 5020#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 5021#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 5022#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 5023#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 5024//MMEA1_DRAM_WR_PRI_FIXED 5025#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 5026#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 5027#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 5028#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 5029#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 5030#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 5031#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 5032#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 5033//MMEA1_DRAM_RD_PRI_URGENCY 5034#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 5035#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 5036#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 5037#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 5038#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 5039#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 5040#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 5041#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 5042#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 5043#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 5044#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 5045#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 5046#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 5047#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 5048#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 5049#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 5050//MMEA1_DRAM_WR_PRI_URGENCY 5051#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 5052#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 5053#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 5054#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 5055#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 5056#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 5057#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 5058#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 5059#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 5060#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 5061#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 5062#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 5063#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 5064#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 5065#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 5066#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 5067//MMEA1_DRAM_RD_PRI_QUANT_PRI1 5068#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 5069#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 5070#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 5071#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 5072#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 5073#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 5074#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 5075#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 5076//MMEA1_DRAM_RD_PRI_QUANT_PRI2 5077#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 5078#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 5079#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 5080#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 5081#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 5082#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 5083#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 5084#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 5085//MMEA1_DRAM_RD_PRI_QUANT_PRI3 5086#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 5087#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 5088#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 5089#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 5090#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 5091#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 5092#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 5093#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 5094//MMEA1_DRAM_WR_PRI_QUANT_PRI1 5095#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 5096#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 5097#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 5098#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 5099#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 5100#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 5101#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 5102#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 5103//MMEA1_DRAM_WR_PRI_QUANT_PRI2 5104#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 5105#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 5106#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 5107#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 5108#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 5109#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 5110#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 5111#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 5112//MMEA1_DRAM_WR_PRI_QUANT_PRI3 5113#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 5114#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 5115#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 5116#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 5117#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 5118#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 5119#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 5120#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 5121//MMEA1_ADDRNORM_BASE_ADDR0 5122#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 5123#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 5124#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 5125#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 5126#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 5127#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 5128#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 5129#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L 5130#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L 5131#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 5132//MMEA1_ADDRNORM_LIMIT_ADDR0 5133#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 5134#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 5135#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa 5136#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 5137#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL 5138#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 5139#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L 5140#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 5141//MMEA1_ADDRNORM_BASE_ADDR1 5142#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 5143#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 5144#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 5145#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 5146#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 5147#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 5148#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 5149#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L 5150#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L 5151#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 5152//MMEA1_ADDRNORM_LIMIT_ADDR1 5153#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 5154#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 5155#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa 5156#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 5157#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL 5158#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 5159#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L 5160#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 5161//MMEA1_ADDRNORM_OFFSET_ADDR1 5162#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 5163#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 5164#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 5165#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 5166//MMEA1_ADDRNORM_HOLE_CNTL 5167#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 5168#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 5169#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 5170#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 5171//MMEA1_ADDRDEC_BANK_CFG 5172#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 5173#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 5174#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 5175#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 5176#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 5177#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 5178#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 5179#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 5180#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 5181#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 5182#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 5183#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 5184//MMEA1_ADDRDEC_MISC_CFG 5185#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 5186#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 5187#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 5188#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 5189#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 5190#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 5191#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 5192#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 5193#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 5194#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 5195#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 5196#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 5197#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b 5198#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 5199#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 5200#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 5201#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 5202#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 5203#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 5204#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 5205#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L 5206#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L 5207#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L 5208#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L 5209#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L 5210#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L 5211//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 5212#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 5213#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 5214#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 5215#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 5216#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 5217#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 5218//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 5219#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 5220#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 5221#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 5222#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 5223#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 5224#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 5225//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 5226#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 5227#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 5228#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 5229#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 5230#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 5231#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 5232//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 5233#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 5234#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 5235#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 5236#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 5237#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 5238#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 5239//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 5240#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 5241#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 5242#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 5243#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 5244#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 5245#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 5246//MMEA1_ADDRDECDRAM_ADDR_HASH_PC 5247#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 5248#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 5249#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 5250#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 5251#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 5252#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 5253//MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 5254#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 5255#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 5256//MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 5257#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 5258#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 5259#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 5260#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 5261//MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 5262#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 5263#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 5264#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 5265#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 5266//MMEA1_ADDRDECDRAM_HARVEST_ENABLE 5267#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 5268#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 5269#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 5270#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 5271#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 5272#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 5273#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 5274#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 5275//MMEA1_ADDRDEC0_BASE_ADDR_CS0 5276#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 5277#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 5278#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 5279#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 5280//MMEA1_ADDRDEC0_BASE_ADDR_CS1 5281#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 5282#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 5283#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 5284#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 5285//MMEA1_ADDRDEC0_BASE_ADDR_CS2 5286#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 5287#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 5288#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 5289#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 5290//MMEA1_ADDRDEC0_BASE_ADDR_CS3 5291#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 5292#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 5293#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 5294#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 5295//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 5296#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 5297#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 5298#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 5299#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 5300//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 5301#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 5302#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 5303#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 5304#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 5305//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 5306#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 5307#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 5308#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 5309#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 5310//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 5311#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 5312#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 5313#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 5314#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 5315//MMEA1_ADDRDEC0_ADDR_MASK_CS01 5316#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 5317#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 5318//MMEA1_ADDRDEC0_ADDR_MASK_CS23 5319#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 5320#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 5321//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 5322#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 5323#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 5324//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 5325#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 5326#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 5327//MMEA1_ADDRDEC0_ADDR_CFG_CS01 5328#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 5329#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 5330#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 5331#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 5332#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 5333#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 5334#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 5335#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 5336#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 5337#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 5338#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 5339#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 5340//MMEA1_ADDRDEC0_ADDR_CFG_CS23 5341#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 5342#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 5343#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 5344#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 5345#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 5346#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 5347#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 5348#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 5349#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 5350#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 5351#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 5352#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 5353//MMEA1_ADDRDEC0_ADDR_SEL_CS01 5354#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 5355#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 5356#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 5357#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 5358#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 5359#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 5360#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 5361#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 5362#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 5363#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 5364#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 5365#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 5366#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 5367#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 5368//MMEA1_ADDRDEC0_ADDR_SEL_CS23 5369#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 5370#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 5371#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 5372#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 5373#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 5374#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 5375#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 5376#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 5377#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 5378#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 5379#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 5380#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 5381#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 5382#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 5383//MMEA1_ADDRDEC0_COL_SEL_LO_CS01 5384#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 5385#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 5386#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 5387#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 5388#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 5389#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 5390#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 5391#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 5392#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 5393#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 5394#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 5395#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 5396#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 5397#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 5398#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 5399#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 5400//MMEA1_ADDRDEC0_COL_SEL_LO_CS23 5401#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 5402#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 5403#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 5404#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 5405#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 5406#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 5407#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 5408#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 5409#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 5410#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 5411#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 5412#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 5413#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 5414#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 5415#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 5416#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 5417//MMEA1_ADDRDEC0_COL_SEL_HI_CS01 5418#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 5419#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 5420#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 5421#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 5422#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 5423#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 5424#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 5425#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 5426#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 5427#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 5428#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 5429#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 5430#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 5431#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 5432#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 5433#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 5434//MMEA1_ADDRDEC0_COL_SEL_HI_CS23 5435#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 5436#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 5437#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 5438#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 5439#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 5440#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 5441#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 5442#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 5443#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 5444#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 5445#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 5446#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 5447#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 5448#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 5449#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 5450#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 5451//MMEA1_ADDRDEC0_RM_SEL_CS01 5452#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 5453#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 5454#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 5455#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 5456#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 5457#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 5458#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 5459#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 5460#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 5461#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 5462#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 5463#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 5464//MMEA1_ADDRDEC0_RM_SEL_CS23 5465#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 5466#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 5467#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 5468#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 5469#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 5470#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 5471#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 5472#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 5473#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 5474#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 5475#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 5476#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 5477//MMEA1_ADDRDEC0_RM_SEL_SECCS01 5478#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 5479#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 5480#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 5481#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 5482#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 5483#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 5484#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 5485#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 5486#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 5487#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 5488#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 5489#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 5490//MMEA1_ADDRDEC0_RM_SEL_SECCS23 5491#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 5492#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 5493#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 5494#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 5495#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 5496#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 5497#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 5498#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 5499#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 5500#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 5501#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 5502#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 5503//MMEA1_ADDRDEC1_BASE_ADDR_CS0 5504#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 5505#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 5506#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 5507#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 5508//MMEA1_ADDRDEC1_BASE_ADDR_CS1 5509#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 5510#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 5511#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 5512#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 5513//MMEA1_ADDRDEC1_BASE_ADDR_CS2 5514#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 5515#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 5516#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 5517#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 5518//MMEA1_ADDRDEC1_BASE_ADDR_CS3 5519#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 5520#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 5521#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 5522#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 5523//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 5524#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 5525#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 5526#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 5527#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 5528//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 5529#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 5530#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 5531#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 5532#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 5533//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 5534#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 5535#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 5536#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 5537#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 5538//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 5539#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 5540#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 5541#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 5542#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 5543//MMEA1_ADDRDEC1_ADDR_MASK_CS01 5544#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 5545#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 5546//MMEA1_ADDRDEC1_ADDR_MASK_CS23 5547#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 5548#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 5549//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 5550#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 5551#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 5552//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 5553#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 5554#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 5555//MMEA1_ADDRDEC1_ADDR_CFG_CS01 5556#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 5557#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 5558#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 5559#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 5560#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 5561#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 5562#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 5563#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 5564#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 5565#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 5566#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 5567#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 5568//MMEA1_ADDRDEC1_ADDR_CFG_CS23 5569#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 5570#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 5571#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 5572#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 5573#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 5574#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 5575#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 5576#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 5577#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 5578#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 5579#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 5580#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 5581//MMEA1_ADDRDEC1_ADDR_SEL_CS01 5582#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 5583#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 5584#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 5585#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 5586#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 5587#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 5588#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 5589#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 5590#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 5591#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 5592#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 5593#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 5594#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 5595#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 5596//MMEA1_ADDRDEC1_ADDR_SEL_CS23 5597#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 5598#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 5599#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 5600#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 5601#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 5602#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 5603#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 5604#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 5605#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 5606#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 5607#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 5608#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 5609#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 5610#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 5611//MMEA1_ADDRDEC1_COL_SEL_LO_CS01 5612#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 5613#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 5614#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 5615#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 5616#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 5617#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 5618#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 5619#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 5620#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 5621#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 5622#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 5623#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 5624#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 5625#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 5626#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 5627#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 5628//MMEA1_ADDRDEC1_COL_SEL_LO_CS23 5629#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 5630#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 5631#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 5632#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 5633#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 5634#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 5635#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 5636#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 5637#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 5638#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 5639#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 5640#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 5641#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 5642#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 5643#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 5644#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 5645//MMEA1_ADDRDEC1_COL_SEL_HI_CS01 5646#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 5647#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 5648#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 5649#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 5650#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 5651#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 5652#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 5653#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 5654#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 5655#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 5656#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 5657#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 5658#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 5659#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 5660#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 5661#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 5662//MMEA1_ADDRDEC1_COL_SEL_HI_CS23 5663#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 5664#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 5665#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 5666#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 5667#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 5668#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 5669#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 5670#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 5671#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 5672#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 5673#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 5674#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 5675#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 5676#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 5677#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 5678#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 5679//MMEA1_ADDRDEC1_RM_SEL_CS01 5680#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 5681#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 5682#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 5683#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 5684#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 5685#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 5686#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 5687#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 5688#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 5689#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 5690#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 5691#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 5692//MMEA1_ADDRDEC1_RM_SEL_CS23 5693#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 5694#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 5695#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 5696#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 5697#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 5698#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 5699#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 5700#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 5701#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 5702#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 5703#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 5704#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 5705//MMEA1_ADDRDEC1_RM_SEL_SECCS01 5706#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 5707#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 5708#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 5709#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 5710#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 5711#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 5712#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 5713#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 5714#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 5715#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 5716#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 5717#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 5718//MMEA1_ADDRDEC1_RM_SEL_SECCS23 5719#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 5720#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 5721#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 5722#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 5723#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 5724#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 5725#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 5726#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 5727#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 5728#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 5729#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 5730#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 5731//MMEA1_IO_RD_CLI2GRP_MAP0 5732#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 5733#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 5734#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 5735#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 5736#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 5737#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 5738#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 5739#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 5740#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 5741#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 5742#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 5743#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 5744#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 5745#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 5746#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 5747#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 5748#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 5749#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 5750#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 5751#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 5752#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 5753#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 5754#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 5755#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 5756#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 5757#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 5758#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 5759#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 5760#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 5761#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 5762#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 5763#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 5764//MMEA1_IO_RD_CLI2GRP_MAP1 5765#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 5766#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 5767#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 5768#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 5769#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 5770#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 5771#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 5772#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 5773#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 5774#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 5775#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 5776#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 5777#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 5778#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 5779#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 5780#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 5781#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 5782#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 5783#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 5784#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 5785#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 5786#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 5787#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 5788#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 5789#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 5790#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 5791#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 5792#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 5793#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 5794#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 5795#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 5796#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 5797//MMEA1_IO_WR_CLI2GRP_MAP0 5798#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 5799#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 5800#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 5801#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 5802#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 5803#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 5804#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 5805#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 5806#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 5807#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 5808#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 5809#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 5810#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 5811#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 5812#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 5813#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 5814#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 5815#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 5816#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 5817#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 5818#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 5819#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 5820#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 5821#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 5822#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 5823#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 5824#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 5825#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 5826#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 5827#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 5828#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 5829#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 5830//MMEA1_IO_WR_CLI2GRP_MAP1 5831#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 5832#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 5833#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 5834#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 5835#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 5836#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 5837#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 5838#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 5839#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 5840#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 5841#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 5842#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 5843#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 5844#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 5845#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 5846#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 5847#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 5848#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 5849#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 5850#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 5851#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 5852#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 5853#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 5854#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 5855#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 5856#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 5857#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 5858#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 5859#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 5860#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 5861#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 5862#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 5863//MMEA1_IO_RD_COMBINE_FLUSH 5864#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 5865#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 5866#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 5867#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 5868#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 5869#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 5870#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 5871#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 5872//MMEA1_IO_WR_COMBINE_FLUSH 5873#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 5874#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 5875#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 5876#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 5877#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 5878#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 5879#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 5880#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 5881//MMEA1_IO_GROUP_BURST 5882#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 5883#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 5884#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 5885#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 5886#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 5887#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 5888#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 5889#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 5890//MMEA1_IO_RD_PRI_AGE 5891#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 5892#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 5893#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 5894#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 5895#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 5896#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 5897#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 5898#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 5899#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 5900#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 5901#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 5902#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 5903#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 5904#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 5905#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 5906#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 5907//MMEA1_IO_WR_PRI_AGE 5908#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 5909#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 5910#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 5911#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 5912#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 5913#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 5914#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 5915#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 5916#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 5917#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 5918#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 5919#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 5920#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 5921#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 5922#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 5923#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 5924//MMEA1_IO_RD_PRI_QUEUING 5925#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 5926#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 5927#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 5928#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 5929#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 5930#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 5931#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 5932#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 5933//MMEA1_IO_WR_PRI_QUEUING 5934#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 5935#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 5936#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 5937#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 5938#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 5939#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 5940#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 5941#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 5942//MMEA1_IO_RD_PRI_FIXED 5943#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 5944#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 5945#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 5946#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 5947#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 5948#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 5949#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 5950#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 5951//MMEA1_IO_WR_PRI_FIXED 5952#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 5953#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 5954#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 5955#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 5956#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 5957#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 5958#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 5959#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 5960//MMEA1_IO_RD_PRI_URGENCY 5961#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 5962#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 5963#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 5964#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 5965#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 5966#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 5967#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 5968#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 5969#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 5970#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 5971#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 5972#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 5973#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 5974#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 5975#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 5976#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 5977//MMEA1_IO_WR_PRI_URGENCY 5978#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 5979#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 5980#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 5981#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 5982#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 5983#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 5984#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 5985#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 5986#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 5987#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 5988#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 5989#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 5990#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 5991#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 5992#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 5993#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 5994//MMEA1_IO_RD_PRI_URGENCY_MASK 5995#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 5996#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 5997#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 5998#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 5999#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 6000#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 6001#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 6002#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 6003#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 6004#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 6005#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 6006#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 6007#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 6008#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 6009#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 6010#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 6011#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 6012#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 6013#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 6014#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 6015#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 6016#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 6017#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 6018#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 6019#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 6020#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 6021#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 6022#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 6023#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 6024#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 6025#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 6026#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 6027#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 6028#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 6029#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 6030#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 6031#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 6032#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 6033#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 6034#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 6035#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 6036#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 6037#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 6038#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 6039#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 6040#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 6041#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 6042#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 6043#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 6044#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 6045#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 6046#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 6047#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 6048#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 6049#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 6050#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 6051#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 6052#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 6053#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 6054#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 6055#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 6056#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 6057#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 6058#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 6059//MMEA1_IO_WR_PRI_URGENCY_MASK 6060#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 6061#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 6062#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 6063#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 6064#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 6065#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 6066#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 6067#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 6068#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 6069#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 6070#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 6071#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 6072#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 6073#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 6074#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 6075#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 6076#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 6077#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 6078#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 6079#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 6080#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 6081#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 6082#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 6083#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 6084#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 6085#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 6086#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 6087#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 6088#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 6089#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 6090#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 6091#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 6092#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 6093#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 6094#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 6095#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 6096#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 6097#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 6098#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 6099#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 6100#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 6101#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 6102#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 6103#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 6104#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 6105#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 6106#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 6107#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 6108#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 6109#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 6110#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 6111#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 6112#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 6113#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 6114#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 6115#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 6116#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 6117#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 6118#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 6119#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 6120#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 6121#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 6122#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 6123#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 6124//MMEA1_IO_RD_PRI_QUANT_PRI1 6125#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 6126#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 6127#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 6128#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 6129#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 6130#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 6131#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 6132#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 6133//MMEA1_IO_RD_PRI_QUANT_PRI2 6134#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 6135#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 6136#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 6137#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 6138#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 6139#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 6140#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 6141#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 6142//MMEA1_IO_RD_PRI_QUANT_PRI3 6143#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 6144#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 6145#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 6146#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 6147#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 6148#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 6149#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 6150#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 6151//MMEA1_IO_WR_PRI_QUANT_PRI1 6152#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 6153#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 6154#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 6155#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 6156#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 6157#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 6158#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 6159#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 6160//MMEA1_IO_WR_PRI_QUANT_PRI2 6161#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 6162#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 6163#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 6164#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 6165#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 6166#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 6167#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 6168#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 6169//MMEA1_IO_WR_PRI_QUANT_PRI3 6170#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 6171#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 6172#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 6173#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 6174#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 6175#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 6176#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 6177#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 6178//MMEA1_SDP_ARB_DRAM 6179#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 6180#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 6181#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 6182#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 6183#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 6184#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 6185#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 6186#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 6187#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 6188#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 6189#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 6190#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 6191#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 6192#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 6193//MMEA1_SDP_ARB_FINAL 6194#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 6195#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 6196#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 6197#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 6198#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 6199#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 6200#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 6201#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 6202#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 6203#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 6204#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 6205#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 6206#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 6207#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 6208#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 6209#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 6210#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 6211#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 6212#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 6213#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 6214#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 6215#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 6216#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 6217#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 6218#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 6219#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 6220#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 6221#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 6222//MMEA1_SDP_DRAM_PRIORITY 6223#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 6224#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 6225#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 6226#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 6227#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 6228#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 6229#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 6230#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 6231#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 6232#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 6233#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 6234#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 6235#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 6236#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 6237#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 6238#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 6239//MMEA1_SDP_IO_PRIORITY 6240#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 6241#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 6242#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 6243#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 6244#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 6245#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 6246#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 6247#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 6248#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 6249#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 6250#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 6251#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 6252#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 6253#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 6254#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 6255#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 6256//MMEA1_SDP_CREDITS 6257#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 6258#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 6259#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 6260#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 6261#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 6262#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 6263//MMEA1_SDP_TAG_RESERVE0 6264#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 6265#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 6266#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 6267#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 6268#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 6269#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 6270#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 6271#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 6272//MMEA1_SDP_TAG_RESERVE1 6273#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 6274#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 6275#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 6276#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 6277#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 6278#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 6279#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 6280#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 6281//MMEA1_SDP_VCC_RESERVE0 6282#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 6283#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 6284#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 6285#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 6286#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 6287#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 6288#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 6289#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 6290#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 6291#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 6292//MMEA1_SDP_VCC_RESERVE1 6293#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 6294#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 6295#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 6296#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 6297#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 6298#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 6299#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 6300#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 6301//MMEA1_SDP_VCD_RESERVE0 6302#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 6303#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 6304#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 6305#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 6306#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 6307#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 6308#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 6309#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 6310#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 6311#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 6312//MMEA1_SDP_VCD_RESERVE1 6313#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 6314#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 6315#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 6316#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 6317#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 6318#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 6319#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 6320#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 6321//MMEA1_SDP_REQ_CNTL 6322#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 6323#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 6324#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 6325#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 6326#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 6327#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 6328#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 6329#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 6330#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 6331#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 6332//MMEA1_MISC 6333#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 6334#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 6335#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 6336#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 6337#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 6338#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 6339#define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6 6340#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 6341#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 6342#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa 6343#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc 6344#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe 6345#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 6346#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 6347#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 6348#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 6349#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 6350#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 6351#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 6352#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 6353#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 6354#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 6355#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 6356#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 6357#define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L 6358#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L 6359#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L 6360#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L 6361#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L 6362#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L 6363#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L 6364#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L 6365#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L 6366#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L 6367#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L 6368#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L 6369//MMEA1_LATENCY_SAMPLING 6370#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 6371#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 6372#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 6373#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 6374#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 6375#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 6376#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 6377#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 6378#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 6379#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 6380#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 6381#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 6382#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 6383#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 6384#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 6385#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 6386#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 6387#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 6388#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 6389#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 6390#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 6391#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 6392#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 6393#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 6394#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 6395#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 6396#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 6397#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 6398#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 6399#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 6400#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 6401#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 6402//MMEA1_PERFCOUNTER_LO 6403#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6404#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6405//MMEA1_PERFCOUNTER_HI 6406#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6407#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6408#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6409#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6410//MMEA1_PERFCOUNTER0_CFG 6411#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6412#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6413#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6414#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6415#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6416#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6417#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6418#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6419#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6420#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6421//MMEA1_PERFCOUNTER1_CFG 6422#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6423#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6424#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6425#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6426#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6427#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6428#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6429#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6430#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6431#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6432//MMEA1_PERFCOUNTER_RSLT_CNTL 6433#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6434#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6435#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6436#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6437#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6438#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6439#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6440#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6441#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6442#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6443#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6444#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6445//MMEA1_EDC_CNT 6446#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 6447#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 6448#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 6449#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 6450#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 6451#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 6452#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 6453#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 6454#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 6455#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 6456#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 6457#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 6458#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 6459#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 6460#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 6461#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 6462#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 6463#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 6464#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 6465#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 6466#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 6467#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 6468#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 6469#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 6470#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 6471#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 6472#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 6473#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 6474#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 6475#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 6476//MMEA1_EDC_CNT2 6477#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 6478#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 6479#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 6480#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 6481#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 6482#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 6483#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 6484#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 6485#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 6486#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 6487#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 6488#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 6489#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 6490#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 6491#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 6492#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 6493//MMEA1_DSM_CNTL 6494#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 6495#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 6496#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 6497#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 6498#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 6499#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 6500#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 6501#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 6502#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 6503#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 6504#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 6505#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 6506#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 6507#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 6508#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 6509#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 6510#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 6511#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 6512#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 6513#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 6514#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 6515#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 6516#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 6517#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 6518#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 6519#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 6520#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 6521#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 6522#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 6523#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 6524#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 6525#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 6526//MMEA1_DSM_CNTLA 6527#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 6528#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 6529#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 6530#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 6531#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 6532#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 6533#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 6534#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 6535#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 6536#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 6537#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 6538#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 6539#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 6540#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 6541#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 6542#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 6543#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 6544#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 6545#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 6546#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 6547#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 6548#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 6549#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 6550#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 6551#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 6552#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 6553#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 6554#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 6555//MMEA1_DSM_CNTLB 6556//MMEA1_DSM_CNTL2 6557#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 6558#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 6559#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 6560#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 6561#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 6562#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 6563#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 6564#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 6565#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 6566#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 6567#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 6568#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 6569#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 6570#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 6571#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 6572#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 6573#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 6574#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 6575#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 6576#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 6577#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 6578#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 6579#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 6580#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 6581#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 6582#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 6583#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 6584#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 6585#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 6586#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 6587#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 6588#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 6589#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 6590#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 6591//MMEA1_DSM_CNTL2A 6592#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 6593#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 6594#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 6595#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 6596#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 6597#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 6598#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 6599#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 6600#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 6601#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 6602#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 6603#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 6604#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 6605#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 6606#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 6607#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 6608#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 6609#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 6610#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 6611#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 6612#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 6613#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 6614#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 6615#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 6616#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 6617#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 6618#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 6619#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 6620//MMEA1_DSM_CNTL2B 6621//MMEA1_CGTT_CLK_CTRL 6622#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6623#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6624#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 6625#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 6626#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 6627#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 6628#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 6629#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 6630#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 6631#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 6632#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 6633#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 6634#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 6635#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 6636#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 6637#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 6638//MMEA1_EDC_MODE 6639#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 6640#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 6641#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 6642#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d 6643#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f 6644#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 6645#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L 6646#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L 6647#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L 6648#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L 6649//MMEA1_ERR_STATUS 6650#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 6651#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 6652#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 6653#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 6654#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa 6655#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 6656#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 6657#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L 6658#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L 6659#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L 6660//MMEA1_MISC2 6661#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 6662#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 6663#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 6664#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 6665#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 6666#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 6667#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 6668#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 6669 6670 6671// addressBlock: mmhub_pctldec 6672//PCTL_MISC 6673#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 6674#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 6675#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 6676#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb 6677#define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc 6678#define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd 6679#define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe 6680#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L 6681#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L 6682#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L 6683#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L 6684#define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L 6685#define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L 6686#define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L 6687//PCTL_MMHUB_DEEPSLEEP 6688#define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 6689#define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 6690#define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 6691#define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 6692#define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 6693#define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 6694#define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 6695#define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 6696#define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 6697#define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 6698#define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa 6699#define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb 6700#define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc 6701#define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd 6702#define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe 6703#define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf 6704#define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 6705#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f 6706#define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L 6707#define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L 6708#define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L 6709#define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L 6710#define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L 6711#define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L 6712#define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L 6713#define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L 6714#define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L 6715#define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L 6716#define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L 6717#define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L 6718#define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L 6719#define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L 6720#define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L 6721#define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L 6722#define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L 6723#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L 6724//PCTL_MMHUB_DEEPSLEEP_OVERRIDE 6725#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 6726#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 6727#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 6728#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 6729#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 6730#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 6731#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 6732#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 6733#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 6734#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 6735#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 6736#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 6737#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 6738#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 6739#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 6740#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 6741#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 6742#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 6743#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 6744#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 6745#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 6746#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 6747#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 6748#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 6749#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 6750#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 6751#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 6752#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 6753#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 6754#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 6755#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 6756#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 6757#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 6758#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 6759//PCTL_PG_IGNORE_DEEPSLEEP 6760#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 6761#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 6762#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 6763#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 6764#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 6765#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 6766#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 6767#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 6768#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 6769#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 6770#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa 6771#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb 6772#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc 6773#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd 6774#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe 6775#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf 6776#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 6777#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 6778#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L 6779#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L 6780#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L 6781#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L 6782#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L 6783#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L 6784#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L 6785#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L 6786#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L 6787#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L 6788#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L 6789#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L 6790#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L 6791#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L 6792#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L 6793#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L 6794#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L 6795#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L 6796//PCTL_PG_DAGB 6797#define PCTL_PG_DAGB__DS0__SHIFT 0x0 6798#define PCTL_PG_DAGB__DS1__SHIFT 0x1 6799#define PCTL_PG_DAGB__DS2__SHIFT 0x2 6800#define PCTL_PG_DAGB__DS3__SHIFT 0x3 6801#define PCTL_PG_DAGB__DS4__SHIFT 0x4 6802#define PCTL_PG_DAGB__DS5__SHIFT 0x5 6803#define PCTL_PG_DAGB__DS6__SHIFT 0x6 6804#define PCTL_PG_DAGB__DS7__SHIFT 0x7 6805#define PCTL_PG_DAGB__DS8__SHIFT 0x8 6806#define PCTL_PG_DAGB__DS9__SHIFT 0x9 6807#define PCTL_PG_DAGB__DS10__SHIFT 0xa 6808#define PCTL_PG_DAGB__DS11__SHIFT 0xb 6809#define PCTL_PG_DAGB__DS12__SHIFT 0xc 6810#define PCTL_PG_DAGB__DS13__SHIFT 0xd 6811#define PCTL_PG_DAGB__DS14__SHIFT 0xe 6812#define PCTL_PG_DAGB__DS15__SHIFT 0xf 6813#define PCTL_PG_DAGB__DS16__SHIFT 0x10 6814#define PCTL_PG_DAGB__DS0_MASK 0x00000001L 6815#define PCTL_PG_DAGB__DS1_MASK 0x00000002L 6816#define PCTL_PG_DAGB__DS2_MASK 0x00000004L 6817#define PCTL_PG_DAGB__DS3_MASK 0x00000008L 6818#define PCTL_PG_DAGB__DS4_MASK 0x00000010L 6819#define PCTL_PG_DAGB__DS5_MASK 0x00000020L 6820#define PCTL_PG_DAGB__DS6_MASK 0x00000040L 6821#define PCTL_PG_DAGB__DS7_MASK 0x00000080L 6822#define PCTL_PG_DAGB__DS8_MASK 0x00000100L 6823#define PCTL_PG_DAGB__DS9_MASK 0x00000200L 6824#define PCTL_PG_DAGB__DS10_MASK 0x00000400L 6825#define PCTL_PG_DAGB__DS11_MASK 0x00000800L 6826#define PCTL_PG_DAGB__DS12_MASK 0x00001000L 6827#define PCTL_PG_DAGB__DS13_MASK 0x00002000L 6828#define PCTL_PG_DAGB__DS14_MASK 0x00004000L 6829#define PCTL_PG_DAGB__DS15_MASK 0x00008000L 6830#define PCTL_PG_DAGB__DS16_MASK 0x00010000L 6831//PCTL0_RENG_RAM_INDEX 6832#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 6833#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 6834//PCTL0_RENG_RAM_DATA 6835#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 6836#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 6837//PCTL0_RENG_EXECUTE 6838#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 6839#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 6840#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 6841#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 6842#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe 6843#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19 6844#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 6845#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 6846#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 6847#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L 6848#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L 6849#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L 6850//PCTL0_MISC 6851#define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 6852#define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 6853#define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 6854#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 6855#define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 6856#define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 6857#define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 6858#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 6859//PCTL0_STCTRL_REGISTER_SAVE_RANGE0 6860#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 6861#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 6862#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 6863#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 6864//PCTL0_STCTRL_REGISTER_SAVE_RANGE1 6865#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 6866#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 6867#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 6868#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 6869//PCTL0_STCTRL_REGISTER_SAVE_RANGE2 6870#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 6871#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 6872#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 6873#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 6874//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 6875#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 6876#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 6877#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 6878#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 6879//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 6880#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 6881#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 6882#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 6883#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 6884//PCTL1_RENG_RAM_INDEX 6885#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 6886#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 6887//PCTL1_RENG_RAM_DATA 6888#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 6889#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 6890//PCTL1_RENG_EXECUTE 6891#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 6892#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 6893#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 6894#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 6895#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 6896#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 6897#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 6898#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 6899#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 6900#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L 6901#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L 6902#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L 6903//PCTL1_MISC 6904#define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 6905#define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 6906#define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 6907#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 6908#define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 6909#define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 6910#define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 6911#define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 6912#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 6913#define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 6914//PCTL1_STCTRL_REGISTER_SAVE_RANGE0 6915#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 6916#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 6917#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 6918#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 6919//PCTL1_STCTRL_REGISTER_SAVE_RANGE1 6920#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 6921#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 6922#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 6923#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 6924//PCTL1_STCTRL_REGISTER_SAVE_RANGE2 6925#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 6926#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 6927#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 6928#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 6929//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 6930#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 6931#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 6932#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 6933#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 6934//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 6935#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 6936#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 6937#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 6938#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 6939//PCTL2_RENG_RAM_INDEX 6940#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 6941#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 6942//PCTL2_RENG_RAM_DATA 6943#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 6944#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 6945//PCTL2_RENG_EXECUTE 6946#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 6947#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 6948#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 6949#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 6950#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 6951#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 6952#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 6953#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 6954#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 6955#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L 6956#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L 6957#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L 6958//PCTL2_MISC 6959#define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 6960#define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 6961#define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 6962#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 6963#define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 6964#define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 6965#define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 6966#define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 6967#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 6968#define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 6969//PCTL2_STCTRL_REGISTER_SAVE_RANGE0 6970#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 6971#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 6972#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 6973#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 6974//PCTL2_STCTRL_REGISTER_SAVE_RANGE1 6975#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 6976#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 6977#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 6978#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 6979//PCTL2_STCTRL_REGISTER_SAVE_RANGE2 6980#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 6981#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 6982#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 6983#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 6984//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 6985#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 6986#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 6987#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 6988#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 6989//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 6990#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 6991#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 6992#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 6993#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 6994 6995 6996// addressBlock: mmhub_l1tlb_vml1dec 6997//MC_VM_MX_L1_TLB0_STATUS 6998#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 6999#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7000#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 7001#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7002//MC_VM_MX_L1_TLB1_STATUS 7003#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 7004#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7005#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 7006#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7007//MC_VM_MX_L1_TLB2_STATUS 7008#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 7009#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7010#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 7011#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7012//MC_VM_MX_L1_TLB3_STATUS 7013#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 7014#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7015#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 7016#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7017//MC_VM_MX_L1_TLB4_STATUS 7018#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 7019#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7020#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 7021#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7022//MC_VM_MX_L1_TLB5_STATUS 7023#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 7024#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7025#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 7026#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7027//MC_VM_MX_L1_TLB6_STATUS 7028#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 7029#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7030#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 7031#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7032//MC_VM_MX_L1_TLB7_STATUS 7033#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 7034#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7035#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 7036#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7037 7038 7039// addressBlock: mmhub_l1tlb_vml1pldec 7040//MC_VM_MX_L1_PERFCOUNTER0_CFG 7041#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7042#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7043#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7044#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7045#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7046#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7047#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7048#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7049#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7050#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7051//MC_VM_MX_L1_PERFCOUNTER1_CFG 7052#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7053#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7054#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7055#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7056#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7057#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7058#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7059#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7060#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7061#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7062//MC_VM_MX_L1_PERFCOUNTER2_CFG 7063#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 7064#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 7065#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 7066#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 7067#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 7068#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 7069#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 7070#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 7071#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 7072#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 7073//MC_VM_MX_L1_PERFCOUNTER3_CFG 7074#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 7075#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 7076#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 7077#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 7078#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 7079#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 7080#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 7081#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 7082#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 7083#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 7084//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 7085#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7086#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7087#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7088#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7089#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7090#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7091#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7092#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7093#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7094#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7095#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7096#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7097 7098 7099// addressBlock: mmhub_l1tlb_vml1prdec 7100//MC_VM_MX_L1_PERFCOUNTER_LO 7101#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7102#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7103//MC_VM_MX_L1_PERFCOUNTER_HI 7104#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7105#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7106#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7107#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7108 7109 7110// addressBlock: mmhub_l1tlb_vmtlspfdec 7111//VM_L2_SAW_CNTL 7112#define VM_L2_SAW_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 7113#define VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 7114#define VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 7115#define VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 7116#define VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 7117#define VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 7118#define VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 7119#define VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 7120#define VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 7121#define VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 7122#define VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 7123#define VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 7124#define VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 7125#define VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS__SHIFT 0x1a 7126#define VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS__SHIFT 0x1c 7127#define VM_L2_SAW_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 7128#define VM_L2_SAW_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 7129#define VM_L2_SAW_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 7130#define VM_L2_SAW_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 7131#define VM_L2_SAW_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 7132#define VM_L2_SAW_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 7133#define VM_L2_SAW_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 7134#define VM_L2_SAW_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 7135#define VM_L2_SAW_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 7136#define VM_L2_SAW_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 7137#define VM_L2_SAW_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 7138#define VM_L2_SAW_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 7139#define VM_L2_SAW_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 7140#define VM_L2_SAW_CNTL__L2_CACHE_4K_SWAP_TAG_INDEX_LSBS_MASK 0x0C000000L 7141#define VM_L2_SAW_CNTL__L2_CACHE_BIGK_SWAP_TAG_INDEX_LSBS_MASK 0x70000000L 7142//VM_L2_SAW_CNTL2 7143#define VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 7144#define VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 7145#define VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 7146#define VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 7147#define VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE__SHIFT 0x17 7148#define VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 7149#define VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 7150#define VM_L2_SAW_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 7151#define VM_L2_SAW_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 7152#define VM_L2_SAW_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 7153#define VM_L2_SAW_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 7154#define VM_L2_SAW_CNTL2__L2_CACHE_BIGK_VMID_MODE_MASK 0x03800000L 7155#define VM_L2_SAW_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 7156#define VM_L2_SAW_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 7157//VM_L2_SAW_CNTL3 7158#define VM_L2_SAW_CNTL3__BANK_SELECT__SHIFT 0x0 7159#define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 7160#define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 7161#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 7162#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 7163#define VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 7164#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 7165#define VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 7166#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 7167#define VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 7168#define VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 7169#define VM_L2_SAW_CNTL3__BANK_SELECT_MASK 0x0000003FL 7170#define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 7171#define VM_L2_SAW_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 7172#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 7173#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 7174#define VM_L2_SAW_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 7175#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 7176#define VM_L2_SAW_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 7177#define VM_L2_SAW_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 7178#define VM_L2_SAW_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 7179#define VM_L2_SAW_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 7180//VM_L2_SAW_CNTL4 7181#define VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 7182#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL__SHIFT 0x6 7183#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED__SHIFT 0x7 7184#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP__SHIFT 0x8 7185#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL__SHIFT 0x9 7186#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED__SHIFT 0xa 7187#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP__SHIFT 0xb 7188#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL__SHIFT 0xc 7189#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED__SHIFT 0xd 7190#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP__SHIFT 0xe 7191#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL__SHIFT 0xf 7192#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED__SHIFT 0x10 7193#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP__SHIFT 0x11 7194#define VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING__SHIFT 0x12 7195#define VM_L2_SAW_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 7196#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 7197#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SHARED_MASK 0x00000080L 7198#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PDE_REQUEST_SNOOP_MASK 0x00000100L 7199#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_PHYSICAL_MASK 0x00000200L 7200#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SHARED_MASK 0x00000400L 7201#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT0_PTE_REQUEST_SNOOP_MASK 0x00000800L 7202#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_PHYSICAL_MASK 0x00001000L 7203#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SHARED_MASK 0x00002000L 7204#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PDE_REQUEST_SNOOP_MASK 0x00004000L 7205#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_PHYSICAL_MASK 0x00008000L 7206#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SHARED_MASK 0x00010000L 7207#define VM_L2_SAW_CNTL4__VMC_TAP_CONTEXT1_PTE_REQUEST_SNOOP_MASK 0x00020000L 7208#define VM_L2_SAW_CNTL4__L2_CACHE_4K_LRU_ADDR_MATCHING_MASK 0x00040000L 7209//VM_L2_SAW_CONTEXT0_CNTL 7210#define VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7211#define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7212#define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x3 7213#define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 7214#define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x6 7215#define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 7216#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7217#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7218#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xb 7219#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xc 7220#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xd 7221#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0xe 7222#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7223#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7224#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x11 7225#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x12 7226#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x13 7227#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x14 7228#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7229#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7230#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE__SHIFT 0x17 7231#define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x18 7232#define VM_L2_SAW_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7233#define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7234#define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000008L 7235#define VM_L2_SAW_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 7236#define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000040L 7237#define VM_L2_SAW_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 7238#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7239#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7240#define VM_L2_SAW_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00000800L 7241#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00001000L 7242#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00002000L 7243#define VM_L2_SAW_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00004000L 7244#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7245#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7246#define VM_L2_SAW_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00020000L 7247#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00040000L 7248#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00080000L 7249#define VM_L2_SAW_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00100000L 7250#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7251#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7252#define VM_L2_SAW_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_SAVE_MASK 0x00800000L 7253#define VM_L2_SAW_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x0F000000L 7254//VM_L2_SAW_CONTEXT0_CNTL2 7255#define VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 7256#define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT__SHIFT 0x1 7257#define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT__SHIFT 0x2 7258#define VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x3 7259#define VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE__SHIFT 0x4 7260#define VM_L2_SAW_CONTEXT0_CNTL2__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 7261#define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_CLEAR_PROTECTION_FAULT_STATUS_ADDR_WHEN_INVALIDATE_CONTEXT_MASK 0x00000002L 7262#define VM_L2_SAW_CONTEXT0_CNTL2__ENABLE_INTERRUPT_PROCESSING_FOR_SUBSEQUENT_FAULTS_PER_CONTEXT_MASK 0x00000004L 7263#define VM_L2_SAW_CONTEXT0_CNTL2__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000008L 7264#define VM_L2_SAW_CONTEXT0_CNTL2__WAIT_FOR_IDLE_WHEN_INVALIDATE_MASK 0x00000010L 7265//VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 7266#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32__SHIFT 0x0 7267#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PHYSICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 7268//VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 7269#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4__SHIFT 0x0 7270#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PHYSICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 7271//VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 7272#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 7273#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 7274//VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 7275#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 7276#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 7277//VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 7278#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 7279#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 7280//VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 7281#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 7282#define VM_L2_SAW_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 7283//VM_L2_SAW_CONTEXTS_DISABLE 7284#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 7285#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 7286#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 7287#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 7288#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 7289#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 7290#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 7291#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 7292#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 7293#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 7294#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 7295#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 7296#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 7297#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 7298#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 7299#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 7300#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 7301#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 7302#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 7303#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 7304#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 7305#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 7306#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 7307#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 7308#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 7309#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 7310#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 7311#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 7312#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 7313#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 7314#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 7315#define VM_L2_SAW_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 7316//VM_L2_SAW_PIPES_BUSY 7317#define VM_L2_SAW_PIPES_BUSY__PIPES_BUSY__SHIFT 0x0 7318#define VM_L2_SAW_PIPES_BUSY__PIPES_BUSY_MASK 0xFFFFFFFFL 7319 7320 7321// addressBlock: mmhub_utcl2_atcl2dec 7322//ATC_L2_CNTL 7323#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 7324#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 7325#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 7326#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 7327#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 7328#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 7329#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 7330#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 7331#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 7332#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 7333#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L 7334#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 7335//ATC_L2_CNTL2 7336#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 7337#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 7338#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 7339#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 7340#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 7341#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 7342#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 7343#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 7344#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 7345#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 7346#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 7347#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 7348//ATC_L2_CACHE_DATA0 7349#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 7350#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 7351#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 7352#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 7353#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 7354#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 7355#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL 7356#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L 7357//ATC_L2_CACHE_DATA1 7358#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 7359#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 7360//ATC_L2_CACHE_DATA2 7361#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 7362#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 7363//ATC_L2_CNTL3 7364#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 7365#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 7366#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L 7367#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L 7368//ATC_L2_STATUS 7369#define ATC_L2_STATUS__BUSY__SHIFT 0x0 7370#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 7371#define ATC_L2_STATUS__BUSY_MASK 0x00000001L 7372#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL 7373//ATC_L2_STATUS2 7374#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 7375#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 7376#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 7377#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 7378//ATC_L2_MISC_CG 7379#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 7380#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 7381#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 7382#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 7383#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 7384#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 7385//ATC_L2_MEM_POWER_LS 7386#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 7387#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 7388#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 7389#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 7390//ATC_L2_CGTT_CLK_CTRL 7391#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7392#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7393#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 7394#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 7395#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 7396#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7397#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7398#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 7399#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 7400#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 7401 7402 7403// addressBlock: mmhub_utcl2_vml2pfdec 7404//VM_L2_CNTL 7405#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 7406#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 7407#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 7408#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 7409#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 7410#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 7411#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 7412#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 7413#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 7414#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 7415#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 7416#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 7417#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 7418#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 7419#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 7420#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 7421#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 7422#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 7423#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 7424#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 7425#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 7426#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 7427#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 7428#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 7429#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 7430#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 7431#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 7432#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 7433//VM_L2_CNTL2 7434#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 7435#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 7436#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 7437#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 7438#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 7439#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 7440#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 7441#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 7442#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 7443#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 7444#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 7445#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 7446#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 7447#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 7448//VM_L2_CNTL3 7449#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 7450#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 7451#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 7452#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 7453#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 7454#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 7455#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 7456#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 7457#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 7458#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 7459#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 7460#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 7461#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 7462#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 7463#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 7464#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 7465#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 7466#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 7467#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 7468#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 7469#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 7470#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 7471//VM_L2_STATUS 7472#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 7473#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 7474#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 7475#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 7476#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 7477#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 7478#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 7479#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L 7480#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 7481#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 7482#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 7483#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 7484#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 7485#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 7486//VM_DUMMY_PAGE_FAULT_CNTL 7487#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 7488#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 7489#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 7490#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 7491#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 7492#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 7493//VM_DUMMY_PAGE_FAULT_ADDR_LO32 7494#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 7495#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7496//VM_DUMMY_PAGE_FAULT_ADDR_HI32 7497#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 7498#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 7499//VM_L2_PROTECTION_FAULT_CNTL 7500#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 7501#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 7502#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 7503#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 7504#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 7505#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 7506#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 7507#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 7508#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 7509#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 7510#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7511#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 7512#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7513#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 7514#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 7515#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 7516#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 7517#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 7518#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 7519#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 7520#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 7521#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 7522#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 7523#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 7524#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 7525#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 7526#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 7527#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7528#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 7529#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7530#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 7531#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 7532#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 7533#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 7534//VM_L2_PROTECTION_FAULT_CNTL2 7535#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 7536#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 7537#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 7538#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 7539#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 7540#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 7541#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 7542#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 7543#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 7544#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 7545//VM_L2_PROTECTION_FAULT_MM_CNTL3 7546#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 7547#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 7548//VM_L2_PROTECTION_FAULT_MM_CNTL4 7549#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 7550#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 7551//VM_L2_PROTECTION_FAULT_STATUS 7552#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 7553#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 7554#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 7555#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 7556#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 7557#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 7558#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 7559#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 7560#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 7561#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 7562#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 7563#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 7564#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 7565#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 7566#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 7567#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 7568#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 7569#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 7570#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 7571#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 7572//VM_L2_PROTECTION_FAULT_ADDR_LO32 7573#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 7574#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7575//VM_L2_PROTECTION_FAULT_ADDR_HI32 7576#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 7577#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 7578//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 7579#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 7580#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7581//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 7582#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 7583#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 7584//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 7585#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 7586#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 7587//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 7588#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 7589#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 7590//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 7591#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 7592#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 7593//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 7594#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 7595#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 7596//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 7597#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 7598#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 7599//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 7600#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 7601#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 7602//VM_L2_CNTL4 7603#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 7604#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 7605#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 7606#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 7607#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 7608#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 7609#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 7610#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 7611#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 7612#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 7613#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 7614#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 7615//VM_L2_MM_GROUP_RT_CLASSES 7616#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 7617#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 7618#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 7619#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 7620#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 7621#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 7622#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 7623#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 7624#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 7625#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 7626#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 7627#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 7628#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 7629#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 7630#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 7631#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 7632#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 7633#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 7634#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 7635#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 7636#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 7637#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 7638#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 7639#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 7640#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 7641#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 7642#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 7643#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 7644#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 7645#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 7646#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 7647#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 7648#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 7649#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 7650#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 7651#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 7652#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 7653#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 7654#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 7655#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 7656#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 7657#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 7658#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 7659#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 7660#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 7661#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 7662#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 7663#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 7664#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 7665#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 7666#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 7667#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 7668#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 7669#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 7670#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 7671#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 7672#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 7673#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 7674#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 7675#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 7676#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 7677#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 7678#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 7679#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 7680//VM_L2_BANK_SELECT_RESERVED_CID 7681#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 7682#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 7683#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 7684#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 7685#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 7686#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 7687#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 7688#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 7689#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 7690#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 7691//VM_L2_BANK_SELECT_RESERVED_CID2 7692#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 7693#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 7694#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 7695#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 7696#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 7697#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 7698#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 7699#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 7700#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 7701#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 7702//VM_L2_CACHE_PARITY_CNTL 7703#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 7704#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 7705#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 7706#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 7707#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 7708#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 7709#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 7710#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 7711#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 7712#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 7713#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 7714#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 7715#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 7716#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 7717#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 7718#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 7719#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 7720#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 7721//VM_L2_CGTT_CLK_CTRL 7722#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7723#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7724#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 7725#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 7726#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 7727#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7728#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7729#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 7730#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 7731#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 7732 7733 7734// addressBlock: mmhub_utcl2_vml2vcdec 7735//VM_CONTEXT0_CNTL 7736#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7737#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7738#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7739#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7740#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7741#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7742#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7743#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7744#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7745#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7746#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7747#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7748#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7749#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7750#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7751#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7752#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7753#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7754#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7755#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7756#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7757#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7758#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7759#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7760#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7761#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7762#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7763#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7764#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7765#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7766#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7767#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7768#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7769#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7770#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7771#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7772#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7773#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7774//VM_CONTEXT1_CNTL 7775#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7776#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7777#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7778#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7779#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7780#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7781#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7782#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7783#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7784#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7785#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7786#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7787#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7788#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7789#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7790#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7791#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7792#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7793#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7794#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7795#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7796#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7797#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7798#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7799#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7800#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7801#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7802#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7803#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7804#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7805#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7806#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7807#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7808#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7809#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7810#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7811#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7812#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7813//VM_CONTEXT2_CNTL 7814#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7815#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7816#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7817#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7818#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7819#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7820#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7821#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7822#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7823#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7824#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7825#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7826#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7827#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7828#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7829#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7830#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7831#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7832#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7833#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7834#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7835#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7836#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7837#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7838#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7839#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7840#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7841#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7842#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7843#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7844#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7845#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7846#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7847#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7848#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7849#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7850#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7851#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7852//VM_CONTEXT3_CNTL 7853#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7854#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7855#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7856#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7857#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7858#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7859#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7860#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7861#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7862#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7863#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7864#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7865#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7866#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7867#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7868#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7869#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7870#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7871#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7872#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7873#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7874#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7875#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7876#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7877#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7878#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7879#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7880#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7881#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7882#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7883#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7884#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7885#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7886#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7887#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7888#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7889#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7890#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7891//VM_CONTEXT4_CNTL 7892#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7893#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7894#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7895#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7896#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7897#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7898#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7899#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7900#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7901#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7902#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7903#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7904#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7905#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7906#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7907#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7908#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7909#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7910#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7911#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7912#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7913#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7914#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7915#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7916#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7917#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7918#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7919#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7920#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7921#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7922#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7923#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7924#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7925#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7926#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7927#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7928#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7929#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7930//VM_CONTEXT5_CNTL 7931#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7932#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7933#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7934#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7935#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7936#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7937#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7938#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7939#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7940#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7941#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7942#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7943#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7944#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7945#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7946#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7947#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7948#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7949#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7950#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7951#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7952#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7953#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7954#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7955#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7956#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7957#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7958#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7959#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7960#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 7961#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 7962#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 7963#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 7964#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 7965#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 7966#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 7967#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 7968#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 7969//VM_CONTEXT6_CNTL 7970#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 7971#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 7972#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 7973#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 7974#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 7975#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 7976#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7977#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 7978#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7979#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 7980#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 7981#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 7982#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 7983#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 7984#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 7985#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 7986#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 7987#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 7988#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 7989#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 7990#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 7991#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 7992#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 7993#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 7994#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 7995#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7996#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 7997#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7998#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 7999#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8000#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8001#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8002#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8003#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8004#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8005#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8006#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8007#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8008//VM_CONTEXT7_CNTL 8009#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8010#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8011#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8012#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8013#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8014#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8015#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8016#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8017#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8018#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8019#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8020#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8021#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8022#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8023#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8024#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8025#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8026#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8027#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8028#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8029#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8030#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8031#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8032#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8033#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8034#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8035#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8036#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8037#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8038#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8039#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8040#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8041#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8042#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8043#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8044#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8045#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8046#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8047//VM_CONTEXT8_CNTL 8048#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8049#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8050#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8051#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8052#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8053#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8054#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8055#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8056#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8057#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8058#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8059#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8060#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8061#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8062#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8063#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8064#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8065#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8066#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8067#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8068#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8069#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8070#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8071#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8072#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8073#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8074#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8075#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8076#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8077#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8078#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8079#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8080#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8081#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8082#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8083#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8084#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8085#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8086//VM_CONTEXT9_CNTL 8087#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8088#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8089#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8090#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8091#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8092#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8093#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8094#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8095#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8096#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8097#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8098#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8099#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8100#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8101#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8102#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8103#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8104#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8105#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8106#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8107#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8108#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8109#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8110#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8111#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8112#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8113#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8114#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8115#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8116#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8117#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8118#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8119#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8120#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8121#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8122#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8123#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8124#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8125//VM_CONTEXT10_CNTL 8126#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8127#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8128#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8129#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8130#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8131#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8132#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8133#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8134#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8135#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8136#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8137#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8138#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8139#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8140#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8141#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8142#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8143#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8144#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8145#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8146#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8147#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8148#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8149#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8150#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8151#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8152#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8153#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8154#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8155#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8156#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8157#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8158#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8159#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8160#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8161#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8162#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8163#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8164//VM_CONTEXT11_CNTL 8165#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8166#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8167#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8168#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8169#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8170#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8171#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8172#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8173#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8174#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8175#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8176#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8177#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8178#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8179#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8180#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8181#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8182#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8183#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8184#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8185#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8186#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8187#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8188#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8189#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8190#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8191#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8192#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8193#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8194#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8195#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8196#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8197#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8198#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8199#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8200#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8201#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8202#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8203//VM_CONTEXT12_CNTL 8204#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8205#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8206#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8207#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8208#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8209#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8210#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8211#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8212#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8213#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8214#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8215#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8216#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8217#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8218#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8219#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8220#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8221#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8222#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8223#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8224#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8225#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8226#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8227#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8228#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8229#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8230#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8231#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8232#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8233#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8234#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8235#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8236#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8237#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8238#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8239#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8240#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8241#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8242//VM_CONTEXT13_CNTL 8243#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8244#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8245#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8246#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8247#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8248#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8249#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8250#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8251#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8252#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8253#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8254#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8255#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8256#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8257#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8258#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8259#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8260#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8261#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8262#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8263#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8264#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8265#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8266#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8267#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8268#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8269#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8270#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8271#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8272#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8273#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8274#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8275#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8276#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8277#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8278#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8279#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8280#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8281//VM_CONTEXT14_CNTL 8282#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8283#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8284#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8285#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8286#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8287#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8288#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8289#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8290#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8291#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8292#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8293#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8294#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8295#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8296#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8297#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8298#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8299#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8300#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8301#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8302#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8303#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8304#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8305#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8306#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8307#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8308#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8309#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8310#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8311#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8312#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8313#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8314#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8315#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8316#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8317#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8318#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8319#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8320//VM_CONTEXT15_CNTL 8321#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8322#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8323#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8324#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8325#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8326#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8327#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8328#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8329#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8330#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8331#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8332#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8333#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8334#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8335#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8336#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8337#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8338#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8339#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8340#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8341#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8342#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8343#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8344#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8345#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8346#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8347#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8348#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8349#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8350#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8351#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8352#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8353#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8354#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8355#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8356#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8357#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8358#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8359//VM_CONTEXTS_DISABLE 8360#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 8361#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 8362#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 8363#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 8364#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 8365#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 8366#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 8367#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 8368#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 8369#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 8370#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 8371#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 8372#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 8373#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 8374#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 8375#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 8376#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 8377#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 8378#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 8379#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 8380#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 8381#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 8382#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 8383#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 8384#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 8385#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 8386#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 8387#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 8388#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 8389#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 8390#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 8391#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 8392//VM_INVALIDATE_ENG0_SEM 8393#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 8394#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 8395//VM_INVALIDATE_ENG1_SEM 8396#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 8397#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 8398//VM_INVALIDATE_ENG2_SEM 8399#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 8400#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 8401//VM_INVALIDATE_ENG3_SEM 8402#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 8403#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 8404//VM_INVALIDATE_ENG4_SEM 8405#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 8406#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 8407//VM_INVALIDATE_ENG5_SEM 8408#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 8409#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 8410//VM_INVALIDATE_ENG6_SEM 8411#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 8412#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 8413//VM_INVALIDATE_ENG7_SEM 8414#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 8415#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 8416//VM_INVALIDATE_ENG8_SEM 8417#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 8418#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 8419//VM_INVALIDATE_ENG9_SEM 8420#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 8421#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 8422//VM_INVALIDATE_ENG10_SEM 8423#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 8424#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 8425//VM_INVALIDATE_ENG11_SEM 8426#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 8427#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 8428//VM_INVALIDATE_ENG12_SEM 8429#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 8430#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 8431//VM_INVALIDATE_ENG13_SEM 8432#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 8433#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 8434//VM_INVALIDATE_ENG14_SEM 8435#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 8436#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 8437//VM_INVALIDATE_ENG15_SEM 8438#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 8439#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 8440//VM_INVALIDATE_ENG16_SEM 8441#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 8442#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 8443//VM_INVALIDATE_ENG17_SEM 8444#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 8445#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 8446//VM_INVALIDATE_ENG0_REQ 8447#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8448#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 8449#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8450#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8451#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8452#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8453#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8454#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8455#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8456#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L 8457#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8458#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8459#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8460#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8461#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8462#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8463//VM_INVALIDATE_ENG1_REQ 8464#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8465#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 8466#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8467#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8468#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8469#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8470#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8471#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8472#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8473#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L 8474#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8475#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8476#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8477#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8478#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8479#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8480//VM_INVALIDATE_ENG2_REQ 8481#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8482#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 8483#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8484#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8485#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8486#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8487#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8488#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8489#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8490#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L 8491#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8492#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8493#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8494#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8495#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8496#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8497//VM_INVALIDATE_ENG3_REQ 8498#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8499#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 8500#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8501#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8502#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8503#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8504#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8505#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8506#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8507#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L 8508#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8509#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8510#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8511#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8512#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8513#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8514//VM_INVALIDATE_ENG4_REQ 8515#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8516#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 8517#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8518#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8519#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8520#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8521#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8522#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8523#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8524#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L 8525#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8526#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8527#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8528#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8529#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8530#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8531//VM_INVALIDATE_ENG5_REQ 8532#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8533#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 8534#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8535#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8536#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8537#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8538#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8539#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8540#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8541#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L 8542#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8543#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8544#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8545#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8546#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8547#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8548//VM_INVALIDATE_ENG6_REQ 8549#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8550#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 8551#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8552#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8553#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8554#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8555#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8556#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8557#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8558#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L 8559#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8560#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8561#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8562#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8563#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8564#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8565//VM_INVALIDATE_ENG7_REQ 8566#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8567#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 8568#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8569#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8570#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8571#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8572#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8573#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8574#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8575#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L 8576#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8577#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8578#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8579#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8580#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8581#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8582//VM_INVALIDATE_ENG8_REQ 8583#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8584#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 8585#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8586#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8587#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8588#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8589#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8590#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8591#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8592#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L 8593#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8594#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8595#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8596#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8597#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8598#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8599//VM_INVALIDATE_ENG9_REQ 8600#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8601#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 8602#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8603#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8604#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8605#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8606#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8607#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8608#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8609#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L 8610#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8611#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8612#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8613#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8614#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8615#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8616//VM_INVALIDATE_ENG10_REQ 8617#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8618#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 8619#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8620#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8621#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8622#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8623#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8624#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8625#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8626#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L 8627#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8628#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8629#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8630#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8631#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8632#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8633//VM_INVALIDATE_ENG11_REQ 8634#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8635#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 8636#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8637#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8638#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8639#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8640#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8641#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8642#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8643#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L 8644#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8645#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8646#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8647#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8648#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8649#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8650//VM_INVALIDATE_ENG12_REQ 8651#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8652#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 8653#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8654#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8655#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8656#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8657#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8658#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8659#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8660#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L 8661#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8662#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8663#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8664#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8665#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8666#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8667//VM_INVALIDATE_ENG13_REQ 8668#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8669#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 8670#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8671#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8672#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8673#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8674#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8675#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8676#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8677#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L 8678#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8679#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8680#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8681#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8682#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8683#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8684//VM_INVALIDATE_ENG14_REQ 8685#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8686#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 8687#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8688#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8689#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8690#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8691#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8692#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8693#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8694#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L 8695#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8696#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8697#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8698#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8699#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8700#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8701//VM_INVALIDATE_ENG15_REQ 8702#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8703#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 8704#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8705#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8706#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8707#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8708#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8709#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8710#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8711#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L 8712#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8713#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8714#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8715#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8716#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8717#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8718//VM_INVALIDATE_ENG16_REQ 8719#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8720#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 8721#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8722#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8723#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8724#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8725#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8726#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8727#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8728#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L 8729#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8730#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8731#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8732#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8733#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8734#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8735//VM_INVALIDATE_ENG17_REQ 8736#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8737#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 8738#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8739#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8740#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8741#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8742#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8743#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8744#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8745#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L 8746#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8747#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8748#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8749#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8750#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8751#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8752//VM_INVALIDATE_ENG0_ACK 8753#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8754#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 8755#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8756#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 8757//VM_INVALIDATE_ENG1_ACK 8758#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8759#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 8760#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8761#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 8762//VM_INVALIDATE_ENG2_ACK 8763#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8764#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 8765#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8766#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 8767//VM_INVALIDATE_ENG3_ACK 8768#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8769#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 8770#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8771#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 8772//VM_INVALIDATE_ENG4_ACK 8773#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8774#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 8775#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8776#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 8777//VM_INVALIDATE_ENG5_ACK 8778#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8779#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 8780#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8781#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 8782//VM_INVALIDATE_ENG6_ACK 8783#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8784#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 8785#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8786#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 8787//VM_INVALIDATE_ENG7_ACK 8788#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8789#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 8790#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8791#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 8792//VM_INVALIDATE_ENG8_ACK 8793#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8794#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 8795#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8796#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 8797//VM_INVALIDATE_ENG9_ACK 8798#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8799#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 8800#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8801#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 8802//VM_INVALIDATE_ENG10_ACK 8803#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8804#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 8805#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8806#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 8807//VM_INVALIDATE_ENG11_ACK 8808#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8809#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 8810#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8811#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 8812//VM_INVALIDATE_ENG12_ACK 8813#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8814#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 8815#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8816#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 8817//VM_INVALIDATE_ENG13_ACK 8818#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8819#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 8820#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8821#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 8822//VM_INVALIDATE_ENG14_ACK 8823#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8824#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 8825#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8826#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 8827//VM_INVALIDATE_ENG15_ACK 8828#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8829#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 8830#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8831#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 8832//VM_INVALIDATE_ENG16_ACK 8833#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8834#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 8835#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8836#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 8837//VM_INVALIDATE_ENG17_ACK 8838#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 8839#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 8840#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 8841#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 8842//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 8843#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8844#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8845#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8846#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8847//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 8848#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8849#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8850//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 8851#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8852#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8853#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8854#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8855//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 8856#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8857#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8858//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 8859#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8860#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8861#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8862#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8863//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 8864#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8865#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8866//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 8867#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8868#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8869#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8870#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8871//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 8872#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8873#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8874//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 8875#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8876#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8877#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8878#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8879//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 8880#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8881#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8882//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 8883#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8884#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8885#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8886#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8887//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 8888#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8889#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8890//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 8891#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8892#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8893#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8894#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8895//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 8896#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8897#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8898//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 8899#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8900#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8901#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8902#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8903//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 8904#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8905#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8906//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 8907#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8908#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8909#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8910#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8911//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 8912#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8913#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8914//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 8915#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8916#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8917#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8918#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8919//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 8920#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8921#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8922//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 8923#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8924#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8925#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8926#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8927//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 8928#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8929#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8930//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 8931#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8932#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8933#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8934#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8935//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 8936#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8937#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8938//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 8939#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8940#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8941#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8942#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8943//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 8944#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8945#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8946//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 8947#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8948#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8949#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8950#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8951//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 8952#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8953#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8954//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 8955#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8956#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8957#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8958#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8959//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 8960#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8961#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8962//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 8963#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8964#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8965#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8966#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8967//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 8968#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8969#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8970//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 8971#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8972#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8973#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8974#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8975//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 8976#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8977#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8978//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 8979#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 8980#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 8981#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 8982#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 8983//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 8984#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 8985#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 8986//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 8987#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8988#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8989//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 8990#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8991#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8992//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 8993#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 8994#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 8995//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 8996#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 8997#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 8998//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 8999#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9000#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9001//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 9002#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9003#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9004//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 9005#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9006#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9007//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 9008#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9009#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9010//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 9011#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9012#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9013//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 9014#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9015#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9016//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 9017#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9018#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9019//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 9020#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9021#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9022//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 9023#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9024#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9025//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 9026#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9027#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9028//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 9029#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9030#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9031//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 9032#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9033#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9034//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 9035#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9036#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9037//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 9038#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9039#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9040//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 9041#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9042#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9043//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 9044#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9045#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9046//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 9047#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9048#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9049//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 9050#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9051#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9052//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 9053#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9054#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9055//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 9056#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9057#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9058//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 9059#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9060#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9061//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 9062#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9063#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9064//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 9065#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9066#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9067//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 9068#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9069#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9070//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 9071#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9072#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9073//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 9074#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9075#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9076//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 9077#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9078#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9079//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 9080#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9081#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9082//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 9083#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9084#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9085//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 9086#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9087#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9088//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 9089#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9090#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9091//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 9092#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9093#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9094//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 9095#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9096#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9097//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 9098#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9099#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9100//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 9101#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9102#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9103//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 9104#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9105#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9106//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 9107#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9108#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9109//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 9110#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9111#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9112//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 9113#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9114#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9115//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 9116#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9117#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9118//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 9119#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9120#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9121//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 9122#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9123#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9124//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 9125#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9126#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9127//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 9128#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9129#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9130//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 9131#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9132#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9133//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 9134#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9135#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9136//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 9137#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9138#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9139//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 9140#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9141#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9142//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 9143#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9144#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9145//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 9146#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9147#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9148//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 9149#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9150#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9151//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 9152#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9153#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9154//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 9155#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9156#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9157//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 9158#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9159#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9160//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 9161#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9162#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9163//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 9164#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9165#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9166//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 9167#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9168#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9169//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 9170#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9171#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9172//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 9173#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9174#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9175//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 9176#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9177#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9178//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 9179#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9180#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9181//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 9182#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9183#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9184//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 9185#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9186#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9187//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 9188#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9189#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9190//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 9191#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9192#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9193//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 9194#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9195#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9196//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 9197#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9198#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9199//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 9200#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9201#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9202//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 9203#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9204#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9205//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 9206#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9207#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9208//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 9209#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9210#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9211//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 9212#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9213#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9214//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 9215#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9216#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9217//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 9218#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9219#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9220//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 9221#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9222#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9223//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 9224#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9225#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9226//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 9227#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9228#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9229//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 9230#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9231#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9232//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 9233#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9234#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9235//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 9236#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9237#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9238//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 9239#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9240#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9241//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 9242#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9243#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9244//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 9245#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9246#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9247//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 9248#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9249#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9250//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 9251#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9252#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9253//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 9254#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9255#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9256//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 9257#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9258#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9259//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 9260#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9261#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9262//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 9263#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9264#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9265//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 9266#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9267#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9268//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 9269#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9270#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9271//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 9272#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9273#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9274 9275 9276// addressBlock: mmhub_utcl2_vml2pldec 9277//MC_VM_L2_PERFCOUNTER0_CFG 9278#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 9279#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 9280#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 9281#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 9282#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 9283#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 9284#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 9285#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 9286#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 9287#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 9288//MC_VM_L2_PERFCOUNTER1_CFG 9289#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 9290#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 9291#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 9292#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 9293#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 9294#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 9295#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 9296#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 9297#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 9298#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 9299//MC_VM_L2_PERFCOUNTER2_CFG 9300#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 9301#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 9302#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 9303#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 9304#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 9305#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 9306#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 9307#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 9308#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 9309#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 9310//MC_VM_L2_PERFCOUNTER3_CFG 9311#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 9312#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 9313#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 9314#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 9315#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 9316#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 9317#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 9318#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 9319#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 9320#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 9321//MC_VM_L2_PERFCOUNTER4_CFG 9322#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 9323#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 9324#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 9325#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 9326#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 9327#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 9328#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 9329#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 9330#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 9331#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 9332//MC_VM_L2_PERFCOUNTER5_CFG 9333#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 9334#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 9335#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 9336#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 9337#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 9338#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 9339#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 9340#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 9341#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 9342#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 9343//MC_VM_L2_PERFCOUNTER6_CFG 9344#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 9345#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 9346#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 9347#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 9348#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 9349#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 9350#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 9351#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 9352#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 9353#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 9354//MC_VM_L2_PERFCOUNTER7_CFG 9355#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 9356#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 9357#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 9358#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 9359#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 9360#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 9361#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 9362#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 9363#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 9364#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 9365//MC_VM_L2_PERFCOUNTER_RSLT_CNTL 9366#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 9367#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 9368#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 9369#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 9370#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 9371#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 9372#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 9373#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 9374#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 9375#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 9376#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 9377#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 9378 9379 9380// addressBlock: mmhub_utcl2_vml2prdec 9381//MC_VM_L2_PERFCOUNTER_LO 9382#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 9383#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 9384//MC_VM_L2_PERFCOUNTER_HI 9385#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 9386#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 9387#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 9388#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 9389 9390 9391// addressBlock: mmhub_utcl2_vmsharedhvdec 9392//MC_VM_FB_SIZE_OFFSET_VF0 9393#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 9394#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 9395#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 9396#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 9397//MC_VM_FB_SIZE_OFFSET_VF1 9398#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 9399#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 9400#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 9401#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 9402//MC_VM_FB_SIZE_OFFSET_VF2 9403#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 9404#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 9405#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 9406#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 9407//MC_VM_FB_SIZE_OFFSET_VF3 9408#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 9409#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 9410#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 9411#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 9412//MC_VM_FB_SIZE_OFFSET_VF4 9413#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 9414#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 9415#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 9416#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 9417//MC_VM_FB_SIZE_OFFSET_VF5 9418#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 9419#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 9420#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 9421#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 9422//MC_VM_FB_SIZE_OFFSET_VF6 9423#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 9424#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 9425#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 9426#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 9427//MC_VM_FB_SIZE_OFFSET_VF7 9428#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 9429#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 9430#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 9431#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 9432//MC_VM_FB_SIZE_OFFSET_VF8 9433#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 9434#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 9435#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 9436#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 9437//MC_VM_FB_SIZE_OFFSET_VF9 9438#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 9439#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 9440#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 9441#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 9442//MC_VM_FB_SIZE_OFFSET_VF10 9443#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 9444#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 9445#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 9446#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 9447//MC_VM_FB_SIZE_OFFSET_VF11 9448#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 9449#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 9450#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 9451#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 9452//MC_VM_FB_SIZE_OFFSET_VF12 9453#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 9454#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 9455#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 9456#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 9457//MC_VM_FB_SIZE_OFFSET_VF13 9458#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 9459#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 9460#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 9461#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 9462//MC_VM_FB_SIZE_OFFSET_VF14 9463#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 9464#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 9465#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 9466#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 9467//MC_VM_FB_SIZE_OFFSET_VF15 9468#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 9469#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 9470#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 9471#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 9472//VM_IOMMU_MMIO_CNTRL_1 9473#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 9474#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 9475//MC_VM_MARC_BASE_LO_0 9476#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 9477#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 9478//MC_VM_MARC_BASE_LO_1 9479#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 9480#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 9481//MC_VM_MARC_BASE_LO_2 9482#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 9483#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 9484//MC_VM_MARC_BASE_LO_3 9485#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 9486#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 9487//MC_VM_MARC_BASE_HI_0 9488#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 9489#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 9490//MC_VM_MARC_BASE_HI_1 9491#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 9492#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 9493//MC_VM_MARC_BASE_HI_2 9494#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 9495#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 9496//MC_VM_MARC_BASE_HI_3 9497#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 9498#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 9499//MC_VM_MARC_RELOC_LO_0 9500#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 9501#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 9502#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 9503#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 9504#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 9505#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 9506//MC_VM_MARC_RELOC_LO_1 9507#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 9508#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 9509#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 9510#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 9511#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 9512#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 9513//MC_VM_MARC_RELOC_LO_2 9514#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 9515#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 9516#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 9517#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 9518#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 9519#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 9520//MC_VM_MARC_RELOC_LO_3 9521#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 9522#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 9523#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 9524#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 9525#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 9526#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 9527//MC_VM_MARC_RELOC_HI_0 9528#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 9529#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 9530//MC_VM_MARC_RELOC_HI_1 9531#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 9532#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 9533//MC_VM_MARC_RELOC_HI_2 9534#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 9535#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 9536//MC_VM_MARC_RELOC_HI_3 9537#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 9538#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 9539//MC_VM_MARC_LEN_LO_0 9540#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 9541#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 9542//MC_VM_MARC_LEN_LO_1 9543#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 9544#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 9545//MC_VM_MARC_LEN_LO_2 9546#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 9547#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 9548//MC_VM_MARC_LEN_LO_3 9549#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 9550#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 9551//MC_VM_MARC_LEN_HI_0 9552#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 9553#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 9554//MC_VM_MARC_LEN_HI_1 9555#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 9556#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 9557//MC_VM_MARC_LEN_HI_2 9558#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 9559#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 9560//MC_VM_MARC_LEN_HI_3 9561#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 9562#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 9563//VM_IOMMU_CONTROL_REGISTER 9564#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 9565#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 9566//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 9567#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 9568#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 9569//VM_PCIE_ATS_CNTL 9570#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 9571#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 9572#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 9573#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 9574//VM_PCIE_ATS_CNTL_VF_0 9575#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 9576#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 9577//VM_PCIE_ATS_CNTL_VF_1 9578#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 9579#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 9580//VM_PCIE_ATS_CNTL_VF_2 9581#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 9582#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 9583//VM_PCIE_ATS_CNTL_VF_3 9584#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 9585#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 9586//VM_PCIE_ATS_CNTL_VF_4 9587#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 9588#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 9589//VM_PCIE_ATS_CNTL_VF_5 9590#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 9591#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 9592//VM_PCIE_ATS_CNTL_VF_6 9593#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 9594#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 9595//VM_PCIE_ATS_CNTL_VF_7 9596#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 9597#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 9598//VM_PCIE_ATS_CNTL_VF_8 9599#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 9600#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 9601//VM_PCIE_ATS_CNTL_VF_9 9602#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 9603#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 9604//VM_PCIE_ATS_CNTL_VF_10 9605#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 9606#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 9607//VM_PCIE_ATS_CNTL_VF_11 9608#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 9609#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 9610//VM_PCIE_ATS_CNTL_VF_12 9611#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 9612#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 9613//VM_PCIE_ATS_CNTL_VF_13 9614#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 9615#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 9616//VM_PCIE_ATS_CNTL_VF_14 9617#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 9618#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 9619//VM_PCIE_ATS_CNTL_VF_15 9620#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 9621#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 9622//UTCL2_CGTT_CLK_CTRL 9623#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 9624#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 9625#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 9626#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 9627#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 9628#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 9629#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 9630#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 9631#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 9632#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 9633#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 9634#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 9635 9636 9637// addressBlock: mmhub_utcl2_vmsharedpfdec 9638//MC_VM_NB_MMIOBASE 9639#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 9640#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 9641//MC_VM_NB_MMIOLIMIT 9642#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 9643#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 9644//MC_VM_NB_PCI_CTRL 9645#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 9646#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 9647//MC_VM_NB_PCI_ARB 9648#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 9649#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 9650//MC_VM_NB_TOP_OF_DRAM_SLOT1 9651#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 9652#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 9653//MC_VM_NB_LOWER_TOP_OF_DRAM2 9654#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 9655#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 9656#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 9657#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 9658//MC_VM_NB_UPPER_TOP_OF_DRAM2 9659#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 9660#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 9661//MC_VM_FB_OFFSET 9662#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 9663#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 9664//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 9665#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 9666#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 9667//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 9668#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 9669#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 9670//MC_VM_STEERING 9671#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 9672#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 9673//MC_SHARED_VIRT_RESET_REQ 9674#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 9675#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 9676#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 9677#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 9678//MC_MEM_POWER_LS 9679#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 9680#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 9681#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 9682#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 9683//MC_VM_CACHEABLE_DRAM_ADDRESS_START 9684#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 9685#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 9686//MC_VM_CACHEABLE_DRAM_ADDRESS_END 9687#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 9688#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 9689//MC_VM_APT_CNTL 9690#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 9691#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 9692#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 9693#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 9694//MC_VM_LOCAL_HBM_ADDRESS_START 9695#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 9696#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 9697//MC_VM_LOCAL_HBM_ADDRESS_END 9698#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 9699#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 9700//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 9701#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 9702#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 9703 9704 9705// addressBlock: mmhub_utcl2_vmsharedvcdec 9706//MC_VM_FB_LOCATION_BASE 9707#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 9708#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 9709//MC_VM_FB_LOCATION_TOP 9710#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 9711#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 9712//MC_VM_AGP_TOP 9713#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 9714#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 9715//MC_VM_AGP_BOT 9716#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 9717#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 9718//MC_VM_AGP_BASE 9719#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 9720#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 9721//MC_VM_SYSTEM_APERTURE_LOW_ADDR 9722#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 9723#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 9724//MC_VM_SYSTEM_APERTURE_HIGH_ADDR 9725#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 9726#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 9727//MC_VM_MX_L1_TLB_CNTL 9728#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 9729#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 9730#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 9731#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 9732#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 9733#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 9734#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd 9735#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 9736#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 9737#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 9738#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 9739#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 9740#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L 9741#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L 9742 9743 9744// addressBlock: mmhub_utcl2_atcl2pfcntrdec 9745//ATC_L2_PERFCOUNTER_LO 9746#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 9747#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 9748//ATC_L2_PERFCOUNTER_HI 9749#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 9750#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 9751#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 9752#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 9753 9754 9755// addressBlock: mmhub_utcl2_atcl2pfcntldec 9756//ATC_L2_PERFCOUNTER0_CFG 9757#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 9758#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 9759#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 9760#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 9761#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 9762#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 9763#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 9764#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 9765#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 9766#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 9767//ATC_L2_PERFCOUNTER1_CFG 9768#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 9769#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 9770#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 9771#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 9772#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 9773#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 9774#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 9775#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 9776#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 9777#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 9778//ATC_L2_PERFCOUNTER_RSLT_CNTL 9779#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 9780#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 9781#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 9782#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 9783#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 9784#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 9785#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 9786#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 9787#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 9788#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 9789#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 9790#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 9791 9792#endif 9793