1/* $NetBSD: mmhub_1_0_sh_mask.h,v 1.2 2021/12/18 23:45:16 riastradh Exp $ */ 2 3/* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23#ifndef _mmhub_1_0_SH_MASK_HEADER 24#define _mmhub_1_0_SH_MASK_HEADER 25 26 27// addressBlock: mmhub_dagbdec 28//DAGB0_RDCLI0 29#define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 30#define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31#define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 32#define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 33#define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34#define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 35#define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 36#define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 37#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38#define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 39#define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 40#define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 41#define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 42#define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 43#define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 44#define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 45#define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 46#define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 47#define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 48#define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 49//DAGB0_RDCLI1 50#define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 51#define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 52#define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 53#define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 54#define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 55#define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 56#define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 57#define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 58#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 59#define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 60#define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 61#define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 62#define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 63#define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 64#define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 65#define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 66#define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 67#define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 68#define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 69#define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 70//DAGB0_RDCLI2 71#define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 72#define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 73#define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 74#define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 75#define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 76#define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 77#define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 78#define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 79#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 80#define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 81#define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 82#define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 83#define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 84#define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 85#define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 86#define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 87#define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 88#define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 89#define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 90#define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 91//DAGB0_RDCLI3 92#define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 93#define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 94#define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 95#define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 96#define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 97#define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 98#define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 99#define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 100#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 101#define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 102#define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 103#define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 104#define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 105#define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 106#define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 107#define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 108#define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 109#define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 110#define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 111#define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 112//DAGB0_RDCLI4 113#define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 114#define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 115#define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 116#define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 117#define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 118#define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 119#define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 120#define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 121#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122#define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 123#define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 124#define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 125#define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 126#define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 127#define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 128#define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 129#define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 130#define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 131#define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 132#define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 133//DAGB0_RDCLI5 134#define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 135#define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 136#define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 137#define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 138#define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 139#define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 140#define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 141#define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 142#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 143#define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 144#define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 145#define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 146#define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 147#define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 148#define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 149#define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 150#define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 151#define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 152#define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 153#define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 154//DAGB0_RDCLI6 155#define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 156#define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 157#define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 158#define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 159#define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 160#define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 161#define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 162#define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 163#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 164#define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 165#define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 166#define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 167#define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 168#define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 169#define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 170#define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 171#define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 172#define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 173#define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 174#define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 175//DAGB0_RDCLI7 176#define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 177#define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 178#define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 179#define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 180#define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 181#define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 182#define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 183#define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 184#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 185#define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 186#define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 187#define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 188#define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 189#define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 190#define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 191#define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 192#define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 193#define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 194#define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 195#define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 196//DAGB0_RDCLI8 197#define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 198#define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 199#define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 200#define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 201#define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 202#define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 203#define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 204#define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 205#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 206#define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 207#define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 208#define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 209#define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 210#define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 211#define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 212#define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 213#define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 214#define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 215#define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 216#define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 217//DAGB0_RDCLI9 218#define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 219#define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 220#define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 221#define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 222#define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 223#define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 224#define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 225#define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 226#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 227#define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 228#define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 229#define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 230#define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 231#define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 232#define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 233#define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 234#define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 235#define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 236#define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 237#define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 238//DAGB0_RDCLI10 239#define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 240#define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 241#define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 242#define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 243#define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 244#define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 245#define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 246#define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 247#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 248#define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 249#define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 250#define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 251#define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 252#define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 253#define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 254#define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 255#define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 256#define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 257#define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 258#define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 259//DAGB0_RDCLI11 260#define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 261#define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 262#define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 263#define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 264#define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 265#define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 266#define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 267#define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 268#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 269#define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 270#define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 271#define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 272#define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 273#define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 274#define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 275#define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 276#define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 277#define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 278#define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 279#define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 280//DAGB0_RDCLI12 281#define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 282#define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 283#define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 284#define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 285#define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 286#define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 287#define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 288#define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 289#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 290#define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 291#define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 292#define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 293#define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 294#define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 295#define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 296#define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 297#define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 298#define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 299#define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 300#define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 301//DAGB0_RDCLI13 302#define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 303#define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 304#define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 305#define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 306#define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 307#define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 308#define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 309#define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 310#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 311#define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 312#define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 313#define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 314#define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 315#define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 316#define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 317#define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 318#define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 319#define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 320#define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 321#define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 322//DAGB0_RDCLI14 323#define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 324#define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 325#define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 326#define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 327#define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 328#define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 329#define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 330#define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 331#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 332#define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 333#define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 334#define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 335#define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 336#define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 337#define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 338#define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 339#define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 340#define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 341#define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 342#define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 343//DAGB0_RDCLI15 344#define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 345#define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 346#define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 347#define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 348#define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 349#define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 350#define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 351#define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 352#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 353#define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 354#define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 355#define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 356#define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 357#define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 358#define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 359#define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 360#define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 361#define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 362#define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 363#define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 364//DAGB0_RD_CNTL 365#define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 366#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 367#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 368#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 369#define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 370#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 371#define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 372#define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 373#define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 374#define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 375#define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 376#define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 377#define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 378#define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 379//DAGB0_RD_GMI_CNTL 380#define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 381#define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 382#define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 383#define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 384#define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 385#define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 386#define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 387#define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 388//DAGB0_RD_ADDR_DAGB 389#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 390#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 391#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 392#define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 393#define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 394#define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 395#define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 396#define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 397//DAGB0_RD_OUTPUT_DAGB_MAX_BURST 398#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 399#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 400#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 401#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 402#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 403#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 404#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 405#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 406#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 407#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 408#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 409#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 410#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 411#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 412#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 413#define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 414//DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 415#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 416#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 417#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 418#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 419#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 420#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 421#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 422#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 423#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 424#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 425#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 426#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 427#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 428#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 429#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 430#define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 431//DAGB0_RD_CGTT_CLK_CTRL 432#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 433#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 434#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 435#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 436#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 437#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 438#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 439#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 440#define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 441#define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 442#define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 443#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 444#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 445#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 446#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 447#define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 448//DAGB0_L1TLB_RD_CGTT_CLK_CTRL 449#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 450#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 451#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 452#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 453#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 454#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 455#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 456#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 457#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 458#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 459#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 460#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 461#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 462#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 463#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 464#define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 465//DAGB0_ATCVM_RD_CGTT_CLK_CTRL 466#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 467#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 468#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 469#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 470#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 471#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 472#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 473#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 474#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 475#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 476#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 477#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 478#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 479#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 480#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 481#define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 482//DAGB0_RD_ADDR_DAGB_MAX_BURST0 483#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 484#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 485#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 486#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 487#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 488#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 489#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 490#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 491#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 492#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 493#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 494#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 495#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 496#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 497#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 498#define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 499//DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 500#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 501#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 502#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 503#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 504#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 505#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 506#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 507#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 508#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 509#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 510#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 511#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 512#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 513#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 514#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 515#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 516//DAGB0_RD_ADDR_DAGB_MAX_BURST1 517#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 518#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 519#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 520#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 521#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 522#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 523#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 524#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 525#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 526#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 527#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 528#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 529#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 530#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 531#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 532#define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 533//DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 534#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 535#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 536#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 537#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 538#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 539#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 540#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 541#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 542#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 543#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 544#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 545#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 546#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 547#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 548#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 549#define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 550//DAGB0_RD_VC0_CNTL 551#define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 552#define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 553#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 554#define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 555#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 556#define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 557#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 558#define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 559#define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 560#define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 561#define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 562#define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 563#define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 564#define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 565#define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 566#define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 567//DAGB0_RD_VC1_CNTL 568#define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 569#define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 570#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 571#define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 572#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 573#define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 574#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 575#define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 576#define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 577#define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 578#define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 579#define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 580#define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 581#define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 582#define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 583#define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 584//DAGB0_RD_VC2_CNTL 585#define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 586#define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 587#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 588#define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 589#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 590#define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 591#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 592#define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 593#define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 594#define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 595#define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 596#define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 597#define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 598#define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 599#define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 600#define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 601//DAGB0_RD_VC3_CNTL 602#define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 603#define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 604#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 605#define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 606#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 607#define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 608#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 609#define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 610#define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 611#define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 612#define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 613#define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 614#define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 615#define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 616#define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 617#define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 618//DAGB0_RD_VC4_CNTL 619#define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 620#define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 621#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 622#define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 623#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 624#define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 625#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 626#define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 627#define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 628#define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 629#define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 630#define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 631#define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 632#define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 633#define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 634#define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 635//DAGB0_RD_VC5_CNTL 636#define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 637#define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 638#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 639#define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 640#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 641#define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 642#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 643#define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 644#define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 645#define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 646#define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 647#define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 648#define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 649#define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 650#define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 651#define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 652//DAGB0_RD_VC6_CNTL 653#define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 654#define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 655#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 656#define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 657#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 658#define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 659#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 660#define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 661#define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 662#define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 663#define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 664#define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 665#define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 666#define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 667#define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 668#define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 669//DAGB0_RD_VC7_CNTL 670#define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 671#define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 672#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 673#define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 674#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 675#define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 676#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 677#define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 678#define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 679#define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 680#define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 681#define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 682#define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 683#define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 684#define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 685#define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 686//DAGB0_RD_CNTL_MISC 687#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 688#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 689#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 690#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 691#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 692#define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 693#define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 694#define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 695#define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 696#define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 697#define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 698#define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 699//DAGB0_RD_TLB_CREDIT 700#define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 701#define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 702#define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 703#define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 704#define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 705#define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 706#define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 707#define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 708#define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 709#define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 710#define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 711#define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 712//DAGB0_RDCLI_ASK_PENDING 713#define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 714#define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 715//DAGB0_RDCLI_GO_PENDING 716#define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 717#define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 718//DAGB0_RDCLI_GBLSEND_PENDING 719#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 720#define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 721//DAGB0_RDCLI_TLB_PENDING 722#define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 723#define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 724//DAGB0_RDCLI_OARB_PENDING 725#define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 726#define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 727//DAGB0_RDCLI_OSD_PENDING 728#define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 729#define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 730//DAGB0_WRCLI0 731#define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 732#define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 733#define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 734#define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 735#define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 736#define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 737#define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 738#define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 739#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 740#define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 741#define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 742#define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 743#define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 744#define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 745#define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 746#define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 747#define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 748#define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 749#define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 750#define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 751//DAGB0_WRCLI1 752#define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 753#define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 754#define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 755#define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 756#define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 757#define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 758#define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 759#define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 760#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 761#define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 762#define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 763#define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 764#define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 765#define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 766#define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 767#define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 768#define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 769#define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 770#define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 771#define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 772//DAGB0_WRCLI2 773#define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 774#define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 775#define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 776#define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 777#define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 778#define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 779#define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 780#define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 781#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 782#define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 783#define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 784#define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 785#define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 786#define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 787#define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 788#define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 789#define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 790#define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 791#define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 792#define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 793//DAGB0_WRCLI3 794#define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 795#define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 796#define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 797#define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 798#define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 799#define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 800#define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 801#define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 802#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 803#define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 804#define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 805#define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 806#define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 807#define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 808#define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 809#define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 810#define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 811#define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 812#define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 813#define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 814//DAGB0_WRCLI4 815#define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 816#define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 817#define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 818#define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 819#define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 820#define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 821#define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 822#define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 823#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 824#define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 825#define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 826#define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 827#define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 828#define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 829#define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 830#define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 831#define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 832#define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 833#define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 834#define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 835//DAGB0_WRCLI5 836#define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 837#define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 838#define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 839#define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 840#define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 841#define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 842#define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 843#define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 844#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 845#define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 846#define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 847#define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 848#define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 849#define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 850#define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 851#define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 852#define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 853#define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 854#define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 855#define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 856//DAGB0_WRCLI6 857#define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 858#define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 859#define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 860#define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 861#define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 862#define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 863#define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 864#define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 865#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 866#define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 867#define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 868#define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 869#define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 870#define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 871#define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 872#define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 873#define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 874#define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 875#define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 876#define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 877//DAGB0_WRCLI7 878#define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 879#define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 880#define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 881#define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 882#define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 883#define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 884#define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 885#define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 886#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 887#define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 888#define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 889#define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 890#define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 891#define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 892#define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 893#define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 894#define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 895#define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 896#define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 897#define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 898//DAGB0_WRCLI8 899#define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 900#define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 901#define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 902#define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 903#define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 904#define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 905#define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 906#define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 907#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 908#define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 909#define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 910#define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 911#define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 912#define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 913#define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 914#define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 915#define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 916#define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 917#define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 918#define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 919//DAGB0_WRCLI9 920#define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 921#define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 922#define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 923#define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 924#define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 925#define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 926#define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 927#define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 928#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 929#define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 930#define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 931#define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 932#define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 933#define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 934#define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 935#define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 936#define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 937#define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 938#define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 939#define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 940//DAGB0_WRCLI10 941#define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 942#define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 943#define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 944#define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 945#define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 946#define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 947#define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 948#define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 949#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 950#define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 951#define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 952#define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 953#define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 954#define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 955#define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 956#define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 957#define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 958#define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 959#define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 960#define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 961//DAGB0_WRCLI11 962#define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 963#define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 964#define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 965#define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 966#define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 967#define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 968#define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 969#define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 970#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 971#define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 972#define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 973#define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 974#define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 975#define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 976#define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 977#define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 978#define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 979#define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 980#define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 981#define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 982//DAGB0_WRCLI12 983#define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 984#define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 985#define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 986#define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 987#define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 988#define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 989#define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 990#define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 991#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 992#define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 993#define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 994#define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 995#define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 996#define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 997#define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 998#define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 999#define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1000#define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1001#define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1002#define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1003//DAGB0_WRCLI13 1004#define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1005#define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1006#define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1007#define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1008#define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1009#define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1010#define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1011#define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1012#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1013#define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1014#define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1015#define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1016#define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1017#define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1018#define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1019#define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1020#define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1021#define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1022#define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1023#define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1024//DAGB0_WRCLI14 1025#define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1026#define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1027#define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1028#define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1029#define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1030#define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1031#define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1032#define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1033#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1034#define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1035#define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1036#define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1037#define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1038#define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1039#define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1040#define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1041#define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1042#define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1043#define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1044#define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1045//DAGB0_WRCLI15 1046#define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1047#define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1048#define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1049#define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1050#define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1051#define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1052#define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1053#define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1054#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1055#define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1056#define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1057#define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1058#define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1059#define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1060#define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1061#define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1062#define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1063#define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1064#define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1065#define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1066//DAGB0_WR_CNTL 1067#define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 1068#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 1069#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 1070#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 1071#define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 1072#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 1073#define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 1074#define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 1075#define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 1076#define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 1077#define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 1078#define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 1079#define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 1080#define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 1081//DAGB0_WR_GMI_CNTL 1082#define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 1083#define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 1084#define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 1085#define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 1086#define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 1087#define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 1088#define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 1089#define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 1090//DAGB0_WR_ADDR_DAGB 1091#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1092#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1093#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1094#define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1095#define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1096#define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1097#define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1098#define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1099//DAGB0_WR_OUTPUT_DAGB_MAX_BURST 1100#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 1101#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 1102#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 1103#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 1104#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 1105#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 1106#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 1107#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 1108#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 1109#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 1110#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 1111#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 1112#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 1113#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 1114#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 1115#define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 1116//DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 1117#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 1118#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 1119#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 1120#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 1121#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 1122#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 1123#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 1124#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 1125#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 1126#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 1127#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 1128#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 1129#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 1130#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 1131#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 1132#define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 1133//DAGB0_WR_CGTT_CLK_CTRL 1134#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1135#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1136#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1137#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1138#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1139#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1140#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1141#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1142#define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1143#define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1144#define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1145#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1146#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1147#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1148#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1149#define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1150//DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1151#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1152#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1153#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1154#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1155#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1156#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1157#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1158#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1159#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1160#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1161#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1162#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1163#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1164#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1165#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1166#define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1167//DAGB0_ATCVM_WR_CGTT_CLK_CTRL 1168#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1169#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1170#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1171#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1172#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1173#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1174#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1175#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1176#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1177#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1178#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1179#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1180#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1181#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1182#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1183#define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1184//DAGB0_WR_ADDR_DAGB_MAX_BURST0 1185#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1186#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1187#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1188#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1189#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1190#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1191#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1192#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1193#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1194#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1195#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1196#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1197#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1198#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1199#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1200#define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1201//DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1202#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1203#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1204#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1205#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1206#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1207#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1208#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1209#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1210#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1211#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1212#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1213#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1214#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1215#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1216#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1217#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1218//DAGB0_WR_ADDR_DAGB_MAX_BURST1 1219#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1220#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1221#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1222#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1223#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1224#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1225#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1226#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1227#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1228#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1229#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1230#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1231#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1232#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1233#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1234#define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1235//DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1236#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1237#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1238#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1239#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1240#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1241#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1242#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1243#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1244#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1245#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1246#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1247#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1248#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1249#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1250#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1251#define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1252//DAGB0_WR_DATA_DAGB 1253#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1254#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1255#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1256#define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1257#define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1258#define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1259#define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1260#define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1261//DAGB0_WR_DATA_DAGB_MAX_BURST0 1262#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1263#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1264#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1265#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1266#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1267#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1268#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1269#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1270#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1271#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1272#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1273#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1274#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1275#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1276#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1277#define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1278//DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1279#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1280#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1281#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1282#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1283#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1284#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1285#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1286#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1287#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1288#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1289#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1290#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1291#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1292#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1293#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1294#define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1295//DAGB0_WR_DATA_DAGB_MAX_BURST1 1296#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1297#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1298#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1299#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1300#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1301#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1302#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1303#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1304#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1305#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1306#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1307#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1308#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1309#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1310#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1311#define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1312//DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1313#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1314#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1315#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1316#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1317#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1318#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1319#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1320#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1321#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1322#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1323#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1324#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1325#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1326#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1327#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1328#define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1329//DAGB0_WR_VC0_CNTL 1330#define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 1331#define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 1332#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1333#define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 1334#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1335#define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 1336#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1337#define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 1338#define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 1339#define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 1340#define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1341#define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 1342#define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1343#define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 1344#define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1345#define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 1346//DAGB0_WR_VC1_CNTL 1347#define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 1348#define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 1349#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1350#define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 1351#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1352#define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 1353#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1354#define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 1355#define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 1356#define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 1357#define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1358#define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 1359#define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1360#define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 1361#define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1362#define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 1363//DAGB0_WR_VC2_CNTL 1364#define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 1365#define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 1366#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1367#define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 1368#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1369#define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 1370#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1371#define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 1372#define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 1373#define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 1374#define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1375#define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1376#define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1377#define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1378#define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1379#define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1380//DAGB0_WR_VC3_CNTL 1381#define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1382#define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 1383#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1384#define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 1385#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1386#define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 1387#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1388#define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 1389#define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1390#define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 1391#define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1392#define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1393#define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1394#define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1395#define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1396#define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1397//DAGB0_WR_VC4_CNTL 1398#define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1399#define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 1400#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1401#define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 1402#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1403#define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 1404#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1405#define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 1406#define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1407#define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 1408#define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1409#define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1410#define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1411#define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1412#define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1413#define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1414//DAGB0_WR_VC5_CNTL 1415#define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1416#define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 1417#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1418#define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 1419#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1420#define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 1421#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1422#define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 1423#define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1424#define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 1425#define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1426#define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1427#define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1428#define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1429#define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1430#define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1431//DAGB0_WR_VC6_CNTL 1432#define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 1433#define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 1434#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1435#define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 1436#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1437#define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 1438#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1439#define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 1440#define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 1441#define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 1442#define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1443#define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 1444#define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1445#define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 1446#define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1447#define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 1448//DAGB0_WR_VC7_CNTL 1449#define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 1450#define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 1451#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1452#define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 1453#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1454#define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 1455#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1456#define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 1457#define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 1458#define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 1459#define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1460#define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 1461#define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1462#define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 1463#define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1464#define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 1465//DAGB0_WR_CNTL_MISC 1466#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1467#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 1468#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 1469#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 1470#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 1471#define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 1472#define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1473#define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 1474#define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 1475#define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 1476#define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 1477#define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 1478//DAGB0_WR_TLB_CREDIT 1479#define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 1480#define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 1481#define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1482#define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 1483#define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 1484#define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 1485#define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 1486#define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 1487#define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 1488#define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 1489#define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 1490#define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 1491//DAGB0_WR_DATA_CREDIT 1492#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 1493#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 1494#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 1495#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 1496#define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 1497#define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 1498#define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 1499#define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 1500//DAGB0_WR_MISC_CREDIT 1501#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 1502#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 1503#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 1504#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 1505#define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 1506#define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 1507#define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 1508#define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 1509//DAGB0_WRCLI_ASK_PENDING 1510#define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 1511#define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1512//DAGB0_WRCLI_GO_PENDING 1513#define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 1514#define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1515//DAGB0_WRCLI_GBLSEND_PENDING 1516#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1517#define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1518//DAGB0_WRCLI_TLB_PENDING 1519#define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 1520#define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1521//DAGB0_WRCLI_OARB_PENDING 1522#define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 1523#define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1524//DAGB0_WRCLI_OSD_PENDING 1525#define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 1526#define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1527//DAGB0_WRCLI_DBUS_ASK_PENDING 1528#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 1529#define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1530//DAGB0_WRCLI_DBUS_GO_PENDING 1531#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 1532#define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1533//DAGB0_DAGB_DLY 1534#define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 1535#define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 1536#define DAGB0_DAGB_DLY__POS__SHIFT 0x10 1537#define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 1538#define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 1539#define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 1540//DAGB0_CNTL_MISC 1541#define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 1542#define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 1543#define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 1544#define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 1545#define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 1546#define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 1547#define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 1548#define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 1549#define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 1550#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 1551#define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 1552#define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 1553#define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 1554#define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 1555#define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 1556#define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 1557#define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 1558#define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 1559#define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 1560#define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 1561//DAGB0_CNTL_MISC2 1562#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 1563#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 1564#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 1565#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 1566#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 1567#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 1568#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 1569#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 1570#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 1571#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 1572#define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 1573#define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 1574#define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 1575#define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 1576#define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 1577#define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 1578#define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 1579#define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 1580#define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 1581#define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 1582#define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 1583#define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 1584//DAGB0_FIFO_EMPTY 1585#define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 1586#define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 1587//DAGB0_FIFO_FULL 1588#define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 1589#define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL 1590//DAGB0_WR_CREDITS_FULL 1591#define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 1592#define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL 1593//DAGB0_RD_CREDITS_FULL 1594#define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 1595#define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 1596//DAGB0_PERFCOUNTER_LO 1597#define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1598#define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1599//DAGB0_PERFCOUNTER_HI 1600#define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1601#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1602#define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1603#define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1604//DAGB0_PERFCOUNTER0_CFG 1605#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1606#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1607#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1608#define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1609#define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1610#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1611#define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1612#define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1613#define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1614#define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1615//DAGB0_PERFCOUNTER1_CFG 1616#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1617#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1618#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1619#define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1620#define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1621#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1622#define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1623#define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1624#define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1625#define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1626//DAGB0_PERFCOUNTER2_CFG 1627#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1628#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1629#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1630#define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1631#define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1632#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1633#define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1634#define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1635#define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1636#define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1637//DAGB0_PERFCOUNTER_RSLT_CNTL 1638#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1639#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1640#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1641#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1642#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1643#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1644#define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1645#define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1646#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1647#define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1648#define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1649#define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1650//DAGB0_RESERVE0 1651#define DAGB0_RESERVE0__RESERVE__SHIFT 0x0 1652#define DAGB0_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 1653//DAGB0_RESERVE1 1654#define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 1655#define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 1656//DAGB0_RESERVE2 1657#define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 1658#define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 1659//DAGB0_RESERVE3 1660#define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 1661#define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 1662//DAGB0_RESERVE4 1663#define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 1664#define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 1665//DAGB0_RESERVE5 1666#define DAGB0_RESERVE5__RESERVE__SHIFT 0x0 1667#define DAGB0_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 1668//DAGB0_RESERVE6 1669#define DAGB0_RESERVE6__RESERVE__SHIFT 0x0 1670#define DAGB0_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 1671//DAGB0_RESERVE7 1672#define DAGB0_RESERVE7__RESERVE__SHIFT 0x0 1673#define DAGB0_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 1674//DAGB0_RESERVE8 1675#define DAGB0_RESERVE8__RESERVE__SHIFT 0x0 1676#define DAGB0_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 1677//DAGB0_RESERVE9 1678#define DAGB0_RESERVE9__RESERVE__SHIFT 0x0 1679#define DAGB0_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 1680//DAGB0_RESERVE10 1681#define DAGB0_RESERVE10__RESERVE__SHIFT 0x0 1682#define DAGB0_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 1683//DAGB0_RESERVE11 1684#define DAGB0_RESERVE11__RESERVE__SHIFT 0x0 1685#define DAGB0_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 1686//DAGB0_RESERVE12 1687#define DAGB0_RESERVE12__RESERVE__SHIFT 0x0 1688#define DAGB0_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 1689//DAGB0_RESERVE13 1690#define DAGB0_RESERVE13__RESERVE__SHIFT 0x0 1691#define DAGB0_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 1692//DAGB0_RESERVE14 1693#define DAGB0_RESERVE14__RESERVE__SHIFT 0x0 1694#define DAGB0_RESERVE14__RESERVE_MASK 0xFFFFFFFFL 1695//DAGB0_RESERVE15 1696#define DAGB0_RESERVE15__RESERVE__SHIFT 0x0 1697#define DAGB0_RESERVE15__RESERVE_MASK 0xFFFFFFFFL 1698//DAGB0_RESERVE16 1699#define DAGB0_RESERVE16__RESERVE__SHIFT 0x0 1700#define DAGB0_RESERVE16__RESERVE_MASK 0xFFFFFFFFL 1701//DAGB0_RESERVE17 1702#define DAGB0_RESERVE17__RESERVE__SHIFT 0x0 1703#define DAGB0_RESERVE17__RESERVE_MASK 0xFFFFFFFFL 1704//DAGB1_RDCLI0 1705#define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 1706#define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 1707#define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 1708#define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 1709#define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 1710#define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd 1711#define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 1712#define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 1713#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 1714#define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a 1715#define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L 1716#define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 1717#define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L 1718#define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L 1719#define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 1720#define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L 1721#define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 1722#define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L 1723#define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 1724#define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L 1725//DAGB1_RDCLI1 1726#define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 1727#define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 1728#define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 1729#define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 1730#define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 1731#define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd 1732#define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 1733#define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 1734#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 1735#define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a 1736#define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L 1737#define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 1738#define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L 1739#define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L 1740#define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 1741#define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L 1742#define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 1743#define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L 1744#define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 1745#define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L 1746//DAGB1_RDCLI2 1747#define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 1748#define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 1749#define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 1750#define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 1751#define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 1752#define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd 1753#define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 1754#define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 1755#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 1756#define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a 1757#define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L 1758#define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 1759#define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L 1760#define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L 1761#define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 1762#define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L 1763#define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 1764#define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L 1765#define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 1766#define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L 1767//DAGB1_RDCLI3 1768#define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 1769#define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 1770#define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 1771#define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 1772#define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 1773#define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd 1774#define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 1775#define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 1776#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 1777#define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a 1778#define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L 1779#define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 1780#define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L 1781#define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L 1782#define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 1783#define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L 1784#define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 1785#define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L 1786#define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 1787#define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L 1788//DAGB1_RDCLI4 1789#define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 1790#define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 1791#define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 1792#define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 1793#define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 1794#define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd 1795#define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 1796#define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 1797#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 1798#define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a 1799#define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L 1800#define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 1801#define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L 1802#define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L 1803#define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 1804#define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L 1805#define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 1806#define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L 1807#define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 1808#define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L 1809//DAGB1_RDCLI5 1810#define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 1811#define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1812#define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 1813#define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 1814#define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 1815#define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd 1816#define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 1817#define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 1818#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1819#define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a 1820#define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L 1821#define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1822#define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L 1823#define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L 1824#define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1825#define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L 1826#define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1827#define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L 1828#define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1829#define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L 1830//DAGB1_RDCLI6 1831#define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 1832#define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1833#define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 1834#define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 1835#define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 1836#define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd 1837#define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 1838#define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 1839#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1840#define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a 1841#define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L 1842#define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1843#define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L 1844#define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L 1845#define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1846#define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L 1847#define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1848#define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L 1849#define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1850#define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L 1851//DAGB1_RDCLI7 1852#define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 1853#define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1854#define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 1855#define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 1856#define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 1857#define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd 1858#define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 1859#define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 1860#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1861#define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a 1862#define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L 1863#define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1864#define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L 1865#define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L 1866#define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1867#define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L 1868#define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1869#define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L 1870#define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1871#define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L 1872//DAGB1_RDCLI8 1873#define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 1874#define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1875#define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 1876#define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 1877#define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 1878#define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd 1879#define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 1880#define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 1881#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1882#define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a 1883#define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L 1884#define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1885#define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L 1886#define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L 1887#define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1888#define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L 1889#define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 1890#define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L 1891#define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 1892#define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L 1893//DAGB1_RDCLI9 1894#define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 1895#define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 1896#define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 1897#define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 1898#define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 1899#define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd 1900#define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 1901#define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 1902#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 1903#define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a 1904#define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L 1905#define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 1906#define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L 1907#define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L 1908#define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 1909#define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L 1910#define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 1911#define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L 1912#define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 1913#define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L 1914//DAGB1_RDCLI10 1915#define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 1916#define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 1917#define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 1918#define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 1919#define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 1920#define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd 1921#define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 1922#define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 1923#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 1924#define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a 1925#define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L 1926#define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 1927#define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L 1928#define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L 1929#define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 1930#define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L 1931#define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 1932#define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L 1933#define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 1934#define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L 1935//DAGB1_RDCLI11 1936#define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 1937#define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 1938#define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 1939#define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 1940#define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 1941#define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd 1942#define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 1943#define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 1944#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 1945#define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a 1946#define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L 1947#define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1948#define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L 1949#define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L 1950#define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1951#define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L 1952#define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1953#define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L 1954#define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1955#define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L 1956//DAGB1_RDCLI12 1957#define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 1958#define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1959#define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 1960#define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 1961#define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 1962#define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd 1963#define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 1964#define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 1965#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1966#define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a 1967#define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L 1968#define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1969#define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L 1970#define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L 1971#define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1972#define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L 1973#define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1974#define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L 1975#define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1976#define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L 1977//DAGB1_RDCLI13 1978#define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 1979#define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1980#define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 1981#define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 1982#define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 1983#define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd 1984#define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 1985#define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 1986#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1987#define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a 1988#define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L 1989#define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1990#define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L 1991#define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L 1992#define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1993#define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L 1994#define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1995#define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L 1996#define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1997#define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L 1998//DAGB1_RDCLI14 1999#define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 2000#define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 2001#define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 2002#define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 2003#define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 2004#define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd 2005#define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 2006#define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 2007#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2008#define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a 2009#define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L 2010#define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2011#define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L 2012#define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L 2013#define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2014#define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L 2015#define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2016#define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L 2017#define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2018#define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L 2019//DAGB1_RDCLI15 2020#define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 2021#define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2022#define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 2023#define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 2024#define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 2025#define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd 2026#define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 2027#define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 2028#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2029#define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a 2030#define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L 2031#define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2032#define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L 2033#define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L 2034#define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2035#define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L 2036#define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2037#define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L 2038#define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2039#define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L 2040//DAGB1_RD_CNTL 2041#define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0 2042#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 2043#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 2044#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 2045#define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11 2046#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 2047#define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 2048#define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 2049#define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 2050#define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 2051#define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 2052#define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 2053#define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 2054#define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 2055//DAGB1_RD_GMI_CNTL 2056#define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 2057#define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6 2058#define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 2059#define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 2060#define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 2061#define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 2062#define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 2063#define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 2064//DAGB1_RD_ADDR_DAGB 2065#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2066#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2067#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2068#define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 2069#define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2070#define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2071#define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2072#define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2073//DAGB1_RD_OUTPUT_DAGB_MAX_BURST 2074#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 2075#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 2076#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 2077#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 2078#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 2079#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 2080#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 2081#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 2082#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 2083#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 2084#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 2085#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 2086#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 2087#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 2088#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 2089#define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 2090//DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 2091#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 2092#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 2093#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 2094#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 2095#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 2096#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 2097#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 2098#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 2099#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 2100#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 2101#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 2102#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 2103#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 2104#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 2105#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 2106#define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 2107//DAGB1_RD_CGTT_CLK_CTRL 2108#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2109#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2110#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2111#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2112#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2113#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2114#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2115#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2116#define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2117#define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2118#define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2119#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2120#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2121#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2122#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2123#define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2124//DAGB1_L1TLB_RD_CGTT_CLK_CTRL 2125#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2126#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2127#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2128#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2129#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2130#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2131#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2132#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2133#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2134#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2135#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2136#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2137#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2138#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2139#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2140#define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2141//DAGB1_ATCVM_RD_CGTT_CLK_CTRL 2142#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2143#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2144#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2145#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2146#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2147#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2148#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2149#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2150#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2151#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2152#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2153#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2154#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2155#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2156#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2157#define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2158//DAGB1_RD_ADDR_DAGB_MAX_BURST0 2159#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2160#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2161#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2162#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2163#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2164#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2165#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2166#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2167#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2168#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2169#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2170#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2171#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2172#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2173#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2174#define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2175//DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 2176#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2177#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2178#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2179#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2180#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2181#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2182#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2183#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2184#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2185#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2186#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2187#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2188#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2189#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2190#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2191#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2192//DAGB1_RD_ADDR_DAGB_MAX_BURST1 2193#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2194#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2195#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2196#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2197#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2198#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2199#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2200#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2201#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2202#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2203#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2204#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2205#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2206#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2207#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2208#define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2209//DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 2210#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2211#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2212#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2213#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2214#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2215#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2216#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2217#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2218#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2219#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2220#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2221#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2222#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2223#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2224#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2225#define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2226//DAGB1_RD_VC0_CNTL 2227#define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 2228#define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 2229#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2230#define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 2231#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2232#define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 2233#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2234#define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 2235#define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 2236#define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 2237#define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2238#define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 2239#define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2240#define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 2241#define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2242#define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 2243//DAGB1_RD_VC1_CNTL 2244#define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 2245#define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 2246#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2247#define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 2248#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2249#define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 2250#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2251#define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 2252#define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 2253#define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 2254#define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2255#define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 2256#define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2257#define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 2258#define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2259#define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 2260//DAGB1_RD_VC2_CNTL 2261#define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 2262#define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 2263#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2264#define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 2265#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2266#define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 2267#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2268#define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 2269#define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 2270#define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 2271#define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2272#define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 2273#define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2274#define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 2275#define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2276#define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 2277//DAGB1_RD_VC3_CNTL 2278#define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 2279#define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 2280#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2281#define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 2282#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2283#define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 2284#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2285#define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 2286#define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 2287#define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 2288#define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2289#define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 2290#define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2291#define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 2292#define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2293#define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 2294//DAGB1_RD_VC4_CNTL 2295#define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 2296#define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 2297#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2298#define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 2299#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2300#define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 2301#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2302#define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 2303#define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 2304#define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 2305#define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2306#define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 2307#define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2308#define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 2309#define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2310#define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 2311//DAGB1_RD_VC5_CNTL 2312#define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 2313#define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 2314#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2315#define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 2316#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2317#define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 2318#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2319#define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 2320#define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 2321#define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 2322#define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2323#define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 2324#define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2325#define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 2326#define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2327#define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 2328//DAGB1_RD_VC6_CNTL 2329#define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 2330#define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 2331#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2332#define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 2333#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2334#define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 2335#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2336#define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 2337#define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 2338#define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 2339#define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2340#define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 2341#define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2342#define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 2343#define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2344#define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 2345//DAGB1_RD_VC7_CNTL 2346#define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 2347#define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 2348#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2349#define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 2350#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2351#define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 2352#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2353#define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 2354#define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 2355#define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 2356#define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2357#define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 2358#define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2359#define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 2360#define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2361#define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 2362//DAGB1_RD_CNTL_MISC 2363#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 2364#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 2365#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 2366#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 2367#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 2368#define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 2369#define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 2370#define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 2371#define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 2372#define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 2373#define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 2374#define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 2375//DAGB1_RD_TLB_CREDIT 2376#define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 2377#define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 2378#define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa 2379#define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf 2380#define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 2381#define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 2382#define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 2383#define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 2384#define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 2385#define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 2386#define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 2387#define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 2388//DAGB1_RDCLI_ASK_PENDING 2389#define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 2390#define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2391//DAGB1_RDCLI_GO_PENDING 2392#define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 2393#define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2394//DAGB1_RDCLI_GBLSEND_PENDING 2395#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 2396#define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 2397//DAGB1_RDCLI_TLB_PENDING 2398#define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 2399#define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 2400//DAGB1_RDCLI_OARB_PENDING 2401#define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 2402#define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2403//DAGB1_RDCLI_OSD_PENDING 2404#define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 2405#define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2406//DAGB1_WRCLI0 2407#define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0 2408#define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 2409#define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4 2410#define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8 2411#define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 2412#define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd 2413#define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 2414#define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 2415#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 2416#define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a 2417#define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L 2418#define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 2419#define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L 2420#define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L 2421#define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 2422#define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L 2423#define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 2424#define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L 2425#define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 2426#define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L 2427//DAGB1_WRCLI1 2428#define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0 2429#define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 2430#define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4 2431#define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8 2432#define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 2433#define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd 2434#define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 2435#define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 2436#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 2437#define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a 2438#define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L 2439#define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 2440#define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L 2441#define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L 2442#define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 2443#define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L 2444#define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 2445#define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L 2446#define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 2447#define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L 2448//DAGB1_WRCLI2 2449#define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0 2450#define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 2451#define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4 2452#define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8 2453#define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 2454#define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd 2455#define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 2456#define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 2457#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 2458#define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a 2459#define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L 2460#define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 2461#define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L 2462#define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L 2463#define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 2464#define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L 2465#define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 2466#define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L 2467#define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 2468#define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L 2469//DAGB1_WRCLI3 2470#define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0 2471#define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 2472#define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4 2473#define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8 2474#define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 2475#define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd 2476#define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 2477#define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 2478#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 2479#define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a 2480#define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L 2481#define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 2482#define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L 2483#define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L 2484#define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 2485#define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L 2486#define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 2487#define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L 2488#define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 2489#define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L 2490//DAGB1_WRCLI4 2491#define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0 2492#define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 2493#define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4 2494#define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8 2495#define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 2496#define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd 2497#define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 2498#define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 2499#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 2500#define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a 2501#define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L 2502#define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 2503#define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L 2504#define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L 2505#define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 2506#define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L 2507#define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 2508#define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L 2509#define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 2510#define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L 2511//DAGB1_WRCLI5 2512#define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0 2513#define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 2514#define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4 2515#define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8 2516#define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 2517#define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd 2518#define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 2519#define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 2520#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 2521#define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a 2522#define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L 2523#define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 2524#define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L 2525#define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L 2526#define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 2527#define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L 2528#define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 2529#define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L 2530#define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 2531#define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L 2532//DAGB1_WRCLI6 2533#define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0 2534#define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 2535#define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4 2536#define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8 2537#define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 2538#define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd 2539#define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 2540#define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 2541#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 2542#define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a 2543#define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L 2544#define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 2545#define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L 2546#define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L 2547#define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 2548#define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L 2549#define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 2550#define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L 2551#define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 2552#define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L 2553//DAGB1_WRCLI7 2554#define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0 2555#define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 2556#define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4 2557#define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8 2558#define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 2559#define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd 2560#define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 2561#define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 2562#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 2563#define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a 2564#define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L 2565#define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 2566#define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L 2567#define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L 2568#define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 2569#define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L 2570#define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 2571#define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L 2572#define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 2573#define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L 2574//DAGB1_WRCLI8 2575#define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0 2576#define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 2577#define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4 2578#define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8 2579#define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 2580#define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd 2581#define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 2582#define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 2583#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 2584#define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a 2585#define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L 2586#define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 2587#define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L 2588#define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L 2589#define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 2590#define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L 2591#define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 2592#define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L 2593#define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 2594#define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L 2595//DAGB1_WRCLI9 2596#define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0 2597#define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 2598#define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4 2599#define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8 2600#define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 2601#define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd 2602#define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 2603#define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 2604#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 2605#define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a 2606#define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L 2607#define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 2608#define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L 2609#define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L 2610#define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 2611#define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L 2612#define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 2613#define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L 2614#define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 2615#define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L 2616//DAGB1_WRCLI10 2617#define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0 2618#define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 2619#define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4 2620#define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8 2621#define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 2622#define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd 2623#define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 2624#define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 2625#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 2626#define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a 2627#define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L 2628#define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 2629#define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L 2630#define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L 2631#define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 2632#define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L 2633#define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 2634#define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L 2635#define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 2636#define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L 2637//DAGB1_WRCLI11 2638#define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0 2639#define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 2640#define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4 2641#define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8 2642#define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 2643#define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd 2644#define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 2645#define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 2646#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 2647#define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a 2648#define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L 2649#define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 2650#define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L 2651#define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L 2652#define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 2653#define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L 2654#define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 2655#define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L 2656#define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 2657#define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L 2658//DAGB1_WRCLI12 2659#define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0 2660#define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 2661#define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4 2662#define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8 2663#define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 2664#define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd 2665#define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 2666#define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 2667#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 2668#define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a 2669#define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L 2670#define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 2671#define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L 2672#define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L 2673#define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 2674#define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L 2675#define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 2676#define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L 2677#define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 2678#define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L 2679//DAGB1_WRCLI13 2680#define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0 2681#define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 2682#define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4 2683#define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8 2684#define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 2685#define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd 2686#define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 2687#define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 2688#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 2689#define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a 2690#define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L 2691#define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 2692#define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L 2693#define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L 2694#define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 2695#define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L 2696#define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 2697#define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L 2698#define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 2699#define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L 2700//DAGB1_WRCLI14 2701#define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0 2702#define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 2703#define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4 2704#define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8 2705#define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 2706#define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd 2707#define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 2708#define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 2709#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2710#define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a 2711#define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L 2712#define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2713#define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L 2714#define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L 2715#define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2716#define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L 2717#define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2718#define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L 2719#define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2720#define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L 2721//DAGB1_WRCLI15 2722#define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0 2723#define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2724#define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4 2725#define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8 2726#define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 2727#define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd 2728#define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 2729#define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 2730#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2731#define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a 2732#define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L 2733#define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2734#define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L 2735#define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L 2736#define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2737#define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L 2738#define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2739#define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L 2740#define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2741#define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L 2742//DAGB1_WR_CNTL 2743#define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0 2744#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 2745#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 2746#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 2747#define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11 2748#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 2749#define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 2750#define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 2751#define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 2752#define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 2753#define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 2754#define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 2755#define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 2756#define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 2757//DAGB1_WR_GMI_CNTL 2758#define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 2759#define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6 2760#define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 2761#define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 2762#define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 2763#define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 2764#define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 2765#define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 2766//DAGB1_WR_ADDR_DAGB 2767#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2768#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2769#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2770#define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 2771#define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2772#define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2773#define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2774#define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2775//DAGB1_WR_OUTPUT_DAGB_MAX_BURST 2776#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 2777#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 2778#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 2779#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 2780#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 2781#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 2782#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 2783#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 2784#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 2785#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 2786#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 2787#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 2788#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 2789#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 2790#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 2791#define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 2792//DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 2793#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 2794#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 2795#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 2796#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 2797#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 2798#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 2799#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 2800#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 2801#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 2802#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 2803#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 2804#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 2805#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 2806#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 2807#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 2808#define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 2809//DAGB1_WR_CGTT_CLK_CTRL 2810#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2811#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2812#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2813#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2814#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2815#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2816#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2817#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2818#define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2819#define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2820#define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2821#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2822#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2823#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2824#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2825#define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2826//DAGB1_L1TLB_WR_CGTT_CLK_CTRL 2827#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2828#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2829#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2830#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2831#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2832#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2833#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2834#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2835#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2836#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2837#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2838#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2839#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2840#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2841#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2842#define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2843//DAGB1_ATCVM_WR_CGTT_CLK_CTRL 2844#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2845#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2846#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2847#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2848#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2849#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2850#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2851#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2852#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2853#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2854#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2855#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2856#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2857#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2858#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2859#define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2860//DAGB1_WR_ADDR_DAGB_MAX_BURST0 2861#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2862#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2863#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2864#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2865#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2866#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2867#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2868#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2869#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2870#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2871#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2872#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2873#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2874#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2875#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2876#define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2877//DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 2878#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2879#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2880#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2881#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2882#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2883#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2884#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2885#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2886#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2887#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2888#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2889#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2890#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2891#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2892#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2893#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2894//DAGB1_WR_ADDR_DAGB_MAX_BURST1 2895#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2896#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2897#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2898#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2899#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2900#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2901#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2902#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2903#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2904#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2905#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2906#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2907#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2908#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2909#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2910#define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2911//DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 2912#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2913#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2914#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2915#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2916#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2917#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2918#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2919#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2920#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2921#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2922#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2923#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2924#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2925#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2926#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2927#define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2928//DAGB1_WR_DATA_DAGB 2929#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 2930#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2931#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2932#define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 2933#define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 2934#define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2935#define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2936#define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 2937//DAGB1_WR_DATA_DAGB_MAX_BURST0 2938#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2939#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2940#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2941#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2942#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2943#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2944#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2945#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2946#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2947#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2948#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2949#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2950#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2951#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2952#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2953#define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2954//DAGB1_WR_DATA_DAGB_LAZY_TIMER0 2955#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2956#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2957#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2958#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2959#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2960#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2961#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2962#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2963#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2964#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2965#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2966#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2967#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2968#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2969#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2970#define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2971//DAGB1_WR_DATA_DAGB_MAX_BURST1 2972#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2973#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2974#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2975#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2976#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2977#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2978#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2979#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2980#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2981#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2982#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2983#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2984#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2985#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2986#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2987#define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2988//DAGB1_WR_DATA_DAGB_LAZY_TIMER1 2989#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2990#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2991#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2992#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2993#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2994#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2995#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2996#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2997#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2998#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2999#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 3000#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 3001#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 3002#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 3003#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 3004#define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 3005//DAGB1_WR_VC0_CNTL 3006#define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 3007#define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 3008#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3009#define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 3010#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3011#define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 3012#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3013#define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 3014#define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 3015#define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 3016#define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3017#define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 3018#define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3019#define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 3020#define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3021#define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 3022//DAGB1_WR_VC1_CNTL 3023#define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 3024#define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 3025#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3026#define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 3027#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3028#define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 3029#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3030#define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 3031#define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 3032#define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 3033#define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3034#define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 3035#define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3036#define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 3037#define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3038#define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 3039//DAGB1_WR_VC2_CNTL 3040#define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 3041#define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 3042#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3043#define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 3044#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3045#define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 3046#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3047#define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 3048#define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 3049#define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 3050#define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3051#define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 3052#define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3053#define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 3054#define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3055#define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 3056//DAGB1_WR_VC3_CNTL 3057#define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 3058#define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 3059#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3060#define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 3061#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3062#define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 3063#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3064#define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 3065#define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 3066#define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 3067#define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3068#define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 3069#define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3070#define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 3071#define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3072#define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 3073//DAGB1_WR_VC4_CNTL 3074#define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 3075#define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 3076#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3077#define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 3078#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3079#define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 3080#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3081#define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 3082#define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 3083#define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 3084#define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3085#define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 3086#define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3087#define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 3088#define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3089#define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 3090//DAGB1_WR_VC5_CNTL 3091#define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 3092#define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 3093#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3094#define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 3095#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3096#define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 3097#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3098#define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 3099#define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 3100#define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 3101#define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3102#define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 3103#define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3104#define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 3105#define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3106#define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 3107//DAGB1_WR_VC6_CNTL 3108#define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 3109#define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 3110#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3111#define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 3112#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3113#define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 3114#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3115#define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 3116#define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 3117#define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 3118#define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3119#define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 3120#define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3121#define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 3122#define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3123#define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 3124//DAGB1_WR_VC7_CNTL 3125#define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 3126#define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 3127#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3128#define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 3129#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3130#define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 3131#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3132#define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 3133#define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 3134#define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 3135#define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3136#define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 3137#define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3138#define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 3139#define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3140#define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 3141//DAGB1_WR_CNTL_MISC 3142#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 3143#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 3144#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 3145#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 3146#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 3147#define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 3148#define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 3149#define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 3150#define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 3151#define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 3152#define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 3153#define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 3154//DAGB1_WR_TLB_CREDIT 3155#define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 3156#define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 3157#define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa 3158#define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf 3159#define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14 3160#define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19 3161#define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 3162#define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 3163#define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 3164#define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 3165#define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 3166#define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 3167//DAGB1_WR_DATA_CREDIT 3168#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 3169#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 3170#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 3171#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 3172#define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 3173#define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 3174#define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 3175#define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 3176//DAGB1_WR_MISC_CREDIT 3177#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 3178#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 3179#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 3180#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 3181#define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 3182#define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 3183#define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 3184#define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 3185//DAGB1_WRCLI_ASK_PENDING 3186#define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 3187#define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3188//DAGB1_WRCLI_GO_PENDING 3189#define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 3190#define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3191//DAGB1_WRCLI_GBLSEND_PENDING 3192#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 3193#define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 3194//DAGB1_WRCLI_TLB_PENDING 3195#define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 3196#define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 3197//DAGB1_WRCLI_OARB_PENDING 3198#define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 3199#define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 3200//DAGB1_WRCLI_OSD_PENDING 3201#define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 3202#define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 3203//DAGB1_WRCLI_DBUS_ASK_PENDING 3204#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 3205#define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3206//DAGB1_WRCLI_DBUS_GO_PENDING 3207#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 3208#define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3209//DAGB1_DAGB_DLY 3210#define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 3211#define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 3212#define DAGB1_DAGB_DLY__POS__SHIFT 0x10 3213#define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL 3214#define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L 3215#define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L 3216//DAGB1_CNTL_MISC 3217#define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 3218#define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 3219#define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 3220#define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 3221#define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 3222#define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 3223#define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 3224#define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 3225#define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 3226#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 3227#define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 3228#define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 3229#define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 3230#define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 3231#define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 3232#define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 3233#define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 3234#define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 3235#define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 3236#define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 3237//DAGB1_CNTL_MISC2 3238#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 3239#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 3240#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 3241#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 3242#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 3243#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 3244#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 3245#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 3246#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 3247#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 3248#define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 3249#define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 3250#define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 3251#define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 3252#define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 3253#define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 3254#define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 3255#define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 3256#define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 3257#define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 3258#define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 3259#define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 3260//DAGB1_FIFO_EMPTY 3261#define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 3262#define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 3263//DAGB1_FIFO_FULL 3264#define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 3265#define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL 3266//DAGB1_WR_CREDITS_FULL 3267#define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 3268#define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x0007FFFFL 3269//DAGB1_RD_CREDITS_FULL 3270#define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 3271#define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 3272//DAGB1_PERFCOUNTER_LO 3273#define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3274#define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3275//DAGB1_PERFCOUNTER_HI 3276#define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3277#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3278#define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3279#define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3280//DAGB1_PERFCOUNTER0_CFG 3281#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3282#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3283#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3284#define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3285#define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3286#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3287#define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3288#define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3289#define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3290#define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3291//DAGB1_PERFCOUNTER1_CFG 3292#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3293#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3294#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3295#define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3296#define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3297#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3298#define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3299#define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3300#define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3301#define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3302//DAGB1_PERFCOUNTER2_CFG 3303#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 3304#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 3305#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 3306#define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 3307#define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 3308#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 3309#define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 3310#define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 3311#define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 3312#define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 3313//DAGB1_PERFCOUNTER_RSLT_CNTL 3314#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3315#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3316#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3317#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3318#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3319#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3320#define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 3321#define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3322#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3323#define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3324#define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3325#define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3326//DAGB1_RESERVE0 3327#define DAGB1_RESERVE0__RESERVE__SHIFT 0x0 3328#define DAGB1_RESERVE0__RESERVE_MASK 0xFFFFFFFFL 3329//DAGB1_RESERVE1 3330#define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 3331#define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 3332//DAGB1_RESERVE2 3333#define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 3334#define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 3335//DAGB1_RESERVE3 3336#define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 3337#define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 3338//DAGB1_RESERVE4 3339#define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 3340#define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 3341//DAGB1_RESERVE5 3342#define DAGB1_RESERVE5__RESERVE__SHIFT 0x0 3343#define DAGB1_RESERVE5__RESERVE_MASK 0xFFFFFFFFL 3344//DAGB1_RESERVE6 3345#define DAGB1_RESERVE6__RESERVE__SHIFT 0x0 3346#define DAGB1_RESERVE6__RESERVE_MASK 0xFFFFFFFFL 3347//DAGB1_RESERVE7 3348#define DAGB1_RESERVE7__RESERVE__SHIFT 0x0 3349#define DAGB1_RESERVE7__RESERVE_MASK 0xFFFFFFFFL 3350//DAGB1_RESERVE8 3351#define DAGB1_RESERVE8__RESERVE__SHIFT 0x0 3352#define DAGB1_RESERVE8__RESERVE_MASK 0xFFFFFFFFL 3353//DAGB1_RESERVE9 3354#define DAGB1_RESERVE9__RESERVE__SHIFT 0x0 3355#define DAGB1_RESERVE9__RESERVE_MASK 0xFFFFFFFFL 3356//DAGB1_RESERVE10 3357#define DAGB1_RESERVE10__RESERVE__SHIFT 0x0 3358#define DAGB1_RESERVE10__RESERVE_MASK 0xFFFFFFFFL 3359//DAGB1_RESERVE11 3360#define DAGB1_RESERVE11__RESERVE__SHIFT 0x0 3361#define DAGB1_RESERVE11__RESERVE_MASK 0xFFFFFFFFL 3362//DAGB1_RESERVE12 3363#define DAGB1_RESERVE12__RESERVE__SHIFT 0x0 3364#define DAGB1_RESERVE12__RESERVE_MASK 0xFFFFFFFFL 3365//DAGB1_RESERVE13 3366#define DAGB1_RESERVE13__RESERVE__SHIFT 0x0 3367#define DAGB1_RESERVE13__RESERVE_MASK 0xFFFFFFFFL 3368//DAGB1_RESERVE14 3369#define DAGB1_RESERVE14__RESERVE__SHIFT 0x0 3370#define DAGB1_RESERVE14__RESERVE_MASK 0xFFFFFFFFL 3371//DAGB1_RESERVE15 3372#define DAGB1_RESERVE15__RESERVE__SHIFT 0x0 3373#define DAGB1_RESERVE15__RESERVE_MASK 0xFFFFFFFFL 3374//DAGB1_RESERVE16 3375#define DAGB1_RESERVE16__RESERVE__SHIFT 0x0 3376#define DAGB1_RESERVE16__RESERVE_MASK 0xFFFFFFFFL 3377//DAGB1_RESERVE17 3378#define DAGB1_RESERVE17__RESERVE__SHIFT 0x0 3379#define DAGB1_RESERVE17__RESERVE_MASK 0xFFFFFFFFL 3380 3381 3382// addressBlock: mmhub_ea_mmeadec 3383//MMEA0_DRAM_RD_CLI2GRP_MAP0 3384#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3385#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3386#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3387#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3388#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3389#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3390#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3391#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3392#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3393#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3394#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3395#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3396#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3397#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3398#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3399#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3400#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3401#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3402#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3403#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3404#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3405#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3406#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3407#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3408#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3409#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3410#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3411#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3412#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3413#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3414#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3415#define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3416//MMEA0_DRAM_RD_CLI2GRP_MAP1 3417#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3418#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3419#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3420#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3421#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3422#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3423#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3424#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3425#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3426#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3427#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3428#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3429#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3430#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3431#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3432#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3433#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3434#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3435#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3436#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3437#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3438#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3439#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3440#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3441#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3442#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3443#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3444#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3445#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3446#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3447#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3448#define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3449//MMEA0_DRAM_WR_CLI2GRP_MAP0 3450#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 3451#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 3452#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 3453#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 3454#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 3455#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 3456#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 3457#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 3458#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 3459#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 3460#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 3461#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 3462#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 3463#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 3464#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 3465#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 3466#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 3467#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 3468#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 3469#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 3470#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 3471#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 3472#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 3473#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 3474#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 3475#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 3476#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 3477#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 3478#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 3479#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 3480#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 3481#define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 3482//MMEA0_DRAM_WR_CLI2GRP_MAP1 3483#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 3484#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 3485#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 3486#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 3487#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 3488#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 3489#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 3490#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 3491#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 3492#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 3493#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 3494#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 3495#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 3496#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 3497#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 3498#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 3499#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 3500#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 3501#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 3502#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 3503#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 3504#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 3505#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 3506#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 3507#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 3508#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 3509#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 3510#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 3511#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 3512#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 3513#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 3514#define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 3515//MMEA0_DRAM_RD_GRP2VC_MAP 3516#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 3517#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 3518#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 3519#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 3520#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 3521#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 3522#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 3523#define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 3524//MMEA0_DRAM_WR_GRP2VC_MAP 3525#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 3526#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 3527#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 3528#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 3529#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 3530#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 3531#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 3532#define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 3533//MMEA0_DRAM_RD_LAZY 3534#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 3535#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 3536#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 3537#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 3538#define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 3539#define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 3540#define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 3541#define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 3542//MMEA0_DRAM_WR_LAZY 3543#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 3544#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 3545#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 3546#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 3547#define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 3548#define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 3549#define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 3550#define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 3551//MMEA0_DRAM_RD_CAM_CNTL 3552#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 3553#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 3554#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 3555#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 3556#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 3557#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 3558#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 3559#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 3560#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 3561#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 3562#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 3563#define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 3564#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 3565#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 3566#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 3567#define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 3568//MMEA0_DRAM_WR_CAM_CNTL 3569#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 3570#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 3571#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 3572#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 3573#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 3574#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 3575#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 3576#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 3577#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 3578#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 3579#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 3580#define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 3581#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 3582#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 3583#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 3584#define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 3585//MMEA0_DRAM_PAGE_BURST 3586#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 3587#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 3588#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 3589#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 3590#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 3591#define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 3592#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 3593#define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 3594//MMEA0_DRAM_RD_PRI_AGE 3595#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3596#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3597#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3598#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3599#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3600#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3601#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3602#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3603#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3604#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3605#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3606#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3607#define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3608#define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3609#define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3610#define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3611//MMEA0_DRAM_WR_PRI_AGE 3612#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 3613#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 3614#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 3615#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 3616#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 3617#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 3618#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 3619#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 3620#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 3621#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 3622#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 3623#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 3624#define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 3625#define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 3626#define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 3627#define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 3628//MMEA0_DRAM_RD_PRI_QUEUING 3629#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3630#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3631#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3632#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3633#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3634#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3635#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3636#define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3637//MMEA0_DRAM_WR_PRI_QUEUING 3638#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 3639#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 3640#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 3641#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 3642#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 3643#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 3644#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 3645#define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 3646//MMEA0_DRAM_RD_PRI_FIXED 3647#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3648#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3649#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3650#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3651#define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3652#define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3653#define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3654#define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3655//MMEA0_DRAM_WR_PRI_FIXED 3656#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 3657#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 3658#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 3659#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 3660#define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 3661#define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 3662#define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 3663#define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 3664//MMEA0_DRAM_RD_PRI_URGENCY 3665#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3666#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3667#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3668#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3669#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3670#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3671#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3672#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3673#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3674#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3675#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3676#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3677#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3678#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3679#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3680#define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3681//MMEA0_DRAM_WR_PRI_URGENCY 3682#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 3683#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 3684#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 3685#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 3686#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 3687#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 3688#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 3689#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 3690#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 3691#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 3692#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 3693#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 3694#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 3695#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 3696#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 3697#define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 3698//MMEA0_DRAM_RD_PRI_QUANT_PRI1 3699#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3700#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3701#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3702#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3703#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3704#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3705#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3706#define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3707//MMEA0_DRAM_RD_PRI_QUANT_PRI2 3708#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3709#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3710#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3711#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3712#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3713#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3714#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3715#define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3716//MMEA0_DRAM_RD_PRI_QUANT_PRI3 3717#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3718#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3719#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3720#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3721#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3722#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3723#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3724#define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3725//MMEA0_DRAM_WR_PRI_QUANT_PRI1 3726#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 3727#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 3728#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 3729#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 3730#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 3731#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 3732#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 3733#define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 3734//MMEA0_DRAM_WR_PRI_QUANT_PRI2 3735#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 3736#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 3737#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 3738#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 3739#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 3740#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 3741#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 3742#define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 3743//MMEA0_DRAM_WR_PRI_QUANT_PRI3 3744#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 3745#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 3746#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 3747#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 3748#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 3749#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 3750#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 3751#define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 3752//MMEA0_ADDRNORM_BASE_ADDR0 3753#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 3754#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 3755#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 3756#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 3757#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 3758#define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 3759#define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 3760#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L 3761#define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L 3762#define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 3763//MMEA0_ADDRNORM_LIMIT_ADDR0 3764#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 3765#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 3766#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa 3767#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 3768#define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL 3769#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 3770#define MMEA0_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L 3771#define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 3772//MMEA0_ADDRNORM_BASE_ADDR1 3773#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 3774#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 3775#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 3776#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 3777#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 3778#define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 3779#define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 3780#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L 3781#define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L 3782#define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 3783//MMEA0_ADDRNORM_LIMIT_ADDR1 3784#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 3785#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 3786#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa 3787#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 3788#define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL 3789#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 3790#define MMEA0_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L 3791#define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 3792//MMEA0_ADDRNORM_OFFSET_ADDR1 3793#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 3794#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 3795#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 3796#define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 3797//MMEA0_ADDRNORM_HOLE_CNTL 3798#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 3799#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 3800#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 3801#define MMEA0_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 3802//MMEA0_ADDRDEC_BANK_CFG 3803#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 3804#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 3805#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 3806#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 3807#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 3808#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 3809#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 3810#define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 3811#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 3812#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 3813#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 3814#define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 3815//MMEA0_ADDRDEC_MISC_CFG 3816#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 3817#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 3818#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 3819#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 3820#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 3821#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 3822#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 3823#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 3824#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 3825#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 3826#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 3827#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 3828#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b 3829#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 3830#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 3831#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 3832#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 3833#define MMEA0_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 3834#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 3835#define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 3836#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L 3837#define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L 3838#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L 3839#define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L 3840#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L 3841#define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L 3842//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0 3843#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 3844#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 3845#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 3846#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 3847#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 3848#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 3849//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1 3850#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 3851#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 3852#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 3853#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 3854#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 3855#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 3856//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2 3857#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 3858#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 3859#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 3860#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 3861#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 3862#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 3863//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3 3864#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 3865#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 3866#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 3867#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 3868#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 3869#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 3870//MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4 3871#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 3872#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 3873#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 3874#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 3875#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 3876#define MMEA0_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 3877//MMEA0_ADDRDECDRAM_ADDR_HASH_PC 3878#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 3879#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 3880#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 3881#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 3882#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 3883#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 3884//MMEA0_ADDRDECDRAM_ADDR_HASH_PC2 3885#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 3886#define MMEA0_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 3887//MMEA0_ADDRDECDRAM_ADDR_HASH_CS0 3888#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 3889#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 3890#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 3891#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 3892//MMEA0_ADDRDECDRAM_ADDR_HASH_CS1 3893#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 3894#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 3895#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 3896#define MMEA0_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 3897//MMEA0_ADDRDECDRAM_HARVEST_ENABLE 3898#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 3899#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 3900#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 3901#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 3902#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 3903#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 3904#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 3905#define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 3906//MMEA0_ADDRDEC0_BASE_ADDR_CS0 3907#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 3908#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 3909#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 3910#define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 3911//MMEA0_ADDRDEC0_BASE_ADDR_CS1 3912#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 3913#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 3914#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 3915#define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 3916//MMEA0_ADDRDEC0_BASE_ADDR_CS2 3917#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 3918#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 3919#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 3920#define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 3921//MMEA0_ADDRDEC0_BASE_ADDR_CS3 3922#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 3923#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 3924#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 3925#define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 3926//MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 3927#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 3928#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 3929#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 3930#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 3931//MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 3932#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 3933#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 3934#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 3935#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 3936//MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 3937#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 3938#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 3939#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 3940#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 3941//MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 3942#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 3943#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 3944#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 3945#define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 3946//MMEA0_ADDRDEC0_ADDR_MASK_CS01 3947#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 3948#define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 3949//MMEA0_ADDRDEC0_ADDR_MASK_CS23 3950#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 3951#define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 3952//MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 3953#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 3954#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 3955//MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 3956#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 3957#define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 3958//MMEA0_ADDRDEC0_ADDR_CFG_CS01 3959#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 3960#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 3961#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 3962#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 3963#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 3964#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 3965#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 3966#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 3967#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 3968#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 3969#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 3970#define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 3971//MMEA0_ADDRDEC0_ADDR_CFG_CS23 3972#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 3973#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 3974#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 3975#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 3976#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 3977#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 3978#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 3979#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 3980#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 3981#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 3982#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 3983#define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 3984//MMEA0_ADDRDEC0_ADDR_SEL_CS01 3985#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 3986#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 3987#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 3988#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 3989#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 3990#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 3991#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 3992#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 3993#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 3994#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 3995#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 3996#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 3997#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 3998#define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 3999//MMEA0_ADDRDEC0_ADDR_SEL_CS23 4000#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 4001#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 4002#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 4003#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 4004#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 4005#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 4006#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 4007#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 4008#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 4009#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 4010#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 4011#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 4012#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 4013#define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 4014//MMEA0_ADDRDEC0_COL_SEL_LO_CS01 4015#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 4016#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 4017#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 4018#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 4019#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 4020#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 4021#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 4022#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 4023#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 4024#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 4025#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 4026#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 4027#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 4028#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 4029#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 4030#define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 4031//MMEA0_ADDRDEC0_COL_SEL_LO_CS23 4032#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 4033#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 4034#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 4035#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 4036#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 4037#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 4038#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 4039#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 4040#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 4041#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 4042#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 4043#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 4044#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 4045#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 4046#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 4047#define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 4048//MMEA0_ADDRDEC0_COL_SEL_HI_CS01 4049#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 4050#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 4051#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 4052#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 4053#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 4054#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 4055#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 4056#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 4057#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 4058#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 4059#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 4060#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 4061#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 4062#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 4063#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 4064#define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 4065//MMEA0_ADDRDEC0_COL_SEL_HI_CS23 4066#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 4067#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 4068#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 4069#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 4070#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 4071#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 4072#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 4073#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 4074#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 4075#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 4076#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 4077#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 4078#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 4079#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 4080#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 4081#define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 4082//MMEA0_ADDRDEC0_RM_SEL_CS01 4083#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 4084#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 4085#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 4086#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 4087#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4088#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4089#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 4090#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 4091#define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 4092#define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 4093#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4094#define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4095//MMEA0_ADDRDEC0_RM_SEL_CS23 4096#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 4097#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 4098#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 4099#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 4100#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4101#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4102#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 4103#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 4104#define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 4105#define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 4106#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4107#define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4108//MMEA0_ADDRDEC0_RM_SEL_SECCS01 4109#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 4110#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 4111#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 4112#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 4113#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4114#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4115#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 4116#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 4117#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 4118#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 4119#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4120#define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4121//MMEA0_ADDRDEC0_RM_SEL_SECCS23 4122#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 4123#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 4124#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 4125#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 4126#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4127#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4128#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 4129#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 4130#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 4131#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 4132#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4133#define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4134//MMEA0_ADDRDEC1_BASE_ADDR_CS0 4135#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 4136#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 4137#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 4138#define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 4139//MMEA0_ADDRDEC1_BASE_ADDR_CS1 4140#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 4141#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 4142#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 4143#define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 4144//MMEA0_ADDRDEC1_BASE_ADDR_CS2 4145#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 4146#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 4147#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 4148#define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 4149//MMEA0_ADDRDEC1_BASE_ADDR_CS3 4150#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 4151#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 4152#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 4153#define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 4154//MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 4155#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 4156#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 4157#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 4158#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 4159//MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 4160#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 4161#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 4162#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 4163#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 4164//MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 4165#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 4166#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 4167#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 4168#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 4169//MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 4170#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 4171#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 4172#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 4173#define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 4174//MMEA0_ADDRDEC1_ADDR_MASK_CS01 4175#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 4176#define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 4177//MMEA0_ADDRDEC1_ADDR_MASK_CS23 4178#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 4179#define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 4180//MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 4181#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 4182#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 4183//MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 4184#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 4185#define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 4186//MMEA0_ADDRDEC1_ADDR_CFG_CS01 4187#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 4188#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 4189#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 4190#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 4191#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 4192#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 4193#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 4194#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 4195#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 4196#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 4197#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 4198#define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 4199//MMEA0_ADDRDEC1_ADDR_CFG_CS23 4200#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 4201#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 4202#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 4203#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 4204#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 4205#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 4206#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 4207#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 4208#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 4209#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 4210#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 4211#define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 4212//MMEA0_ADDRDEC1_ADDR_SEL_CS01 4213#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 4214#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 4215#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 4216#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 4217#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 4218#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 4219#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 4220#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 4221#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 4222#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 4223#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 4224#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 4225#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 4226#define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 4227//MMEA0_ADDRDEC1_ADDR_SEL_CS23 4228#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 4229#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 4230#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 4231#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 4232#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 4233#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 4234#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 4235#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 4236#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 4237#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 4238#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 4239#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 4240#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 4241#define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 4242//MMEA0_ADDRDEC1_COL_SEL_LO_CS01 4243#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 4244#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 4245#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 4246#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 4247#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 4248#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 4249#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 4250#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 4251#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 4252#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 4253#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 4254#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 4255#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 4256#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 4257#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 4258#define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 4259//MMEA0_ADDRDEC1_COL_SEL_LO_CS23 4260#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 4261#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 4262#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 4263#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 4264#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 4265#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 4266#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 4267#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 4268#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 4269#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 4270#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 4271#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 4272#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 4273#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 4274#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 4275#define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 4276//MMEA0_ADDRDEC1_COL_SEL_HI_CS01 4277#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 4278#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 4279#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 4280#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 4281#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 4282#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 4283#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 4284#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 4285#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 4286#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 4287#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 4288#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 4289#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 4290#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 4291#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 4292#define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 4293//MMEA0_ADDRDEC1_COL_SEL_HI_CS23 4294#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 4295#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 4296#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 4297#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 4298#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 4299#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 4300#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 4301#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 4302#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 4303#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 4304#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 4305#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 4306#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 4307#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 4308#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 4309#define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 4310//MMEA0_ADDRDEC1_RM_SEL_CS01 4311#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 4312#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 4313#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 4314#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 4315#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4316#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4317#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 4318#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 4319#define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 4320#define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 4321#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4322#define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4323//MMEA0_ADDRDEC1_RM_SEL_CS23 4324#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 4325#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 4326#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 4327#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 4328#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4329#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4330#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 4331#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 4332#define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 4333#define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 4334#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4335#define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4336//MMEA0_ADDRDEC1_RM_SEL_SECCS01 4337#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 4338#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 4339#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 4340#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 4341#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4342#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4343#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 4344#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 4345#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 4346#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 4347#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4348#define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4349//MMEA0_ADDRDEC1_RM_SEL_SECCS23 4350#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 4351#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 4352#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 4353#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 4354#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 4355#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 4356#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 4357#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 4358#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 4359#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 4360#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 4361#define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 4362//MMEA0_IO_RD_CLI2GRP_MAP0 4363#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 4364#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 4365#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 4366#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 4367#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 4368#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 4369#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 4370#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 4371#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 4372#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 4373#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 4374#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 4375#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 4376#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 4377#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 4378#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 4379#define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 4380#define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 4381#define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 4382#define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 4383#define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 4384#define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 4385#define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 4386#define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 4387#define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 4388#define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 4389#define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 4390#define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 4391#define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 4392#define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 4393#define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 4394#define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 4395//MMEA0_IO_RD_CLI2GRP_MAP1 4396#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 4397#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 4398#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 4399#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 4400#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 4401#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 4402#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 4403#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 4404#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 4405#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 4406#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 4407#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 4408#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 4409#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 4410#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 4411#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 4412#define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 4413#define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 4414#define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 4415#define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 4416#define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 4417#define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 4418#define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 4419#define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 4420#define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 4421#define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 4422#define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 4423#define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 4424#define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 4425#define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 4426#define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 4427#define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 4428//MMEA0_IO_WR_CLI2GRP_MAP0 4429#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 4430#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 4431#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 4432#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 4433#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 4434#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 4435#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 4436#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 4437#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 4438#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 4439#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 4440#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 4441#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 4442#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 4443#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 4444#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 4445#define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 4446#define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 4447#define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 4448#define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 4449#define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 4450#define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 4451#define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 4452#define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 4453#define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 4454#define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 4455#define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 4456#define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 4457#define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 4458#define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 4459#define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 4460#define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 4461//MMEA0_IO_WR_CLI2GRP_MAP1 4462#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 4463#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 4464#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 4465#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 4466#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 4467#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 4468#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 4469#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 4470#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 4471#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 4472#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 4473#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 4474#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 4475#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 4476#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 4477#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 4478#define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 4479#define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 4480#define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 4481#define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 4482#define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 4483#define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 4484#define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 4485#define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 4486#define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 4487#define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 4488#define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 4489#define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 4490#define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 4491#define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 4492#define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 4493#define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 4494//MMEA0_IO_RD_COMBINE_FLUSH 4495#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 4496#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 4497#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 4498#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 4499#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 4500#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 4501#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 4502#define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 4503//MMEA0_IO_WR_COMBINE_FLUSH 4504#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 4505#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 4506#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 4507#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 4508#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 4509#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 4510#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 4511#define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 4512//MMEA0_IO_GROUP_BURST 4513#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 4514#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 4515#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 4516#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 4517#define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 4518#define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 4519#define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 4520#define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 4521//MMEA0_IO_RD_PRI_AGE 4522#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 4523#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 4524#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 4525#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 4526#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 4527#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 4528#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 4529#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 4530#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 4531#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 4532#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 4533#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 4534#define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 4535#define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 4536#define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 4537#define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 4538//MMEA0_IO_WR_PRI_AGE 4539#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 4540#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 4541#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 4542#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 4543#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 4544#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 4545#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 4546#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 4547#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 4548#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 4549#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 4550#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 4551#define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 4552#define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 4553#define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 4554#define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 4555//MMEA0_IO_RD_PRI_QUEUING 4556#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 4557#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 4558#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 4559#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 4560#define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 4561#define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 4562#define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 4563#define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 4564//MMEA0_IO_WR_PRI_QUEUING 4565#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 4566#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 4567#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 4568#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 4569#define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 4570#define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 4571#define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 4572#define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 4573//MMEA0_IO_RD_PRI_FIXED 4574#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 4575#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 4576#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 4577#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 4578#define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 4579#define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 4580#define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 4581#define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 4582//MMEA0_IO_WR_PRI_FIXED 4583#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 4584#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 4585#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 4586#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 4587#define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 4588#define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 4589#define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 4590#define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 4591//MMEA0_IO_RD_PRI_URGENCY 4592#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 4593#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 4594#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 4595#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 4596#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 4597#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 4598#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 4599#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 4600#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 4601#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 4602#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 4603#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 4604#define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 4605#define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 4606#define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 4607#define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 4608//MMEA0_IO_WR_PRI_URGENCY 4609#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 4610#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 4611#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 4612#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 4613#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 4614#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 4615#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 4616#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 4617#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 4618#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 4619#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 4620#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 4621#define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 4622#define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 4623#define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 4624#define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 4625//MMEA0_IO_RD_PRI_URGENCY_MASK 4626#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 4627#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 4628#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 4629#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 4630#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 4631#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 4632#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 4633#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 4634#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 4635#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 4636#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 4637#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 4638#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 4639#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 4640#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 4641#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 4642#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 4643#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 4644#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 4645#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 4646#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 4647#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 4648#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 4649#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 4650#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 4651#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 4652#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 4653#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 4654#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 4655#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 4656#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 4657#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 4658#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 4659#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 4660#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 4661#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 4662#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 4663#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 4664#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 4665#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 4666#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 4667#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 4668#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 4669#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 4670#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 4671#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 4672#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 4673#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 4674#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 4675#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 4676#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 4677#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 4678#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 4679#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 4680#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 4681#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 4682#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 4683#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 4684#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 4685#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 4686#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 4687#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 4688#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 4689#define MMEA0_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 4690//MMEA0_IO_WR_PRI_URGENCY_MASK 4691#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 4692#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 4693#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 4694#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 4695#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 4696#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 4697#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 4698#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 4699#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 4700#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 4701#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 4702#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 4703#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 4704#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 4705#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 4706#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 4707#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 4708#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 4709#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 4710#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 4711#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 4712#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 4713#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 4714#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 4715#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 4716#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 4717#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 4718#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 4719#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 4720#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 4721#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 4722#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 4723#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 4724#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 4725#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 4726#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 4727#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 4728#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 4729#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 4730#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 4731#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 4732#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 4733#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 4734#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 4735#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 4736#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 4737#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 4738#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 4739#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 4740#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 4741#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 4742#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 4743#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 4744#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 4745#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 4746#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 4747#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 4748#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 4749#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 4750#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 4751#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 4752#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 4753#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 4754#define MMEA0_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 4755//MMEA0_IO_RD_PRI_QUANT_PRI1 4756#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 4757#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 4758#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 4759#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 4760#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 4761#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 4762#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 4763#define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 4764//MMEA0_IO_RD_PRI_QUANT_PRI2 4765#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 4766#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 4767#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 4768#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 4769#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 4770#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 4771#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 4772#define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 4773//MMEA0_IO_RD_PRI_QUANT_PRI3 4774#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 4775#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 4776#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 4777#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 4778#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 4779#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 4780#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 4781#define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 4782//MMEA0_IO_WR_PRI_QUANT_PRI1 4783#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 4784#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 4785#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 4786#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 4787#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 4788#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 4789#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 4790#define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 4791//MMEA0_IO_WR_PRI_QUANT_PRI2 4792#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 4793#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 4794#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 4795#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 4796#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 4797#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 4798#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 4799#define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 4800//MMEA0_IO_WR_PRI_QUANT_PRI3 4801#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 4802#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 4803#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 4804#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 4805#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 4806#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 4807#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 4808#define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 4809//MMEA0_SDP_ARB_DRAM 4810#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 4811#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 4812#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 4813#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 4814#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 4815#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 4816#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 4817#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 4818#define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 4819#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 4820#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 4821#define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 4822#define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 4823#define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 4824//MMEA0_SDP_ARB_FINAL 4825#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 4826#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 4827#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 4828#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 4829#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 4830#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 4831#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 4832#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 4833#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 4834#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 4835#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 4836#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 4837#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 4838#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 4839#define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 4840#define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 4841#define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 4842#define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 4843#define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 4844#define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 4845#define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 4846#define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 4847#define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 4848#define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 4849#define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 4850#define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 4851#define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 4852#define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 4853//MMEA0_SDP_DRAM_PRIORITY 4854#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 4855#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 4856#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 4857#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 4858#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 4859#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 4860#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 4861#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 4862#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 4863#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 4864#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 4865#define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 4866#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 4867#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 4868#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 4869#define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 4870//MMEA0_SDP_IO_PRIORITY 4871#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 4872#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 4873#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 4874#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 4875#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 4876#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 4877#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 4878#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 4879#define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 4880#define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 4881#define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 4882#define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 4883#define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 4884#define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 4885#define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 4886#define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 4887//MMEA0_SDP_CREDITS 4888#define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 4889#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 4890#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 4891#define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 4892#define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 4893#define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 4894//MMEA0_SDP_TAG_RESERVE0 4895#define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 4896#define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 4897#define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 4898#define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 4899#define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 4900#define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 4901#define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 4902#define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 4903//MMEA0_SDP_TAG_RESERVE1 4904#define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 4905#define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 4906#define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 4907#define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 4908#define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 4909#define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 4910#define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 4911#define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 4912//MMEA0_SDP_VCC_RESERVE0 4913#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 4914#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 4915#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 4916#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 4917#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 4918#define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 4919#define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 4920#define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 4921#define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 4922#define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 4923//MMEA0_SDP_VCC_RESERVE1 4924#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 4925#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 4926#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 4927#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 4928#define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 4929#define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 4930#define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 4931#define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 4932//MMEA0_SDP_VCD_RESERVE0 4933#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 4934#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 4935#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 4936#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 4937#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 4938#define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 4939#define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 4940#define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 4941#define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 4942#define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 4943//MMEA0_SDP_VCD_RESERVE1 4944#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 4945#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 4946#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 4947#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 4948#define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 4949#define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 4950#define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 4951#define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 4952//MMEA0_SDP_REQ_CNTL 4953#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 4954#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 4955#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 4956#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 4957#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 4958#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 4959#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 4960#define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 4961#define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 4962#define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 4963//MMEA0_MISC 4964#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 4965#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 4966#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 4967#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 4968#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 4969#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 4970#define MMEA0_MISC__RRET_SWAP_MODE__SHIFT 0x6 4971#define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 4972#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 4973#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa 4974#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc 4975#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe 4976#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 4977#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 4978#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 4979#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 4980#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 4981#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 4982#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 4983#define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 4984#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 4985#define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 4986#define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 4987#define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 4988#define MMEA0_MISC__RRET_SWAP_MODE_MASK 0x00000040L 4989#define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L 4990#define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L 4991#define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L 4992#define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L 4993#define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L 4994#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L 4995#define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L 4996#define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L 4997#define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L 4998#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L 4999#define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L 5000//MMEA0_LATENCY_SAMPLING 5001#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 5002#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 5003#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 5004#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 5005#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 5006#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 5007#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 5008#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 5009#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 5010#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 5011#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 5012#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 5013#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 5014#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 5015#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 5016#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 5017#define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 5018#define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 5019#define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 5020#define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 5021#define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 5022#define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 5023#define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 5024#define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 5025#define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 5026#define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 5027#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 5028#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 5029#define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 5030#define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 5031#define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 5032#define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 5033//MMEA0_PERFCOUNTER_LO 5034#define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5035#define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 5036//MMEA0_PERFCOUNTER_HI 5037#define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5038#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5039#define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 5040#define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 5041//MMEA0_PERFCOUNTER0_CFG 5042#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5043#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5044#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5045#define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5046#define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5047#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 5048#define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 5049#define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 5050#define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 5051#define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 5052//MMEA0_PERFCOUNTER1_CFG 5053#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5054#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5055#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5056#define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5057#define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5058#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 5059#define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 5060#define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 5061#define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 5062#define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 5063//MMEA0_PERFCOUNTER_RSLT_CNTL 5064#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5065#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5066#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5067#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5068#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5069#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5070#define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 5071#define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 5072#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 5073#define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 5074#define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 5075#define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 5076//MMEA0_EDC_CNT 5077#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 5078#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 5079#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 5080#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 5081#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 5082#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 5083#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 5084#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 5085#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 5086#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 5087#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 5088#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 5089#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 5090#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 5091#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 5092#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 5093#define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 5094#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 5095#define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 5096#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 5097#define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 5098#define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 5099#define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 5100#define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 5101#define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 5102#define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 5103#define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 5104#define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 5105#define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 5106#define MMEA0_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 5107//MMEA0_EDC_CNT2 5108#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 5109#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 5110#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 5111#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 5112#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 5113#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 5114#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 5115#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 5116#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 5117#define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 5118#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 5119#define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 5120#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 5121#define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 5122#define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 5123#define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 5124//MMEA0_DSM_CNTL 5125#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 5126#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 5127#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 5128#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 5129#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 5130#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 5131#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 5132#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 5133#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 5134#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 5135#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 5136#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 5137#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 5138#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 5139#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 5140#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 5141#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 5142#define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 5143#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 5144#define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 5145#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 5146#define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 5147#define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 5148#define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 5149#define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 5150#define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 5151#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 5152#define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 5153#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 5154#define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 5155#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 5156#define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 5157//MMEA0_DSM_CNTLA 5158#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 5159#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 5160#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 5161#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 5162#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 5163#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 5164#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 5165#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 5166#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 5167#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 5168#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 5169#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 5170#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 5171#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 5172#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 5173#define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 5174#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 5175#define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 5176#define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 5177#define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 5178#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 5179#define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 5180#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 5181#define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 5182#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 5183#define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 5184#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 5185#define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 5186//MMEA0_DSM_CNTLB 5187//MMEA0_DSM_CNTL2 5188#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 5189#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 5190#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 5191#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 5192#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 5193#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 5194#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 5195#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 5196#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 5197#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 5198#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 5199#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 5200#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 5201#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 5202#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 5203#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 5204#define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 5205#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 5206#define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 5207#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 5208#define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 5209#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 5210#define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 5211#define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 5212#define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 5213#define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 5214#define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 5215#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 5216#define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 5217#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 5218#define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 5219#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 5220#define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 5221#define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 5222//MMEA0_DSM_CNTL2A 5223#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 5224#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 5225#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 5226#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 5227#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 5228#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 5229#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 5230#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 5231#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 5232#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 5233#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 5234#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 5235#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 5236#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 5237#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 5238#define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 5239#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 5240#define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 5241#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 5242#define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 5243#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 5244#define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 5245#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 5246#define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 5247#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 5248#define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 5249#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 5250#define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 5251//MMEA0_DSM_CNTL2B 5252//MMEA0_CGTT_CLK_CTRL 5253#define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5254#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5255#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 5256#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 5257#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 5258#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 5259#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 5260#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 5261#define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5262#define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5263#define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 5264#define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 5265#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 5266#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 5267#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 5268#define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 5269//MMEA0_EDC_MODE 5270#define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 5271#define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 5272#define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 5273#define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 5274#define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 5275#define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 5276#define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 5277#define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 5278#define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 5279#define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 5280//MMEA0_ERR_STATUS 5281#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 5282#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 5283#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 5284#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 5285#define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa 5286#define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 5287#define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 5288#define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L 5289#define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L 5290#define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L 5291//MMEA0_MISC2 5292#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 5293#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 5294#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 5295#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 5296#define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 5297#define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 5298#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 5299#define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 5300//MMEA1_DRAM_RD_CLI2GRP_MAP0 5301#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 5302#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 5303#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 5304#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 5305#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 5306#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 5307#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 5308#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 5309#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 5310#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 5311#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 5312#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 5313#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 5314#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 5315#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 5316#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 5317#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 5318#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 5319#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 5320#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 5321#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 5322#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 5323#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 5324#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 5325#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 5326#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 5327#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 5328#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 5329#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 5330#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 5331#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 5332#define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 5333//MMEA1_DRAM_RD_CLI2GRP_MAP1 5334#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 5335#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 5336#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 5337#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 5338#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 5339#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 5340#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 5341#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 5342#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 5343#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 5344#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 5345#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 5346#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 5347#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 5348#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 5349#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 5350#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 5351#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 5352#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 5353#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 5354#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 5355#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 5356#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 5357#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 5358#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 5359#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 5360#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 5361#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 5362#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 5363#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 5364#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 5365#define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 5366//MMEA1_DRAM_WR_CLI2GRP_MAP0 5367#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 5368#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 5369#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 5370#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 5371#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 5372#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 5373#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 5374#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 5375#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 5376#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 5377#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 5378#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 5379#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 5380#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 5381#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 5382#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 5383#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 5384#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 5385#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 5386#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 5387#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 5388#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 5389#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 5390#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 5391#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 5392#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 5393#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 5394#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 5395#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 5396#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 5397#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 5398#define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 5399//MMEA1_DRAM_WR_CLI2GRP_MAP1 5400#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 5401#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 5402#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 5403#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 5404#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 5405#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 5406#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 5407#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 5408#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 5409#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 5410#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 5411#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 5412#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 5413#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 5414#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 5415#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 5416#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 5417#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 5418#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 5419#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 5420#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 5421#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 5422#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 5423#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 5424#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 5425#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 5426#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 5427#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 5428#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 5429#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 5430#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 5431#define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 5432//MMEA1_DRAM_RD_GRP2VC_MAP 5433#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 5434#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 5435#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 5436#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 5437#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 5438#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 5439#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 5440#define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 5441//MMEA1_DRAM_WR_GRP2VC_MAP 5442#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 5443#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 5444#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 5445#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 5446#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 5447#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 5448#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 5449#define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 5450//MMEA1_DRAM_RD_LAZY 5451#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 5452#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 5453#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 5454#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 5455#define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 5456#define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 5457#define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 5458#define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 5459//MMEA1_DRAM_WR_LAZY 5460#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 5461#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 5462#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 5463#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 5464#define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 5465#define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 5466#define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 5467#define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 5468//MMEA1_DRAM_RD_CAM_CNTL 5469#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 5470#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 5471#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 5472#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 5473#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 5474#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 5475#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 5476#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 5477#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 5478#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 5479#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 5480#define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 5481#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 5482#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 5483#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 5484#define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 5485//MMEA1_DRAM_WR_CAM_CNTL 5486#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 5487#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 5488#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 5489#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 5490#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 5491#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 5492#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 5493#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 5494#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 5495#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 5496#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 5497#define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 5498#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 5499#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 5500#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 5501#define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 5502//MMEA1_DRAM_PAGE_BURST 5503#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 5504#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 5505#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 5506#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 5507#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 5508#define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 5509#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 5510#define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 5511//MMEA1_DRAM_RD_PRI_AGE 5512#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 5513#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 5514#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 5515#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 5516#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 5517#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 5518#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 5519#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 5520#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 5521#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 5522#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 5523#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 5524#define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 5525#define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 5526#define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 5527#define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 5528//MMEA1_DRAM_WR_PRI_AGE 5529#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 5530#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 5531#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 5532#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 5533#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 5534#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 5535#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 5536#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 5537#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 5538#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 5539#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 5540#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 5541#define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 5542#define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 5543#define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 5544#define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 5545//MMEA1_DRAM_RD_PRI_QUEUING 5546#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 5547#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 5548#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 5549#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 5550#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 5551#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 5552#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 5553#define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 5554//MMEA1_DRAM_WR_PRI_QUEUING 5555#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 5556#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 5557#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 5558#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 5559#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 5560#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 5561#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 5562#define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 5563//MMEA1_DRAM_RD_PRI_FIXED 5564#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 5565#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 5566#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 5567#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 5568#define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 5569#define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 5570#define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 5571#define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 5572//MMEA1_DRAM_WR_PRI_FIXED 5573#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 5574#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 5575#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 5576#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 5577#define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 5578#define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 5579#define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 5580#define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 5581//MMEA1_DRAM_RD_PRI_URGENCY 5582#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 5583#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 5584#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 5585#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 5586#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 5587#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 5588#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 5589#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 5590#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 5591#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 5592#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 5593#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 5594#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 5595#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 5596#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 5597#define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 5598//MMEA1_DRAM_WR_PRI_URGENCY 5599#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 5600#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 5601#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 5602#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 5603#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 5604#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 5605#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 5606#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 5607#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 5608#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 5609#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 5610#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 5611#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 5612#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 5613#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 5614#define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 5615//MMEA1_DRAM_RD_PRI_QUANT_PRI1 5616#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 5617#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 5618#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 5619#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 5620#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 5621#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 5622#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 5623#define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 5624//MMEA1_DRAM_RD_PRI_QUANT_PRI2 5625#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 5626#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 5627#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 5628#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 5629#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 5630#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 5631#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 5632#define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 5633//MMEA1_DRAM_RD_PRI_QUANT_PRI3 5634#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 5635#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 5636#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 5637#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 5638#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 5639#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 5640#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 5641#define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 5642//MMEA1_DRAM_WR_PRI_QUANT_PRI1 5643#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 5644#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 5645#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 5646#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 5647#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 5648#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 5649#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 5650#define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 5651//MMEA1_DRAM_WR_PRI_QUANT_PRI2 5652#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 5653#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 5654#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 5655#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 5656#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 5657#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 5658#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 5659#define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 5660//MMEA1_DRAM_WR_PRI_QUANT_PRI3 5661#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 5662#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 5663#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 5664#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 5665#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 5666#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 5667#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 5668#define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 5669//MMEA1_ADDRNORM_BASE_ADDR0 5670#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 5671#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 5672#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x4 5673#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x8 5674#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 5675#define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 5676#define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 5677#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x000000F0L 5678#define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000700L 5679#define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 5680//MMEA1_ADDRNORM_LIMIT_ADDR0 5681#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 5682#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 5683#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES__SHIFT 0xa 5684#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 5685#define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000000FL 5686#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 5687#define MMEA1_ADDRNORM_LIMIT_ADDR0__INTLV_NUM_DIES_MASK 0x00000C00L 5688#define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 5689//MMEA1_ADDRNORM_BASE_ADDR1 5690#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 5691#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 5692#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x4 5693#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x8 5694#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 5695#define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 5696#define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 5697#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x000000F0L 5698#define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000700L 5699#define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 5700//MMEA1_ADDRNORM_LIMIT_ADDR1 5701#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 5702#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 5703#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES__SHIFT 0xa 5704#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 5705#define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000000FL 5706#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 5707#define MMEA1_ADDRNORM_LIMIT_ADDR1__INTLV_NUM_DIES_MASK 0x00000C00L 5708#define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 5709//MMEA1_ADDRNORM_OFFSET_ADDR1 5710#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 5711#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0x14 5712#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 5713#define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0xFFF00000L 5714//MMEA1_ADDRNORM_HOLE_CNTL 5715#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 5716#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 5717#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 5718#define MMEA1_ADDRNORM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 5719//MMEA1_ADDRDEC_BANK_CFG 5720#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 5721#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x5 5722#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xa 5723#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xd 5724#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x10 5725#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x11 5726#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000001FL 5727#define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x000003E0L 5728#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00001C00L 5729#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x0000E000L 5730#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00010000L 5731#define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00020000L 5732//MMEA1_ADDRDEC_MISC_CFG 5733#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 5734#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 5735#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 5736#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3__SHIFT 0x3 5737#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4__SHIFT 0x4 5738#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 5739#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 5740#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 5741#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x10 5742#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x14 5743#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x16 5744#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x18 5745#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1b 5746#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 5747#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 5748#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 5749#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN3_MASK 0x00000008L 5750#define MMEA1_ADDRDEC_MISC_CFG__VCM_EN4_MASK 0x00000010L 5751#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 5752#define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 5753#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0000F000L 5754#define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x000F0000L 5755#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00300000L 5756#define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x00C00000L 5757#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x07000000L 5758#define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0x38000000L 5759//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0 5760#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE__SHIFT 0x0 5761#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR__SHIFT 0x1 5762#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR__SHIFT 0xe 5763#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__XOR_ENABLE_MASK 0x00000001L 5764#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__COL_XOR_MASK 0x00003FFEL 5765#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK0__ROW_XOR_MASK 0xFFFFC000L 5766//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1 5767#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE__SHIFT 0x0 5768#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR__SHIFT 0x1 5769#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR__SHIFT 0xe 5770#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__XOR_ENABLE_MASK 0x00000001L 5771#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__COL_XOR_MASK 0x00003FFEL 5772#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK1__ROW_XOR_MASK 0xFFFFC000L 5773//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2 5774#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE__SHIFT 0x0 5775#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR__SHIFT 0x1 5776#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR__SHIFT 0xe 5777#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__XOR_ENABLE_MASK 0x00000001L 5778#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__COL_XOR_MASK 0x00003FFEL 5779#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK2__ROW_XOR_MASK 0xFFFFC000L 5780//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3 5781#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE__SHIFT 0x0 5782#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR__SHIFT 0x1 5783#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR__SHIFT 0xe 5784#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__XOR_ENABLE_MASK 0x00000001L 5785#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__COL_XOR_MASK 0x00003FFEL 5786#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK3__ROW_XOR_MASK 0xFFFFC000L 5787//MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4 5788#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE__SHIFT 0x0 5789#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR__SHIFT 0x1 5790#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR__SHIFT 0xe 5791#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__XOR_ENABLE_MASK 0x00000001L 5792#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__COL_XOR_MASK 0x00003FFEL 5793#define MMEA1_ADDRDECDRAM_ADDR_HASH_BANK4__ROW_XOR_MASK 0xFFFFC000L 5794//MMEA1_ADDRDECDRAM_ADDR_HASH_PC 5795#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE__SHIFT 0x0 5796#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR__SHIFT 0x1 5797#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR__SHIFT 0xe 5798#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__XOR_ENABLE_MASK 0x00000001L 5799#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__COL_XOR_MASK 0x00003FFEL 5800#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC__ROW_XOR_MASK 0xFFFFC000L 5801//MMEA1_ADDRDECDRAM_ADDR_HASH_PC2 5802#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR__SHIFT 0x0 5803#define MMEA1_ADDRDECDRAM_ADDR_HASH_PC2__BANK_XOR_MASK 0x0000001FL 5804//MMEA1_ADDRDECDRAM_ADDR_HASH_CS0 5805#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE__SHIFT 0x0 5806#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR__SHIFT 0x1 5807#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__XOR_ENABLE_MASK 0x00000001L 5808#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS0__NA_XOR_MASK 0xFFFFFFFEL 5809//MMEA1_ADDRDECDRAM_ADDR_HASH_CS1 5810#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE__SHIFT 0x0 5811#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR__SHIFT 0x1 5812#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__XOR_ENABLE_MASK 0x00000001L 5813#define MMEA1_ADDRDECDRAM_ADDR_HASH_CS1__NA_XOR_MASK 0xFFFFFFFEL 5814//MMEA1_ADDRDECDRAM_HARVEST_ENABLE 5815#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 5816#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 5817#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 5818#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 5819#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 5820#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 5821#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 5822#define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 5823//MMEA1_ADDRDEC0_BASE_ADDR_CS0 5824#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 5825#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 5826#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 5827#define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 5828//MMEA1_ADDRDEC0_BASE_ADDR_CS1 5829#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 5830#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 5831#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 5832#define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 5833//MMEA1_ADDRDEC0_BASE_ADDR_CS2 5834#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 5835#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 5836#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 5837#define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 5838//MMEA1_ADDRDEC0_BASE_ADDR_CS3 5839#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 5840#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 5841#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 5842#define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 5843//MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 5844#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 5845#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 5846#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 5847#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 5848//MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 5849#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 5850#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 5851#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 5852#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 5853//MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 5854#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 5855#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 5856#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 5857#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 5858//MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 5859#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 5860#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 5861#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 5862#define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 5863//MMEA1_ADDRDEC0_ADDR_MASK_CS01 5864#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 5865#define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 5866//MMEA1_ADDRDEC0_ADDR_MASK_CS23 5867#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 5868#define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 5869//MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 5870#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 5871#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 5872//MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 5873#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 5874#define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 5875//MMEA1_ADDRDEC0_ADDR_CFG_CS01 5876#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 5877#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 5878#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 5879#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 5880#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 5881#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 5882#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 5883#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 5884#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 5885#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 5886#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 5887#define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 5888//MMEA1_ADDRDEC0_ADDR_CFG_CS23 5889#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 5890#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 5891#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 5892#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 5893#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 5894#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 5895#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 5896#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 5897#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 5898#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 5899#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 5900#define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 5901//MMEA1_ADDRDEC0_ADDR_SEL_CS01 5902#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 5903#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 5904#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 5905#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 5906#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 5907#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 5908#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 5909#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 5910#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 5911#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 5912#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 5913#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 5914#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 5915#define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 5916//MMEA1_ADDRDEC0_ADDR_SEL_CS23 5917#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 5918#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 5919#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 5920#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 5921#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 5922#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 5923#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 5924#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 5925#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 5926#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 5927#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 5928#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 5929#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 5930#define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 5931//MMEA1_ADDRDEC0_COL_SEL_LO_CS01 5932#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 5933#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 5934#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 5935#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 5936#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 5937#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 5938#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 5939#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 5940#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 5941#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 5942#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 5943#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 5944#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 5945#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 5946#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 5947#define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 5948//MMEA1_ADDRDEC0_COL_SEL_LO_CS23 5949#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 5950#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 5951#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 5952#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 5953#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 5954#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 5955#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 5956#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 5957#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 5958#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 5959#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 5960#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 5961#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 5962#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 5963#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 5964#define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 5965//MMEA1_ADDRDEC0_COL_SEL_HI_CS01 5966#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 5967#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 5968#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 5969#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 5970#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 5971#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 5972#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 5973#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 5974#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 5975#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 5976#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 5977#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 5978#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 5979#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 5980#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 5981#define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 5982//MMEA1_ADDRDEC0_COL_SEL_HI_CS23 5983#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 5984#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 5985#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 5986#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 5987#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 5988#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 5989#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 5990#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 5991#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 5992#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 5993#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 5994#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 5995#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 5996#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 5997#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 5998#define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 5999//MMEA1_ADDRDEC0_RM_SEL_CS01 6000#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 6001#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 6002#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 6003#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 6004#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6005#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6006#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 6007#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 6008#define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 6009#define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 6010#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6011#define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6012//MMEA1_ADDRDEC0_RM_SEL_CS23 6013#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 6014#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 6015#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 6016#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 6017#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6018#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6019#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 6020#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 6021#define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 6022#define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 6023#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6024#define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6025//MMEA1_ADDRDEC0_RM_SEL_SECCS01 6026#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 6027#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 6028#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 6029#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 6030#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6031#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6032#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 6033#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 6034#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 6035#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 6036#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6037#define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6038//MMEA1_ADDRDEC0_RM_SEL_SECCS23 6039#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 6040#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 6041#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 6042#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 6043#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6044#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6045#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 6046#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 6047#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 6048#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 6049#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6050#define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6051//MMEA1_ADDRDEC1_BASE_ADDR_CS0 6052#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE__SHIFT 0x0 6053#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 6054#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_ENABLE_MASK 0x00000001L 6055#define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 6056//MMEA1_ADDRDEC1_BASE_ADDR_CS1 6057#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE__SHIFT 0x0 6058#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 6059#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_ENABLE_MASK 0x00000001L 6060#define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 6061//MMEA1_ADDRDEC1_BASE_ADDR_CS2 6062#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE__SHIFT 0x0 6063#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 6064#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_ENABLE_MASK 0x00000001L 6065#define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 6066//MMEA1_ADDRDEC1_BASE_ADDR_CS3 6067#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE__SHIFT 0x0 6068#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 6069#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_ENABLE_MASK 0x00000001L 6070#define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 6071//MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 6072#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE__SHIFT 0x0 6073#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 6074#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_ENABLE_MASK 0x00000001L 6075#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 6076//MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 6077#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE__SHIFT 0x0 6078#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 6079#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_ENABLE_MASK 0x00000001L 6080#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 6081//MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 6082#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE__SHIFT 0x0 6083#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 6084#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_ENABLE_MASK 0x00000001L 6085#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 6086//MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 6087#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE__SHIFT 0x0 6088#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 6089#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_ENABLE_MASK 0x00000001L 6090#define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 6091//MMEA1_ADDRDEC1_ADDR_MASK_CS01 6092#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 6093#define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 6094//MMEA1_ADDRDEC1_ADDR_MASK_CS23 6095#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 6096#define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 6097//MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 6098#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 6099#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 6100//MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 6101#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 6102#define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 6103//MMEA1_ADDRDEC1_ADDR_CFG_CS01 6104#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x2 6105#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 6106#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 6107#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 6108#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 6109#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 6110#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000CL 6111#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 6112#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 6113#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 6114#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 6115#define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 6116//MMEA1_ADDRDEC1_ADDR_CFG_CS23 6117#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x2 6118#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 6119#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 6120#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 6121#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 6122#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 6123#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000CL 6124#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 6125#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 6126#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 6127#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 6128#define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 6129//MMEA1_ADDRDEC1_ADDR_SEL_CS01 6130#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 6131#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 6132#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 6133#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 6134#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 6135#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 6136#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 6137#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 6138#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 6139#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 6140#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 6141#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x000F0000L 6142#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 6143#define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 6144//MMEA1_ADDRDEC1_ADDR_SEL_CS23 6145#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 6146#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 6147#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 6148#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 6149#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 6150#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 6151#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 6152#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 6153#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 6154#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 6155#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 6156#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x000F0000L 6157#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 6158#define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 6159//MMEA1_ADDRDEC1_COL_SEL_LO_CS01 6160#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 6161#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 6162#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 6163#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 6164#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 6165#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 6166#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 6167#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 6168#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 6169#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 6170#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 6171#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 6172#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 6173#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 6174#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 6175#define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 6176//MMEA1_ADDRDEC1_COL_SEL_LO_CS23 6177#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 6178#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 6179#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 6180#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 6181#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 6182#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 6183#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 6184#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 6185#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 6186#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 6187#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 6188#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 6189#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 6190#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 6191#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 6192#define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 6193//MMEA1_ADDRDEC1_COL_SEL_HI_CS01 6194#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 6195#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 6196#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 6197#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 6198#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 6199#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 6200#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 6201#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 6202#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 6203#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 6204#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 6205#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 6206#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 6207#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 6208#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 6209#define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 6210//MMEA1_ADDRDEC1_COL_SEL_HI_CS23 6211#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 6212#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 6213#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 6214#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 6215#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 6216#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 6217#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 6218#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 6219#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 6220#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 6221#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 6222#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 6223#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 6224#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 6225#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 6226#define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 6227//MMEA1_ADDRDEC1_RM_SEL_CS01 6228#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 6229#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 6230#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 6231#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 6232#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6233#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6234#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 6235#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 6236#define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 6237#define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 6238#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6239#define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6240//MMEA1_ADDRDEC1_RM_SEL_CS23 6241#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 6242#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 6243#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 6244#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 6245#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6246#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6247#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 6248#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 6249#define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 6250#define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 6251#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6252#define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6253//MMEA1_ADDRDEC1_RM_SEL_SECCS01 6254#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 6255#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 6256#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 6257#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 6258#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6259#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6260#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 6261#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 6262#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 6263#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 6264#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6265#define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6266//MMEA1_ADDRDEC1_RM_SEL_SECCS23 6267#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 6268#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 6269#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 6270#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 6271#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 6272#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 6273#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 6274#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 6275#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 6276#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 6277#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 6278#define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 6279//MMEA1_IO_RD_CLI2GRP_MAP0 6280#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 6281#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 6282#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 6283#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 6284#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 6285#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 6286#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 6287#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 6288#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 6289#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 6290#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 6291#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 6292#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 6293#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 6294#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 6295#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 6296#define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 6297#define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 6298#define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 6299#define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 6300#define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 6301#define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 6302#define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 6303#define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 6304#define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 6305#define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 6306#define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 6307#define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 6308#define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 6309#define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 6310#define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 6311#define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 6312//MMEA1_IO_RD_CLI2GRP_MAP1 6313#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 6314#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 6315#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 6316#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 6317#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 6318#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 6319#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 6320#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 6321#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 6322#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 6323#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 6324#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 6325#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 6326#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 6327#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 6328#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 6329#define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 6330#define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 6331#define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 6332#define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 6333#define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 6334#define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 6335#define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 6336#define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 6337#define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 6338#define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 6339#define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 6340#define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 6341#define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 6342#define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 6343#define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 6344#define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 6345//MMEA1_IO_WR_CLI2GRP_MAP0 6346#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 6347#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 6348#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 6349#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 6350#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 6351#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 6352#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 6353#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 6354#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 6355#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 6356#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 6357#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 6358#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 6359#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 6360#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 6361#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 6362#define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 6363#define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 6364#define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 6365#define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 6366#define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 6367#define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 6368#define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 6369#define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 6370#define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 6371#define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 6372#define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 6373#define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 6374#define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 6375#define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 6376#define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 6377#define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 6378//MMEA1_IO_WR_CLI2GRP_MAP1 6379#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 6380#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 6381#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 6382#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 6383#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 6384#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 6385#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 6386#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 6387#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 6388#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 6389#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 6390#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 6391#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 6392#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 6393#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 6394#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 6395#define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 6396#define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 6397#define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 6398#define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 6399#define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 6400#define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 6401#define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 6402#define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 6403#define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 6404#define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 6405#define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 6406#define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 6407#define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 6408#define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 6409#define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 6410#define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 6411//MMEA1_IO_RD_COMBINE_FLUSH 6412#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 6413#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 6414#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 6415#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 6416#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 6417#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 6418#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 6419#define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 6420//MMEA1_IO_WR_COMBINE_FLUSH 6421#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 6422#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 6423#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 6424#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 6425#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 6426#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 6427#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 6428#define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 6429//MMEA1_IO_GROUP_BURST 6430#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 6431#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 6432#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 6433#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 6434#define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 6435#define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 6436#define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 6437#define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 6438//MMEA1_IO_RD_PRI_AGE 6439#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 6440#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 6441#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 6442#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 6443#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 6444#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 6445#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 6446#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 6447#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 6448#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 6449#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 6450#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 6451#define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 6452#define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 6453#define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 6454#define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 6455//MMEA1_IO_WR_PRI_AGE 6456#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 6457#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 6458#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 6459#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 6460#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 6461#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 6462#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 6463#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 6464#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 6465#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 6466#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 6467#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 6468#define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 6469#define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 6470#define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 6471#define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 6472//MMEA1_IO_RD_PRI_QUEUING 6473#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 6474#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 6475#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 6476#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 6477#define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 6478#define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 6479#define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 6480#define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 6481//MMEA1_IO_WR_PRI_QUEUING 6482#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 6483#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 6484#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 6485#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 6486#define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 6487#define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 6488#define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 6489#define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 6490//MMEA1_IO_RD_PRI_FIXED 6491#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 6492#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 6493#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 6494#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 6495#define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 6496#define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 6497#define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 6498#define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 6499//MMEA1_IO_WR_PRI_FIXED 6500#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 6501#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 6502#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 6503#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 6504#define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 6505#define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 6506#define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 6507#define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 6508//MMEA1_IO_RD_PRI_URGENCY 6509#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 6510#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 6511#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 6512#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 6513#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 6514#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 6515#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 6516#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 6517#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 6518#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 6519#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 6520#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 6521#define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 6522#define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 6523#define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 6524#define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 6525//MMEA1_IO_WR_PRI_URGENCY 6526#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 6527#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 6528#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 6529#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 6530#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 6531#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 6532#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 6533#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 6534#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 6535#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 6536#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 6537#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 6538#define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 6539#define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 6540#define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 6541#define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 6542//MMEA1_IO_RD_PRI_URGENCY_MASK 6543#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 6544#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 6545#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 6546#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 6547#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 6548#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 6549#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 6550#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 6551#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 6552#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 6553#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 6554#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 6555#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 6556#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 6557#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 6558#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 6559#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 6560#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 6561#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 6562#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 6563#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 6564#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 6565#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 6566#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 6567#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 6568#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 6569#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 6570#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 6571#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 6572#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 6573#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 6574#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 6575#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 6576#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 6577#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 6578#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 6579#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 6580#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 6581#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 6582#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 6583#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 6584#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 6585#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 6586#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 6587#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 6588#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 6589#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 6590#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 6591#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 6592#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 6593#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 6594#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 6595#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 6596#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 6597#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 6598#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 6599#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 6600#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 6601#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 6602#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 6603#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 6604#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 6605#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 6606#define MMEA1_IO_RD_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 6607//MMEA1_IO_WR_PRI_URGENCY_MASK 6608#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK__SHIFT 0x0 6609#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK__SHIFT 0x1 6610#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK__SHIFT 0x2 6611#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK__SHIFT 0x3 6612#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK__SHIFT 0x4 6613#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK__SHIFT 0x5 6614#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK__SHIFT 0x6 6615#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK__SHIFT 0x7 6616#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK__SHIFT 0x8 6617#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK__SHIFT 0x9 6618#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK__SHIFT 0xa 6619#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK__SHIFT 0xb 6620#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK__SHIFT 0xc 6621#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK__SHIFT 0xd 6622#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK__SHIFT 0xe 6623#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK__SHIFT 0xf 6624#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK__SHIFT 0x10 6625#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK__SHIFT 0x11 6626#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK__SHIFT 0x12 6627#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK__SHIFT 0x13 6628#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK__SHIFT 0x14 6629#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK__SHIFT 0x15 6630#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK__SHIFT 0x16 6631#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK__SHIFT 0x17 6632#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK__SHIFT 0x18 6633#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK__SHIFT 0x19 6634#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK__SHIFT 0x1a 6635#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK__SHIFT 0x1b 6636#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK__SHIFT 0x1c 6637#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK__SHIFT 0x1d 6638#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK__SHIFT 0x1e 6639#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK__SHIFT 0x1f 6640#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID0_MASK_MASK 0x00000001L 6641#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID1_MASK_MASK 0x00000002L 6642#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID2_MASK_MASK 0x00000004L 6643#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID3_MASK_MASK 0x00000008L 6644#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID4_MASK_MASK 0x00000010L 6645#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID5_MASK_MASK 0x00000020L 6646#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID6_MASK_MASK 0x00000040L 6647#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID7_MASK_MASK 0x00000080L 6648#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID8_MASK_MASK 0x00000100L 6649#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID9_MASK_MASK 0x00000200L 6650#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID10_MASK_MASK 0x00000400L 6651#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID11_MASK_MASK 0x00000800L 6652#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID12_MASK_MASK 0x00001000L 6653#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID13_MASK_MASK 0x00002000L 6654#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID14_MASK_MASK 0x00004000L 6655#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID15_MASK_MASK 0x00008000L 6656#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID16_MASK_MASK 0x00010000L 6657#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID17_MASK_MASK 0x00020000L 6658#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID18_MASK_MASK 0x00040000L 6659#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID19_MASK_MASK 0x00080000L 6660#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID20_MASK_MASK 0x00100000L 6661#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID21_MASK_MASK 0x00200000L 6662#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID22_MASK_MASK 0x00400000L 6663#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID23_MASK_MASK 0x00800000L 6664#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID24_MASK_MASK 0x01000000L 6665#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID25_MASK_MASK 0x02000000L 6666#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID26_MASK_MASK 0x04000000L 6667#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID27_MASK_MASK 0x08000000L 6668#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID28_MASK_MASK 0x10000000L 6669#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID29_MASK_MASK 0x20000000L 6670#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID30_MASK_MASK 0x40000000L 6671#define MMEA1_IO_WR_PRI_URGENCY_MASK__CID31_MASK_MASK 0x80000000L 6672//MMEA1_IO_RD_PRI_QUANT_PRI1 6673#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 6674#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 6675#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 6676#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 6677#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 6678#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 6679#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 6680#define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 6681//MMEA1_IO_RD_PRI_QUANT_PRI2 6682#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 6683#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 6684#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 6685#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 6686#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 6687#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 6688#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 6689#define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 6690//MMEA1_IO_RD_PRI_QUANT_PRI3 6691#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 6692#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 6693#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 6694#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 6695#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 6696#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 6697#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 6698#define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 6699//MMEA1_IO_WR_PRI_QUANT_PRI1 6700#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 6701#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 6702#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 6703#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 6704#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 6705#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 6706#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 6707#define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 6708//MMEA1_IO_WR_PRI_QUANT_PRI2 6709#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 6710#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 6711#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 6712#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 6713#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 6714#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 6715#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 6716#define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 6717//MMEA1_IO_WR_PRI_QUANT_PRI3 6718#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 6719#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 6720#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 6721#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 6722#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 6723#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 6724#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 6725#define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 6726//MMEA1_SDP_ARB_DRAM 6727#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 6728#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 6729#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 6730#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 6731#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 6732#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 6733#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 6734#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 6735#define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 6736#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 6737#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 6738#define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 6739#define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 6740#define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 6741//MMEA1_SDP_ARB_FINAL 6742#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 6743#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 6744#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 6745#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 6746#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 6747#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 6748#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 6749#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 6750#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 6751#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 6752#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 6753#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 6754#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 6755#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 6756#define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 6757#define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 6758#define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 6759#define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 6760#define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 6761#define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 6762#define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 6763#define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 6764#define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 6765#define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 6766#define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 6767#define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 6768#define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 6769#define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 6770//MMEA1_SDP_DRAM_PRIORITY 6771#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 6772#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 6773#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 6774#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 6775#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 6776#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 6777#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 6778#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 6779#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 6780#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 6781#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 6782#define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 6783#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 6784#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 6785#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 6786#define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 6787//MMEA1_SDP_IO_PRIORITY 6788#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 6789#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 6790#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 6791#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 6792#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 6793#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 6794#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 6795#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 6796#define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 6797#define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 6798#define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 6799#define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 6800#define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 6801#define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 6802#define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 6803#define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 6804//MMEA1_SDP_CREDITS 6805#define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 6806#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 6807#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 6808#define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 6809#define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 6810#define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 6811//MMEA1_SDP_TAG_RESERVE0 6812#define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 6813#define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 6814#define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 6815#define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 6816#define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 6817#define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 6818#define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 6819#define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 6820//MMEA1_SDP_TAG_RESERVE1 6821#define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 6822#define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 6823#define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 6824#define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 6825#define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 6826#define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 6827#define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 6828#define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 6829//MMEA1_SDP_VCC_RESERVE0 6830#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 6831#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 6832#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 6833#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 6834#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 6835#define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 6836#define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 6837#define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 6838#define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 6839#define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 6840//MMEA1_SDP_VCC_RESERVE1 6841#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 6842#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 6843#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 6844#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 6845#define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 6846#define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 6847#define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 6848#define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 6849//MMEA1_SDP_VCD_RESERVE0 6850#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 6851#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 6852#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 6853#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 6854#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 6855#define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 6856#define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 6857#define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 6858#define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 6859#define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 6860//MMEA1_SDP_VCD_RESERVE1 6861#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 6862#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 6863#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 6864#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 6865#define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 6866#define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 6867#define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 6868#define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 6869//MMEA1_SDP_REQ_CNTL 6870#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 6871#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 6872#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 6873#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 6874#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x4 6875#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 6876#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 6877#define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 6878#define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 6879#define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000010L 6880//MMEA1_MISC 6881#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 6882#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 6883#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 6884#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 6885#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 6886#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 6887#define MMEA1_MISC__RRET_SWAP_MODE__SHIFT 0x6 6888#define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0x7 6889#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0x8 6890#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0xa 6891#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0xc 6892#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0xe 6893#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x13 6894#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x14 6895#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x15 6896#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x16 6897#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x17 6898#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x18 6899#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 6900#define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 6901#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 6902#define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 6903#define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 6904#define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 6905#define MMEA1_MISC__RRET_SWAP_MODE_MASK 0x00000040L 6906#define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00000080L 6907#define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00000300L 6908#define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00000C00L 6909#define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00003000L 6910#define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x0007C000L 6911#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x00080000L 6912#define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x00100000L 6913#define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x00200000L 6914#define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x00400000L 6915#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x00800000L 6916#define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x01000000L 6917//MMEA1_LATENCY_SAMPLING 6918#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 6919#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 6920#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 6921#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 6922#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 6923#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 6924#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 6925#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 6926#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 6927#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 6928#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 6929#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 6930#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 6931#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 6932#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 6933#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 6934#define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 6935#define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 6936#define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 6937#define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 6938#define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 6939#define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 6940#define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 6941#define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 6942#define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 6943#define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 6944#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 6945#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 6946#define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 6947#define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 6948#define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 6949#define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 6950//MMEA1_PERFCOUNTER_LO 6951#define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 6952#define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 6953//MMEA1_PERFCOUNTER_HI 6954#define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 6955#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 6956#define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 6957#define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 6958//MMEA1_PERFCOUNTER0_CFG 6959#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 6960#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 6961#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 6962#define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 6963#define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 6964#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 6965#define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 6966#define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 6967#define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 6968#define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 6969//MMEA1_PERFCOUNTER1_CFG 6970#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 6971#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 6972#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 6973#define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 6974#define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 6975#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 6976#define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 6977#define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 6978#define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 6979#define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 6980//MMEA1_PERFCOUNTER_RSLT_CNTL 6981#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 6982#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 6983#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 6984#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 6985#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 6986#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 6987#define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 6988#define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 6989#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 6990#define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 6991#define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 6992#define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 6993//MMEA1_EDC_CNT 6994#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 6995#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 6996#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 6997#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 6998#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 6999#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 7000#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 7001#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 7002#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 7003#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 7004#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 7005#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 7006#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 7007#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 7008#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 7009#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 7010#define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 7011#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 7012#define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 7013#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 7014#define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 7015#define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 7016#define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 7017#define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 7018#define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 7019#define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 7020#define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 7021#define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 7022#define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 7023#define MMEA1_EDC_CNT__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 7024//MMEA1_EDC_CNT2 7025#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 7026#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 7027#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 7028#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 7029#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 7030#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 7031#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 7032#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 7033#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 7034#define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 7035#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 7036#define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 7037#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 7038#define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 7039#define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 7040#define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 7041//MMEA1_DSM_CNTL 7042#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 7043#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 7044#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 7045#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 7046#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 7047#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 7048#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 7049#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 7050#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 7051#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 7052#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 7053#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 7054#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 7055#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 7056#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 7057#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 7058#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 7059#define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 7060#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 7061#define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 7062#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 7063#define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 7064#define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 7065#define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 7066#define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 7067#define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 7068#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 7069#define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 7070#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 7071#define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 7072#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 7073#define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 7074//MMEA1_DSM_CNTLA 7075#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 7076#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 7077#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 7078#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 7079#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 7080#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 7081#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 7082#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 7083#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 7084#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 7085#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 7086#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 7087#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 7088#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 7089#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 7090#define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 7091#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 7092#define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 7093#define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 7094#define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 7095#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 7096#define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 7097#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 7098#define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 7099#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 7100#define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 7101#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 7102#define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 7103//MMEA1_DSM_CNTLB 7104//MMEA1_DSM_CNTL2 7105#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 7106#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 7107#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 7108#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 7109#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 7110#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 7111#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 7112#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 7113#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 7114#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 7115#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 7116#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 7117#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 7118#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 7119#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 7120#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 7121#define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 7122#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 7123#define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 7124#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 7125#define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 7126#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 7127#define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 7128#define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 7129#define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 7130#define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 7131#define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 7132#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 7133#define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 7134#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 7135#define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 7136#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 7137#define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 7138#define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 7139//MMEA1_DSM_CNTL2A 7140#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 7141#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 7142#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 7143#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 7144#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 7145#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 7146#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 7147#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 7148#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 7149#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 7150#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 7151#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 7152#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 7153#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 7154#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 7155#define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 7156#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 7157#define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 7158#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 7159#define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 7160#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 7161#define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 7162#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 7163#define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 7164#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 7165#define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 7166#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 7167#define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 7168//MMEA1_DSM_CNTL2B 7169//MMEA1_CGTT_CLK_CTRL 7170#define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7171#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7172#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7173#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7174#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 7175#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 7176#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 7177#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 7178#define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7179#define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7180#define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7181#define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7182#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 7183#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 7184#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 7185#define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 7186//MMEA1_EDC_MODE 7187#define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 7188#define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 7189#define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 7190#define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d 7191#define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f 7192#define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 7193#define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L 7194#define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L 7195#define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L 7196#define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L 7197//MMEA1_ERR_STATUS 7198#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 7199#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 7200#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0x8 7201#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0x9 7202#define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xa 7203#define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 7204#define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 7205#define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000100L 7206#define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000200L 7207#define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00000400L 7208//MMEA1_MISC2 7209#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 7210#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 7211#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 7212#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 7213#define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 7214#define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 7215#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 7216#define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 7217 7218 7219// addressBlock: mmhub_pctldec 7220//PCTL_MISC 7221#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x0 7222#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD__SHIFT 0x3 7223#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0x6 7224#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0xb 7225#define PCTL_MISC__IGNORE_EA0_SDP_ACK__SHIFT 0xc 7226#define PCTL_MISC__IGNORE_EA1_SDP_ACK__SHIFT 0xd 7227#define PCTL_MISC__PGFSM_CMD_STATUS__SHIFT 0xe 7228#define PCTL_MISC__ALLOW_DEEP_SLEEP_MODE_MASK 0x00000007L 7229#define PCTL_MISC__STCTRL_RSMU_IDLE_THRESHOLD_MASK 0x00000038L 7230#define PCTL_MISC__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x000007C0L 7231#define PCTL_MISC__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00000800L 7232#define PCTL_MISC__IGNORE_EA0_SDP_ACK_MASK 0x00001000L 7233#define PCTL_MISC__IGNORE_EA1_SDP_ACK_MASK 0x00002000L 7234#define PCTL_MISC__PGFSM_CMD_STATUS_MASK 0x0000C000L 7235//PCTL_MMHUB_DEEPSLEEP 7236#define PCTL_MMHUB_DEEPSLEEP__DS0__SHIFT 0x0 7237#define PCTL_MMHUB_DEEPSLEEP__DS1__SHIFT 0x1 7238#define PCTL_MMHUB_DEEPSLEEP__DS2__SHIFT 0x2 7239#define PCTL_MMHUB_DEEPSLEEP__DS3__SHIFT 0x3 7240#define PCTL_MMHUB_DEEPSLEEP__DS4__SHIFT 0x4 7241#define PCTL_MMHUB_DEEPSLEEP__DS5__SHIFT 0x5 7242#define PCTL_MMHUB_DEEPSLEEP__DS6__SHIFT 0x6 7243#define PCTL_MMHUB_DEEPSLEEP__DS7__SHIFT 0x7 7244#define PCTL_MMHUB_DEEPSLEEP__DS8__SHIFT 0x8 7245#define PCTL_MMHUB_DEEPSLEEP__DS9__SHIFT 0x9 7246#define PCTL_MMHUB_DEEPSLEEP__DS10__SHIFT 0xa 7247#define PCTL_MMHUB_DEEPSLEEP__DS11__SHIFT 0xb 7248#define PCTL_MMHUB_DEEPSLEEP__DS12__SHIFT 0xc 7249#define PCTL_MMHUB_DEEPSLEEP__DS13__SHIFT 0xd 7250#define PCTL_MMHUB_DEEPSLEEP__DS14__SHIFT 0xe 7251#define PCTL_MMHUB_DEEPSLEEP__DS15__SHIFT 0xf 7252#define PCTL_MMHUB_DEEPSLEEP__DS16__SHIFT 0x10 7253#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR__SHIFT 0x1f 7254#define PCTL_MMHUB_DEEPSLEEP__DS0_MASK 0x00000001L 7255#define PCTL_MMHUB_DEEPSLEEP__DS1_MASK 0x00000002L 7256#define PCTL_MMHUB_DEEPSLEEP__DS2_MASK 0x00000004L 7257#define PCTL_MMHUB_DEEPSLEEP__DS3_MASK 0x00000008L 7258#define PCTL_MMHUB_DEEPSLEEP__DS4_MASK 0x00000010L 7259#define PCTL_MMHUB_DEEPSLEEP__DS5_MASK 0x00000020L 7260#define PCTL_MMHUB_DEEPSLEEP__DS6_MASK 0x00000040L 7261#define PCTL_MMHUB_DEEPSLEEP__DS7_MASK 0x00000080L 7262#define PCTL_MMHUB_DEEPSLEEP__DS8_MASK 0x00000100L 7263#define PCTL_MMHUB_DEEPSLEEP__DS9_MASK 0x00000200L 7264#define PCTL_MMHUB_DEEPSLEEP__DS10_MASK 0x00000400L 7265#define PCTL_MMHUB_DEEPSLEEP__DS11_MASK 0x00000800L 7266#define PCTL_MMHUB_DEEPSLEEP__DS12_MASK 0x00001000L 7267#define PCTL_MMHUB_DEEPSLEEP__DS13_MASK 0x00002000L 7268#define PCTL_MMHUB_DEEPSLEEP__DS14_MASK 0x00004000L 7269#define PCTL_MMHUB_DEEPSLEEP__DS15_MASK 0x00008000L 7270#define PCTL_MMHUB_DEEPSLEEP__DS16_MASK 0x00010000L 7271#define PCTL_MMHUB_DEEPSLEEP__SETCLEAR_MASK 0x80000000L 7272//PCTL_MMHUB_DEEPSLEEP_OVERRIDE 7273#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 7274#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 7275#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 7276#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 7277#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 7278#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 7279#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 7280#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 7281#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 7282#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 7283#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 7284#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 7285#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 7286#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 7287#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 7288#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 7289#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 7290#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 7291#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 7292#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 7293#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 7294#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 7295#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 7296#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 7297#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 7298#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 7299#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 7300#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 7301#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 7302#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 7303#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 7304#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 7305#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 7306#define PCTL_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 7307//PCTL_PG_IGNORE_DEEPSLEEP 7308#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x0 7309#define PCTL_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x1 7310#define PCTL_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x2 7311#define PCTL_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x3 7312#define PCTL_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x4 7313#define PCTL_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x5 7314#define PCTL_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x6 7315#define PCTL_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x7 7316#define PCTL_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x8 7317#define PCTL_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x9 7318#define PCTL_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0xa 7319#define PCTL_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xb 7320#define PCTL_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xc 7321#define PCTL_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xd 7322#define PCTL_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xe 7323#define PCTL_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xf 7324#define PCTL_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0x10 7325#define PCTL_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x11 7326#define PCTL_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00000001L 7327#define PCTL_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000002L 7328#define PCTL_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000004L 7329#define PCTL_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000008L 7330#define PCTL_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000010L 7331#define PCTL_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000020L 7332#define PCTL_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000040L 7333#define PCTL_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000080L 7334#define PCTL_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000100L 7335#define PCTL_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000200L 7336#define PCTL_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000400L 7337#define PCTL_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000800L 7338#define PCTL_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00001000L 7339#define PCTL_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00002000L 7340#define PCTL_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00004000L 7341#define PCTL_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00008000L 7342#define PCTL_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00010000L 7343#define PCTL_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00020000L 7344//PCTL_PG_DAGB 7345#define PCTL_PG_DAGB__DS0__SHIFT 0x0 7346#define PCTL_PG_DAGB__DS1__SHIFT 0x1 7347#define PCTL_PG_DAGB__DS2__SHIFT 0x2 7348#define PCTL_PG_DAGB__DS3__SHIFT 0x3 7349#define PCTL_PG_DAGB__DS4__SHIFT 0x4 7350#define PCTL_PG_DAGB__DS5__SHIFT 0x5 7351#define PCTL_PG_DAGB__DS6__SHIFT 0x6 7352#define PCTL_PG_DAGB__DS7__SHIFT 0x7 7353#define PCTL_PG_DAGB__DS8__SHIFT 0x8 7354#define PCTL_PG_DAGB__DS9__SHIFT 0x9 7355#define PCTL_PG_DAGB__DS10__SHIFT 0xa 7356#define PCTL_PG_DAGB__DS11__SHIFT 0xb 7357#define PCTL_PG_DAGB__DS12__SHIFT 0xc 7358#define PCTL_PG_DAGB__DS13__SHIFT 0xd 7359#define PCTL_PG_DAGB__DS14__SHIFT 0xe 7360#define PCTL_PG_DAGB__DS15__SHIFT 0xf 7361#define PCTL_PG_DAGB__DS16__SHIFT 0x10 7362#define PCTL_PG_DAGB__DS0_MASK 0x00000001L 7363#define PCTL_PG_DAGB__DS1_MASK 0x00000002L 7364#define PCTL_PG_DAGB__DS2_MASK 0x00000004L 7365#define PCTL_PG_DAGB__DS3_MASK 0x00000008L 7366#define PCTL_PG_DAGB__DS4_MASK 0x00000010L 7367#define PCTL_PG_DAGB__DS5_MASK 0x00000020L 7368#define PCTL_PG_DAGB__DS6_MASK 0x00000040L 7369#define PCTL_PG_DAGB__DS7_MASK 0x00000080L 7370#define PCTL_PG_DAGB__DS8_MASK 0x00000100L 7371#define PCTL_PG_DAGB__DS9_MASK 0x00000200L 7372#define PCTL_PG_DAGB__DS10_MASK 0x00000400L 7373#define PCTL_PG_DAGB__DS11_MASK 0x00000800L 7374#define PCTL_PG_DAGB__DS12_MASK 0x00001000L 7375#define PCTL_PG_DAGB__DS13_MASK 0x00002000L 7376#define PCTL_PG_DAGB__DS14_MASK 0x00004000L 7377#define PCTL_PG_DAGB__DS15_MASK 0x00008000L 7378#define PCTL_PG_DAGB__DS16_MASK 0x00010000L 7379//PCTL0_RENG_RAM_INDEX 7380#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 7381#define PCTL0_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000007FFL 7382//PCTL0_RENG_RAM_DATA 7383#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 7384#define PCTL0_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 7385//PCTL0_RENG_EXECUTE 7386#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 7387#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 7388#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 7389#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 7390#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xe 7391#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x19 7392#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 7393#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 7394#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 7395#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00003FF8L 7396#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x01FFC000L 7397#define PCTL0_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x02000000L 7398//PCTL0_MISC 7399#define PCTL0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 7400#define PCTL0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 7401#define PCTL0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 7402#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 7403#define PCTL0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 7404#define PCTL0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 7405#define PCTL0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 7406#define PCTL0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 7407//PCTL0_STCTRL_REGISTER_SAVE_RANGE0 7408#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7409#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7410#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7411#define PCTL0_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7412//PCTL0_STCTRL_REGISTER_SAVE_RANGE1 7413#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7414#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7415#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7416#define PCTL0_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7417//PCTL0_STCTRL_REGISTER_SAVE_RANGE2 7418#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7419#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7420#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7421#define PCTL0_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7422//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET 7423#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 7424#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 7425#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 7426#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 7427//PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1 7428#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 7429#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 7430#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 7431#define PCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 7432//PCTL1_RENG_RAM_INDEX 7433#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 7434#define PCTL1_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 7435//PCTL1_RENG_RAM_DATA 7436#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 7437#define PCTL1_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 7438//PCTL1_RENG_EXECUTE 7439#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 7440#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 7441#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 7442#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 7443#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 7444#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 7445#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 7446#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 7447#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 7448#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L 7449#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L 7450#define PCTL1_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L 7451//PCTL1_MISC 7452#define PCTL1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 7453#define PCTL1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 7454#define PCTL1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 7455#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 7456#define PCTL1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 7457#define PCTL1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 7458#define PCTL1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 7459#define PCTL1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 7460#define PCTL1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 7461#define PCTL1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 7462//PCTL1_STCTRL_REGISTER_SAVE_RANGE0 7463#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7464#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7465#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7466#define PCTL1_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7467//PCTL1_STCTRL_REGISTER_SAVE_RANGE1 7468#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7469#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7470#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7471#define PCTL1_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7472//PCTL1_STCTRL_REGISTER_SAVE_RANGE2 7473#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7474#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7475#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7476#define PCTL1_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7477//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET 7478#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 7479#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 7480#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 7481#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 7482//PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1 7483#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 7484#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 7485#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 7486#define PCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 7487//PCTL2_RENG_RAM_INDEX 7488#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX__SHIFT 0x0 7489#define PCTL2_RENG_RAM_INDEX__RENG_RAM_INDEX_MASK 0x000003FFL 7490//PCTL2_RENG_RAM_DATA 7491#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA__SHIFT 0x0 7492#define PCTL2_RENG_RAM_DATA__RENG_RAM_DATA_MASK 0xFFFFFFFFL 7493//PCTL2_RENG_EXECUTE 7494#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP__SHIFT 0x0 7495#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW__SHIFT 0x1 7496#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE__SHIFT 0x2 7497#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR__SHIFT 0x3 7498#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR__SHIFT 0xd 7499#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x17 7500#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK 0x00000001L 7501#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MASK 0x00000002L 7502#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_MODE_MASK 0x00000004L 7503#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_NOW_START_PTR_MASK 0x00001FF8L 7504#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_END_PTR_MASK 0x007FE000L 7505#define PCTL2_RENG_EXECUTE__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00800000L 7506//PCTL2_MISC 7507#define PCTL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 7508#define PCTL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 7509#define PCTL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 7510#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 7511#define PCTL2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 7512#define PCTL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 7513#define PCTL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 7514#define PCTL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 7515#define PCTL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 7516#define PCTL2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 7517//PCTL2_STCTRL_REGISTER_SAVE_RANGE0 7518#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7519#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7520#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7521#define PCTL2_STCTRL_REGISTER_SAVE_RANGE0__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7522//PCTL2_STCTRL_REGISTER_SAVE_RANGE1 7523#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7524#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7525#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7526#define PCTL2_STCTRL_REGISTER_SAVE_RANGE1__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7527//PCTL2_STCTRL_REGISTER_SAVE_RANGE2 7528#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE__SHIFT 0x0 7529#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT__SHIFT 0x10 7530#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_BASE_MASK 0x0000FFFFL 7531#define PCTL2_STCTRL_REGISTER_SAVE_RANGE2__STCTRL_REGISTER_SAVE_LIMIT_MASK 0xFFFF0000L 7532//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET 7533#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0__SHIFT 0x0 7534#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1__SHIFT 0x10 7535#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL0_MASK 0x0000FFFFL 7536#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET__STCTRL_REGISTER_SAVE_EXCL1_MASK 0xFFFF0000L 7537//PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1 7538#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2__SHIFT 0x0 7539#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3__SHIFT 0x10 7540#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL2_MASK 0x0000FFFFL 7541#define PCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1__STCTRL_REGISTER_SAVE_EXCL3_MASK 0xFFFF0000L 7542 7543 7544// addressBlock: mmhub_l1tlb_vml1dec 7545//MC_VM_MX_L1_TLB0_STATUS 7546#define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 7547#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7548#define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 7549#define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7550//MC_VM_MX_L1_TLB1_STATUS 7551#define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 7552#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7553#define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 7554#define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7555//MC_VM_MX_L1_TLB2_STATUS 7556#define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 7557#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7558#define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 7559#define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7560//MC_VM_MX_L1_TLB3_STATUS 7561#define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 7562#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7563#define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 7564#define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7565//MC_VM_MX_L1_TLB4_STATUS 7566#define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 7567#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7568#define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 7569#define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7570//MC_VM_MX_L1_TLB5_STATUS 7571#define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 7572#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7573#define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 7574#define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7575//MC_VM_MX_L1_TLB6_STATUS 7576#define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 7577#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7578#define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 7579#define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7580//MC_VM_MX_L1_TLB7_STATUS 7581#define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 7582#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 7583#define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 7584#define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 7585 7586 7587// addressBlock: mmhub_l1tlb_vml1pldec 7588//MC_VM_MX_L1_PERFCOUNTER0_CFG 7589#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7590#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7591#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7592#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7593#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7594#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7595#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7596#define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7597#define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7598#define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7599//MC_VM_MX_L1_PERFCOUNTER1_CFG 7600#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7601#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7602#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7603#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7604#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7605#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7606#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7607#define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7608#define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7609#define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7610//MC_VM_MX_L1_PERFCOUNTER2_CFG 7611#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 7612#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 7613#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 7614#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 7615#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 7616#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 7617#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 7618#define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 7619#define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 7620#define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 7621//MC_VM_MX_L1_PERFCOUNTER3_CFG 7622#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 7623#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 7624#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 7625#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 7626#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 7627#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 7628#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 7629#define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 7630#define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 7631#define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 7632//MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 7633#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7634#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7635#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7636#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7637#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7638#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7639#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7640#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7641#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7642#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7643#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7644#define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7645 7646 7647// addressBlock: mmhub_l1tlb_vml1prdec 7648//MC_VM_MX_L1_PERFCOUNTER_LO 7649#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7650#define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7651//MC_VM_MX_L1_PERFCOUNTER_HI 7652#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7653#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7654#define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7655#define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7656 7657 7658// addressBlock: mmhub_utcl2_atcl2dec 7659//ATC_L2_CNTL 7660#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 7661#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 7662#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 7663#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 7664#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x8 7665#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 7666#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 7667#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 7668#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 7669#define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 7670#define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00000700L 7671#define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 7672//ATC_L2_CNTL2 7673#define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 7674#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x6 7675#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x8 7676#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0x9 7677#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xc 7678#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0xf 7679#define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 7680#define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 7681#define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000100L 7682#define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00000E00L 7683#define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00007000L 7684#define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x001F8000L 7685//ATC_L2_CACHE_DATA0 7686#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 7687#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 7688#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 7689#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 7690#define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 7691#define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 7692#define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL 7693#define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L 7694//ATC_L2_CACHE_DATA1 7695#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 7696#define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 7697//ATC_L2_CACHE_DATA2 7698#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 7699#define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 7700//ATC_L2_CNTL3 7701#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x0 7702#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x3 7703#define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x00000007L 7704#define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x000001F8L 7705//ATC_L2_STATUS 7706#define ATC_L2_STATUS__BUSY__SHIFT 0x0 7707#define ATC_L2_STATUS__PARITY_ERROR_INFO__SHIFT 0x1 7708#define ATC_L2_STATUS__BUSY_MASK 0x00000001L 7709#define ATC_L2_STATUS__PARITY_ERROR_INFO_MASK 0x3FFFFFFEL 7710//ATC_L2_STATUS2 7711#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO__SHIFT 0x0 7712#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO__SHIFT 0x8 7713#define ATC_L2_STATUS2__IFIFO_NON_FATAL_PARITY_ERROR_INFO_MASK 0x000000FFL 7714#define ATC_L2_STATUS2__IFIFO_FATAL_PARITY_ERROR_INFO_MASK 0x0000FF00L 7715//ATC_L2_MISC_CG 7716#define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 7717#define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 7718#define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 7719#define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 7720#define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 7721#define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 7722//ATC_L2_MEM_POWER_LS 7723#define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 7724#define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 7725#define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 7726#define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 7727//ATC_L2_CGTT_CLK_CTRL 7728#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7729#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7730#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 7731#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 7732#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 7733#define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7734#define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7735#define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 7736#define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 7737#define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 7738 7739 7740// addressBlock: mmhub_utcl2_vml2pfdec 7741//VM_L2_CNTL 7742#define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 7743#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 7744#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 7745#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 7746#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 7747#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 7748#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 7749#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 7750#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 7751#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 7752#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 7753#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 7754#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 7755#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 7756#define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 7757#define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 7758#define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 7759#define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 7760#define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 7761#define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 7762#define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 7763#define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 7764#define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 7765#define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 7766#define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 7767#define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 7768#define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 7769#define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 7770//VM_L2_CNTL2 7771#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 7772#define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 7773#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 7774#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 7775#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 7776#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 7777#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 7778#define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 7779#define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 7780#define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 7781#define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 7782#define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 7783#define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 7784#define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 7785//VM_L2_CNTL3 7786#define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 7787#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 7788#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 7789#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 7790#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 7791#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 7792#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 7793#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 7794#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 7795#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 7796#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 7797#define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 7798#define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 7799#define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 7800#define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 7801#define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 7802#define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 7803#define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 7804#define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 7805#define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 7806#define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 7807#define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 7808//VM_L2_STATUS 7809#define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 7810#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 7811#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 7812#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 7813#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 7814#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 7815#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 7816#define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L 7817#define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 7818#define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 7819#define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 7820#define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 7821#define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 7822#define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 7823//VM_DUMMY_PAGE_FAULT_CNTL 7824#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 7825#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 7826#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 7827#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 7828#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 7829#define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 7830//VM_DUMMY_PAGE_FAULT_ADDR_LO32 7831#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 7832#define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7833//VM_DUMMY_PAGE_FAULT_ADDR_HI32 7834#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 7835#define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 7836//VM_L2_PROTECTION_FAULT_CNTL 7837#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 7838#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 7839#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 7840#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 7841#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 7842#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 7843#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 7844#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 7845#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 7846#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 7847#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 7848#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 7849#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 7850#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 7851#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 7852#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 7853#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 7854#define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 7855#define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 7856#define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 7857#define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 7858#define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 7859#define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 7860#define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 7861#define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 7862#define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 7863#define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 7864#define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 7865#define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 7866#define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 7867#define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 7868#define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 7869#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 7870#define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 7871//VM_L2_PROTECTION_FAULT_CNTL2 7872#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 7873#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 7874#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 7875#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 7876#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 7877#define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 7878#define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 7879#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 7880#define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 7881#define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 7882//VM_L2_PROTECTION_FAULT_MM_CNTL3 7883#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 7884#define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 7885//VM_L2_PROTECTION_FAULT_MM_CNTL4 7886#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 7887#define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 7888//VM_L2_PROTECTION_FAULT_STATUS 7889#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 7890#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 7891#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 7892#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 7893#define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 7894#define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 7895#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 7896#define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 7897#define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 7898#define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 7899#define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 7900#define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 7901#define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 7902#define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 7903#define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 7904#define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 7905#define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 7906#define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 7907#define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 7908#define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 7909//VM_L2_PROTECTION_FAULT_ADDR_LO32 7910#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 7911#define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7912//VM_L2_PROTECTION_FAULT_ADDR_HI32 7913#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 7914#define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 7915//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 7916#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 7917#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 7918//VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 7919#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 7920#define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 7921//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 7922#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 7923#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 7924//VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 7925#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 7926#define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 7927//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 7928#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 7929#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 7930//VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 7931#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 7932#define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 7933//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 7934#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 7935#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 7936//VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 7937#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 7938#define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 7939//VM_L2_CNTL4 7940#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 7941#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 7942#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 7943#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 7944#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 7945#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 7946#define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 7947#define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 7948#define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 7949#define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 7950#define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 7951#define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 7952//VM_L2_MM_GROUP_RT_CLASSES 7953#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 7954#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 7955#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 7956#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 7957#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 7958#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 7959#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 7960#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 7961#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 7962#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 7963#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 7964#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 7965#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 7966#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 7967#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 7968#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 7969#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 7970#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 7971#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 7972#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 7973#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 7974#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 7975#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 7976#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 7977#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 7978#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 7979#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 7980#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 7981#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 7982#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 7983#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 7984#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 7985#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 7986#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 7987#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 7988#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 7989#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 7990#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 7991#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 7992#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 7993#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 7994#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 7995#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 7996#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 7997#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 7998#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 7999#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 8000#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 8001#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 8002#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 8003#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 8004#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 8005#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 8006#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 8007#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 8008#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 8009#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 8010#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 8011#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 8012#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 8013#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 8014#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 8015#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 8016#define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 8017//VM_L2_BANK_SELECT_RESERVED_CID 8018#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 8019#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 8020#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 8021#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 8022#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 8023#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 8024#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 8025#define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 8026#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 8027#define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 8028//VM_L2_BANK_SELECT_RESERVED_CID2 8029#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 8030#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 8031#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 8032#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 8033#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 8034#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 8035#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 8036#define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 8037#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 8038#define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 8039//VM_L2_CACHE_PARITY_CNTL 8040#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 8041#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 8042#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 8043#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 8044#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 8045#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 8046#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 8047#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 8048#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 8049#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 8050#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 8051#define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 8052#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 8053#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 8054#define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 8055#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 8056#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 8057#define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 8058//VM_L2_CGTT_CLK_CTRL 8059#define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 8060#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 8061#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 8062#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 8063#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 8064#define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 8065#define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 8066#define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 8067#define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 8068#define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 8069 8070 8071// addressBlock: mmhub_utcl2_vml2vcdec 8072//VM_CONTEXT0_CNTL 8073#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8074#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8075#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8076#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8077#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8078#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8079#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8080#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8081#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8082#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8083#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8084#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8085#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8086#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8087#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8088#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8089#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8090#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8091#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8092#define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8093#define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8094#define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8095#define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8096#define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8097#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8098#define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8099#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8100#define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8101#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8102#define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8103#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8104#define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8105#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8106#define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8107#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8108#define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8109#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8110#define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8111//VM_CONTEXT1_CNTL 8112#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8113#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8114#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8115#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8116#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8117#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8118#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8119#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8120#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8121#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8122#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8123#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8124#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8125#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8126#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8127#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8128#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8129#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8130#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8131#define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8132#define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8133#define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8134#define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8135#define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8136#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8137#define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8138#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8139#define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8140#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8141#define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8142#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8143#define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8144#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8145#define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8146#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8147#define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8148#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8149#define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8150//VM_CONTEXT2_CNTL 8151#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8152#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8153#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8154#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8155#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8156#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8157#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8158#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8159#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8160#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8161#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8162#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8163#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8164#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8165#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8166#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8167#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8168#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8169#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8170#define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8171#define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8172#define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8173#define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8174#define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8175#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8176#define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8177#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8178#define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8179#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8180#define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8181#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8182#define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8183#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8184#define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8185#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8186#define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8187#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8188#define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8189//VM_CONTEXT3_CNTL 8190#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8191#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8192#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8193#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8194#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8195#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8196#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8197#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8198#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8199#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8200#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8201#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8202#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8203#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8204#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8205#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8206#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8207#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8208#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8209#define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8210#define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8211#define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8212#define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8213#define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8214#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8215#define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8216#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8217#define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8218#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8219#define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8220#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8221#define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8222#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8223#define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8224#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8225#define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8226#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8227#define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8228//VM_CONTEXT4_CNTL 8229#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8230#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8231#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8232#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8233#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8234#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8235#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8236#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8237#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8238#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8239#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8240#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8241#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8242#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8243#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8244#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8245#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8246#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8247#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8248#define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8249#define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8250#define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8251#define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8252#define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8253#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8254#define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8255#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8256#define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8257#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8258#define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8259#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8260#define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8261#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8262#define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8263#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8264#define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8265#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8266#define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8267//VM_CONTEXT5_CNTL 8268#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8269#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8270#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8271#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8272#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8273#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8274#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8275#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8276#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8277#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8278#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8279#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8280#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8281#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8282#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8283#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8284#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8285#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8286#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8287#define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8288#define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8289#define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8290#define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8291#define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8292#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8293#define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8294#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8295#define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8296#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8297#define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8298#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8299#define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8300#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8301#define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8302#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8303#define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8304#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8305#define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8306//VM_CONTEXT6_CNTL 8307#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8308#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8309#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8310#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8311#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8312#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8313#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8314#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8315#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8316#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8317#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8318#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8319#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8320#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8321#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8322#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8323#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8324#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8325#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8326#define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8327#define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8328#define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8329#define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8330#define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8331#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8332#define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8333#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8334#define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8335#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8336#define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8337#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8338#define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8339#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8340#define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8341#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8342#define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8343#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8344#define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8345//VM_CONTEXT7_CNTL 8346#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8347#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8348#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8349#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8350#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8351#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8352#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8353#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8354#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8355#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8356#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8357#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8358#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8359#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8360#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8361#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8362#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8363#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8364#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8365#define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8366#define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8367#define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8368#define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8369#define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8370#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8371#define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8372#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8373#define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8374#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8375#define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8376#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8377#define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8378#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8379#define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8380#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8381#define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8382#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8383#define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8384//VM_CONTEXT8_CNTL 8385#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8386#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8387#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8388#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8389#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8390#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8391#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8392#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8393#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8394#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8395#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8396#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8397#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8398#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8399#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8400#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8401#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8402#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8403#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8404#define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8405#define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8406#define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8407#define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8408#define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8409#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8410#define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8411#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8412#define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8413#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8414#define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8415#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8416#define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8417#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8418#define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8419#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8420#define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8421#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8422#define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8423//VM_CONTEXT9_CNTL 8424#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8425#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8426#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8427#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8428#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8429#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8430#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8431#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8432#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8433#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8434#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8435#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8436#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8437#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8438#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8439#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8440#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8441#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8442#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8443#define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8444#define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8445#define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8446#define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8447#define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8448#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8449#define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8450#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8451#define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8452#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8453#define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8454#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8455#define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8456#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8457#define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8458#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8459#define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8460#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8461#define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8462//VM_CONTEXT10_CNTL 8463#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8464#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8465#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8466#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8467#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8468#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8469#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8470#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8471#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8472#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8473#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8474#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8475#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8476#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8477#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8478#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8479#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8480#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8481#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8482#define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8483#define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8484#define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8485#define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8486#define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8487#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8488#define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8489#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8490#define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8491#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8492#define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8493#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8494#define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8495#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8496#define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8497#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8498#define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8499#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8500#define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8501//VM_CONTEXT11_CNTL 8502#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8503#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8504#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8505#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8506#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8507#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8508#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8509#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8510#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8511#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8512#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8513#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8514#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8515#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8516#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8517#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8518#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8519#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8520#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8521#define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8522#define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8523#define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8524#define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8525#define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8526#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8527#define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8528#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8529#define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8530#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8531#define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8532#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8533#define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8534#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8535#define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8536#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8537#define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8538#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8539#define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8540//VM_CONTEXT12_CNTL 8541#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8542#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8543#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8544#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8545#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8546#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8547#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8548#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8549#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8550#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8551#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8552#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8553#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8554#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8555#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8556#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8557#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8558#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8559#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8560#define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8561#define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8562#define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8563#define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8564#define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8565#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8566#define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8567#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8568#define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8569#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8570#define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8571#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8572#define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8573#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8574#define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8575#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8576#define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8577#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8578#define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8579//VM_CONTEXT13_CNTL 8580#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8581#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8582#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8583#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8584#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8585#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8586#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8587#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8588#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8589#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8590#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8591#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8592#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8593#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8594#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8595#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8596#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8597#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8598#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8599#define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8600#define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8601#define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8602#define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8603#define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8604#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8605#define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8606#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8607#define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8608#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8609#define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8610#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8611#define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8612#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8613#define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8614#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8615#define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8616#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8617#define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8618//VM_CONTEXT14_CNTL 8619#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8620#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8621#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8622#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8623#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8624#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8625#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8626#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8627#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8628#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8629#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8630#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8631#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8632#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8633#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8634#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8635#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8636#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8637#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8638#define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8639#define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8640#define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8641#define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8642#define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8643#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8644#define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8645#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8646#define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8647#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8648#define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8649#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8650#define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8651#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8652#define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8653#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8654#define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8655#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8656#define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8657//VM_CONTEXT15_CNTL 8658#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 8659#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 8660#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 8661#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 8662#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 8663#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 8664#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 8665#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 8666#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 8667#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 8668#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 8669#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 8670#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 8671#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 8672#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 8673#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 8674#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 8675#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 8676#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 8677#define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 8678#define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 8679#define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 8680#define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 8681#define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 8682#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 8683#define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 8684#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 8685#define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 8686#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 8687#define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 8688#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 8689#define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 8690#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 8691#define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 8692#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 8693#define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 8694#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 8695#define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 8696//VM_CONTEXTS_DISABLE 8697#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 8698#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 8699#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 8700#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 8701#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 8702#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 8703#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 8704#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 8705#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 8706#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 8707#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 8708#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 8709#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 8710#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 8711#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 8712#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 8713#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 8714#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 8715#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 8716#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 8717#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 8718#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 8719#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 8720#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 8721#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 8722#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 8723#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 8724#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 8725#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 8726#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 8727#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 8728#define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 8729//VM_INVALIDATE_ENG0_SEM 8730#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 8731#define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 8732//VM_INVALIDATE_ENG1_SEM 8733#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 8734#define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 8735//VM_INVALIDATE_ENG2_SEM 8736#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 8737#define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 8738//VM_INVALIDATE_ENG3_SEM 8739#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 8740#define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 8741//VM_INVALIDATE_ENG4_SEM 8742#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 8743#define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 8744//VM_INVALIDATE_ENG5_SEM 8745#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 8746#define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 8747//VM_INVALIDATE_ENG6_SEM 8748#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 8749#define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 8750//VM_INVALIDATE_ENG7_SEM 8751#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 8752#define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 8753//VM_INVALIDATE_ENG8_SEM 8754#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 8755#define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 8756//VM_INVALIDATE_ENG9_SEM 8757#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 8758#define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 8759//VM_INVALIDATE_ENG10_SEM 8760#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 8761#define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 8762//VM_INVALIDATE_ENG11_SEM 8763#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 8764#define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 8765//VM_INVALIDATE_ENG12_SEM 8766#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 8767#define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 8768//VM_INVALIDATE_ENG13_SEM 8769#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 8770#define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 8771//VM_INVALIDATE_ENG14_SEM 8772#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 8773#define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 8774//VM_INVALIDATE_ENG15_SEM 8775#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 8776#define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 8777//VM_INVALIDATE_ENG16_SEM 8778#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 8779#define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 8780//VM_INVALIDATE_ENG17_SEM 8781#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 8782#define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 8783//VM_INVALIDATE_ENG0_REQ 8784#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8785#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 8786#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8787#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8788#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8789#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8790#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8791#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8792#define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8793#define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L 8794#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8795#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8796#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8797#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8798#define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8799#define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8800//VM_INVALIDATE_ENG1_REQ 8801#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8802#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 8803#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8804#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8805#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8806#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8807#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8808#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8809#define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8810#define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L 8811#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8812#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8813#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8814#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8815#define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8816#define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8817//VM_INVALIDATE_ENG2_REQ 8818#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8819#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 8820#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8821#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8822#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8823#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8824#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8825#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8826#define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8827#define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L 8828#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8829#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8830#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8831#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8832#define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8833#define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8834//VM_INVALIDATE_ENG3_REQ 8835#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8836#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 8837#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8838#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8839#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8840#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8841#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8842#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8843#define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8844#define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L 8845#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8846#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8847#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8848#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8849#define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8850#define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8851//VM_INVALIDATE_ENG4_REQ 8852#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8853#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 8854#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8855#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8856#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8857#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8858#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8859#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8860#define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8861#define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L 8862#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8863#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8864#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8865#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8866#define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8867#define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8868//VM_INVALIDATE_ENG5_REQ 8869#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8870#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 8871#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8872#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8873#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8874#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8875#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8876#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8877#define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8878#define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L 8879#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8880#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8881#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8882#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8883#define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8884#define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8885//VM_INVALIDATE_ENG6_REQ 8886#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8887#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 8888#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8889#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8890#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8891#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8892#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8893#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8894#define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8895#define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L 8896#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8897#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8898#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8899#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8900#define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8901#define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8902//VM_INVALIDATE_ENG7_REQ 8903#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8904#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 8905#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8906#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8907#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8908#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8909#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8910#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8911#define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8912#define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L 8913#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8914#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8915#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8916#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8917#define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8918#define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8919//VM_INVALIDATE_ENG8_REQ 8920#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8921#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 8922#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8923#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8924#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8925#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8926#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8927#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8928#define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8929#define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L 8930#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8931#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8932#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8933#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8934#define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8935#define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8936//VM_INVALIDATE_ENG9_REQ 8937#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8938#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 8939#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8940#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8941#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8942#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8943#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8944#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8945#define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8946#define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L 8947#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8948#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8949#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8950#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8951#define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8952#define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8953//VM_INVALIDATE_ENG10_REQ 8954#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8955#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 8956#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8957#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8958#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8959#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8960#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8961#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8962#define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8963#define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L 8964#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8965#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8966#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8967#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8968#define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8969#define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8970//VM_INVALIDATE_ENG11_REQ 8971#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8972#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 8973#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8974#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8975#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8976#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8977#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8978#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8979#define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8980#define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L 8981#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8982#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 8983#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 8984#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 8985#define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 8986#define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 8987//VM_INVALIDATE_ENG12_REQ 8988#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 8989#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 8990#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 8991#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 8992#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 8993#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 8994#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 8995#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 8996#define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 8997#define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L 8998#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 8999#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9000#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9001#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9002#define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9003#define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9004//VM_INVALIDATE_ENG13_REQ 9005#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9006#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 9007#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9008#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9009#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9010#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9011#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9012#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9013#define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9014#define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L 9015#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9016#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9017#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9018#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9019#define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9020#define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9021//VM_INVALIDATE_ENG14_REQ 9022#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9023#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 9024#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9025#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9026#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9027#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9028#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9029#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9030#define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9031#define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L 9032#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9033#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9034#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9035#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9036#define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9037#define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9038//VM_INVALIDATE_ENG15_REQ 9039#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9040#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 9041#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9042#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9043#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9044#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9045#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9046#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9047#define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9048#define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L 9049#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9050#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9051#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9052#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9053#define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9054#define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9055//VM_INVALIDATE_ENG16_REQ 9056#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9057#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 9058#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9059#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9060#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9061#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9062#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9063#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9064#define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9065#define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L 9066#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9067#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9068#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9069#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9070#define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9071#define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9072//VM_INVALIDATE_ENG17_REQ 9073#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 9074#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 9075#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 9076#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 9077#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 9078#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 9079#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 9080#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 9081#define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 9082#define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L 9083#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 9084#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 9085#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 9086#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 9087#define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 9088#define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 9089//VM_INVALIDATE_ENG0_ACK 9090#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9091#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 9092#define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9093#define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 9094//VM_INVALIDATE_ENG1_ACK 9095#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9096#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 9097#define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9098#define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 9099//VM_INVALIDATE_ENG2_ACK 9100#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9101#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 9102#define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9103#define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 9104//VM_INVALIDATE_ENG3_ACK 9105#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9106#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 9107#define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9108#define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 9109//VM_INVALIDATE_ENG4_ACK 9110#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9111#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 9112#define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9113#define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 9114//VM_INVALIDATE_ENG5_ACK 9115#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9116#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 9117#define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9118#define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 9119//VM_INVALIDATE_ENG6_ACK 9120#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9121#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 9122#define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9123#define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 9124//VM_INVALIDATE_ENG7_ACK 9125#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9126#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 9127#define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9128#define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 9129//VM_INVALIDATE_ENG8_ACK 9130#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9131#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 9132#define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9133#define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 9134//VM_INVALIDATE_ENG9_ACK 9135#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9136#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 9137#define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9138#define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 9139//VM_INVALIDATE_ENG10_ACK 9140#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9141#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 9142#define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9143#define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 9144//VM_INVALIDATE_ENG11_ACK 9145#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9146#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 9147#define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9148#define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 9149//VM_INVALIDATE_ENG12_ACK 9150#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9151#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 9152#define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9153#define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 9154//VM_INVALIDATE_ENG13_ACK 9155#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9156#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 9157#define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9158#define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 9159//VM_INVALIDATE_ENG14_ACK 9160#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9161#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 9162#define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9163#define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 9164//VM_INVALIDATE_ENG15_ACK 9165#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9166#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 9167#define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9168#define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 9169//VM_INVALIDATE_ENG16_ACK 9170#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9171#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 9172#define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9173#define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 9174//VM_INVALIDATE_ENG17_ACK 9175#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 9176#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 9177#define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 9178#define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 9179//VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 9180#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9181#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9182#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9183#define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9184//VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 9185#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9186#define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9187//VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 9188#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9189#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9190#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9191#define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9192//VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 9193#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9194#define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9195//VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 9196#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9197#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9198#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9199#define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9200//VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 9201#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9202#define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9203//VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 9204#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9205#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9206#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9207#define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9208//VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 9209#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9210#define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9211//VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 9212#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9213#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9214#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9215#define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9216//VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 9217#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9218#define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9219//VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 9220#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9221#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9222#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9223#define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9224//VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 9225#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9226#define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9227//VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 9228#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9229#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9230#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9231#define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9232//VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 9233#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9234#define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9235//VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 9236#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9237#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9238#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9239#define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9240//VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 9241#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9242#define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9243//VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 9244#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9245#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9246#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9247#define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9248//VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 9249#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9250#define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9251//VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 9252#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9253#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9254#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9255#define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9256//VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 9257#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9258#define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9259//VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 9260#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9261#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9262#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9263#define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9264//VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 9265#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9266#define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9267//VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 9268#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9269#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9270#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9271#define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9272//VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 9273#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9274#define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9275//VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 9276#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9277#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9278#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9279#define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9280//VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 9281#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9282#define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9283//VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 9284#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9285#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9286#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9287#define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9288//VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 9289#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9290#define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9291//VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 9292#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9293#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9294#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9295#define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9296//VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 9297#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9298#define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9299//VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 9300#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9301#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9302#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9303#define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9304//VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 9305#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9306#define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9307//VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 9308#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9309#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9310#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9311#define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9312//VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 9313#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9314#define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9315//VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 9316#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 9317#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 9318#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 9319#define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 9320//VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 9321#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 9322#define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 9323//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 9324#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9325#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9326//VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 9327#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9328#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9329//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 9330#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9331#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9332//VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 9333#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9334#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9335//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 9336#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9337#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9338//VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 9339#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9340#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9341//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 9342#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9343#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9344//VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 9345#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9346#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9347//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 9348#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9349#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9350//VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 9351#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9352#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9353//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 9354#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9355#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9356//VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 9357#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9358#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9359//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 9360#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9361#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9362//VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 9363#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9364#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9365//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 9366#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9367#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9368//VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 9369#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9370#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9371//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 9372#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9373#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9374//VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 9375#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9376#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9377//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 9378#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9379#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9380//VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 9381#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9382#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9383//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 9384#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9385#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9386//VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 9387#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9388#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9389//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 9390#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9391#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9392//VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 9393#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9394#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9395//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 9396#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9397#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9398//VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 9399#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9400#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9401//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 9402#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9403#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9404//VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 9405#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9406#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9407//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 9408#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9409#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9410//VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 9411#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9412#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9413//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 9414#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 9415#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 9416//VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 9417#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 9418#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 9419//VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 9420#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9421#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9422//VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 9423#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9424#define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9425//VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 9426#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9427#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9428//VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 9429#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9430#define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9431//VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 9432#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9433#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9434//VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 9435#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9436#define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9437//VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 9438#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9439#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9440//VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 9441#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9442#define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9443//VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 9444#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9445#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9446//VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 9447#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9448#define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9449//VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 9450#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9451#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9452//VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 9453#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9454#define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9455//VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 9456#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9457#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9458//VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 9459#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9460#define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9461//VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 9462#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9463#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9464//VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 9465#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9466#define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9467//VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 9468#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9469#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9470//VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 9471#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9472#define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9473//VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 9474#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9475#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9476//VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 9477#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9478#define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9479//VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 9480#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9481#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9482//VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 9483#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9484#define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9485//VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 9486#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9487#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9488//VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 9489#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9490#define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9491//VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 9492#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9493#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9494//VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 9495#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9496#define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9497//VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 9498#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9499#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9500//VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 9501#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9502#define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9503//VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 9504#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9505#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9506//VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 9507#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9508#define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9509//VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 9510#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9511#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9512//VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 9513#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9514#define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9515//VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 9516#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9517#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9518//VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 9519#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9520#define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9521//VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 9522#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9523#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9524//VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 9525#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9526#define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9527//VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 9528#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9529#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9530//VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 9531#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9532#define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9533//VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 9534#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9535#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9536//VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 9537#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9538#define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9539//VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 9540#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9541#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9542//VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 9543#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9544#define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9545//VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 9546#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9547#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9548//VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 9549#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9550#define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9551//VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 9552#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9553#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9554//VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 9555#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9556#define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9557//VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 9558#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9559#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9560//VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 9561#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9562#define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9563//VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 9564#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9565#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9566//VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 9567#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9568#define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9569//VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 9570#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9571#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9572//VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 9573#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9574#define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9575//VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 9576#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9577#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9578//VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 9579#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9580#define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9581//VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 9582#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9583#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9584//VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 9585#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9586#define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9587//VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 9588#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9589#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9590//VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 9591#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9592#define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9593//VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 9594#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9595#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9596//VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 9597#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9598#define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9599//VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 9600#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9601#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9602//VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 9603#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9604#define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9605//VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 9606#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 9607#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 9608//VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 9609#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 9610#define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 9611 9612 9613// addressBlock: mmhub_utcl2_vml2pldec 9614//MC_VM_L2_PERFCOUNTER0_CFG 9615#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 9616#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 9617#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 9618#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 9619#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 9620#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 9621#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 9622#define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 9623#define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 9624#define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 9625//MC_VM_L2_PERFCOUNTER1_CFG 9626#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 9627#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 9628#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 9629#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 9630#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 9631#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 9632#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 9633#define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 9634#define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 9635#define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 9636//MC_VM_L2_PERFCOUNTER2_CFG 9637#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 9638#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 9639#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 9640#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 9641#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 9642#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 9643#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 9644#define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 9645#define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 9646#define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 9647//MC_VM_L2_PERFCOUNTER3_CFG 9648#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 9649#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 9650#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 9651#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 9652#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 9653#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 9654#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 9655#define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 9656#define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 9657#define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 9658//MC_VM_L2_PERFCOUNTER4_CFG 9659#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 9660#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 9661#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 9662#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 9663#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 9664#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 9665#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 9666#define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 9667#define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 9668#define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 9669//MC_VM_L2_PERFCOUNTER5_CFG 9670#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 9671#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 9672#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 9673#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 9674#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 9675#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 9676#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 9677#define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 9678#define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 9679#define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 9680//MC_VM_L2_PERFCOUNTER6_CFG 9681#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 9682#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 9683#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 9684#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 9685#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 9686#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 9687#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 9688#define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 9689#define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 9690#define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 9691//MC_VM_L2_PERFCOUNTER7_CFG 9692#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 9693#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 9694#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 9695#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 9696#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 9697#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 9698#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 9699#define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 9700#define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 9701#define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 9702//MC_VM_L2_PERFCOUNTER_RSLT_CNTL 9703#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 9704#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 9705#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 9706#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 9707#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 9708#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 9709#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 9710#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 9711#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 9712#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 9713#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 9714#define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 9715 9716 9717// addressBlock: mmhub_utcl2_vml2prdec 9718//MC_VM_L2_PERFCOUNTER_LO 9719#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 9720#define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 9721//MC_VM_L2_PERFCOUNTER_HI 9722#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 9723#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 9724#define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 9725#define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 9726 9727 9728// addressBlock: mmhub_utcl2_vmsharedhvdec 9729//MC_VM_FB_SIZE_OFFSET_VF0 9730#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 9731#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 9732#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 9733#define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 9734//MC_VM_FB_SIZE_OFFSET_VF1 9735#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 9736#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 9737#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 9738#define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 9739//MC_VM_FB_SIZE_OFFSET_VF2 9740#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 9741#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 9742#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 9743#define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 9744//MC_VM_FB_SIZE_OFFSET_VF3 9745#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 9746#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 9747#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 9748#define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 9749//MC_VM_FB_SIZE_OFFSET_VF4 9750#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 9751#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 9752#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 9753#define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 9754//MC_VM_FB_SIZE_OFFSET_VF5 9755#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 9756#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 9757#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 9758#define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 9759//MC_VM_FB_SIZE_OFFSET_VF6 9760#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 9761#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 9762#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 9763#define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 9764//MC_VM_FB_SIZE_OFFSET_VF7 9765#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 9766#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 9767#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 9768#define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 9769//MC_VM_FB_SIZE_OFFSET_VF8 9770#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 9771#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 9772#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 9773#define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 9774//MC_VM_FB_SIZE_OFFSET_VF9 9775#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 9776#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 9777#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 9778#define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 9779//MC_VM_FB_SIZE_OFFSET_VF10 9780#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 9781#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 9782#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 9783#define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 9784//MC_VM_FB_SIZE_OFFSET_VF11 9785#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 9786#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 9787#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 9788#define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 9789//MC_VM_FB_SIZE_OFFSET_VF12 9790#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 9791#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 9792#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 9793#define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 9794//MC_VM_FB_SIZE_OFFSET_VF13 9795#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 9796#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 9797#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 9798#define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 9799//MC_VM_FB_SIZE_OFFSET_VF14 9800#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 9801#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 9802#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 9803#define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 9804//MC_VM_FB_SIZE_OFFSET_VF15 9805#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 9806#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 9807#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 9808#define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 9809//VM_IOMMU_MMIO_CNTRL_1 9810#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN__SHIFT 0x8 9811#define VM_IOMMU_MMIO_CNTRL_1__MARC_EN_MASK 0x00000100L 9812//MC_VM_MARC_BASE_LO_0 9813#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 9814#define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 9815//MC_VM_MARC_BASE_LO_1 9816#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 9817#define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 9818//MC_VM_MARC_BASE_LO_2 9819#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 9820#define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 9821//MC_VM_MARC_BASE_LO_3 9822#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 9823#define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 9824//MC_VM_MARC_BASE_HI_0 9825#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 9826#define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 9827//MC_VM_MARC_BASE_HI_1 9828#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 9829#define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 9830//MC_VM_MARC_BASE_HI_2 9831#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 9832#define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 9833//MC_VM_MARC_BASE_HI_3 9834#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 9835#define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 9836//MC_VM_MARC_RELOC_LO_0 9837#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 9838#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 9839#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 9840#define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 9841#define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 9842#define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 9843//MC_VM_MARC_RELOC_LO_1 9844#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 9845#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 9846#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 9847#define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 9848#define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 9849#define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 9850//MC_VM_MARC_RELOC_LO_2 9851#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 9852#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 9853#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 9854#define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 9855#define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 9856#define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 9857//MC_VM_MARC_RELOC_LO_3 9858#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 9859#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 9860#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 9861#define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 9862#define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 9863#define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 9864//MC_VM_MARC_RELOC_HI_0 9865#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 9866#define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 9867//MC_VM_MARC_RELOC_HI_1 9868#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 9869#define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 9870//MC_VM_MARC_RELOC_HI_2 9871#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 9872#define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 9873//MC_VM_MARC_RELOC_HI_3 9874#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 9875#define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 9876//MC_VM_MARC_LEN_LO_0 9877#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 9878#define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 9879//MC_VM_MARC_LEN_LO_1 9880#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 9881#define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 9882//MC_VM_MARC_LEN_LO_2 9883#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 9884#define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 9885//MC_VM_MARC_LEN_LO_3 9886#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 9887#define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 9888//MC_VM_MARC_LEN_HI_0 9889#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 9890#define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 9891//MC_VM_MARC_LEN_HI_1 9892#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 9893#define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 9894//MC_VM_MARC_LEN_HI_2 9895#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 9896#define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 9897//MC_VM_MARC_LEN_HI_3 9898#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 9899#define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 9900//VM_IOMMU_CONTROL_REGISTER 9901#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN__SHIFT 0x0 9902#define VM_IOMMU_CONTROL_REGISTER__IOMMUEN_MASK 0x00000001L 9903//VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER 9904#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN__SHIFT 0xd 9905#define VM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER__PERFOPTEN_MASK 0x00002000L 9906//VM_PCIE_ATS_CNTL 9907#define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 9908#define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 9909#define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 9910#define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 9911//VM_PCIE_ATS_CNTL_VF_0 9912#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 9913#define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 9914//VM_PCIE_ATS_CNTL_VF_1 9915#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 9916#define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 9917//VM_PCIE_ATS_CNTL_VF_2 9918#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 9919#define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 9920//VM_PCIE_ATS_CNTL_VF_3 9921#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 9922#define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 9923//VM_PCIE_ATS_CNTL_VF_4 9924#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 9925#define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 9926//VM_PCIE_ATS_CNTL_VF_5 9927#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 9928#define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 9929//VM_PCIE_ATS_CNTL_VF_6 9930#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 9931#define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 9932//VM_PCIE_ATS_CNTL_VF_7 9933#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 9934#define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 9935//VM_PCIE_ATS_CNTL_VF_8 9936#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 9937#define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 9938//VM_PCIE_ATS_CNTL_VF_9 9939#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 9940#define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 9941//VM_PCIE_ATS_CNTL_VF_10 9942#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 9943#define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 9944//VM_PCIE_ATS_CNTL_VF_11 9945#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 9946#define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 9947//VM_PCIE_ATS_CNTL_VF_12 9948#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 9949#define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 9950//VM_PCIE_ATS_CNTL_VF_13 9951#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 9952#define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 9953//VM_PCIE_ATS_CNTL_VF_14 9954#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 9955#define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 9956//VM_PCIE_ATS_CNTL_VF_15 9957#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 9958#define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 9959//UTCL2_CGTT_CLK_CTRL 9960#define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 9961#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 9962#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 9963#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 9964#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 9965#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 9966#define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 9967#define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 9968#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 9969#define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 9970#define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 9971#define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 9972 9973 9974// addressBlock: mmhub_utcl2_vmsharedpfdec 9975//MC_VM_NB_MMIOBASE 9976#define MC_VM_NB_MMIOBASE__MMIOBASE__SHIFT 0x0 9977#define MC_VM_NB_MMIOBASE__MMIOBASE_MASK 0xFFFFFFFFL 9978//MC_VM_NB_MMIOLIMIT 9979#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT__SHIFT 0x0 9980#define MC_VM_NB_MMIOLIMIT__MMIOLIMIT_MASK 0xFFFFFFFFL 9981//MC_VM_NB_PCI_CTRL 9982#define MC_VM_NB_PCI_CTRL__MMIOENABLE__SHIFT 0x17 9983#define MC_VM_NB_PCI_CTRL__MMIOENABLE_MASK 0x00800000L 9984//MC_VM_NB_PCI_ARB 9985#define MC_VM_NB_PCI_ARB__VGA_HOLE__SHIFT 0x3 9986#define MC_VM_NB_PCI_ARB__VGA_HOLE_MASK 0x00000008L 9987//MC_VM_NB_TOP_OF_DRAM_SLOT1 9988#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM__SHIFT 0x17 9989#define MC_VM_NB_TOP_OF_DRAM_SLOT1__TOP_OF_DRAM_MASK 0xFF800000L 9990//MC_VM_NB_LOWER_TOP_OF_DRAM2 9991#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE__SHIFT 0x0 9992#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2__SHIFT 0x17 9993#define MC_VM_NB_LOWER_TOP_OF_DRAM2__ENABLE_MASK 0x00000001L 9994#define MC_VM_NB_LOWER_TOP_OF_DRAM2__LOWER_TOM2_MASK 0xFF800000L 9995//MC_VM_NB_UPPER_TOP_OF_DRAM2 9996#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2__SHIFT 0x0 9997#define MC_VM_NB_UPPER_TOP_OF_DRAM2__UPPER_TOM2_MASK 0x00000FFFL 9998//MC_VM_FB_OFFSET 9999#define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 10000#define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 10001//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 10002#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 10003#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 10004//MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 10005#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 10006#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 10007//MC_VM_STEERING 10008#define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 10009#define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 10010//MC_SHARED_VIRT_RESET_REQ 10011#define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 10012#define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 10013#define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 10014#define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 10015//MC_MEM_POWER_LS 10016#define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 10017#define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 10018#define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 10019#define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 10020//MC_VM_CACHEABLE_DRAM_ADDRESS_START 10021#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 10022#define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 10023//MC_VM_CACHEABLE_DRAM_ADDRESS_END 10024#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 10025#define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 10026//MC_VM_APT_CNTL 10027#define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 10028#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 10029#define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 10030#define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 10031//MC_VM_LOCAL_HBM_ADDRESS_START 10032#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 10033#define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x000FFFFFL 10034//MC_VM_LOCAL_HBM_ADDRESS_END 10035#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 10036#define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x000FFFFFL 10037//MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 10038#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 10039#define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 10040 10041 10042// addressBlock: mmhub_utcl2_vmsharedvcdec 10043//MC_VM_FB_LOCATION_BASE 10044#define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 10045#define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 10046//MC_VM_FB_LOCATION_TOP 10047#define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 10048#define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 10049//MC_VM_AGP_TOP 10050#define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 10051#define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 10052//MC_VM_AGP_BOT 10053#define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 10054#define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 10055//MC_VM_AGP_BASE 10056#define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 10057#define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 10058//MC_VM_SYSTEM_APERTURE_LOW_ADDR 10059#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 10060#define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 10061//MC_VM_SYSTEM_APERTURE_HIGH_ADDR 10062#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 10063#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 10064//MC_VM_MX_L1_TLB_CNTL 10065#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 10066#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 10067#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 10068#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 10069#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 10070#define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 10071#define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd 10072#define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 10073#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 10074#define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 10075#define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 10076#define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 10077#define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L 10078#define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L 10079 10080 10081// addressBlock: mmhub_utcl2_atcl2pfcntrdec 10082//ATC_L2_PERFCOUNTER_LO 10083#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 10084#define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 10085//ATC_L2_PERFCOUNTER_HI 10086#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 10087#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 10088#define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 10089#define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 10090 10091 10092// addressBlock: mmhub_utcl2_atcl2pfcntldec 10093//ATC_L2_PERFCOUNTER0_CFG 10094#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 10095#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 10096#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 10097#define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 10098#define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 10099#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 10100#define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 10101#define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 10102#define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 10103#define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 10104//ATC_L2_PERFCOUNTER1_CFG 10105#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 10106#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 10107#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 10108#define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 10109#define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 10110#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 10111#define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 10112#define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 10113#define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 10114#define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 10115//ATC_L2_PERFCOUNTER_RSLT_CNTL 10116#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 10117#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 10118#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 10119#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 10120#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 10121#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 10122#define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 10123#define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 10124#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 10125#define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 10126#define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 10127#define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 10128 10129//MMEA0_EDC_CNT 10130#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 10131#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 10132#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 10133#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 10134#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 10135#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 10136#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 10137#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 10138#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 10139#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 10140#define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 10141#define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 10142#define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 10143#define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 10144#define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 10145#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 10146#define MMEA0_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 10147#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 10148#define MMEA0_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 10149#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 10150#define MMEA0_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 10151#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 10152#define MMEA0_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 10153#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 10154#define MMEA0_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 10155#define MMEA0_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 10156#define MMEA0_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 10157#define MMEA0_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 10158#define MMEA0_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 10159#define MMEA0_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 10160//MMEA0_EDC_CNT2 10161#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 10162#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 10163#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 10164#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 10165#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 10166#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 10167#define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 10168#define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 10169#define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT 0x10 10170#define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT 0x12 10171#define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT 0x14 10172#define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT 0x16 10173#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 10174#define MMEA0_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 10175#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 10176#define MMEA0_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 10177#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 10178#define MMEA0_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 10179#define MMEA0_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 10180#define MMEA0_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 10181#define MMEA0_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 10182#define MMEA0_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 10183#define MMEA0_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 10184#define MMEA0_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 10185//MMEA1_EDC_CNT 10186#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 10187#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 10188#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 10189#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 10190#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 10191#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 10192#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 10193#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 10194#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 10195#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 10196#define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x14 10197#define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x16 10198#define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT__SHIFT 0x18 10199#define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1a 10200#define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT__SHIFT 0x1c 10201#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 10202#define MMEA1_EDC_CNT_VG20__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 10203#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 10204#define MMEA1_EDC_CNT_VG20__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 10205#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 10206#define MMEA1_EDC_CNT_VG20__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 10207#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 10208#define MMEA1_EDC_CNT_VG20__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 10209#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 10210#define MMEA1_EDC_CNT_VG20__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 10211#define MMEA1_EDC_CNT_VG20__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x00300000L 10212#define MMEA1_EDC_CNT_VG20__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x00C00000L 10213#define MMEA1_EDC_CNT_VG20__IORD_CMDMEM_SED_COUNT_MASK 0x03000000L 10214#define MMEA1_EDC_CNT_VG20__IOWR_CMDMEM_SED_COUNT_MASK 0x0C000000L 10215#define MMEA1_EDC_CNT_VG20__IOWR_DATAMEM_SED_COUNT_MASK 0x30000000L 10216//MMEA1_EDC_CNT2 10217#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 10218#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 10219#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 10220#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 10221#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 10222#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 10223#define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 10224#define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 10225#define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT__SHIFT 0x10 10226#define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT__SHIFT 0x12 10227#define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT__SHIFT 0x14 10228#define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT__SHIFT 0x16 10229#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 10230#define MMEA1_EDC_CNT2_VG20__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 10231#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 10232#define MMEA1_EDC_CNT2_VG20__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 10233#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 10234#define MMEA1_EDC_CNT2_VG20__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 10235#define MMEA1_EDC_CNT2_VG20__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 10236#define MMEA1_EDC_CNT2_VG20__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 10237#define MMEA1_EDC_CNT2_VG20__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 10238#define MMEA1_EDC_CNT2_VG20__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 10239#define MMEA1_EDC_CNT2_VG20__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 10240#define MMEA1_EDC_CNT2_VG20__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 10241 10242// addressBlock: mmhub_utcl2_vmsharedpfdec 10243//MC_VM_XGMI_LFB_CNTL 10244#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 10245#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 10246#define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x00000007L 10247#define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x00000070L 10248//MC_VM_XGMI_LFB_SIZE 10249#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 10250#define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0000FFFFL 10251#endif 10252