Searched refs:Rt2 (Results 1 - 16 of 16) sorted by relevance

/netbsd-current/sys/arch/aarch64/aarch64/
H A Ddisasm.c1810 OP4FUNC(op_ldaxp, size, Rt2, Rn, Rt)
1814 ZREGNAME(size, Rt2),
1839 OP5FUNC(op_ldnp, sf, imm7, Rt2, Rn, Rt)
1844 ZREGNAME(sf, Rt2),
1849 ZREGNAME(sf, Rt2),
1855 OP5FUNC(op_ldp_postidx, sf, imm7, Rt2, Rn, Rt)
1859 ZREGNAME(sf, Rt2),
1864 OP5FUNC(op_ldp_preidx, sf, imm7, Rt2, Rn, Rt)
1868 ZREGNAME(sf, Rt2),
1873 OP5FUNC(op_ldp_signed, sf, imm7, Rt2, R
[all...]
H A Ddb_trace.c390 uint64_t Rt2 = (insn >> 10) & 0x1f; local
397 } else if (Rt2 == 30) {
411 if (func_entry_autodetect && Rt1 == 29 && Rt2 == 30)
420 uint64_t Rt2 = (insn >> 10) & 0x1f; local
426 Rt2, imm7);
429 } else if (Rt2 == 30) {
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1336 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1390 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1399 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1408 Rt == Rt2)
1419 unsigned Rt2 = fieldFromInstruction(insn, 10, 5); local
1483 DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1496 DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1507 DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1518 DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1529 DecodeFPR32RegisterClass(Inst, Rt2, Add
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2006 unsigned Rt2 = Rt + 1; local
2030 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
2034 if (Rt2 == 15)
2053 if (Rt2 == 15)
2059 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
2063 if (writeback && (Rn == Rt || Rn == Rt2))
5475 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
5480 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
5489 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Addres
5501 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
5558 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); local
5595 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); local
5664 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); local
5874 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); local
6457 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
6480 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); local
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp4200 // the Rt == Rt2. All of those are undefined behaviour.
4208 unsigned Rt2 = Inst.getOperand(2).getReg(); local
4213 if (RI->isSubRegisterEq(Rn, Rt2))
4225 unsigned Rt2 = Inst.getOperand(1).getReg(); local
4226 if (Rt == Rt2)
4227 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4238 unsigned Rt2 = Inst.getOperand(2).getReg(); local
4239 if (Rt == Rt2)
4240 return Error(Loc[1], "unpredictable LDP instruction, Rt2==Rt");
4254 unsigned Rt2 local
4335 unsigned Rt2 = Inst.getOperand(2).getReg(); local
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/sim/arm/
H A Dthumbemu.c319 ARMword Rt2 = ntBITS (8, 11); local
325 tASSERT (Rt2 == Rt + 1);
345 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
346 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
347 // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
/netbsd-current/external/gpl3/gdb/dist/sim/arm/
H A Dthumbemu.c322 ARMword Rt2 = ntBITS (8, 11); local
328 tASSERT (Rt2 == Rt + 1);
348 // STRD<c> <Rt>,<Rt2>,[<Rn>{,#+/-<imm8>}]
349 // STRD<c> <Rt>,<Rt2>,[<Rn>],#+/-<imm8>
350 // STRD<c> <Rt>,<Rt2>,[<Rn>,#+/-<imm8>]!
/netbsd-current/external/gpl3/binutils/dist/opcodes/
H A Daarch64-tbl.h3757 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
3758 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
3761 CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
3762 CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
3779 CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3780 CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3784 CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3785 CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3788 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
3789 MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM1
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/opcodes/
H A Daarch64-tbl.h3581 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
3582 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
3585 CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
3586 CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
3603 CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3604 CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3608 CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3609 CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3612 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
3613 MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM1
[all...]
/netbsd-current/external/gpl3/gdb/dist/opcodes/
H A Daarch64-tbl.h3771 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
3772 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
3775 CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
3776 CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
3793 CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3794 CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3798 CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3799 CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3802 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
3803 MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM1
[all...]
/netbsd-current/external/gpl3/binutils.old/dist/opcodes/
H A Daarch64-tbl.h3757 CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
3758 CORE_INSN ("stlxp", 0x88208000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
3761 CORE_INSN ("ldxp", 0x887f0000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
3762 CORE_INSN ("ldaxp", 0x887f8000, 0xbfe08000, ldstexcl, 0, OP3 (Rt, Rt2, ADDR_SIMPLE), QL_R2NIL, F_GPRSIZE_IN_Q),
3779 CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3780 CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3784 CORE_INSN ("stp", 0x29000000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3785 CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
3788 {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
3789 MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM1
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp5813 // mnemonic, condition code, Rt, Rt2, Qd, idx, Qd again, idx2
5817 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1); // Rt2
6932 // We have to be careful to not emit an invalid Rt2 here, because the rest of
7416 unsigned Rt2 = MRI->getEncodingValue(Reg2); local
7418 // Rt2 must be Rt + 1 and Rt must be even.
7419 if (Rt + 1 != Rt2 || (Rt & 1)) {
7537 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(RtIndex + 1).getReg()); local
7550 // Rt2 must be Rt + 1.
7551 if (Rt2 != Rt + 1) {
7565 if (Rt2
[all...]
/netbsd-current/external/gpl3/binutils/dist/gas/config/
H A Dtc-arm.c6815 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
7038 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
8122 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
20061 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
20067 Rt2 = 3;
20073 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg,
20076 || inst.operands[Rt2].reg == REG_SP,
20079 || inst.operands[Rt2].reg == REG_PC,
20085 inst.instruction |= inst.operands[Rt2].reg << 16;
20143 16. VMOV<c> <Rt>, <Rt2>, <Q
20055 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3; local
[all...]
/netbsd-current/external/gpl3/gdb.old/dist/gas/config/
H A Dtc-arm.c6762 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6985 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
8065 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
20001 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
20007 Rt2 = 3;
20013 constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg,
20016 || inst.operands[Rt2].reg == REG_SP,
20019 || inst.operands[Rt2].reg == REG_PC,
20025 inst.instruction |= inst.operands[Rt2].reg << 16;
20083 16. VMOV<c> <Rt>, <Rt2>, <Q
19995 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3; local
[all...]
/netbsd-current/external/gpl3/binutils.old/dist/gas/config/
H A Dtc-arm.c6815 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
7038 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
8122 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
20061 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
20067 Rt2 = 3;
20073 constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg,
20076 || inst.operands[Rt2].reg == REG_SP,
20079 || inst.operands[Rt2].reg == REG_PC,
20085 inst.instruction |= inst.operands[Rt2].reg << 16;
20143 16. VMOV<c> <Rt>, <Rt2>, <Q
20055 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3; local
[all...]
/netbsd-current/external/apache2/llvm/dist/clang/lib/CodeGen/
H A DCGBuiltin.cpp7351 // the intrinsic has 4 because Rt and Rt2
7364 Value *Rt2 = Builder.CreateLShr(RtAndRt2, C1);
7365 Rt2 = Builder.CreateTruncOrBitCast(Rt2, Int32Ty);
7367 return Builder.CreateCall(F, {Coproc, Opc1, Rt, Rt2, CRm});

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