1/* tc-arm.c -- Assemble for the ARM
2   Copyright (C) 1994-2022 Free Software Foundation, Inc.
3   Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4	Modified by David Taylor (dtaylor@armltd.co.uk)
5	Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6	Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7	Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
8
9   This file is part of GAS, the GNU Assembler.
10
11   GAS is free software; you can redistribute it and/or modify
12   it under the terms of the GNU General Public License as published by
13   the Free Software Foundation; either version 3, or (at your option)
14   any later version.
15
16   GAS is distributed in the hope that it will be useful,
17   but WITHOUT ANY WARRANTY; without even the implied warranty of
18   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
19   GNU General Public License for more details.
20
21   You should have received a copy of the GNU General Public License
22   along with GAS; see the file COPYING.  If not, write to the Free
23   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24   02110-1301, USA.  */
25
26#include "as.h"
27#include <limits.h>
28#include <stdarg.h>
29#define	 NO_RELOC 0
30#include "safe-ctype.h"
31#include "subsegs.h"
32#include "obstack.h"
33#include "libiberty.h"
34#include "opcode/arm.h"
35#include "cpu-arm.h"
36
37#ifdef OBJ_ELF
38#include "elf/arm.h"
39#include "dw2gencfi.h"
40#endif
41
42#include "dwarf2dbg.h"
43
44#ifdef OBJ_ELF
45/* Must be at least the size of the largest unwind opcode (currently two).  */
46#define ARM_OPCODE_CHUNK_SIZE 8
47
48/* This structure holds the unwinding state.  */
49
50static struct
51{
52  symbolS *	  proc_start;
53  symbolS *	  table_entry;
54  symbolS *	  personality_routine;
55  int		  personality_index;
56  /* The segment containing the function.  */
57  segT		  saved_seg;
58  subsegT	  saved_subseg;
59  /* Opcodes generated from this function.  */
60  unsigned char * opcodes;
61  int		  opcode_count;
62  int		  opcode_alloc;
63  /* The number of bytes pushed to the stack.  */
64  offsetT	  frame_size;
65  /* We don't add stack adjustment opcodes immediately so that we can merge
66     multiple adjustments.  We can also omit the final adjustment
67     when using a frame pointer.  */
68  offsetT	  pending_offset;
69  /* These two fields are set by both unwind_movsp and unwind_setfp.  They
70     hold the reg+offset to use when restoring sp from a frame pointer.	 */
71  offsetT	  fp_offset;
72  int		  fp_reg;
73  /* Nonzero if an unwind_setfp directive has been seen.  */
74  unsigned	  fp_used:1;
75  /* Nonzero if the last opcode restores sp from fp_reg.  */
76  unsigned	  sp_restored:1;
77} unwind;
78
79/* Whether --fdpic was given.  */
80static int arm_fdpic;
81
82#endif /* OBJ_ELF */
83
84/* Results from operand parsing worker functions.  */
85
86typedef enum
87{
88  PARSE_OPERAND_SUCCESS,
89  PARSE_OPERAND_FAIL,
90  PARSE_OPERAND_FAIL_NO_BACKTRACK
91} parse_operand_result;
92
93enum arm_float_abi
94{
95  ARM_FLOAT_ABI_HARD,
96  ARM_FLOAT_ABI_SOFTFP,
97  ARM_FLOAT_ABI_SOFT
98};
99
100/* Types of processor to assemble for.	*/
101#ifndef CPU_DEFAULT
102/* The code that was here used to select a default CPU depending on compiler
103   pre-defines which were only present when doing native builds, thus
104   changing gas' default behaviour depending upon the build host.
105
106   If you have a target that requires a default CPU option then the you
107   should define CPU_DEFAULT here.  */
108#endif
109
110/* Perform range checks on positive and negative overflows by checking if the
111   VALUE given fits within the range of an BITS sized immediate.  */
112static bool out_of_range_p (offsetT value, offsetT bits)
113 {
114  gas_assert (bits < (offsetT)(sizeof (value) * 8));
115  return (value & ~((1 << bits)-1))
116	  && ((value & ~((1 << bits)-1)) != ~((1 << bits)-1));
117}
118
119#ifndef FPU_DEFAULT
120# ifdef TE_LINUX
121#  define FPU_DEFAULT FPU_ARCH_FPA
122# elif defined (TE_NetBSD)
123#  ifdef OBJ_ELF
124#   define FPU_DEFAULT FPU_ARCH_VFP	/* Soft-float, but VFP order.  */
125#  else
126    /* Legacy a.out format.  */
127#   define FPU_DEFAULT FPU_ARCH_FPA	/* Soft-float, but FPA order.  */
128#  endif
129# elif defined (TE_VXWORKS)
130#  define FPU_DEFAULT FPU_ARCH_VFP	/* Soft-float, VFP order.  */
131# else
132   /* For backwards compatibility, default to FPA.  */
133#  define FPU_DEFAULT FPU_ARCH_FPA
134# endif
135#endif /* ifndef FPU_DEFAULT */
136
137#define streq(a, b)	      (strcmp (a, b) == 0)
138
139/* Current set of feature bits available (CPU+FPU).  Different from
140   selected_cpu + selected_fpu in case of autodetection since the CPU
141   feature bits are then all set.  */
142static arm_feature_set cpu_variant;
143/* Feature bits used in each execution state.  Used to set build attribute
144   (in particular Tag_*_ISA_use) in CPU autodetection mode.  */
145static arm_feature_set arm_arch_used;
146static arm_feature_set thumb_arch_used;
147
148/* Flags stored in private area of BFD structure.  */
149static int uses_apcs_26	     = false;
150static int atpcs	     = false;
151static int support_interwork = false;
152static int uses_apcs_float   = false;
153static int pic_code	     = false;
154static int fix_v4bx	     = false;
155/* Warn on using deprecated features.  */
156static int warn_on_deprecated = true;
157static int warn_on_restrict_it = false;
158
159/* Understand CodeComposer Studio assembly syntax.  */
160bool codecomposer_syntax = false;
161
162/* Variables that we set while parsing command-line options.  Once all
163   options have been read we re-process these values to set the real
164   assembly flags.  */
165
166/* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167   instead of -mcpu=arm1).  */
168static const arm_feature_set *legacy_cpu = NULL;
169static const arm_feature_set *legacy_fpu = NULL;
170
171/* CPU, extension and FPU feature bits selected by -mcpu.  */
172static const arm_feature_set *mcpu_cpu_opt = NULL;
173static arm_feature_set *mcpu_ext_opt = NULL;
174static const arm_feature_set *mcpu_fpu_opt = NULL;
175
176/* CPU, extension and FPU feature bits selected by -march.  */
177static const arm_feature_set *march_cpu_opt = NULL;
178static arm_feature_set *march_ext_opt = NULL;
179static const arm_feature_set *march_fpu_opt = NULL;
180
181/* Feature bits selected by -mfpu.  */
182static const arm_feature_set *mfpu_opt = NULL;
183
184/* Constants for known architecture features.  */
185static const arm_feature_set fpu_default = FPU_DEFAULT;
186static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
187static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
188static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
189static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
190static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
191static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
192#ifdef OBJ_ELF
193static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
194#endif
195static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
196
197#ifdef CPU_DEFAULT
198static const arm_feature_set cpu_default = CPU_DEFAULT;
199#endif
200
201static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
202static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
203static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
204static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
205static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
206static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
207static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
208static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
209static const arm_feature_set arm_ext_v4t_5 =
210  ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
211static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
212static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
213static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
214static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
215static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
216static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
217static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
218/* Only for compatability of hint instructions.  */
219static const arm_feature_set arm_ext_v6k_v6t2 =
220  ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2);
221static const arm_feature_set arm_ext_v6_notm =
222  ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
223static const arm_feature_set arm_ext_v6_dsp =
224  ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
225static const arm_feature_set arm_ext_barrier =
226  ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
227static const arm_feature_set arm_ext_msr =
228  ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
229static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
230static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
231static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
232static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
233static const arm_feature_set arm_ext_v8r = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8R);
234#ifdef OBJ_ELF
235static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
236#endif
237static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
238static const arm_feature_set arm_ext_m =
239  ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
240		    ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
241static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
242static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
243static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
244static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
245static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
246static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
247static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
248static const arm_feature_set arm_ext_v8m_main =
249  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
250static const arm_feature_set arm_ext_v8_1m_main =
251ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
252/* Instructions in ARMv8-M only found in M profile architectures.  */
253static const arm_feature_set arm_ext_v8m_m_only =
254  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
255static const arm_feature_set arm_ext_v6t2_v8m =
256  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
257/* Instructions shared between ARMv8-A and ARMv8-M.  */
258static const arm_feature_set arm_ext_atomics =
259  ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
260#ifdef OBJ_ELF
261/* DSP instructions Tag_DSP_extension refers to.  */
262static const arm_feature_set arm_ext_dsp =
263  ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
264#endif
265static const arm_feature_set arm_ext_ras =
266  ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
267/* FP16 instructions.  */
268static const arm_feature_set arm_ext_fp16 =
269  ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
270static const arm_feature_set arm_ext_fp16_fml =
271  ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
272static const arm_feature_set arm_ext_v8_2 =
273  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
274static const arm_feature_set arm_ext_v8_3 =
275  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
276static const arm_feature_set arm_ext_sb =
277  ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
278static const arm_feature_set arm_ext_predres =
279  ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
280static const arm_feature_set arm_ext_bf16 =
281  ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16);
282static const arm_feature_set arm_ext_i8mm =
283  ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM);
284static const arm_feature_set arm_ext_crc =
285  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC);
286static const arm_feature_set arm_ext_cde =
287  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE);
288static const arm_feature_set arm_ext_cde0 =
289  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0);
290static const arm_feature_set arm_ext_cde1 =
291  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1);
292static const arm_feature_set arm_ext_cde2 =
293  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2);
294static const arm_feature_set arm_ext_cde3 =
295  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3);
296static const arm_feature_set arm_ext_cde4 =
297  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4);
298static const arm_feature_set arm_ext_cde5 =
299  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5);
300static const arm_feature_set arm_ext_cde6 =
301  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6);
302static const arm_feature_set arm_ext_cde7 =
303  ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7);
304
305static const arm_feature_set arm_arch_any = ARM_ANY;
306static const arm_feature_set fpu_any = FPU_ANY;
307static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
308static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
309static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
310
311static const arm_feature_set arm_cext_iwmmxt2 =
312  ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
313static const arm_feature_set arm_cext_iwmmxt =
314  ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
315static const arm_feature_set arm_cext_xscale =
316  ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
317static const arm_feature_set arm_cext_maverick =
318  ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
319static const arm_feature_set fpu_fpa_ext_v1 =
320  ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
321static const arm_feature_set fpu_fpa_ext_v2 =
322  ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
323static const arm_feature_set fpu_vfp_ext_v1xd =
324  ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
325static const arm_feature_set fpu_vfp_ext_v1 =
326  ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
327static const arm_feature_set fpu_vfp_ext_v2 =
328  ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
329static const arm_feature_set fpu_vfp_ext_v3xd =
330  ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
331static const arm_feature_set fpu_vfp_ext_v3 =
332  ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
333static const arm_feature_set fpu_vfp_ext_d32 =
334  ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
335static const arm_feature_set fpu_neon_ext_v1 =
336  ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
337static const arm_feature_set fpu_vfp_v3_or_neon_ext =
338  ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
339static const arm_feature_set mve_ext =
340  ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE);
341static const arm_feature_set mve_fp_ext =
342  ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP);
343/* Note: This has more than one bit set, which means using it with
344   mark_feature_used (which returns if *any* of the bits are set in the current
345   cpu variant) can give surprising results.  */
346static const arm_feature_set armv8m_fp =
347  ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16);
348#ifdef OBJ_ELF
349static const arm_feature_set fpu_vfp_fp16 =
350  ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
351static const arm_feature_set fpu_neon_ext_fma =
352  ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
353#endif
354static const arm_feature_set fpu_vfp_ext_fma =
355  ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
356static const arm_feature_set fpu_vfp_ext_armv8 =
357  ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
358static const arm_feature_set fpu_vfp_ext_armv8xd =
359  ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
360static const arm_feature_set fpu_neon_ext_armv8 =
361  ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
362static const arm_feature_set fpu_crypto_ext_armv8 =
363  ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
364static const arm_feature_set fpu_neon_ext_v8_1 =
365  ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
366static const arm_feature_set fpu_neon_ext_dotprod =
367  ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
368static const arm_feature_set pacbti_ext =
369  ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI);
370
371static int mfloat_abi_opt = -1;
372/* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
373   directive.  */
374static arm_feature_set selected_arch = ARM_ARCH_NONE;
375/* Extension feature bits selected by the last -mcpu/-march or .arch_extension
376   directive.  */
377static arm_feature_set selected_ext = ARM_ARCH_NONE;
378/* Feature bits selected by the last -mcpu/-march or by the combination of the
379   last .cpu/.arch directive .arch_extension directives since that
380   directive.  */
381static arm_feature_set selected_cpu = ARM_ARCH_NONE;
382/* FPU feature bits selected by the last -mfpu or .fpu directive.  */
383static arm_feature_set selected_fpu = FPU_NONE;
384/* Feature bits selected by the last .object_arch directive.  */
385static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
386/* Must be long enough to hold any of the names in arm_cpus.  */
387static const struct arm_ext_table * selected_ctx_ext_table = NULL;
388static char selected_cpu_name[20];
389
390extern FLONUM_TYPE generic_floating_point_number;
391
392/* Return if no cpu was selected on command-line.  */
393static bool
394no_cpu_selected (void)
395{
396  return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
397}
398
399#ifdef OBJ_ELF
400# ifdef EABI_DEFAULT
401static int meabi_flags = EABI_DEFAULT;
402# else
403static int meabi_flags = EF_ARM_EABI_UNKNOWN;
404# endif
405
406static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
407
408bool
409arm_is_eabi (void)
410{
411  return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
412}
413#endif
414
415#ifdef OBJ_ELF
416/* Pre-defined "_GLOBAL_OFFSET_TABLE_"	*/
417symbolS * GOT_symbol;
418#endif
419
420/* 0: assemble for ARM,
421   1: assemble for Thumb,
422   2: assemble for Thumb even though target CPU does not support thumb
423      instructions.  */
424static int thumb_mode = 0;
425/* A value distinct from the possible values for thumb_mode that we
426   can use to record whether thumb_mode has been copied into the
427   tc_frag_data field of a frag.  */
428#define MODE_RECORDED (1 << 4)
429
430/* Specifies the intrinsic IT insn behavior mode.  */
431enum implicit_it_mode
432{
433  IMPLICIT_IT_MODE_NEVER  = 0x00,
434  IMPLICIT_IT_MODE_ARM    = 0x01,
435  IMPLICIT_IT_MODE_THUMB  = 0x02,
436  IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
437};
438static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
439
440/* If unified_syntax is true, we are processing the new unified
441   ARM/Thumb syntax.  Important differences from the old ARM mode:
442
443     - Immediate operands do not require a # prefix.
444     - Conditional affixes always appear at the end of the
445       instruction.  (For backward compatibility, those instructions
446       that formerly had them in the middle, continue to accept them
447       there.)
448     - The IT instruction may appear, and if it does is validated
449       against subsequent conditional affixes.  It does not generate
450       machine code.
451
452   Important differences from the old Thumb mode:
453
454     - Immediate operands do not require a # prefix.
455     - Most of the V6T2 instructions are only available in unified mode.
456     - The .N and .W suffixes are recognized and honored (it is an error
457       if they cannot be honored).
458     - All instructions set the flags if and only if they have an 's' affix.
459     - Conditional affixes may be used.  They are validated against
460       preceding IT instructions.  Unlike ARM mode, you cannot use a
461       conditional affix except in the scope of an IT instruction.  */
462
463static bool unified_syntax = false;
464
465/* An immediate operand can start with #, and ld*, st*, pld operands
466   can contain [ and ].  We need to tell APP not to elide whitespace
467   before a [, which can appear as the first operand for pld.
468   Likewise, a { can appear as the first operand for push, pop, vld*, etc.  */
469const char arm_symbol_chars[] = "#[]{}";
470
471enum neon_el_type
472{
473  NT_invtype,
474  NT_untyped,
475  NT_integer,
476  NT_float,
477  NT_poly,
478  NT_signed,
479  NT_bfloat,
480  NT_unsigned
481};
482
483struct neon_type_el
484{
485  enum neon_el_type type;
486  unsigned size;
487};
488
489#define NEON_MAX_TYPE_ELS 5
490
491struct neon_type
492{
493  struct neon_type_el el[NEON_MAX_TYPE_ELS];
494  unsigned elems;
495};
496
497enum pred_instruction_type
498{
499   OUTSIDE_PRED_INSN,
500   INSIDE_VPT_INSN,
501   INSIDE_IT_INSN,
502   INSIDE_IT_LAST_INSN,
503   IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
504			      if inside, should be the last one.  */
505   NEUTRAL_IT_INSN,        /* This could be either inside or outside,
506			      i.e. BKPT and NOP.  */
507   IT_INSN,		   /* The IT insn has been parsed.  */
508   VPT_INSN,		   /* The VPT/VPST insn has been parsed.  */
509   MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
510			      a predication code.  */
511   MVE_UNPREDICABLE_INSN,  /* MVE instruction that is non-predicable.  */
512};
513
514/* The maximum number of operands we need.  */
515#define ARM_IT_MAX_OPERANDS 6
516#define ARM_IT_MAX_RELOCS 3
517
518struct arm_it
519{
520  const char *	error;
521  unsigned long instruction;
522  unsigned int	size;
523  unsigned int	size_req;
524  unsigned int	cond;
525  /* "uncond_value" is set to the value in place of the conditional field in
526     unconditional versions of the instruction, or -1u if nothing is
527     appropriate.  */
528  unsigned int	uncond_value;
529  struct neon_type vectype;
530  /* This does not indicate an actual NEON instruction, only that
531     the mnemonic accepts neon-style type suffixes.  */
532  int		is_neon;
533  /* Set to the opcode if the instruction needs relaxation.
534     Zero if the instruction is not relaxed.  */
535  unsigned long	relax;
536  struct
537  {
538    bfd_reloc_code_real_type type;
539    expressionS		     exp;
540    int			     pc_rel;
541  } relocs[ARM_IT_MAX_RELOCS];
542
543  enum pred_instruction_type pred_insn_type;
544
545  struct
546  {
547    unsigned reg;
548    signed int imm;
549    struct neon_type_el vectype;
550    unsigned present	: 1;  /* Operand present.  */
551    unsigned isreg	: 1;  /* Operand was a register.  */
552    unsigned immisreg	: 2;  /* .imm field is a second register.
553				 0: imm, 1: gpr, 2: MVE Q-register.  */
554    unsigned isscalar   : 2;  /* Operand is a (SIMD) scalar:
555				 0) not scalar,
556				 1) Neon scalar,
557				 2) MVE scalar.  */
558    unsigned immisalign : 1;  /* Immediate is an alignment specifier.  */
559    unsigned immisfloat : 1;  /* Immediate was parsed as a float.  */
560    /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
561       instructions. This allows us to disambiguate ARM <-> vector insns.  */
562    unsigned regisimm   : 1;  /* 64-bit immediate, reg forms high 32 bits.  */
563    unsigned isvec      : 1;  /* Is a single, double or quad VFP/Neon reg.  */
564    unsigned isquad     : 1;  /* Operand is SIMD quad register.  */
565    unsigned issingle   : 1;  /* Operand is VFP single-precision register.  */
566    unsigned iszr	: 1;  /* Operand is ZR register.  */
567    unsigned hasreloc	: 1;  /* Operand has relocation suffix.  */
568    unsigned writeback	: 1;  /* Operand has trailing !  */
569    unsigned preind	: 1;  /* Preindexed address.  */
570    unsigned postind	: 1;  /* Postindexed address.  */
571    unsigned negative	: 1;  /* Index register was negated.  */
572    unsigned shifted	: 1;  /* Shift applied to operation.  */
573    unsigned shift_kind : 3;  /* Shift operation (enum shift_kind).  */
574  } operands[ARM_IT_MAX_OPERANDS];
575};
576
577static struct arm_it inst;
578
579#define NUM_FLOAT_VALS 8
580
581const char * fp_const[] =
582{
583  "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
584};
585
586LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
587
588#define FAIL	(-1)
589#define SUCCESS (0)
590
591#define SUFF_S 1
592#define SUFF_D 2
593#define SUFF_E 3
594#define SUFF_P 4
595
596#define CP_T_X	 0x00008000
597#define CP_T_Y	 0x00400000
598
599#define CONDS_BIT	 0x00100000
600#define LOAD_BIT	 0x00100000
601
602#define DOUBLE_LOAD_FLAG 0x00000001
603
604struct asm_cond
605{
606  const char *	 template_name;
607  unsigned long  value;
608};
609
610#define COND_ALWAYS 0xE
611
612struct asm_psr
613{
614  const char *   template_name;
615  unsigned long  field;
616};
617
618struct asm_barrier_opt
619{
620  const char *    template_name;
621  unsigned long   value;
622  const arm_feature_set arch;
623};
624
625/* The bit that distinguishes CPSR and SPSR.  */
626#define SPSR_BIT   (1 << 22)
627
628/* The individual PSR flag bits.  */
629#define PSR_c	(1 << 16)
630#define PSR_x	(1 << 17)
631#define PSR_s	(1 << 18)
632#define PSR_f	(1 << 19)
633
634struct reloc_entry
635{
636  const char *              name;
637  bfd_reloc_code_real_type  reloc;
638};
639
640enum vfp_reg_pos
641{
642  VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
643  VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
644};
645
646enum vfp_ldstm_type
647{
648  VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
649};
650
651/* Bits for DEFINED field in neon_typed_alias.  */
652#define NTA_HASTYPE  1
653#define NTA_HASINDEX 2
654
655struct neon_typed_alias
656{
657  unsigned char        defined;
658  unsigned char        index;
659  struct neon_type_el  eltype;
660};
661
662/* ARM register categories.  This includes coprocessor numbers and various
663   architecture extensions' registers.  Each entry should have an error message
664   in reg_expected_msgs below.  */
665enum arm_reg_type
666{
667  REG_TYPE_RN,
668  REG_TYPE_CP,
669  REG_TYPE_CN,
670  REG_TYPE_FN,
671  REG_TYPE_VFS,
672  REG_TYPE_VFD,
673  REG_TYPE_NQ,
674  REG_TYPE_VFSD,
675  REG_TYPE_NDQ,
676  REG_TYPE_NSD,
677  REG_TYPE_NSDQ,
678  REG_TYPE_VFC,
679  REG_TYPE_MVF,
680  REG_TYPE_MVD,
681  REG_TYPE_MVFX,
682  REG_TYPE_MVDX,
683  REG_TYPE_MVAX,
684  REG_TYPE_MQ,
685  REG_TYPE_DSPSC,
686  REG_TYPE_MMXWR,
687  REG_TYPE_MMXWC,
688  REG_TYPE_MMXWCG,
689  REG_TYPE_XSCALE,
690  REG_TYPE_RNB,
691  REG_TYPE_ZR,
692  REG_TYPE_PSEUDO
693};
694
695/* Structure for a hash table entry for a register.
696   If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
697   information which states whether a vector type or index is specified (for a
698   register alias created with .dn or .qn). Otherwise NEON should be NULL.  */
699struct reg_entry
700{
701  const char *               name;
702  unsigned int               number;
703  unsigned char              type;
704  unsigned char              builtin;
705  struct neon_typed_alias *  neon;
706};
707
708/* Diagnostics used when we don't get a register of the expected type.	*/
709const char * const reg_expected_msgs[] =
710{
711  [REG_TYPE_RN]	    = N_("ARM register expected"),
712  [REG_TYPE_CP]	    = N_("bad or missing co-processor number"),
713  [REG_TYPE_CN]	    = N_("co-processor register expected"),
714  [REG_TYPE_FN]	    = N_("FPA register expected"),
715  [REG_TYPE_VFS]    = N_("VFP single precision register expected"),
716  [REG_TYPE_VFD]    = N_("VFP/Neon double precision register expected"),
717  [REG_TYPE_NQ]	    = N_("Neon quad precision register expected"),
718  [REG_TYPE_VFSD]   = N_("VFP single or double precision register expected"),
719  [REG_TYPE_NDQ]    = N_("Neon double or quad precision register expected"),
720  [REG_TYPE_NSD]    = N_("Neon single or double precision register expected"),
721  [REG_TYPE_NSDQ]   = N_("VFP single, double or Neon quad precision register"
722			 " expected"),
723  [REG_TYPE_VFC]    = N_("VFP system register expected"),
724  [REG_TYPE_MVF]    = N_("Maverick MVF register expected"),
725  [REG_TYPE_MVD]    = N_("Maverick MVD register expected"),
726  [REG_TYPE_MVFX]   = N_("Maverick MVFX register expected"),
727  [REG_TYPE_MVDX]   = N_("Maverick MVDX register expected"),
728  [REG_TYPE_MVAX]   = N_("Maverick MVAX register expected"),
729  [REG_TYPE_DSPSC]  = N_("Maverick DSPSC register expected"),
730  [REG_TYPE_MMXWR]  = N_("iWMMXt data register expected"),
731  [REG_TYPE_MMXWC]  = N_("iWMMXt control register expected"),
732  [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
733  [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
734  [REG_TYPE_MQ]	    = N_("MVE vector register expected"),
735  [REG_TYPE_RNB]    = "",
736  [REG_TYPE_ZR]     = N_("ZR register expected"),
737  [REG_TYPE_PSEUDO] = N_("Pseudo register expected"),
738};
739
740/* Some well known registers that we refer to directly elsewhere.  */
741#define REG_R12	12
742#define REG_SP	13
743#define REG_LR	14
744#define REG_PC	15
745
746/* ARM instructions take 4bytes in the object file, Thumb instructions
747   take 2:  */
748#define INSN_SIZE	4
749
750struct asm_opcode
751{
752  /* Basic string to match.  */
753  const char * template_name;
754
755  /* Parameters to instruction.	 */
756  unsigned int operands[8];
757
758  /* Conditional tag - see opcode_lookup.  */
759  unsigned int tag : 4;
760
761  /* Basic instruction code.  */
762  unsigned int avalue;
763
764  /* Thumb-format instruction code.  */
765  unsigned int tvalue;
766
767  /* Which architecture variant provides this instruction.  */
768  const arm_feature_set * avariant;
769  const arm_feature_set * tvariant;
770
771  /* Function to call to encode instruction in ARM format.  */
772  void (* aencode) (void);
773
774  /* Function to call to encode instruction in Thumb format.  */
775  void (* tencode) (void);
776
777  /* Indicates whether this instruction may be vector predicated.  */
778  unsigned int mayBeVecPred : 1;
779};
780
781/* Defines for various bits that we will want to toggle.  */
782#define INST_IMMEDIATE	0x02000000
783#define OFFSET_REG	0x02000000
784#define HWOFFSET_IMM	0x00400000
785#define SHIFT_BY_REG	0x00000010
786#define PRE_INDEX	0x01000000
787#define INDEX_UP	0x00800000
788#define WRITE_BACK	0x00200000
789#define LDM_TYPE_2_OR_3	0x00400000
790#define CPSI_MMOD	0x00020000
791
792#define LITERAL_MASK	0xf000f000
793#define OPCODE_MASK	0xfe1fffff
794#define V4_STR_BIT	0x00000020
795#define VLDR_VMOV_SAME	0x0040f000
796
797#define T2_SUBS_PC_LR	0xf3de8f00
798
799#define DATA_OP_SHIFT	21
800#define SBIT_SHIFT	20
801
802#define T2_OPCODE_MASK	0xfe1fffff
803#define T2_DATA_OP_SHIFT 21
804#define T2_SBIT_SHIFT	 20
805
806#define A_COND_MASK         0xf0000000
807#define A_PUSH_POP_OP_MASK  0x0fff0000
808
809/* Opcodes for pushing/poping registers to/from the stack.  */
810#define A1_OPCODE_PUSH    0x092d0000
811#define A2_OPCODE_PUSH    0x052d0004
812#define A2_OPCODE_POP     0x049d0004
813
814/* Codes to distinguish the arithmetic instructions.  */
815#define OPCODE_AND	0
816#define OPCODE_EOR	1
817#define OPCODE_SUB	2
818#define OPCODE_RSB	3
819#define OPCODE_ADD	4
820#define OPCODE_ADC	5
821#define OPCODE_SBC	6
822#define OPCODE_RSC	7
823#define OPCODE_TST	8
824#define OPCODE_TEQ	9
825#define OPCODE_CMP	10
826#define OPCODE_CMN	11
827#define OPCODE_ORR	12
828#define OPCODE_MOV	13
829#define OPCODE_BIC	14
830#define OPCODE_MVN	15
831
832#define T2_OPCODE_AND	0
833#define T2_OPCODE_BIC	1
834#define T2_OPCODE_ORR	2
835#define T2_OPCODE_ORN	3
836#define T2_OPCODE_EOR	4
837#define T2_OPCODE_ADD	8
838#define T2_OPCODE_ADC	10
839#define T2_OPCODE_SBC	11
840#define T2_OPCODE_SUB	13
841#define T2_OPCODE_RSB	14
842
843#define T_OPCODE_MUL 0x4340
844#define T_OPCODE_TST 0x4200
845#define T_OPCODE_CMN 0x42c0
846#define T_OPCODE_NEG 0x4240
847#define T_OPCODE_MVN 0x43c0
848
849#define T_OPCODE_ADD_R3	0x1800
850#define T_OPCODE_SUB_R3 0x1a00
851#define T_OPCODE_ADD_HI 0x4400
852#define T_OPCODE_ADD_ST 0xb000
853#define T_OPCODE_SUB_ST 0xb080
854#define T_OPCODE_ADD_SP 0xa800
855#define T_OPCODE_ADD_PC 0xa000
856#define T_OPCODE_ADD_I8 0x3000
857#define T_OPCODE_SUB_I8 0x3800
858#define T_OPCODE_ADD_I3 0x1c00
859#define T_OPCODE_SUB_I3 0x1e00
860
861#define T_OPCODE_ASR_R	0x4100
862#define T_OPCODE_LSL_R	0x4080
863#define T_OPCODE_LSR_R	0x40c0
864#define T_OPCODE_ROR_R	0x41c0
865#define T_OPCODE_ASR_I	0x1000
866#define T_OPCODE_LSL_I	0x0000
867#define T_OPCODE_LSR_I	0x0800
868
869#define T_OPCODE_MOV_I8	0x2000
870#define T_OPCODE_CMP_I8 0x2800
871#define T_OPCODE_CMP_LR 0x4280
872#define T_OPCODE_MOV_HR 0x4600
873#define T_OPCODE_CMP_HR 0x4500
874
875#define T_OPCODE_LDR_PC 0x4800
876#define T_OPCODE_LDR_SP 0x9800
877#define T_OPCODE_STR_SP 0x9000
878#define T_OPCODE_LDR_IW 0x6800
879#define T_OPCODE_STR_IW 0x6000
880#define T_OPCODE_LDR_IH 0x8800
881#define T_OPCODE_STR_IH 0x8000
882#define T_OPCODE_LDR_IB 0x7800
883#define T_OPCODE_STR_IB 0x7000
884#define T_OPCODE_LDR_RW 0x5800
885#define T_OPCODE_STR_RW 0x5000
886#define T_OPCODE_LDR_RH 0x5a00
887#define T_OPCODE_STR_RH 0x5200
888#define T_OPCODE_LDR_RB 0x5c00
889#define T_OPCODE_STR_RB 0x5400
890
891#define T_OPCODE_PUSH	0xb400
892#define T_OPCODE_POP	0xbc00
893
894#define T_OPCODE_BRANCH 0xe000
895
896#define THUMB_SIZE	2	/* Size of thumb instruction.  */
897#define THUMB_PP_PC_LR 0x0100
898#define THUMB_LOAD_BIT 0x0800
899#define THUMB2_LOAD_BIT 0x00100000
900
901#define BAD_SYNTAX	_("syntax error")
902#define BAD_ARGS	_("bad arguments to instruction")
903#define BAD_SP          _("r13 not allowed here")
904#define BAD_PC		_("r15 not allowed here")
905#define BAD_ODD		_("Odd register not allowed here")
906#define BAD_EVEN	_("Even register not allowed here")
907#define BAD_COND	_("instruction cannot be conditional")
908#define BAD_OVERLAP	_("registers may not be the same")
909#define BAD_HIREG	_("lo register required")
910#define BAD_THUMB32	_("instruction not supported in Thumb16 mode")
911#define BAD_ADDR_MODE   _("instruction does not accept this addressing mode")
912#define BAD_BRANCH	_("branch must be last instruction in IT block")
913#define BAD_BRANCH_OFF	_("branch out of range or not a multiple of 2")
914#define BAD_NO_VPT	_("instruction not allowed in VPT block")
915#define BAD_NOT_IT	_("instruction not allowed in IT block")
916#define BAD_NOT_VPT	_("instruction missing MVE vector predication code")
917#define BAD_FPU		_("selected FPU does not support instruction")
918#define BAD_OUT_IT 	_("thumb conditional instruction should be in IT block")
919#define BAD_OUT_VPT	\
920	_("vector predicated instruction should be in VPT/VPST block")
921#define BAD_IT_COND	_("incorrect condition in IT block")
922#define BAD_VPT_COND	_("incorrect condition in VPT/VPST block")
923#define BAD_IT_IT 	_("IT falling in the range of a previous IT block")
924#define MISSING_FNSTART	_("missing .fnstart before unwinding directive")
925#define BAD_PC_ADDRESSING \
926	_("cannot use register index with PC-relative addressing")
927#define BAD_PC_WRITEBACK \
928	_("cannot use writeback with PC-relative addressing")
929#define BAD_RANGE	_("branch out of range")
930#define BAD_FP16	_("selected processor does not support fp16 instruction")
931#define BAD_BF16	_("selected processor does not support bf16 instruction")
932#define BAD_CDE	_("selected processor does not support cde instruction")
933#define BAD_CDE_COPROC	_("coprocessor for insn is not enabled for cde")
934#define UNPRED_REG(R)	_("using " R " results in unpredictable behaviour")
935#define THUMB1_RELOC_ONLY  _("relocation valid in thumb1 code only")
936#define MVE_NOT_IT	_("Warning: instruction is UNPREDICTABLE in an IT " \
937			  "block")
938#define MVE_NOT_VPT	_("Warning: instruction is UNPREDICTABLE in a VPT " \
939			  "block")
940#define MVE_BAD_PC	_("Warning: instruction is UNPREDICTABLE with PC" \
941			  " operand")
942#define MVE_BAD_SP	_("Warning: instruction is UNPREDICTABLE with SP" \
943			  " operand")
944#define BAD_SIMD_TYPE	_("bad type in SIMD instruction")
945#define BAD_MVE_AUTO	\
946  _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
947    " use a valid -march or -mcpu option.")
948#define BAD_MVE_SRCDEST	_("Warning: 32-bit element size and same destination "\
949			  "and source operands makes instruction UNPREDICTABLE")
950#define BAD_EL_TYPE	_("bad element type for instruction")
951#define MVE_BAD_QREG	_("MVE vector register Q[0..7] expected")
952#define BAD_PACBTI	_("selected processor does not support PACBTI extention")
953
954static htab_t  arm_ops_hsh;
955static htab_t  arm_cond_hsh;
956static htab_t  arm_vcond_hsh;
957static htab_t  arm_shift_hsh;
958static htab_t  arm_psr_hsh;
959static htab_t  arm_v7m_psr_hsh;
960static htab_t  arm_reg_hsh;
961static htab_t  arm_reloc_hsh;
962static htab_t  arm_barrier_opt_hsh;
963
964/* Stuff needed to resolve the label ambiguity
965   As:
966     ...
967     label:   <insn>
968   may differ from:
969     ...
970     label:
971	      <insn>  */
972
973symbolS *  last_label_seen;
974static int label_is_thumb_function_name = false;
975
976/* Literal pool structure.  Held on a per-section
977   and per-sub-section basis.  */
978
979#define MAX_LITERAL_POOL_SIZE 1024
980typedef struct literal_pool
981{
982  expressionS	         literals [MAX_LITERAL_POOL_SIZE];
983  unsigned int	         next_free_entry;
984  unsigned int	         id;
985  symbolS *	         symbol;
986  segT		         section;
987  subsegT	         sub_section;
988#ifdef OBJ_ELF
989  struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
990#endif
991  struct literal_pool *  next;
992  unsigned int		 alignment;
993} literal_pool;
994
995/* Pointer to a linked list of literal pools.  */
996literal_pool * list_of_pools = NULL;
997
998typedef enum asmfunc_states
999{
1000  OUTSIDE_ASMFUNC,
1001  WAITING_ASMFUNC_NAME,
1002  WAITING_ENDASMFUNC
1003} asmfunc_states;
1004
1005static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
1006
1007#ifdef OBJ_ELF
1008#  define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1009#else
1010static struct current_pred now_pred;
1011#endif
1012
1013static inline int
1014now_pred_compatible (int cond)
1015{
1016  return (cond & ~1) == (now_pred.cc & ~1);
1017}
1018
1019static inline int
1020conditional_insn (void)
1021{
1022  return inst.cond != COND_ALWAYS;
1023}
1024
1025static int in_pred_block (void);
1026
1027static int handle_pred_state (void);
1028
1029static void force_automatic_it_block_close (void);
1030
1031static void it_fsm_post_encode (void);
1032
1033#define set_pred_insn_type(type)			\
1034  do						\
1035    {						\
1036      inst.pred_insn_type = type;			\
1037      if (handle_pred_state () == FAIL)		\
1038	return;					\
1039    }						\
1040  while (0)
1041
1042#define set_pred_insn_type_nonvoid(type, failret) \
1043  do						\
1044    {                                           \
1045      inst.pred_insn_type = type;			\
1046      if (handle_pred_state () == FAIL)		\
1047	return failret;				\
1048    }						\
1049  while(0)
1050
1051#define set_pred_insn_type_last()				\
1052  do							\
1053    {							\
1054      if (inst.cond == COND_ALWAYS)			\
1055	set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);	\
1056      else						\
1057	set_pred_insn_type (INSIDE_IT_LAST_INSN);		\
1058    }							\
1059  while (0)
1060
1061/* Toggle value[pos].  */
1062#define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1063
1064/* Pure syntax.	 */
1065
1066/* This array holds the chars that always start a comment.  If the
1067   pre-processor is disabled, these aren't very useful.	 */
1068char arm_comment_chars[] = "@";
1069
1070/* This array holds the chars that only start a comment at the beginning of
1071   a line.  If the line seems to have the form '# 123 filename'
1072   .line and .file directives will appear in the pre-processed output.	*/
1073/* Note that input_file.c hand checks for '#' at the beginning of the
1074   first line of the input file.  This is because the compiler outputs
1075   #NO_APP at the beginning of its output.  */
1076/* Also note that comments like this one will always work.  */
1077const char line_comment_chars[] = "#";
1078
1079char arm_line_separator_chars[] = ";";
1080
1081/* Chars that can be used to separate mant
1082   from exp in floating point numbers.	*/
1083const char EXP_CHARS[] = "eE";
1084
1085/* Chars that mean this number is a floating point constant.  */
1086/* As in 0f12.456  */
1087/* or	 0d1.2345e12  */
1088
1089const char FLT_CHARS[] = "rRsSfFdDxXeEpPHh";
1090
1091/* Prefix characters that indicate the start of an immediate
1092   value.  */
1093#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1094
1095/* Separator character handling.  */
1096
1097#define skip_whitespace(str)  do { if (*(str) == ' ') ++(str); } while (0)
1098
1099enum fp_16bit_format
1100{
1101  ARM_FP16_FORMAT_IEEE		= 0x1,
1102  ARM_FP16_FORMAT_ALTERNATIVE	= 0x2,
1103  ARM_FP16_FORMAT_DEFAULT	= 0x3
1104};
1105
1106static enum fp_16bit_format fp16_format = ARM_FP16_FORMAT_DEFAULT;
1107
1108
1109static inline int
1110skip_past_char (char ** str, char c)
1111{
1112  /* PR gas/14987: Allow for whitespace before the expected character.  */
1113  skip_whitespace (*str);
1114
1115  if (**str == c)
1116    {
1117      (*str)++;
1118      return SUCCESS;
1119    }
1120  else
1121    return FAIL;
1122}
1123
1124#define skip_past_comma(str) skip_past_char (str, ',')
1125
1126/* Arithmetic expressions (possibly involving symbols).	 */
1127
1128/* Return TRUE if anything in the expression is a bignum.  */
1129
1130static bool
1131walk_no_bignums (symbolS * sp)
1132{
1133  if (symbol_get_value_expression (sp)->X_op == O_big)
1134    return true;
1135
1136  if (symbol_get_value_expression (sp)->X_add_symbol)
1137    {
1138      return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1139	      || (symbol_get_value_expression (sp)->X_op_symbol
1140		  && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
1141    }
1142
1143  return false;
1144}
1145
1146static bool in_my_get_expression = false;
1147
1148/* Third argument to my_get_expression.	 */
1149#define GE_NO_PREFIX 0
1150#define GE_IMM_PREFIX 1
1151#define GE_OPT_PREFIX 2
1152/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1153   immediates, as can be used in Neon VMVN and VMOV immediate instructions.  */
1154#define GE_OPT_PREFIX_BIG 3
1155
1156static int
1157my_get_expression (expressionS * ep, char ** str, int prefix_mode)
1158{
1159  char * save_in;
1160
1161  /* In unified syntax, all prefixes are optional.  */
1162  if (unified_syntax)
1163    prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
1164		  : GE_OPT_PREFIX;
1165
1166  switch (prefix_mode)
1167    {
1168    case GE_NO_PREFIX: break;
1169    case GE_IMM_PREFIX:
1170      if (!is_immediate_prefix (**str))
1171	{
1172	  inst.error = _("immediate expression requires a # prefix");
1173	  return FAIL;
1174	}
1175      (*str)++;
1176      break;
1177    case GE_OPT_PREFIX:
1178    case GE_OPT_PREFIX_BIG:
1179      if (is_immediate_prefix (**str))
1180	(*str)++;
1181      break;
1182    default:
1183      abort ();
1184    }
1185
1186  memset (ep, 0, sizeof (expressionS));
1187
1188  save_in = input_line_pointer;
1189  input_line_pointer = *str;
1190  in_my_get_expression = true;
1191  expression (ep);
1192  in_my_get_expression = false;
1193
1194  if (ep->X_op == O_illegal || ep->X_op == O_absent)
1195    {
1196      /* We found a bad or missing expression in md_operand().  */
1197      *str = input_line_pointer;
1198      input_line_pointer = save_in;
1199      if (inst.error == NULL)
1200	inst.error = (ep->X_op == O_absent
1201		      ? _("missing expression") :_("bad expression"));
1202      return 1;
1203    }
1204
1205  /* Get rid of any bignums now, so that we don't generate an error for which
1206     we can't establish a line number later on.	 Big numbers are never valid
1207     in instructions, which is where this routine is always called.  */
1208  if (prefix_mode != GE_OPT_PREFIX_BIG
1209      && (ep->X_op == O_big
1210	  || (ep->X_add_symbol
1211	      && (walk_no_bignums (ep->X_add_symbol)
1212		  || (ep->X_op_symbol
1213		      && walk_no_bignums (ep->X_op_symbol))))))
1214    {
1215      inst.error = _("invalid constant");
1216      *str = input_line_pointer;
1217      input_line_pointer = save_in;
1218      return 1;
1219    }
1220
1221  *str = input_line_pointer;
1222  input_line_pointer = save_in;
1223  return SUCCESS;
1224}
1225
1226/* Turn a string in input_line_pointer into a floating point constant
1227   of type TYPE, and store the appropriate bytes in *LITP.  The number
1228   of LITTLENUMS emitted is stored in *SIZEP.  An error message is
1229   returned, or NULL on OK.
1230
1231   Note that fp constants aren't represent in the normal way on the ARM.
1232   In big endian mode, things are as expected.	However, in little endian
1233   mode fp constants are big-endian word-wise, and little-endian byte-wise
1234   within the words.  For example, (double) 1.1 in big endian mode is
1235   the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1236   the byte sequence 99 99 f1 3f 9a 99 99 99.
1237
1238   ??? The format of 12 byte floats is uncertain according to gcc's arm.h.  */
1239
1240const char *
1241md_atof (int type, char * litP, int * sizeP)
1242{
1243  int prec;
1244  LITTLENUM_TYPE words[MAX_LITTLENUMS];
1245  char *t;
1246  int i;
1247
1248  switch (type)
1249    {
1250    case 'H':
1251    case 'h':
1252    /* bfloat16, despite not being part of the IEEE specification, can also
1253       be handled by atof_ieee().  */
1254    case 'b':
1255      prec = 1;
1256      break;
1257
1258    case 'f':
1259    case 'F':
1260    case 's':
1261    case 'S':
1262      prec = 2;
1263      break;
1264
1265    case 'd':
1266    case 'D':
1267    case 'r':
1268    case 'R':
1269      prec = 4;
1270      break;
1271
1272    case 'x':
1273    case 'X':
1274      prec = 5;
1275      break;
1276
1277    case 'p':
1278    case 'P':
1279      prec = 5;
1280      break;
1281
1282    default:
1283      *sizeP = 0;
1284      return _("Unrecognized or unsupported floating point constant");
1285    }
1286
1287  t = atof_ieee (input_line_pointer, type, words);
1288  if (t)
1289    input_line_pointer = t;
1290  *sizeP = prec * sizeof (LITTLENUM_TYPE);
1291
1292  if (target_big_endian || prec == 1)
1293    for (i = 0; i < prec; i++)
1294      {
1295	md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1296	litP += sizeof (LITTLENUM_TYPE);
1297      }
1298  else if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1299    for (i = prec - 1; i >= 0; i--)
1300      {
1301	md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1302	litP += sizeof (LITTLENUM_TYPE);
1303      }
1304  else
1305    /* For a 4 byte float the order of elements in `words' is 1 0.
1306       For an 8 byte float the order is 1 0 3 2.  */
1307    for (i = 0; i < prec; i += 2)
1308      {
1309	md_number_to_chars (litP, (valueT) words[i + 1],
1310			    sizeof (LITTLENUM_TYPE));
1311	md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1312			    (valueT) words[i], sizeof (LITTLENUM_TYPE));
1313	litP += 2 * sizeof (LITTLENUM_TYPE);
1314      }
1315
1316  return NULL;
1317}
1318
1319/* We handle all bad expressions here, so that we can report the faulty
1320   instruction in the error message.  */
1321
1322void
1323md_operand (expressionS * exp)
1324{
1325  if (in_my_get_expression)
1326    exp->X_op = O_illegal;
1327}
1328
1329/* Immediate values.  */
1330
1331#ifdef OBJ_ELF
1332/* Generic immediate-value read function for use in directives.
1333   Accepts anything that 'expression' can fold to a constant.
1334   *val receives the number.  */
1335
1336static int
1337immediate_for_directive (int *val)
1338{
1339  expressionS exp;
1340  exp.X_op = O_illegal;
1341
1342  if (is_immediate_prefix (*input_line_pointer))
1343    {
1344      input_line_pointer++;
1345      expression (&exp);
1346    }
1347
1348  if (exp.X_op != O_constant)
1349    {
1350      as_bad (_("expected #constant"));
1351      ignore_rest_of_line ();
1352      return FAIL;
1353    }
1354  *val = exp.X_add_number;
1355  return SUCCESS;
1356}
1357#endif
1358
1359/* Register parsing.  */
1360
1361/* Generic register parser.  CCP points to what should be the
1362   beginning of a register name.  If it is indeed a valid register
1363   name, advance CCP over it and return the reg_entry structure;
1364   otherwise return NULL.  Does not issue diagnostics.	*/
1365
1366static struct reg_entry *
1367arm_reg_parse_multi (char **ccp)
1368{
1369  char *start = *ccp;
1370  char *p;
1371  struct reg_entry *reg;
1372
1373  skip_whitespace (start);
1374
1375#ifdef REGISTER_PREFIX
1376  if (*start != REGISTER_PREFIX)
1377    return NULL;
1378  start++;
1379#endif
1380#ifdef OPTIONAL_REGISTER_PREFIX
1381  if (*start == OPTIONAL_REGISTER_PREFIX)
1382    start++;
1383#endif
1384
1385  p = start;
1386  if (!ISALPHA (*p) || !is_name_beginner (*p))
1387    return NULL;
1388
1389  do
1390    p++;
1391  while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1392
1393  reg = (struct reg_entry *) str_hash_find_n (arm_reg_hsh, start, p - start);
1394
1395  if (!reg)
1396    return NULL;
1397
1398  *ccp = p;
1399  return reg;
1400}
1401
1402static int
1403arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
1404		    enum arm_reg_type type)
1405{
1406  /* Alternative syntaxes are accepted for a few register classes.  */
1407  switch (type)
1408    {
1409    case REG_TYPE_MVF:
1410    case REG_TYPE_MVD:
1411    case REG_TYPE_MVFX:
1412    case REG_TYPE_MVDX:
1413      /* Generic coprocessor register names are allowed for these.  */
1414      if (reg && reg->type == REG_TYPE_CN)
1415	return reg->number;
1416      break;
1417
1418    case REG_TYPE_CP:
1419      /* For backward compatibility, a bare number is valid here.  */
1420      {
1421	unsigned long processor = strtoul (start, ccp, 10);
1422	if (*ccp != start && processor <= 15)
1423	  return processor;
1424      }
1425      /* Fall through.  */
1426
1427    case REG_TYPE_MMXWC:
1428      /* WC includes WCG.  ??? I'm not sure this is true for all
1429	 instructions that take WC registers.  */
1430      if (reg && reg->type == REG_TYPE_MMXWCG)
1431	return reg->number;
1432      break;
1433
1434    default:
1435      break;
1436    }
1437
1438  return FAIL;
1439}
1440
1441/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1442   return value is the register number or FAIL.  */
1443
1444static int
1445arm_reg_parse (char **ccp, enum arm_reg_type type)
1446{
1447  char *start = *ccp;
1448  struct reg_entry *reg = arm_reg_parse_multi (ccp);
1449  int ret;
1450
1451  /* Do not allow a scalar (reg+index) to parse as a register.  */
1452  if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1453    return FAIL;
1454
1455  if (reg && reg->type == type)
1456    return reg->number;
1457
1458  if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1459    return ret;
1460
1461  *ccp = start;
1462  return FAIL;
1463}
1464
1465/* Parse a Neon type specifier. *STR should point at the leading '.'
1466   character. Does no verification at this stage that the type fits the opcode
1467   properly. E.g.,
1468
1469     .i32.i32.s16
1470     .s32.f32
1471     .u16
1472
1473   Can all be legally parsed by this function.
1474
1475   Fills in neon_type struct pointer with parsed information, and updates STR
1476   to point after the parsed type specifier. Returns SUCCESS if this was a legal
1477   type, FAIL if not.  */
1478
1479static int
1480parse_neon_type (struct neon_type *type, char **str)
1481{
1482  char *ptr = *str;
1483
1484  if (type)
1485    type->elems = 0;
1486
1487  while (type->elems < NEON_MAX_TYPE_ELS)
1488    {
1489      enum neon_el_type thistype = NT_untyped;
1490      unsigned thissize = -1u;
1491
1492      if (*ptr != '.')
1493	break;
1494
1495      ptr++;
1496
1497      /* Just a size without an explicit type.  */
1498      if (ISDIGIT (*ptr))
1499	goto parsesize;
1500
1501      switch (TOLOWER (*ptr))
1502	{
1503	case 'i': thistype = NT_integer; break;
1504	case 'f': thistype = NT_float; break;
1505	case 'p': thistype = NT_poly; break;
1506	case 's': thistype = NT_signed; break;
1507	case 'u': thistype = NT_unsigned; break;
1508	case 'd':
1509	  thistype = NT_float;
1510	  thissize = 64;
1511	  ptr++;
1512	  goto done;
1513	case 'b':
1514	  thistype = NT_bfloat;
1515	  switch (TOLOWER (*(++ptr)))
1516	    {
1517	    case 'f':
1518	      ptr += 1;
1519	      thissize = strtoul (ptr, &ptr, 10);
1520	      if (thissize != 16)
1521		{
1522		  as_bad (_("bad size %d in type specifier"), thissize);
1523		  return FAIL;
1524		}
1525	      goto done;
1526	    case '0': case '1': case '2': case '3': case '4':
1527	    case '5': case '6': case '7': case '8': case '9':
1528	    case ' ': case '.':
1529	      as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1530	      return FAIL;
1531	    default:
1532	      break;
1533	    }
1534	  break;
1535	default:
1536	  as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1537	  return FAIL;
1538	}
1539
1540      ptr++;
1541
1542      /* .f is an abbreviation for .f32.  */
1543      if (thistype == NT_float && !ISDIGIT (*ptr))
1544	thissize = 32;
1545      else
1546	{
1547	parsesize:
1548	  thissize = strtoul (ptr, &ptr, 10);
1549
1550	  if (thissize != 8 && thissize != 16 && thissize != 32
1551	      && thissize != 64)
1552	    {
1553	      as_bad (_("bad size %d in type specifier"), thissize);
1554	      return FAIL;
1555	    }
1556	}
1557
1558      done:
1559      if (type)
1560	{
1561	  type->el[type->elems].type = thistype;
1562	  type->el[type->elems].size = thissize;
1563	  type->elems++;
1564	}
1565    }
1566
1567  /* Empty/missing type is not a successful parse.  */
1568  if (type->elems == 0)
1569    return FAIL;
1570
1571  *str = ptr;
1572
1573  return SUCCESS;
1574}
1575
1576/* Errors may be set multiple times during parsing or bit encoding
1577   (particularly in the Neon bits), but usually the earliest error which is set
1578   will be the most meaningful. Avoid overwriting it with later (cascading)
1579   errors by calling this function.  */
1580
1581static void
1582first_error (const char *err)
1583{
1584  if (!inst.error)
1585    inst.error = err;
1586}
1587
1588/* Parse a single type, e.g. ".s32", leading period included.  */
1589static int
1590parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1591{
1592  char *str = *ccp;
1593  struct neon_type optype;
1594
1595  if (*str == '.')
1596    {
1597      if (parse_neon_type (&optype, &str) == SUCCESS)
1598	{
1599	  if (optype.elems == 1)
1600	    *vectype = optype.el[0];
1601	  else
1602	    {
1603	      first_error (_("only one type should be specified for operand"));
1604	      return FAIL;
1605	    }
1606	}
1607      else
1608	{
1609	  first_error (_("vector type expected"));
1610	  return FAIL;
1611	}
1612    }
1613  else
1614    return FAIL;
1615
1616  *ccp = str;
1617
1618  return SUCCESS;
1619}
1620
1621/* Special meanings for indices (which have a range of 0-7), which will fit into
1622   a 4-bit integer.  */
1623
1624#define NEON_ALL_LANES		15
1625#define NEON_INTERLEAVE_LANES	14
1626
1627/* Record a use of the given feature.  */
1628static void
1629record_feature_use (const arm_feature_set *feature)
1630{
1631  if (thumb_mode)
1632    ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
1633  else
1634    ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
1635}
1636
1637/* If the given feature available in the selected CPU, mark it as used.
1638   Returns TRUE iff feature is available.  */
1639static bool
1640mark_feature_used (const arm_feature_set *feature)
1641{
1642
1643  /* Do not support the use of MVE only instructions when in auto-detection or
1644     -march=all.  */
1645  if (((feature == &mve_ext) || (feature == &mve_fp_ext))
1646      && ARM_CPU_IS_ANY (cpu_variant))
1647    {
1648      first_error (BAD_MVE_AUTO);
1649      return false;
1650    }
1651  /* Ensure the option is valid on the current architecture.  */
1652  if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
1653    return false;
1654
1655  /* Add the appropriate architecture feature for the barrier option used.
1656     */
1657  record_feature_use (feature);
1658
1659  return true;
1660}
1661
1662/* Parse either a register or a scalar, with an optional type. Return the
1663   register number, and optionally fill in the actual type of the register
1664   when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1665   type/index information in *TYPEINFO.  */
1666
1667static int
1668parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
1669			   enum arm_reg_type *rtype,
1670			   struct neon_typed_alias *typeinfo)
1671{
1672  char *str = *ccp;
1673  struct reg_entry *reg = arm_reg_parse_multi (&str);
1674  struct neon_typed_alias atype;
1675  struct neon_type_el parsetype;
1676
1677  atype.defined = 0;
1678  atype.index = -1;
1679  atype.eltype.type = NT_invtype;
1680  atype.eltype.size = -1;
1681
1682  /* Try alternate syntax for some types of register. Note these are mutually
1683     exclusive with the Neon syntax extensions.  */
1684  if (reg == NULL)
1685    {
1686      int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1687      if (altreg != FAIL)
1688	*ccp = str;
1689      if (typeinfo)
1690	*typeinfo = atype;
1691      return altreg;
1692    }
1693
1694  /* Undo polymorphism when a set of register types may be accepted.  */
1695  if ((type == REG_TYPE_NDQ
1696       && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1697      || (type == REG_TYPE_VFSD
1698	  && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1699      || (type == REG_TYPE_NSDQ
1700	  && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1701	      || reg->type == REG_TYPE_NQ))
1702      || (type == REG_TYPE_NSD
1703	  && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
1704      || (type == REG_TYPE_MMXWC
1705	  && (reg->type == REG_TYPE_MMXWCG)))
1706    type = (enum arm_reg_type) reg->type;
1707
1708  if (type == REG_TYPE_MQ)
1709    {
1710      if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1711	return FAIL;
1712
1713      if (!reg || reg->type != REG_TYPE_NQ)
1714	return FAIL;
1715
1716      if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32))
1717	{
1718	  first_error (_("expected MVE register [q0..q7]"));
1719	  return FAIL;
1720	}
1721      type = REG_TYPE_NQ;
1722    }
1723  else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
1724	   && (type == REG_TYPE_NQ))
1725    return FAIL;
1726
1727
1728  if (type != reg->type)
1729    return FAIL;
1730
1731  if (reg->neon)
1732    atype = *reg->neon;
1733
1734  if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1735    {
1736      if ((atype.defined & NTA_HASTYPE) != 0)
1737	{
1738	  first_error (_("can't redefine type for operand"));
1739	  return FAIL;
1740	}
1741      atype.defined |= NTA_HASTYPE;
1742      atype.eltype = parsetype;
1743    }
1744
1745  if (skip_past_char (&str, '[') == SUCCESS)
1746    {
1747      if (type != REG_TYPE_VFD
1748	  && !(type == REG_TYPE_VFS
1749	       && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))
1750	  && !(type == REG_TYPE_NQ
1751	       && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
1752	{
1753	  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1754	    first_error (_("only D and Q registers may be indexed"));
1755	  else
1756	    first_error (_("only D registers may be indexed"));
1757	  return FAIL;
1758	}
1759
1760      if ((atype.defined & NTA_HASINDEX) != 0)
1761	{
1762	  first_error (_("can't change index for operand"));
1763	  return FAIL;
1764	}
1765
1766      atype.defined |= NTA_HASINDEX;
1767
1768      if (skip_past_char (&str, ']') == SUCCESS)
1769	atype.index = NEON_ALL_LANES;
1770      else
1771	{
1772	  expressionS exp;
1773
1774	  my_get_expression (&exp, &str, GE_NO_PREFIX);
1775
1776	  if (exp.X_op != O_constant)
1777	    {
1778	      first_error (_("constant expression required"));
1779	      return FAIL;
1780	    }
1781
1782	  if (skip_past_char (&str, ']') == FAIL)
1783	    return FAIL;
1784
1785	  atype.index = exp.X_add_number;
1786	}
1787    }
1788
1789  if (typeinfo)
1790    *typeinfo = atype;
1791
1792  if (rtype)
1793    *rtype = type;
1794
1795  *ccp = str;
1796
1797  return reg->number;
1798}
1799
1800/* Like arm_reg_parse, but also allow the following extra features:
1801    - If RTYPE is non-zero, return the (possibly restricted) type of the
1802      register (e.g. Neon double or quad reg when either has been requested).
1803    - If this is a Neon vector type with additional type information, fill
1804      in the struct pointed to by VECTYPE (if non-NULL).
1805   This function will fault on encountering a scalar.  */
1806
1807static int
1808arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
1809		     enum arm_reg_type *rtype, struct neon_type_el *vectype)
1810{
1811  struct neon_typed_alias atype;
1812  char *str = *ccp;
1813  int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1814
1815  if (reg == FAIL)
1816    return FAIL;
1817
1818  /* Do not allow regname(... to parse as a register.  */
1819  if (*str == '(')
1820    return FAIL;
1821
1822  /* Do not allow a scalar (reg+index) to parse as a register.  */
1823  if ((atype.defined & NTA_HASINDEX) != 0)
1824    {
1825      first_error (_("register operand expected, but got scalar"));
1826      return FAIL;
1827    }
1828
1829  if (vectype)
1830    *vectype = atype.eltype;
1831
1832  *ccp = str;
1833
1834  return reg;
1835}
1836
1837#define NEON_SCALAR_REG(X)	((X) >> 4)
1838#define NEON_SCALAR_INDEX(X)	((X) & 15)
1839
1840/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1841   have enough information to be able to do a good job bounds-checking. So, we
1842   just do easy checks here, and do further checks later.  */
1843
1844static int
1845parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum
1846	      arm_reg_type reg_type)
1847{
1848  int reg;
1849  char *str = *ccp;
1850  struct neon_typed_alias atype;
1851  unsigned reg_size;
1852
1853  reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
1854
1855  switch (reg_type)
1856    {
1857    case REG_TYPE_VFS:
1858      reg_size = 32;
1859      break;
1860    case REG_TYPE_VFD:
1861      reg_size = 64;
1862      break;
1863    case REG_TYPE_MQ:
1864      reg_size = 128;
1865      break;
1866    default:
1867      gas_assert (0);
1868      return FAIL;
1869    }
1870
1871  if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
1872    return FAIL;
1873
1874  if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES)
1875    {
1876      first_error (_("scalar must have an index"));
1877      return FAIL;
1878    }
1879  else if (atype.index >= reg_size / elsize)
1880    {
1881      first_error (_("scalar index out of range"));
1882      return FAIL;
1883    }
1884
1885  if (type)
1886    *type = atype.eltype;
1887
1888  *ccp = str;
1889
1890  return reg * 16 + atype.index;
1891}
1892
1893/* Types of registers in a list.  */
1894
1895enum reg_list_els
1896{
1897  REGLIST_RN,
1898  REGLIST_PSEUDO,
1899  REGLIST_CLRM,
1900  REGLIST_VFP_S,
1901  REGLIST_VFP_S_VPR,
1902  REGLIST_VFP_D,
1903  REGLIST_VFP_D_VPR,
1904  REGLIST_NEON_D
1905};
1906
1907/* Parse an ARM register list.  Returns the bitmask, or FAIL.  */
1908
1909static long
1910parse_reg_list (char ** strp, enum reg_list_els etype)
1911{
1912  char *str = *strp;
1913  long range = 0;
1914  int another_range;
1915
1916  gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM
1917	      || etype == REGLIST_PSEUDO);
1918
1919  /* We come back here if we get ranges concatenated by '+' or '|'.  */
1920  do
1921    {
1922      skip_whitespace (str);
1923
1924      another_range = 0;
1925
1926      if (*str == '{')
1927	{
1928	  int in_range = 0;
1929	  int cur_reg = -1;
1930
1931	  str++;
1932	  do
1933	    {
1934	      int reg;
1935	      const char apsr_str[] = "apsr";
1936	      int apsr_str_len = strlen (apsr_str);
1937	      enum arm_reg_type rt;
1938
1939	      if (etype == REGLIST_RN || etype == REGLIST_CLRM)
1940		rt = REG_TYPE_RN;
1941	      else
1942		rt = REG_TYPE_PSEUDO;
1943
1944	      reg = arm_reg_parse (&str, rt);
1945
1946	      /* Skip over allowed registers of alternative types in mixed-type
1947	         register lists.  */
1948	      if (reg == FAIL && rt == REG_TYPE_PSEUDO
1949		  && ((reg = arm_reg_parse (&str, REG_TYPE_RN)) != FAIL))
1950		{
1951		  cur_reg = reg;
1952		  continue;
1953		}
1954	      else if (reg == FAIL && rt == REG_TYPE_RN
1955		       && ((reg = arm_reg_parse (&str, REG_TYPE_PSEUDO)) != FAIL))
1956		{
1957		  cur_reg = reg;
1958		  continue;
1959		}
1960
1961	      if (etype == REGLIST_CLRM)
1962		{
1963		  if (reg == REG_SP || reg == REG_PC)
1964		    reg = FAIL;
1965		  else if (reg == FAIL
1966			   && !strncasecmp (str, apsr_str, apsr_str_len)
1967			   && !ISALPHA (*(str + apsr_str_len)))
1968		    {
1969		      reg = 15;
1970		      str += apsr_str_len;
1971		    }
1972
1973		  if (reg == FAIL)
1974		    {
1975		      first_error (_("r0-r12, lr or APSR expected"));
1976		      return FAIL;
1977		    }
1978		}
1979	      else if (etype == REGLIST_PSEUDO)
1980		{
1981		  if (reg == FAIL)
1982		    {
1983		      first_error (_(reg_expected_msgs[REG_TYPE_PSEUDO]));
1984		      return FAIL;
1985		    }
1986		}
1987	      else /* etype == REGLIST_RN.  */
1988		{
1989		  if (reg == FAIL)
1990		    {
1991		      first_error (_(reg_expected_msgs[REGLIST_RN]));
1992		      return FAIL;
1993		    }
1994		}
1995
1996	      if (in_range)
1997		{
1998		  int i;
1999
2000		  if (reg <= cur_reg)
2001		    {
2002		      first_error (_("bad range in register list"));
2003		      return FAIL;
2004		    }
2005
2006		  for (i = cur_reg + 1; i < reg; i++)
2007		    {
2008		      if (range & (1 << i))
2009			as_tsktsk
2010			  (_("Warning: duplicated register (r%d) in register list"),
2011			   i);
2012		      else
2013			range |= 1 << i;
2014		    }
2015		  in_range = 0;
2016		}
2017
2018	      if (range & (1 << reg))
2019		as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2020			   reg);
2021	      else if (reg <= cur_reg)
2022		as_tsktsk (_("Warning: register range not in ascending order"));
2023
2024	      range |= 1 << reg;
2025	      cur_reg = reg;
2026	    }
2027	  while (skip_past_comma (&str) != FAIL
2028		 || (in_range = 1, *str++ == '-'));
2029	  str--;
2030
2031	  if (skip_past_char (&str, '}') == FAIL)
2032	    {
2033	      first_error (_("missing `}'"));
2034	      return FAIL;
2035	    }
2036	}
2037      else if (etype == REGLIST_RN)
2038	{
2039	  expressionS exp;
2040
2041	  if (my_get_expression (&exp, &str, GE_NO_PREFIX))
2042	    return FAIL;
2043
2044	  if (exp.X_op == O_constant)
2045	    {
2046	      if (exp.X_add_number
2047		  != (exp.X_add_number & 0x0000ffff))
2048		{
2049		  inst.error = _("invalid register mask");
2050		  return FAIL;
2051		}
2052
2053	      if ((range & exp.X_add_number) != 0)
2054		{
2055		  int regno = range & exp.X_add_number;
2056
2057		  regno &= -regno;
2058		  regno = (1 << regno) - 1;
2059		  as_tsktsk
2060		    (_("Warning: duplicated register (r%d) in register list"),
2061		     regno);
2062		}
2063
2064	      range |= exp.X_add_number;
2065	    }
2066	  else
2067	    {
2068	      if (inst.relocs[0].type != 0)
2069		{
2070		  inst.error = _("expression too complex");
2071		  return FAIL;
2072		}
2073
2074	      memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
2075	      inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
2076	      inst.relocs[0].pc_rel = 0;
2077	    }
2078	}
2079
2080      if (*str == '|' || *str == '+')
2081	{
2082	  str++;
2083	  another_range = 1;
2084	}
2085    }
2086  while (another_range);
2087
2088  *strp = str;
2089  return range;
2090}
2091
2092/* Parse a VFP register list.  If the string is invalid return FAIL.
2093   Otherwise return the number of registers, and set PBASE to the first
2094   register.  Parses registers of type ETYPE.
2095   If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2096     - Q registers can be used to specify pairs of D registers
2097     - { } can be omitted from around a singleton register list
2098	 FIXME: This is not implemented, as it would require backtracking in
2099	 some cases, e.g.:
2100	   vtbl.8 d3,d4,d5
2101	 This could be done (the meaning isn't really ambiguous), but doesn't
2102	 fit in well with the current parsing framework.
2103     - 32 D registers may be used (also true for VFPv3).
2104   FIXME: Types are ignored in these register lists, which is probably a
2105   bug.  */
2106
2107static int
2108parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
2109		    bool *partial_match)
2110{
2111  char *str = *ccp;
2112  int base_reg;
2113  int new_base;
2114  enum arm_reg_type regtype = (enum arm_reg_type) 0;
2115  int max_regs = 0;
2116  int count = 0;
2117  int warned = 0;
2118  unsigned long mask = 0;
2119  int i;
2120  bool vpr_seen = false;
2121  bool expect_vpr =
2122    (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
2123
2124  if (skip_past_char (&str, '{') == FAIL)
2125    {
2126      inst.error = _("expecting {");
2127      return FAIL;
2128    }
2129
2130  switch (etype)
2131    {
2132    case REGLIST_VFP_S:
2133    case REGLIST_VFP_S_VPR:
2134      regtype = REG_TYPE_VFS;
2135      max_regs = 32;
2136      break;
2137
2138    case REGLIST_VFP_D:
2139    case REGLIST_VFP_D_VPR:
2140      regtype = REG_TYPE_VFD;
2141      break;
2142
2143    case REGLIST_NEON_D:
2144      regtype = REG_TYPE_NDQ;
2145      break;
2146
2147    default:
2148      gas_assert (0);
2149    }
2150
2151  if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
2152    {
2153      /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant.  */
2154      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
2155	{
2156	  max_regs = 32;
2157	  if (thumb_mode)
2158	    ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
2159				    fpu_vfp_ext_d32);
2160	  else
2161	    ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
2162				    fpu_vfp_ext_d32);
2163	}
2164      else
2165	max_regs = 16;
2166    }
2167
2168  base_reg = max_regs;
2169  *partial_match = false;
2170
2171  do
2172    {
2173      unsigned int setmask = 1, addregs = 1;
2174      const char vpr_str[] = "vpr";
2175      size_t vpr_str_len = strlen (vpr_str);
2176
2177      new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
2178
2179      if (expect_vpr)
2180	{
2181	  if (new_base == FAIL
2182	      && !strncasecmp (str, vpr_str, vpr_str_len)
2183	      && !ISALPHA (*(str + vpr_str_len))
2184	      && !vpr_seen)
2185	    {
2186	      vpr_seen = true;
2187	      str += vpr_str_len;
2188	      if (count == 0)
2189		base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs.  */
2190	    }
2191	  else if (vpr_seen)
2192	    {
2193	      first_error (_("VPR expected last"));
2194	      return FAIL;
2195	    }
2196	  else if (new_base == FAIL)
2197	    {
2198	      if (regtype == REG_TYPE_VFS)
2199		first_error (_("VFP single precision register or VPR "
2200			       "expected"));
2201	      else /* regtype == REG_TYPE_VFD.  */
2202		first_error (_("VFP/Neon double precision register or VPR "
2203			       "expected"));
2204	      return FAIL;
2205	    }
2206	}
2207      else if (new_base == FAIL)
2208	{
2209	  first_error (_(reg_expected_msgs[regtype]));
2210	  return FAIL;
2211	}
2212
2213      *partial_match = true;
2214      if (vpr_seen)
2215	continue;
2216
2217      if (new_base >= max_regs)
2218	{
2219	  first_error (_("register out of range in list"));
2220	  return FAIL;
2221	}
2222
2223      /* Note: a value of 2 * n is returned for the register Q<n>.  */
2224      if (regtype == REG_TYPE_NQ)
2225	{
2226	  setmask = 3;
2227	  addregs = 2;
2228	}
2229
2230      if (new_base < base_reg)
2231	base_reg = new_base;
2232
2233      if (mask & (setmask << new_base))
2234	{
2235	  first_error (_("invalid register list"));
2236	  return FAIL;
2237	}
2238
2239      if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
2240	{
2241	  as_tsktsk (_("register list not in ascending order"));
2242	  warned = 1;
2243	}
2244
2245      mask |= setmask << new_base;
2246      count += addregs;
2247
2248      if (*str == '-') /* We have the start of a range expression */
2249	{
2250	  int high_range;
2251
2252	  str++;
2253
2254	  if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
2255	      == FAIL)
2256	    {
2257	      inst.error = gettext (reg_expected_msgs[regtype]);
2258	      return FAIL;
2259	    }
2260
2261	  if (high_range >= max_regs)
2262	    {
2263	      first_error (_("register out of range in list"));
2264	      return FAIL;
2265	    }
2266
2267	  if (regtype == REG_TYPE_NQ)
2268	    high_range = high_range + 1;
2269
2270	  if (high_range <= new_base)
2271	    {
2272	      inst.error = _("register range not in ascending order");
2273	      return FAIL;
2274	    }
2275
2276	  for (new_base += addregs; new_base <= high_range; new_base += addregs)
2277	    {
2278	      if (mask & (setmask << new_base))
2279		{
2280		  inst.error = _("invalid register list");
2281		  return FAIL;
2282		}
2283
2284	      mask |= setmask << new_base;
2285	      count += addregs;
2286	    }
2287	}
2288    }
2289  while (skip_past_comma (&str) != FAIL);
2290
2291  str++;
2292
2293  /* Sanity check -- should have raised a parse error above.  */
2294  if ((!vpr_seen && count == 0) || count > max_regs)
2295    abort ();
2296
2297  *pbase = base_reg;
2298
2299  if (expect_vpr && !vpr_seen)
2300    {
2301      first_error (_("VPR expected last"));
2302      return FAIL;
2303    }
2304
2305  /* Final test -- the registers must be consecutive.  */
2306  mask >>= base_reg;
2307  for (i = 0; i < count; i++)
2308    {
2309      if ((mask & (1u << i)) == 0)
2310	{
2311	  inst.error = _("non-contiguous register range");
2312	  return FAIL;
2313	}
2314    }
2315
2316  *ccp = str;
2317
2318  return count;
2319}
2320
2321/* True if two alias types are the same.  */
2322
2323static bool
2324neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2325{
2326  if (!a && !b)
2327    return true;
2328
2329  if (!a || !b)
2330    return false;
2331
2332  if (a->defined != b->defined)
2333    return false;
2334
2335  if ((a->defined & NTA_HASTYPE) != 0
2336      && (a->eltype.type != b->eltype.type
2337	  || a->eltype.size != b->eltype.size))
2338    return false;
2339
2340  if ((a->defined & NTA_HASINDEX) != 0
2341      && (a->index != b->index))
2342    return false;
2343
2344  return true;
2345}
2346
2347/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2348   The base register is put in *PBASE.
2349   The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2350   the return value.
2351   The register stride (minus one) is put in bit 4 of the return value.
2352   Bits [6:5] encode the list length (minus one).
2353   The type of the list elements is put in *ELTYPE, if non-NULL.  */
2354
2355#define NEON_LANE(X)		((X) & 0xf)
2356#define NEON_REG_STRIDE(X)	((((X) >> 4) & 1) + 1)
2357#define NEON_REGLIST_LENGTH(X)	((((X) >> 5) & 3) + 1)
2358
2359static int
2360parse_neon_el_struct_list (char **str, unsigned *pbase,
2361			   int mve,
2362			   struct neon_type_el *eltype)
2363{
2364  char *ptr = *str;
2365  int base_reg = -1;
2366  int reg_incr = -1;
2367  int count = 0;
2368  int lane = -1;
2369  int leading_brace = 0;
2370  enum arm_reg_type rtype = REG_TYPE_NDQ;
2371  const char *const incr_error = mve ? _("register stride must be 1") :
2372    _("register stride must be 1 or 2");
2373  const char *const type_error = _("mismatched element/structure types in list");
2374  struct neon_typed_alias firsttype;
2375  firsttype.defined = 0;
2376  firsttype.eltype.type = NT_invtype;
2377  firsttype.eltype.size = -1;
2378  firsttype.index = -1;
2379
2380  if (skip_past_char (&ptr, '{') == SUCCESS)
2381    leading_brace = 1;
2382
2383  do
2384    {
2385      struct neon_typed_alias atype;
2386      if (mve)
2387	rtype = REG_TYPE_MQ;
2388      int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2389
2390      if (getreg == FAIL)
2391	{
2392	  first_error (_(reg_expected_msgs[rtype]));
2393	  return FAIL;
2394	}
2395
2396      if (base_reg == -1)
2397	{
2398	  base_reg = getreg;
2399	  if (rtype == REG_TYPE_NQ)
2400	    {
2401	      reg_incr = 1;
2402	    }
2403	  firsttype = atype;
2404	}
2405      else if (reg_incr == -1)
2406	{
2407	  reg_incr = getreg - base_reg;
2408	  if (reg_incr < 1 || reg_incr > 2)
2409	    {
2410	      first_error (_(incr_error));
2411	      return FAIL;
2412	    }
2413	}
2414      else if (getreg != base_reg + reg_incr * count)
2415	{
2416	  first_error (_(incr_error));
2417	  return FAIL;
2418	}
2419
2420      if (! neon_alias_types_same (&atype, &firsttype))
2421	{
2422	  first_error (_(type_error));
2423	  return FAIL;
2424	}
2425
2426      /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2427	 modes.  */
2428      if (ptr[0] == '-')
2429	{
2430	  struct neon_typed_alias htype;
2431	  int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2432	  if (lane == -1)
2433	    lane = NEON_INTERLEAVE_LANES;
2434	  else if (lane != NEON_INTERLEAVE_LANES)
2435	    {
2436	      first_error (_(type_error));
2437	      return FAIL;
2438	    }
2439	  if (reg_incr == -1)
2440	    reg_incr = 1;
2441	  else if (reg_incr != 1)
2442	    {
2443	      first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2444	      return FAIL;
2445	    }
2446	  ptr++;
2447	  hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2448	  if (hireg == FAIL)
2449	    {
2450	      first_error (_(reg_expected_msgs[rtype]));
2451	      return FAIL;
2452	    }
2453	  if (! neon_alias_types_same (&htype, &firsttype))
2454	    {
2455	      first_error (_(type_error));
2456	      return FAIL;
2457	    }
2458	  count += hireg + dregs - getreg;
2459	  continue;
2460	}
2461
2462      /* If we're using Q registers, we can't use [] or [n] syntax.  */
2463      if (rtype == REG_TYPE_NQ)
2464	{
2465	  count += 2;
2466	  continue;
2467	}
2468
2469      if ((atype.defined & NTA_HASINDEX) != 0)
2470	{
2471	  if (lane == -1)
2472	    lane = atype.index;
2473	  else if (lane != atype.index)
2474	    {
2475	      first_error (_(type_error));
2476	      return FAIL;
2477	    }
2478	}
2479      else if (lane == -1)
2480	lane = NEON_INTERLEAVE_LANES;
2481      else if (lane != NEON_INTERLEAVE_LANES)
2482	{
2483	  first_error (_(type_error));
2484	  return FAIL;
2485	}
2486      count++;
2487    }
2488  while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
2489
2490  /* No lane set by [x]. We must be interleaving structures.  */
2491  if (lane == -1)
2492    lane = NEON_INTERLEAVE_LANES;
2493
2494  /* Sanity check.  */
2495  if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
2496      || (count > 1 && reg_incr == -1))
2497    {
2498      first_error (_("error parsing element/structure list"));
2499      return FAIL;
2500    }
2501
2502  if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2503    {
2504      first_error (_("expected }"));
2505      return FAIL;
2506    }
2507
2508  if (reg_incr == -1)
2509    reg_incr = 1;
2510
2511  if (eltype)
2512    *eltype = firsttype.eltype;
2513
2514  *pbase = base_reg;
2515  *str = ptr;
2516
2517  return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2518}
2519
2520/* Parse an explicit relocation suffix on an expression.  This is
2521   either nothing, or a word in parentheses.  Note that if !OBJ_ELF,
2522   arm_reloc_hsh contains no entries, so this function can only
2523   succeed if there is no () after the word.  Returns -1 on error,
2524   BFD_RELOC_UNUSED if there wasn't any suffix.	 */
2525
2526static int
2527parse_reloc (char **str)
2528{
2529  struct reloc_entry *r;
2530  char *p, *q;
2531
2532  if (**str != '(')
2533    return BFD_RELOC_UNUSED;
2534
2535  p = *str + 1;
2536  q = p;
2537
2538  while (*q && *q != ')' && *q != ',')
2539    q++;
2540  if (*q != ')')
2541    return -1;
2542
2543  if ((r = (struct reloc_entry *)
2544       str_hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
2545    return -1;
2546
2547  *str = q + 1;
2548  return r->reloc;
2549}
2550
2551/* Directives: register aliases.  */
2552
2553static struct reg_entry *
2554insert_reg_alias (char *str, unsigned number, int type)
2555{
2556  struct reg_entry *new_reg;
2557  const char *name;
2558
2559  if ((new_reg = (struct reg_entry *) str_hash_find (arm_reg_hsh, str)) != 0)
2560    {
2561      if (new_reg->builtin)
2562	as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
2563
2564      /* Only warn about a redefinition if it's not defined as the
2565	 same register.	 */
2566      else if (new_reg->number != number || new_reg->type != type)
2567	as_warn (_("ignoring redefinition of register alias '%s'"), str);
2568
2569      return NULL;
2570    }
2571
2572  name = xstrdup (str);
2573  new_reg = XNEW (struct reg_entry);
2574
2575  new_reg->name = name;
2576  new_reg->number = number;
2577  new_reg->type = type;
2578  new_reg->builtin = false;
2579  new_reg->neon = NULL;
2580
2581  str_hash_insert (arm_reg_hsh, name, new_reg, 0);
2582
2583  return new_reg;
2584}
2585
2586static void
2587insert_neon_reg_alias (char *str, int number, int type,
2588		       struct neon_typed_alias *atype)
2589{
2590  struct reg_entry *reg = insert_reg_alias (str, number, type);
2591
2592  if (!reg)
2593    {
2594      first_error (_("attempt to redefine typed alias"));
2595      return;
2596    }
2597
2598  if (atype)
2599    {
2600      reg->neon = XNEW (struct neon_typed_alias);
2601      *reg->neon = *atype;
2602    }
2603}
2604
2605/* Look for the .req directive.	 This is of the form:
2606
2607	new_register_name .req existing_register_name
2608
2609   If we find one, or if it looks sufficiently like one that we want to
2610   handle any error here, return TRUE.  Otherwise return FALSE.  */
2611
2612static bool
2613create_register_alias (char * newname, char *p)
2614{
2615  struct reg_entry *old;
2616  char *oldname, *nbuf;
2617  size_t nlen;
2618
2619  /* The input scrubber ensures that whitespace after the mnemonic is
2620     collapsed to single spaces.  */
2621  oldname = p;
2622  if (!startswith (oldname, " .req "))
2623    return false;
2624
2625  oldname += 6;
2626  if (*oldname == '\0')
2627    return false;
2628
2629  old = (struct reg_entry *) str_hash_find (arm_reg_hsh, oldname);
2630  if (!old)
2631    {
2632      as_warn (_("unknown register '%s' -- .req ignored"), oldname);
2633      return true;
2634    }
2635
2636  /* If TC_CASE_SENSITIVE is defined, then newname already points to
2637     the desired alias name, and p points to its end.  If not, then
2638     the desired alias name is in the global original_case_string.  */
2639#ifdef TC_CASE_SENSITIVE
2640  nlen = p - newname;
2641#else
2642  newname = original_case_string;
2643  nlen = strlen (newname);
2644#endif
2645
2646  nbuf = xmemdup0 (newname, nlen);
2647
2648  /* Create aliases under the new name as stated; an all-lowercase
2649     version of the new name; and an all-uppercase version of the new
2650     name.  */
2651  if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2652    {
2653      for (p = nbuf; *p; p++)
2654	*p = TOUPPER (*p);
2655
2656      if (strncmp (nbuf, newname, nlen))
2657	{
2658	  /* If this attempt to create an additional alias fails, do not bother
2659	     trying to create the all-lower case alias.  We will fail and issue
2660	     a second, duplicate error message.  This situation arises when the
2661	     programmer does something like:
2662	       foo .req r0
2663	       Foo .req r1
2664	     The second .req creates the "Foo" alias but then fails to create
2665	     the artificial FOO alias because it has already been created by the
2666	     first .req.  */
2667	  if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2668	    {
2669	      free (nbuf);
2670	      return true;
2671	    }
2672	}
2673
2674      for (p = nbuf; *p; p++)
2675	*p = TOLOWER (*p);
2676
2677      if (strncmp (nbuf, newname, nlen))
2678	insert_reg_alias (nbuf, old->number, old->type);
2679    }
2680
2681  free (nbuf);
2682  return true;
2683}
2684
2685/* Create a Neon typed/indexed register alias using directives, e.g.:
2686     X .dn d5.s32[1]
2687     Y .qn 6.s16
2688     Z .dn d7
2689     T .dn Z[0]
2690   These typed registers can be used instead of the types specified after the
2691   Neon mnemonic, so long as all operands given have types. Types can also be
2692   specified directly, e.g.:
2693     vadd d0.s32, d1.s32, d2.s32  */
2694
2695static bool
2696create_neon_reg_alias (char *newname, char *p)
2697{
2698  enum arm_reg_type basetype;
2699  struct reg_entry *basereg;
2700  struct reg_entry mybasereg;
2701  struct neon_type ntype;
2702  struct neon_typed_alias typeinfo;
2703  char *namebuf, *nameend ATTRIBUTE_UNUSED;
2704  int namelen;
2705
2706  typeinfo.defined = 0;
2707  typeinfo.eltype.type = NT_invtype;
2708  typeinfo.eltype.size = -1;
2709  typeinfo.index = -1;
2710
2711  nameend = p;
2712
2713  if (startswith (p, " .dn "))
2714    basetype = REG_TYPE_VFD;
2715  else if (startswith (p, " .qn "))
2716    basetype = REG_TYPE_NQ;
2717  else
2718    return false;
2719
2720  p += 5;
2721
2722  if (*p == '\0')
2723    return false;
2724
2725  basereg = arm_reg_parse_multi (&p);
2726
2727  if (basereg && basereg->type != basetype)
2728    {
2729      as_bad (_("bad type for register"));
2730      return false;
2731    }
2732
2733  if (basereg == NULL)
2734    {
2735      expressionS exp;
2736      /* Try parsing as an integer.  */
2737      my_get_expression (&exp, &p, GE_NO_PREFIX);
2738      if (exp.X_op != O_constant)
2739	{
2740	  as_bad (_("expression must be constant"));
2741	  return false;
2742	}
2743      basereg = &mybasereg;
2744      basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
2745						  : exp.X_add_number;
2746      basereg->neon = 0;
2747    }
2748
2749  if (basereg->neon)
2750    typeinfo = *basereg->neon;
2751
2752  if (parse_neon_type (&ntype, &p) == SUCCESS)
2753    {
2754      /* We got a type.  */
2755      if (typeinfo.defined & NTA_HASTYPE)
2756	{
2757	  as_bad (_("can't redefine the type of a register alias"));
2758	  return false;
2759	}
2760
2761      typeinfo.defined |= NTA_HASTYPE;
2762      if (ntype.elems != 1)
2763	{
2764	  as_bad (_("you must specify a single type only"));
2765	  return false;
2766	}
2767      typeinfo.eltype = ntype.el[0];
2768    }
2769
2770  if (skip_past_char (&p, '[') == SUCCESS)
2771    {
2772      expressionS exp;
2773      /* We got a scalar index.  */
2774
2775      if (typeinfo.defined & NTA_HASINDEX)
2776	{
2777	  as_bad (_("can't redefine the index of a scalar alias"));
2778	  return false;
2779	}
2780
2781      my_get_expression (&exp, &p, GE_NO_PREFIX);
2782
2783      if (exp.X_op != O_constant)
2784	{
2785	  as_bad (_("scalar index must be constant"));
2786	  return false;
2787	}
2788
2789      typeinfo.defined |= NTA_HASINDEX;
2790      typeinfo.index = exp.X_add_number;
2791
2792      if (skip_past_char (&p, ']') == FAIL)
2793	{
2794	  as_bad (_("expecting ]"));
2795	  return false;
2796	}
2797    }
2798
2799  /* If TC_CASE_SENSITIVE is defined, then newname already points to
2800     the desired alias name, and p points to its end.  If not, then
2801     the desired alias name is in the global original_case_string.  */
2802#ifdef TC_CASE_SENSITIVE
2803  namelen = nameend - newname;
2804#else
2805  newname = original_case_string;
2806  namelen = strlen (newname);
2807#endif
2808
2809  namebuf = xmemdup0 (newname, namelen);
2810
2811  insert_neon_reg_alias (namebuf, basereg->number, basetype,
2812			 typeinfo.defined != 0 ? &typeinfo : NULL);
2813
2814  /* Insert name in all uppercase.  */
2815  for (p = namebuf; *p; p++)
2816    *p = TOUPPER (*p);
2817
2818  if (strncmp (namebuf, newname, namelen))
2819    insert_neon_reg_alias (namebuf, basereg->number, basetype,
2820			   typeinfo.defined != 0 ? &typeinfo : NULL);
2821
2822  /* Insert name in all lowercase.  */
2823  for (p = namebuf; *p; p++)
2824    *p = TOLOWER (*p);
2825
2826  if (strncmp (namebuf, newname, namelen))
2827    insert_neon_reg_alias (namebuf, basereg->number, basetype,
2828			   typeinfo.defined != 0 ? &typeinfo : NULL);
2829
2830  free (namebuf);
2831  return true;
2832}
2833
2834/* Should never be called, as .req goes between the alias and the
2835   register name, not at the beginning of the line.  */
2836
2837static void
2838s_req (int a ATTRIBUTE_UNUSED)
2839{
2840  as_bad (_("invalid syntax for .req directive"));
2841}
2842
2843static void
2844s_dn (int a ATTRIBUTE_UNUSED)
2845{
2846  as_bad (_("invalid syntax for .dn directive"));
2847}
2848
2849static void
2850s_qn (int a ATTRIBUTE_UNUSED)
2851{
2852  as_bad (_("invalid syntax for .qn directive"));
2853}
2854
2855/* The .unreq directive deletes an alias which was previously defined
2856   by .req.  For example:
2857
2858       my_alias .req r11
2859       .unreq my_alias	  */
2860
2861static void
2862s_unreq (int a ATTRIBUTE_UNUSED)
2863{
2864  char * name;
2865  char saved_char;
2866
2867  name = input_line_pointer;
2868
2869  while (*input_line_pointer != 0
2870	 && *input_line_pointer != ' '
2871	 && *input_line_pointer != '\n')
2872    ++input_line_pointer;
2873
2874  saved_char = *input_line_pointer;
2875  *input_line_pointer = 0;
2876
2877  if (!*name)
2878    as_bad (_("invalid syntax for .unreq directive"));
2879  else
2880    {
2881      struct reg_entry *reg
2882	= (struct reg_entry *) str_hash_find (arm_reg_hsh, name);
2883
2884      if (!reg)
2885	as_bad (_("unknown register alias '%s'"), name);
2886      else if (reg->builtin)
2887	as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2888		 name);
2889      else
2890	{
2891	  char * p;
2892	  char * nbuf;
2893
2894	  str_hash_delete (arm_reg_hsh, name);
2895	  free ((char *) reg->name);
2896	  free (reg->neon);
2897	  free (reg);
2898
2899	  /* Also locate the all upper case and all lower case versions.
2900	     Do not complain if we cannot find one or the other as it
2901	     was probably deleted above.  */
2902
2903	  nbuf = strdup (name);
2904	  for (p = nbuf; *p; p++)
2905	    *p = TOUPPER (*p);
2906	  reg = (struct reg_entry *) str_hash_find (arm_reg_hsh, nbuf);
2907	  if (reg)
2908	    {
2909	      str_hash_delete (arm_reg_hsh, nbuf);
2910	      free ((char *) reg->name);
2911	      free (reg->neon);
2912	      free (reg);
2913	    }
2914
2915	  for (p = nbuf; *p; p++)
2916	    *p = TOLOWER (*p);
2917	  reg = (struct reg_entry *) str_hash_find (arm_reg_hsh, nbuf);
2918	  if (reg)
2919	    {
2920	      str_hash_delete (arm_reg_hsh, nbuf);
2921	      free ((char *) reg->name);
2922	      free (reg->neon);
2923	      free (reg);
2924	    }
2925
2926	  free (nbuf);
2927	}
2928    }
2929
2930  *input_line_pointer = saved_char;
2931  demand_empty_rest_of_line ();
2932}
2933
2934/* Directives: Instruction set selection.  */
2935
2936#ifdef OBJ_ELF
2937/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2938   (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2939   Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2940   and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped.  */
2941
2942/* Create a new mapping symbol for the transition to STATE.  */
2943
2944static void
2945make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
2946{
2947  symbolS * symbolP;
2948  const char * symname;
2949  int type;
2950
2951  switch (state)
2952    {
2953    case MAP_DATA:
2954      symname = "$d";
2955      type = BSF_NO_FLAGS;
2956      break;
2957    case MAP_ARM:
2958      symname = "$a";
2959      type = BSF_NO_FLAGS;
2960      break;
2961    case MAP_THUMB:
2962      symname = "$t";
2963      type = BSF_NO_FLAGS;
2964      break;
2965    default:
2966      abort ();
2967    }
2968
2969  symbolP = symbol_new (symname, now_seg, frag, value);
2970  symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2971
2972  switch (state)
2973    {
2974    case MAP_ARM:
2975      THUMB_SET_FUNC (symbolP, 0);
2976      ARM_SET_THUMB (symbolP, 0);
2977      ARM_SET_INTERWORK (symbolP, support_interwork);
2978      break;
2979
2980    case MAP_THUMB:
2981      THUMB_SET_FUNC (symbolP, 1);
2982      ARM_SET_THUMB (symbolP, 1);
2983      ARM_SET_INTERWORK (symbolP, support_interwork);
2984      break;
2985
2986    case MAP_DATA:
2987    default:
2988      break;
2989    }
2990
2991  /* Save the mapping symbols for future reference.  Also check that
2992     we do not place two mapping symbols at the same offset within a
2993     frag.  We'll handle overlap between frags in
2994     check_mapping_symbols.
2995
2996     If .fill or other data filling directive generates zero sized data,
2997     the mapping symbol for the following code will have the same value
2998     as the one generated for the data filling directive.  In this case,
2999     we replace the old symbol with the new one at the same address.  */
3000  if (value == 0)
3001    {
3002      if (frag->tc_frag_data.first_map != NULL)
3003	{
3004	  know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
3005	  symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
3006	}
3007      frag->tc_frag_data.first_map = symbolP;
3008    }
3009  if (frag->tc_frag_data.last_map != NULL)
3010    {
3011      know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
3012      if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
3013	symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
3014    }
3015  frag->tc_frag_data.last_map = symbolP;
3016}
3017
3018/* We must sometimes convert a region marked as code to data during
3019   code alignment, if an odd number of bytes have to be padded.  The
3020   code mapping symbol is pushed to an aligned address.  */
3021
3022static void
3023insert_data_mapping_symbol (enum mstate state,
3024			    valueT value, fragS *frag, offsetT bytes)
3025{
3026  /* If there was already a mapping symbol, remove it.  */
3027  if (frag->tc_frag_data.last_map != NULL
3028      && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
3029    {
3030      symbolS *symp = frag->tc_frag_data.last_map;
3031
3032      if (value == 0)
3033	{
3034	  know (frag->tc_frag_data.first_map == symp);
3035	  frag->tc_frag_data.first_map = NULL;
3036	}
3037      frag->tc_frag_data.last_map = NULL;
3038      symbol_remove (symp, &symbol_rootP, &symbol_lastP);
3039    }
3040
3041  make_mapping_symbol (MAP_DATA, value, frag);
3042  make_mapping_symbol (state, value + bytes, frag);
3043}
3044
3045static void mapping_state_2 (enum mstate state, int max_chars);
3046
3047/* Set the mapping state to STATE.  Only call this when about to
3048   emit some STATE bytes to the file.  */
3049
3050#define TRANSITION(from, to) (mapstate == (from) && state == (to))
3051void
3052mapping_state (enum mstate state)
3053{
3054  enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
3055
3056  if (mapstate == state)
3057    /* The mapping symbol has already been emitted.
3058       There is nothing else to do.  */
3059    return;
3060
3061  if (state == MAP_ARM || state == MAP_THUMB)
3062    /*  PR gas/12931
3063	All ARM instructions require 4-byte alignment.
3064	(Almost) all Thumb instructions require 2-byte alignment.
3065
3066	When emitting instructions into any section, mark the section
3067	appropriately.
3068
3069	Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3070	but themselves require 2-byte alignment; this applies to some
3071	PC- relative forms.  However, these cases will involve implicit
3072	literal pool generation or an explicit .align >=2, both of
3073	which will cause the section to me marked with sufficient
3074	alignment.  Thus, we don't handle those cases here.  */
3075    record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
3076
3077  if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
3078    /* This case will be evaluated later.  */
3079    return;
3080
3081  mapping_state_2 (state, 0);
3082}
3083
3084/* Same as mapping_state, but MAX_CHARS bytes have already been
3085   allocated.  Put the mapping symbol that far back.  */
3086
3087static void
3088mapping_state_2 (enum mstate state, int max_chars)
3089{
3090  enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
3091
3092  if (!SEG_NORMAL (now_seg))
3093    return;
3094
3095  if (mapstate == state)
3096    /* The mapping symbol has already been emitted.
3097       There is nothing else to do.  */
3098    return;
3099
3100  if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
3101	  || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
3102    {
3103      struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
3104      const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
3105
3106      if (add_symbol)
3107	make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
3108    }
3109
3110  seg_info (now_seg)->tc_segment_info_data.mapstate = state;
3111  make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
3112}
3113#undef TRANSITION
3114#else
3115#define mapping_state(x) ((void)0)
3116#define mapping_state_2(x, y) ((void)0)
3117#endif
3118
3119/* Find the real, Thumb encoded start of a Thumb function.  */
3120
3121#ifdef OBJ_COFF
3122static symbolS *
3123find_real_start (symbolS * symbolP)
3124{
3125  char *       real_start;
3126  const char * name = S_GET_NAME (symbolP);
3127  symbolS *    new_target;
3128
3129  /* This definition must agree with the one in gcc/config/arm/thumb.c.	 */
3130#define STUB_NAME ".real_start_of"
3131
3132  if (name == NULL)
3133    abort ();
3134
3135  /* The compiler may generate BL instructions to local labels because
3136     it needs to perform a branch to a far away location. These labels
3137     do not have a corresponding ".real_start_of" label.  We check
3138     both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3139     the ".real_start_of" convention for nonlocal branches.  */
3140  if (S_IS_LOCAL (symbolP) || name[0] == '.')
3141    return symbolP;
3142
3143  real_start = concat (STUB_NAME, name, NULL);
3144  new_target = symbol_find (real_start);
3145  free (real_start);
3146
3147  if (new_target == NULL)
3148    {
3149      as_warn (_("Failed to find real start of function: %s\n"), name);
3150      new_target = symbolP;
3151    }
3152
3153  return new_target;
3154}
3155#endif
3156
3157static void
3158opcode_select (int width)
3159{
3160  switch (width)
3161    {
3162    case 16:
3163      if (! thumb_mode)
3164	{
3165	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
3166	    as_bad (_("selected processor does not support THUMB opcodes"));
3167
3168	  thumb_mode = 1;
3169	  /* No need to force the alignment, since we will have been
3170	     coming from ARM mode, which is word-aligned.  */
3171	  record_alignment (now_seg, 1);
3172	}
3173      break;
3174
3175    case 32:
3176      if (thumb_mode)
3177	{
3178	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
3179	    as_bad (_("selected processor does not support ARM opcodes"));
3180
3181	  thumb_mode = 0;
3182
3183	  if (!need_pass_2)
3184	    frag_align (2, 0, 0);
3185
3186	  record_alignment (now_seg, 1);
3187	}
3188      break;
3189
3190    default:
3191      as_bad (_("invalid instruction size selected (%d)"), width);
3192    }
3193}
3194
3195static void
3196s_arm (int ignore ATTRIBUTE_UNUSED)
3197{
3198  opcode_select (32);
3199  demand_empty_rest_of_line ();
3200}
3201
3202static void
3203s_thumb (int ignore ATTRIBUTE_UNUSED)
3204{
3205  opcode_select (16);
3206  demand_empty_rest_of_line ();
3207}
3208
3209static void
3210s_code (int unused ATTRIBUTE_UNUSED)
3211{
3212  int temp;
3213
3214  temp = get_absolute_expression ();
3215  switch (temp)
3216    {
3217    case 16:
3218    case 32:
3219      opcode_select (temp);
3220      break;
3221
3222    default:
3223      as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
3224    }
3225}
3226
3227static void
3228s_force_thumb (int ignore ATTRIBUTE_UNUSED)
3229{
3230  /* If we are not already in thumb mode go into it, EVEN if
3231     the target processor does not support thumb instructions.
3232     This is used by gcc/config/arm/lib1funcs.asm for example
3233     to compile interworking support functions even if the
3234     target processor should not support interworking.	*/
3235  if (! thumb_mode)
3236    {
3237      thumb_mode = 2;
3238      record_alignment (now_seg, 1);
3239    }
3240
3241  demand_empty_rest_of_line ();
3242}
3243
3244static void
3245s_thumb_func (int ignore ATTRIBUTE_UNUSED)
3246{
3247  s_thumb (0);
3248
3249  /* The following label is the name/address of the start of a Thumb function.
3250     We need to know this for the interworking support.	 */
3251  label_is_thumb_function_name = true;
3252}
3253
3254/* Perform a .set directive, but also mark the alias as
3255   being a thumb function.  */
3256
3257static void
3258s_thumb_set (int equiv)
3259{
3260  /* XXX the following is a duplicate of the code for s_set() in read.c
3261     We cannot just call that code as we need to get at the symbol that
3262     is created.  */
3263  char *    name;
3264  char	    delim;
3265  char *    end_name;
3266  symbolS * symbolP;
3267
3268  /* Especial apologies for the random logic:
3269     This just grew, and could be parsed much more simply!
3270     Dean - in haste.  */
3271  delim	    = get_symbol_name (& name);
3272  end_name  = input_line_pointer;
3273  (void) restore_line_pointer (delim);
3274
3275  if (*input_line_pointer != ',')
3276    {
3277      *end_name = 0;
3278      as_bad (_("expected comma after name \"%s\""), name);
3279      *end_name = delim;
3280      ignore_rest_of_line ();
3281      return;
3282    }
3283
3284  input_line_pointer++;
3285  *end_name = 0;
3286
3287  if (name[0] == '.' && name[1] == '\0')
3288    {
3289      /* XXX - this should not happen to .thumb_set.  */
3290      abort ();
3291    }
3292
3293  if ((symbolP = symbol_find (name)) == NULL
3294      && (symbolP = md_undefined_symbol (name)) == NULL)
3295    {
3296#ifndef NO_LISTING
3297      /* When doing symbol listings, play games with dummy fragments living
3298	 outside the normal fragment chain to record the file and line info
3299	 for this symbol.  */
3300      if (listing & LISTING_SYMBOLS)
3301	{
3302	  extern struct list_info_struct * listing_tail;
3303	  fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
3304
3305	  memset (dummy_frag, 0, sizeof (fragS));
3306	  dummy_frag->fr_type = rs_fill;
3307	  dummy_frag->line = listing_tail;
3308	  symbolP = symbol_new (name, undefined_section, dummy_frag, 0);
3309	  dummy_frag->fr_symbol = symbolP;
3310	}
3311      else
3312#endif
3313	symbolP = symbol_new (name, undefined_section, &zero_address_frag, 0);
3314
3315#ifdef OBJ_COFF
3316      /* "set" symbols are local unless otherwise specified.  */
3317      SF_SET_LOCAL (symbolP);
3318#endif /* OBJ_COFF  */
3319    }				/* Make a new symbol.  */
3320
3321  symbol_table_insert (symbolP);
3322
3323  * end_name = delim;
3324
3325  if (equiv
3326      && S_IS_DEFINED (symbolP)
3327      && S_GET_SEGMENT (symbolP) != reg_section)
3328    as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3329
3330  pseudo_set (symbolP);
3331
3332  demand_empty_rest_of_line ();
3333
3334  /* XXX Now we come to the Thumb specific bit of code.	 */
3335
3336  THUMB_SET_FUNC (symbolP, 1);
3337  ARM_SET_THUMB (symbolP, 1);
3338#if defined OBJ_ELF || defined OBJ_COFF
3339  ARM_SET_INTERWORK (symbolP, support_interwork);
3340#endif
3341}
3342
3343/* Directives: Mode selection.  */
3344
3345/* .syntax [unified|divided] - choose the new unified syntax
3346   (same for Arm and Thumb encoding, modulo slight differences in what
3347   can be represented) or the old divergent syntax for each mode.  */
3348static void
3349s_syntax (int unused ATTRIBUTE_UNUSED)
3350{
3351  char *name, delim;
3352
3353  delim = get_symbol_name (& name);
3354
3355  if (!strcasecmp (name, "unified"))
3356    unified_syntax = true;
3357  else if (!strcasecmp (name, "divided"))
3358    unified_syntax = false;
3359  else
3360    {
3361      as_bad (_("unrecognized syntax mode \"%s\""), name);
3362      return;
3363    }
3364  (void) restore_line_pointer (delim);
3365  demand_empty_rest_of_line ();
3366}
3367
3368/* Directives: sectioning and alignment.  */
3369
3370static void
3371s_bss (int ignore ATTRIBUTE_UNUSED)
3372{
3373  /* We don't support putting frags in the BSS segment, we fake it by
3374     marking in_bss, then looking at s_skip for clues.	*/
3375  subseg_set (bss_section, 0);
3376  demand_empty_rest_of_line ();
3377
3378#ifdef md_elf_section_change_hook
3379  md_elf_section_change_hook ();
3380#endif
3381}
3382
3383static void
3384s_even (int ignore ATTRIBUTE_UNUSED)
3385{
3386  /* Never make frag if expect extra pass.  */
3387  if (!need_pass_2)
3388    frag_align (1, 0, 0);
3389
3390  record_alignment (now_seg, 1);
3391
3392  demand_empty_rest_of_line ();
3393}
3394
3395/* Directives: CodeComposer Studio.  */
3396
3397/*  .ref  (for CodeComposer Studio syntax only).  */
3398static void
3399s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3400{
3401  if (codecomposer_syntax)
3402    ignore_rest_of_line ();
3403  else
3404    as_bad (_(".ref pseudo-op only available with -mccs flag."));
3405}
3406
3407/*  If name is not NULL, then it is used for marking the beginning of a
3408    function, whereas if it is NULL then it means the function end.  */
3409static void
3410asmfunc_debug (const char * name)
3411{
3412  static const char * last_name = NULL;
3413
3414  if (name != NULL)
3415    {
3416      gas_assert (last_name == NULL);
3417      last_name = name;
3418
3419      if (debug_type == DEBUG_STABS)
3420         stabs_generate_asm_func (name, name);
3421    }
3422  else
3423    {
3424      gas_assert (last_name != NULL);
3425
3426      if (debug_type == DEBUG_STABS)
3427        stabs_generate_asm_endfunc (last_name, last_name);
3428
3429      last_name = NULL;
3430    }
3431}
3432
3433static void
3434s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3435{
3436  if (codecomposer_syntax)
3437    {
3438      switch (asmfunc_state)
3439	{
3440	case OUTSIDE_ASMFUNC:
3441	  asmfunc_state = WAITING_ASMFUNC_NAME;
3442	  break;
3443
3444	case WAITING_ASMFUNC_NAME:
3445	  as_bad (_(".asmfunc repeated."));
3446	  break;
3447
3448	case WAITING_ENDASMFUNC:
3449	  as_bad (_(".asmfunc without function."));
3450	  break;
3451	}
3452      demand_empty_rest_of_line ();
3453    }
3454  else
3455    as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3456}
3457
3458static void
3459s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3460{
3461  if (codecomposer_syntax)
3462    {
3463      switch (asmfunc_state)
3464	{
3465	case OUTSIDE_ASMFUNC:
3466	  as_bad (_(".endasmfunc without a .asmfunc."));
3467	  break;
3468
3469	case WAITING_ASMFUNC_NAME:
3470	  as_bad (_(".endasmfunc without function."));
3471	  break;
3472
3473	case WAITING_ENDASMFUNC:
3474	  asmfunc_state = OUTSIDE_ASMFUNC;
3475	  asmfunc_debug (NULL);
3476	  break;
3477	}
3478      demand_empty_rest_of_line ();
3479    }
3480  else
3481    as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3482}
3483
3484static void
3485s_ccs_def (int name)
3486{
3487  if (codecomposer_syntax)
3488    s_globl (name);
3489  else
3490    as_bad (_(".def pseudo-op only available with -mccs flag."));
3491}
3492
3493/* Directives: Literal pools.  */
3494
3495static literal_pool *
3496find_literal_pool (void)
3497{
3498  literal_pool * pool;
3499
3500  for (pool = list_of_pools; pool != NULL; pool = pool->next)
3501    {
3502      if (pool->section == now_seg
3503	  && pool->sub_section == now_subseg)
3504	break;
3505    }
3506
3507  return pool;
3508}
3509
3510static literal_pool *
3511find_or_make_literal_pool (void)
3512{
3513  /* Next literal pool ID number.  */
3514  static unsigned int latest_pool_num = 1;
3515  literal_pool *      pool;
3516
3517  pool = find_literal_pool ();
3518
3519  if (pool == NULL)
3520    {
3521      /* Create a new pool.  */
3522      pool = XNEW (literal_pool);
3523      if (! pool)
3524	return NULL;
3525
3526      pool->next_free_entry = 0;
3527      pool->section	    = now_seg;
3528      pool->sub_section	    = now_subseg;
3529      pool->next	    = list_of_pools;
3530      pool->symbol	    = NULL;
3531      pool->alignment	    = 2;
3532
3533      /* Add it to the list.  */
3534      list_of_pools = pool;
3535    }
3536
3537  /* New pools, and emptied pools, will have a NULL symbol.  */
3538  if (pool->symbol == NULL)
3539    {
3540      pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3541				    &zero_address_frag, 0);
3542      pool->id = latest_pool_num ++;
3543    }
3544
3545  /* Done.  */
3546  return pool;
3547}
3548
3549/* Add the literal in the global 'inst'
3550   structure to the relevant literal pool.  */
3551
3552static int
3553add_to_lit_pool (unsigned int nbytes)
3554{
3555#define PADDING_SLOT 0x1
3556#define LIT_ENTRY_SIZE_MASK 0xFF
3557  literal_pool * pool;
3558  unsigned int entry, pool_size = 0;
3559  bool padding_slot_p = false;
3560  unsigned imm1 = 0;
3561  unsigned imm2 = 0;
3562
3563  if (nbytes == 8)
3564    {
3565      imm1 = inst.operands[1].imm;
3566      imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3567	       : inst.relocs[0].exp.X_unsigned ? 0
3568	       : (int64_t) inst.operands[1].imm >> 32);
3569      if (target_big_endian)
3570	{
3571	  imm1 = imm2;
3572	  imm2 = inst.operands[1].imm;
3573	}
3574    }
3575
3576  pool = find_or_make_literal_pool ();
3577
3578  /* Check if this literal value is already in the pool.  */
3579  for (entry = 0; entry < pool->next_free_entry; entry ++)
3580    {
3581      if (nbytes == 4)
3582	{
3583	  if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3584	      && (inst.relocs[0].exp.X_op == O_constant)
3585	      && (pool->literals[entry].X_add_number
3586		  == inst.relocs[0].exp.X_add_number)
3587	      && (pool->literals[entry].X_md == nbytes)
3588	      && (pool->literals[entry].X_unsigned
3589		  == inst.relocs[0].exp.X_unsigned))
3590	    break;
3591
3592	  if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3593	      && (inst.relocs[0].exp.X_op == O_symbol)
3594	      && (pool->literals[entry].X_add_number
3595		  == inst.relocs[0].exp.X_add_number)
3596	      && (pool->literals[entry].X_add_symbol
3597		  == inst.relocs[0].exp.X_add_symbol)
3598	      && (pool->literals[entry].X_op_symbol
3599		  == inst.relocs[0].exp.X_op_symbol)
3600	      && (pool->literals[entry].X_md == nbytes))
3601	    break;
3602	}
3603      else if ((nbytes == 8)
3604	       && !(pool_size & 0x7)
3605	       && ((entry + 1) != pool->next_free_entry)
3606	       && (pool->literals[entry].X_op == O_constant)
3607	       && (pool->literals[entry].X_add_number == (offsetT) imm1)
3608	       && (pool->literals[entry].X_unsigned
3609		   == inst.relocs[0].exp.X_unsigned)
3610	       && (pool->literals[entry + 1].X_op == O_constant)
3611	       && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
3612	       && (pool->literals[entry + 1].X_unsigned
3613		   == inst.relocs[0].exp.X_unsigned))
3614	break;
3615
3616      padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3617      if (padding_slot_p && (nbytes == 4))
3618	break;
3619
3620      pool_size += 4;
3621    }
3622
3623  /* Do we need to create a new entry?	*/
3624  if (entry == pool->next_free_entry)
3625    {
3626      if (entry >= MAX_LITERAL_POOL_SIZE)
3627	{
3628	  inst.error = _("literal pool overflow");
3629	  return FAIL;
3630	}
3631
3632      if (nbytes == 8)
3633	{
3634	  /* For 8-byte entries, we align to an 8-byte boundary,
3635	     and split it into two 4-byte entries, because on 32-bit
3636	     host, 8-byte constants are treated as big num, thus
3637	     saved in "generic_bignum" which will be overwritten
3638	     by later assignments.
3639
3640	     We also need to make sure there is enough space for
3641	     the split.
3642
3643	     We also check to make sure the literal operand is a
3644	     constant number.  */
3645	  if (!(inst.relocs[0].exp.X_op == O_constant
3646		|| inst.relocs[0].exp.X_op == O_big))
3647	    {
3648	      inst.error = _("invalid type for literal pool");
3649	      return FAIL;
3650	    }
3651	  else if (pool_size & 0x7)
3652	    {
3653	      if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3654		{
3655		  inst.error = _("literal pool overflow");
3656		  return FAIL;
3657		}
3658
3659	      pool->literals[entry] = inst.relocs[0].exp;
3660	      pool->literals[entry].X_op = O_constant;
3661	      pool->literals[entry].X_add_number = 0;
3662	      pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3663	      pool->next_free_entry += 1;
3664	      pool_size += 4;
3665	    }
3666	  else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3667	    {
3668	      inst.error = _("literal pool overflow");
3669	      return FAIL;
3670	    }
3671
3672	  pool->literals[entry] = inst.relocs[0].exp;
3673	  pool->literals[entry].X_op = O_constant;
3674	  pool->literals[entry].X_add_number = imm1;
3675	  pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3676	  pool->literals[entry++].X_md = 4;
3677	  pool->literals[entry] = inst.relocs[0].exp;
3678	  pool->literals[entry].X_op = O_constant;
3679	  pool->literals[entry].X_add_number = imm2;
3680	  pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
3681	  pool->literals[entry].X_md = 4;
3682	  pool->alignment = 3;
3683	  pool->next_free_entry += 1;
3684	}
3685      else
3686	{
3687	  pool->literals[entry] = inst.relocs[0].exp;
3688	  pool->literals[entry].X_md = 4;
3689	}
3690
3691#ifdef OBJ_ELF
3692      /* PR ld/12974: Record the location of the first source line to reference
3693	 this entry in the literal pool.  If it turns out during linking that the
3694	 symbol does not exist we will be able to give an accurate line number for
3695	 the (first use of the) missing reference.  */
3696      if (debug_type == DEBUG_DWARF2)
3697	dwarf2_where (pool->locs + entry);
3698#endif
3699      pool->next_free_entry += 1;
3700    }
3701  else if (padding_slot_p)
3702    {
3703      pool->literals[entry] = inst.relocs[0].exp;
3704      pool->literals[entry].X_md = nbytes;
3705    }
3706
3707  inst.relocs[0].exp.X_op	      = O_symbol;
3708  inst.relocs[0].exp.X_add_number = pool_size;
3709  inst.relocs[0].exp.X_add_symbol = pool->symbol;
3710
3711  return SUCCESS;
3712}
3713
3714bool
3715tc_start_label_without_colon (void)
3716{
3717  bool ret = true;
3718
3719  if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3720    {
3721      const char *label = input_line_pointer;
3722
3723      while (!is_end_of_line[(int) label[-1]])
3724	--label;
3725
3726      if (*label == '.')
3727	{
3728	  as_bad (_("Invalid label '%s'"), label);
3729	  ret = false;
3730	}
3731
3732      asmfunc_debug (label);
3733
3734      asmfunc_state = WAITING_ENDASMFUNC;
3735    }
3736
3737  return ret;
3738}
3739
3740/* Can't use symbol_new here, so have to create a symbol and then at
3741   a later date assign it a value. That's what these functions do.  */
3742
3743static void
3744symbol_locate (symbolS *    symbolP,
3745	       const char * name,	/* It is copied, the caller can modify.	 */
3746	       segT	    segment,	/* Segment identifier (SEG_<something>).  */
3747	       valueT	    valu,	/* Symbol value.  */
3748	       fragS *	    frag)	/* Associated fragment.	 */
3749{
3750  size_t name_length;
3751  char * preserved_copy_of_name;
3752
3753  name_length = strlen (name) + 1;   /* +1 for \0.  */
3754  obstack_grow (&notes, name, name_length);
3755  preserved_copy_of_name = (char *) obstack_finish (&notes);
3756
3757#ifdef tc_canonicalize_symbol_name
3758  preserved_copy_of_name =
3759    tc_canonicalize_symbol_name (preserved_copy_of_name);
3760#endif
3761
3762  S_SET_NAME (symbolP, preserved_copy_of_name);
3763
3764  S_SET_SEGMENT (symbolP, segment);
3765  S_SET_VALUE (symbolP, valu);
3766  symbol_clear_list_pointers (symbolP);
3767
3768  symbol_set_frag (symbolP, frag);
3769
3770  /* Link to end of symbol chain.  */
3771  {
3772    extern int symbol_table_frozen;
3773
3774    if (symbol_table_frozen)
3775      abort ();
3776  }
3777
3778  symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
3779
3780  obj_symbol_new_hook (symbolP);
3781
3782#ifdef tc_symbol_new_hook
3783  tc_symbol_new_hook (symbolP);
3784#endif
3785
3786#ifdef DEBUG_SYMS
3787  verify_symbol_chain (symbol_rootP, symbol_lastP);
3788#endif /* DEBUG_SYMS  */
3789}
3790
3791static void
3792s_ltorg (int ignored ATTRIBUTE_UNUSED)
3793{
3794  unsigned int entry;
3795  literal_pool * pool;
3796  char sym_name[20];
3797
3798  pool = find_literal_pool ();
3799  if (pool == NULL
3800      || pool->symbol == NULL
3801      || pool->next_free_entry == 0)
3802    return;
3803
3804  /* Align pool as you have word accesses.
3805     Only make a frag if we have to.  */
3806  if (!need_pass_2)
3807    frag_align (pool->alignment, 0, 0);
3808
3809  record_alignment (now_seg, 2);
3810
3811#ifdef OBJ_ELF
3812  seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3813  make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
3814#endif
3815  sprintf (sym_name, "$$lit_\002%x", pool->id);
3816
3817  symbol_locate (pool->symbol, sym_name, now_seg,
3818		 (valueT) frag_now_fix (), frag_now);
3819  symbol_table_insert (pool->symbol);
3820
3821  ARM_SET_THUMB (pool->symbol, thumb_mode);
3822
3823#if defined OBJ_COFF || defined OBJ_ELF
3824  ARM_SET_INTERWORK (pool->symbol, support_interwork);
3825#endif
3826
3827  for (entry = 0; entry < pool->next_free_entry; entry ++)
3828    {
3829#ifdef OBJ_ELF
3830      if (debug_type == DEBUG_DWARF2)
3831	dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3832#endif
3833      /* First output the expression in the instruction to the pool.  */
3834      emit_expr (&(pool->literals[entry]),
3835		 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
3836    }
3837
3838  /* Mark the pool as empty.  */
3839  pool->next_free_entry = 0;
3840  pool->symbol = NULL;
3841}
3842
3843#ifdef OBJ_ELF
3844/* Forward declarations for functions below, in the MD interface
3845   section.  */
3846static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3847static valueT create_unwind_entry (int);
3848static void start_unwind_section (const segT, int);
3849static void add_unwind_opcode (valueT, int);
3850static void flush_pending_unwind (void);
3851
3852/* Directives: Data.  */
3853
3854static void
3855s_arm_elf_cons (int nbytes)
3856{
3857  expressionS exp;
3858
3859#ifdef md_flush_pending_output
3860  md_flush_pending_output ();
3861#endif
3862
3863  if (is_it_end_of_statement ())
3864    {
3865      demand_empty_rest_of_line ();
3866      return;
3867    }
3868
3869#ifdef md_cons_align
3870  md_cons_align (nbytes);
3871#endif
3872
3873  mapping_state (MAP_DATA);
3874  do
3875    {
3876      int reloc;
3877      char *base = input_line_pointer;
3878
3879      expression (& exp);
3880
3881      if (exp.X_op != O_symbol)
3882	emit_expr (&exp, (unsigned int) nbytes);
3883      else
3884	{
3885	  char *before_reloc = input_line_pointer;
3886	  reloc = parse_reloc (&input_line_pointer);
3887	  if (reloc == -1)
3888	    {
3889	      as_bad (_("unrecognized relocation suffix"));
3890	      ignore_rest_of_line ();
3891	      return;
3892	    }
3893	  else if (reloc == BFD_RELOC_UNUSED)
3894	    emit_expr (&exp, (unsigned int) nbytes);
3895	  else
3896	    {
3897	      reloc_howto_type *howto = (reloc_howto_type *)
3898		  bfd_reloc_type_lookup (stdoutput,
3899					 (bfd_reloc_code_real_type) reloc);
3900	      int size = bfd_get_reloc_size (howto);
3901
3902	      if (reloc == BFD_RELOC_ARM_PLT32)
3903		{
3904		  as_bad (_("(plt) is only valid on branch targets"));
3905		  reloc = BFD_RELOC_UNUSED;
3906		  size = 0;
3907		}
3908
3909	      if (size > nbytes)
3910		as_bad (ngettext ("%s relocations do not fit in %d byte",
3911				  "%s relocations do not fit in %d bytes",
3912				  nbytes),
3913			howto->name, nbytes);
3914	      else
3915		{
3916		  /* We've parsed an expression stopping at O_symbol.
3917		     But there may be more expression left now that we
3918		     have parsed the relocation marker.  Parse it again.
3919		     XXX Surely there is a cleaner way to do this.  */
3920		  char *p = input_line_pointer;
3921		  int offset;
3922		  char *save_buf = XNEWVEC (char, input_line_pointer - base);
3923
3924		  memcpy (save_buf, base, input_line_pointer - base);
3925		  memmove (base + (input_line_pointer - before_reloc),
3926			   base, before_reloc - base);
3927
3928		  input_line_pointer = base + (input_line_pointer-before_reloc);
3929		  expression (&exp);
3930		  memcpy (base, save_buf, p - base);
3931
3932		  offset = nbytes - size;
3933		  p = frag_more (nbytes);
3934		  memset (p, 0, nbytes);
3935		  fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
3936			       size, &exp, 0, (enum bfd_reloc_code_real) reloc);
3937		  free (save_buf);
3938		}
3939	    }
3940	}
3941    }
3942  while (*input_line_pointer++ == ',');
3943
3944  /* Put terminator back into stream.  */
3945  input_line_pointer --;
3946  demand_empty_rest_of_line ();
3947}
3948
3949/* Emit an expression containing a 32-bit thumb instruction.
3950   Implementation based on put_thumb32_insn.  */
3951
3952static void
3953emit_thumb32_expr (expressionS * exp)
3954{
3955  expressionS exp_high = *exp;
3956
3957  exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3958  emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3959  exp->X_add_number &= 0xffff;
3960  emit_expr (exp, (unsigned int) THUMB_SIZE);
3961}
3962
3963/*  Guess the instruction size based on the opcode.  */
3964
3965static int
3966thumb_insn_size (int opcode)
3967{
3968  if ((unsigned int) opcode < 0xe800u)
3969    return 2;
3970  else if ((unsigned int) opcode >= 0xe8000000u)
3971    return 4;
3972  else
3973    return 0;
3974}
3975
3976static bool
3977emit_insn (expressionS *exp, int nbytes)
3978{
3979  int size = 0;
3980
3981  if (exp->X_op == O_constant)
3982    {
3983      size = nbytes;
3984
3985      if (size == 0)
3986	size = thumb_insn_size (exp->X_add_number);
3987
3988      if (size != 0)
3989	{
3990	  if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3991	    {
3992	      as_bad (_(".inst.n operand too big. "\
3993			"Use .inst.w instead"));
3994	      size = 0;
3995	    }
3996	  else
3997	    {
3998	      if (now_pred.state == AUTOMATIC_PRED_BLOCK)
3999		set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0);
4000	      else
4001		set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
4002
4003	      if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
4004		emit_thumb32_expr (exp);
4005	      else
4006		emit_expr (exp, (unsigned int) size);
4007
4008	      it_fsm_post_encode ();
4009	    }
4010	}
4011      else
4012	as_bad (_("cannot determine Thumb instruction size. "	\
4013		  "Use .inst.n/.inst.w instead"));
4014    }
4015  else
4016    as_bad (_("constant expression required"));
4017
4018  return (size != 0);
4019}
4020
4021/* Like s_arm_elf_cons but do not use md_cons_align and
4022   set the mapping state to MAP_ARM/MAP_THUMB.  */
4023
4024static void
4025s_arm_elf_inst (int nbytes)
4026{
4027  if (is_it_end_of_statement ())
4028    {
4029      demand_empty_rest_of_line ();
4030      return;
4031    }
4032
4033  /* Calling mapping_state () here will not change ARM/THUMB,
4034     but will ensure not to be in DATA state.  */
4035
4036  if (thumb_mode)
4037    mapping_state (MAP_THUMB);
4038  else
4039    {
4040      if (nbytes != 0)
4041	{
4042	  as_bad (_("width suffixes are invalid in ARM mode"));
4043	  ignore_rest_of_line ();
4044	  return;
4045	}
4046
4047      nbytes = 4;
4048
4049      mapping_state (MAP_ARM);
4050    }
4051
4052  dwarf2_emit_insn (0);
4053
4054  do
4055    {
4056      expressionS exp;
4057
4058      expression (& exp);
4059
4060      if (! emit_insn (& exp, nbytes))
4061	{
4062	  ignore_rest_of_line ();
4063	  return;
4064	}
4065    }
4066  while (*input_line_pointer++ == ',');
4067
4068  /* Put terminator back into stream.  */
4069  input_line_pointer --;
4070  demand_empty_rest_of_line ();
4071}
4072
4073/* Parse a .rel31 directive.  */
4074
4075static void
4076s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
4077{
4078  expressionS exp;
4079  char *p;
4080  valueT highbit;
4081
4082  highbit = 0;
4083  if (*input_line_pointer == '1')
4084    highbit = 0x80000000;
4085  else if (*input_line_pointer != '0')
4086    as_bad (_("expected 0 or 1"));
4087
4088  input_line_pointer++;
4089  if (*input_line_pointer != ',')
4090    as_bad (_("missing comma"));
4091  input_line_pointer++;
4092
4093#ifdef md_flush_pending_output
4094  md_flush_pending_output ();
4095#endif
4096
4097#ifdef md_cons_align
4098  md_cons_align (4);
4099#endif
4100
4101  mapping_state (MAP_DATA);
4102
4103  expression (&exp);
4104
4105  p = frag_more (4);
4106  md_number_to_chars (p, highbit, 4);
4107  fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
4108	       BFD_RELOC_ARM_PREL31);
4109
4110  demand_empty_rest_of_line ();
4111}
4112
4113/* Directives: AEABI stack-unwind tables.  */
4114
4115/* Parse an unwind_fnstart directive.  Simply records the current location.  */
4116
4117static void
4118s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
4119{
4120  demand_empty_rest_of_line ();
4121  if (unwind.proc_start)
4122    {
4123      as_bad (_("duplicate .fnstart directive"));
4124      return;
4125    }
4126
4127  /* Mark the start of the function.  */
4128  unwind.proc_start = expr_build_dot ();
4129
4130  /* Reset the rest of the unwind info.	 */
4131  unwind.opcode_count = 0;
4132  unwind.table_entry = NULL;
4133  unwind.personality_routine = NULL;
4134  unwind.personality_index = -1;
4135  unwind.frame_size = 0;
4136  unwind.fp_offset = 0;
4137  unwind.fp_reg = REG_SP;
4138  unwind.fp_used = 0;
4139  unwind.sp_restored = 0;
4140}
4141
4142
4143/* Parse a handlerdata directive.  Creates the exception handling table entry
4144   for the function.  */
4145
4146static void
4147s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
4148{
4149  demand_empty_rest_of_line ();
4150  if (!unwind.proc_start)
4151    as_bad (MISSING_FNSTART);
4152
4153  if (unwind.table_entry)
4154    as_bad (_("duplicate .handlerdata directive"));
4155
4156  create_unwind_entry (1);
4157}
4158
4159/* Parse an unwind_fnend directive.  Generates the index table entry.  */
4160
4161static void
4162s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
4163{
4164  long where;
4165  char *ptr;
4166  valueT val;
4167  unsigned int marked_pr_dependency;
4168
4169  demand_empty_rest_of_line ();
4170
4171  if (!unwind.proc_start)
4172    {
4173      as_bad (_(".fnend directive without .fnstart"));
4174      return;
4175    }
4176
4177  /* Add eh table entry.  */
4178  if (unwind.table_entry == NULL)
4179    val = create_unwind_entry (0);
4180  else
4181    val = 0;
4182
4183  /* Add index table entry.  This is two words.	 */
4184  start_unwind_section (unwind.saved_seg, 1);
4185  frag_align (2, 0, 0);
4186  record_alignment (now_seg, 2);
4187
4188  ptr = frag_more (8);
4189  memset (ptr, 0, 8);
4190  where = frag_now_fix () - 8;
4191
4192  /* Self relative offset of the function start.  */
4193  fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
4194	   BFD_RELOC_ARM_PREL31);
4195
4196  /* Indicate dependency on EHABI-defined personality routines to the
4197     linker, if it hasn't been done already.  */
4198  marked_pr_dependency
4199    = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
4200  if (unwind.personality_index >= 0 && unwind.personality_index < 3
4201      && !(marked_pr_dependency & (1 << unwind.personality_index)))
4202    {
4203      static const char *const name[] =
4204	{
4205	  "__aeabi_unwind_cpp_pr0",
4206	  "__aeabi_unwind_cpp_pr1",
4207	  "__aeabi_unwind_cpp_pr2"
4208	};
4209      symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
4210      fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
4211      seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
4212	|= 1 << unwind.personality_index;
4213    }
4214
4215  if (val)
4216    /* Inline exception table entry.  */
4217    md_number_to_chars (ptr + 4, val, 4);
4218  else
4219    /* Self relative offset of the table entry.	 */
4220    fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
4221	     BFD_RELOC_ARM_PREL31);
4222
4223  /* Restore the original section.  */
4224  subseg_set (unwind.saved_seg, unwind.saved_subseg);
4225
4226  unwind.proc_start = NULL;
4227}
4228
4229
4230/* Parse an unwind_cantunwind directive.  */
4231
4232static void
4233s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
4234{
4235  demand_empty_rest_of_line ();
4236  if (!unwind.proc_start)
4237    as_bad (MISSING_FNSTART);
4238
4239  if (unwind.personality_routine || unwind.personality_index != -1)
4240    as_bad (_("personality routine specified for cantunwind frame"));
4241
4242  unwind.personality_index = -2;
4243}
4244
4245
4246/* Parse a personalityindex directive.	*/
4247
4248static void
4249s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
4250{
4251  expressionS exp;
4252
4253  if (!unwind.proc_start)
4254    as_bad (MISSING_FNSTART);
4255
4256  if (unwind.personality_routine || unwind.personality_index != -1)
4257    as_bad (_("duplicate .personalityindex directive"));
4258
4259  expression (&exp);
4260
4261  if (exp.X_op != O_constant
4262      || exp.X_add_number < 0 || exp.X_add_number > 15)
4263    {
4264      as_bad (_("bad personality routine number"));
4265      ignore_rest_of_line ();
4266      return;
4267    }
4268
4269  unwind.personality_index = exp.X_add_number;
4270
4271  demand_empty_rest_of_line ();
4272}
4273
4274
4275/* Parse a personality directive.  */
4276
4277static void
4278s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
4279{
4280  char *name, *p, c;
4281
4282  if (!unwind.proc_start)
4283    as_bad (MISSING_FNSTART);
4284
4285  if (unwind.personality_routine || unwind.personality_index != -1)
4286    as_bad (_("duplicate .personality directive"));
4287
4288  c = get_symbol_name (& name);
4289  p = input_line_pointer;
4290  if (c == '"')
4291    ++ input_line_pointer;
4292  unwind.personality_routine = symbol_find_or_make (name);
4293  *p = c;
4294  demand_empty_rest_of_line ();
4295}
4296
4297/* Parse a directive saving pseudo registers.  */
4298
4299static void
4300s_arm_unwind_save_pseudo (long range)
4301{
4302  valueT op;
4303
4304  if (range & (1 << 12))
4305    {
4306      /* Opcode for restoring RA_AUTH_CODE.  */
4307      op = 0xb4;
4308      add_unwind_opcode (op, 1);
4309    }
4310}
4311
4312
4313/* Parse a directive saving core registers.  */
4314
4315static void
4316s_arm_unwind_save_core (long range)
4317{
4318  valueT op;
4319  int n;
4320
4321  /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4322     into .unwind_save {..., sp...}.  We aren't bothered about the value of
4323     ip because it is clobbered by calls.  */
4324  if (unwind.sp_restored && unwind.fp_reg == 12
4325      && (range & 0x3000) == 0x1000)
4326    {
4327      unwind.opcode_count--;
4328      unwind.sp_restored = 0;
4329      range = (range | 0x2000) & ~0x1000;
4330      unwind.pending_offset = 0;
4331    }
4332
4333  /* Pop r4-r15.  */
4334  if (range & 0xfff0)
4335    {
4336      /* See if we can use the short opcodes.  These pop a block of up to 8
4337	 registers starting with r4, plus maybe r14.  */
4338      for (n = 0; n < 8; n++)
4339	{
4340	  /* Break at the first non-saved register.	 */
4341	  if ((range & (1 << (n + 4))) == 0)
4342	    break;
4343	}
4344      /* See if there are any other bits set.  */
4345      if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4346	{
4347	  /* Use the long form.  */
4348	  op = 0x8000 | ((range >> 4) & 0xfff);
4349	  add_unwind_opcode (op, 2);
4350	}
4351      else
4352	{
4353	  /* Use the short form.  */
4354	  if (range & 0x4000)
4355	    op = 0xa8; /* Pop r14.	*/
4356	  else
4357	    op = 0xa0; /* Do not pop r14.  */
4358	  op |= (n - 1);
4359	  add_unwind_opcode (op, 1);
4360	}
4361    }
4362
4363  /* Pop r0-r3.	 */
4364  if (range & 0xf)
4365    {
4366      op = 0xb100 | (range & 0xf);
4367      add_unwind_opcode (op, 2);
4368    }
4369
4370  /* Record the number of bytes pushed.	 */
4371  for (n = 0; n < 16; n++)
4372    {
4373      if (range & (1 << n))
4374	unwind.frame_size += 4;
4375    }
4376}
4377
4378
4379/* Parse a directive saving FPA registers.  */
4380
4381static void
4382s_arm_unwind_save_fpa (int reg)
4383{
4384  expressionS exp;
4385  int num_regs;
4386  valueT op;
4387
4388  /* Get Number of registers to transfer.  */
4389  if (skip_past_comma (&input_line_pointer) != FAIL)
4390    expression (&exp);
4391  else
4392    exp.X_op = O_illegal;
4393
4394  if (exp.X_op != O_constant)
4395    {
4396      as_bad (_("expected , <constant>"));
4397      ignore_rest_of_line ();
4398      return;
4399    }
4400
4401  num_regs = exp.X_add_number;
4402
4403  if (num_regs < 1 || num_regs > 4)
4404    {
4405      as_bad (_("number of registers must be in the range [1:4]"));
4406      ignore_rest_of_line ();
4407      return;
4408    }
4409
4410  demand_empty_rest_of_line ();
4411
4412  if (reg == 4)
4413    {
4414      /* Short form.  */
4415      op = 0xb4 | (num_regs - 1);
4416      add_unwind_opcode (op, 1);
4417    }
4418  else
4419    {
4420      /* Long form.  */
4421      op = 0xc800 | (reg << 4) | (num_regs - 1);
4422      add_unwind_opcode (op, 2);
4423    }
4424  unwind.frame_size += num_regs * 12;
4425}
4426
4427
4428/* Parse a directive saving VFP registers for ARMv6 and above.  */
4429
4430static void
4431s_arm_unwind_save_vfp_armv6 (void)
4432{
4433  int count;
4434  unsigned int start;
4435  valueT op;
4436  int num_vfpv3_regs = 0;
4437  int num_regs_below_16;
4438  bool partial_match;
4439
4440  count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
4441			      &partial_match);
4442  if (count == FAIL)
4443    {
4444      as_bad (_("expected register list"));
4445      ignore_rest_of_line ();
4446      return;
4447    }
4448
4449  demand_empty_rest_of_line ();
4450
4451  /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4452     than FSTMX/FLDMX-style ones).  */
4453
4454  /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31.  */
4455  if (start >= 16)
4456    num_vfpv3_regs = count;
4457  else if (start + count > 16)
4458    num_vfpv3_regs = start + count - 16;
4459
4460  if (num_vfpv3_regs > 0)
4461    {
4462      int start_offset = start > 16 ? start - 16 : 0;
4463      op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4464      add_unwind_opcode (op, 2);
4465    }
4466
4467  /* Generate opcode for registers numbered in the range 0 .. 15.  */
4468  num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
4469  gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
4470  if (num_regs_below_16 > 0)
4471    {
4472      op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4473      add_unwind_opcode (op, 2);
4474    }
4475
4476  unwind.frame_size += count * 8;
4477}
4478
4479
4480/* Parse a directive saving VFP registers for pre-ARMv6.  */
4481
4482static void
4483s_arm_unwind_save_vfp (void)
4484{
4485  int count;
4486  unsigned int reg;
4487  valueT op;
4488  bool partial_match;
4489
4490  count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D,
4491			      &partial_match);
4492  if (count == FAIL)
4493    {
4494      as_bad (_("expected register list"));
4495      ignore_rest_of_line ();
4496      return;
4497    }
4498
4499  demand_empty_rest_of_line ();
4500
4501  if (reg == 8)
4502    {
4503      /* Short form.  */
4504      op = 0xb8 | (count - 1);
4505      add_unwind_opcode (op, 1);
4506    }
4507  else
4508    {
4509      /* Long form.  */
4510      op = 0xb300 | (reg << 4) | (count - 1);
4511      add_unwind_opcode (op, 2);
4512    }
4513  unwind.frame_size += count * 8 + 4;
4514}
4515
4516
4517/* Parse a directive saving iWMMXt data registers.  */
4518
4519static void
4520s_arm_unwind_save_mmxwr (void)
4521{
4522  int reg;
4523  int hi_reg;
4524  int i;
4525  unsigned mask = 0;
4526  valueT op;
4527
4528  if (*input_line_pointer == '{')
4529    input_line_pointer++;
4530
4531  do
4532    {
4533      reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4534
4535      if (reg == FAIL)
4536	{
4537	  as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4538	  goto error;
4539	}
4540
4541      if (mask >> reg)
4542	as_tsktsk (_("register list not in ascending order"));
4543      mask |= 1 << reg;
4544
4545      if (*input_line_pointer == '-')
4546	{
4547	  input_line_pointer++;
4548	  hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
4549	  if (hi_reg == FAIL)
4550	    {
4551	      as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
4552	      goto error;
4553	    }
4554	  else if (reg >= hi_reg)
4555	    {
4556	      as_bad (_("bad register range"));
4557	      goto error;
4558	    }
4559	  for (; reg < hi_reg; reg++)
4560	    mask |= 1 << reg;
4561	}
4562    }
4563  while (skip_past_comma (&input_line_pointer) != FAIL);
4564
4565  skip_past_char (&input_line_pointer, '}');
4566
4567  demand_empty_rest_of_line ();
4568
4569  /* Generate any deferred opcodes because we're going to be looking at
4570     the list.	*/
4571  flush_pending_unwind ();
4572
4573  for (i = 0; i < 16; i++)
4574    {
4575      if (mask & (1 << i))
4576	unwind.frame_size += 8;
4577    }
4578
4579  /* Attempt to combine with a previous opcode.	 We do this because gcc
4580     likes to output separate unwind directives for a single block of
4581     registers.	 */
4582  if (unwind.opcode_count > 0)
4583    {
4584      i = unwind.opcodes[unwind.opcode_count - 1];
4585      if ((i & 0xf8) == 0xc0)
4586	{
4587	  i &= 7;
4588	  /* Only merge if the blocks are contiguous.  */
4589	  if (i < 6)
4590	    {
4591	      if ((mask & 0xfe00) == (1 << 9))
4592		{
4593		  mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4594		  unwind.opcode_count--;
4595		}
4596	    }
4597	  else if (i == 6 && unwind.opcode_count >= 2)
4598	    {
4599	      i = unwind.opcodes[unwind.opcode_count - 2];
4600	      reg = i >> 4;
4601	      i &= 0xf;
4602
4603	      op = 0xffff << (reg - 1);
4604	      if (reg > 0
4605		  && ((mask & op) == (1u << (reg - 1))))
4606		{
4607		  op = (1 << (reg + i + 1)) - 1;
4608		  op &= ~((1 << reg) - 1);
4609		  mask |= op;
4610		  unwind.opcode_count -= 2;
4611		}
4612	    }
4613	}
4614    }
4615
4616  hi_reg = 15;
4617  /* We want to generate opcodes in the order the registers have been
4618     saved, ie. descending order.  */
4619  for (reg = 15; reg >= -1; reg--)
4620    {
4621      /* Save registers in blocks.  */
4622      if (reg < 0
4623	  || !(mask & (1 << reg)))
4624	{
4625	  /* We found an unsaved reg.  Generate opcodes to save the
4626	     preceding block.	*/
4627	  if (reg != hi_reg)
4628	    {
4629	      if (reg == 9)
4630		{
4631		  /* Short form.  */
4632		  op = 0xc0 | (hi_reg - 10);
4633		  add_unwind_opcode (op, 1);
4634		}
4635	      else
4636		{
4637		  /* Long form.	 */
4638		  op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4639		  add_unwind_opcode (op, 2);
4640		}
4641	    }
4642	  hi_reg = reg - 1;
4643	}
4644    }
4645
4646  return;
4647 error:
4648  ignore_rest_of_line ();
4649}
4650
4651static void
4652s_arm_unwind_save_mmxwcg (void)
4653{
4654  int reg;
4655  int hi_reg;
4656  unsigned mask = 0;
4657  valueT op;
4658
4659  if (*input_line_pointer == '{')
4660    input_line_pointer++;
4661
4662  skip_whitespace (input_line_pointer);
4663
4664  do
4665    {
4666      reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4667
4668      if (reg == FAIL)
4669	{
4670	  as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4671	  goto error;
4672	}
4673
4674      reg -= 8;
4675      if (mask >> reg)
4676	as_tsktsk (_("register list not in ascending order"));
4677      mask |= 1 << reg;
4678
4679      if (*input_line_pointer == '-')
4680	{
4681	  input_line_pointer++;
4682	  hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
4683	  if (hi_reg == FAIL)
4684	    {
4685	      as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
4686	      goto error;
4687	    }
4688	  else if (reg >= hi_reg)
4689	    {
4690	      as_bad (_("bad register range"));
4691	      goto error;
4692	    }
4693	  for (; reg < hi_reg; reg++)
4694	    mask |= 1 << reg;
4695	}
4696    }
4697  while (skip_past_comma (&input_line_pointer) != FAIL);
4698
4699  skip_past_char (&input_line_pointer, '}');
4700
4701  demand_empty_rest_of_line ();
4702
4703  /* Generate any deferred opcodes because we're going to be looking at
4704     the list.	*/
4705  flush_pending_unwind ();
4706
4707  for (reg = 0; reg < 16; reg++)
4708    {
4709      if (mask & (1 << reg))
4710	unwind.frame_size += 4;
4711    }
4712  op = 0xc700 | mask;
4713  add_unwind_opcode (op, 2);
4714  return;
4715 error:
4716  ignore_rest_of_line ();
4717}
4718
4719/* Convert range and mask_range into a sequence of s_arm_unwind_core
4720   and s_arm_unwind_pseudo operations.  We assume that mask_range will
4721   not have consecutive bits set, or that one operation per bit is
4722   acceptable.  */
4723
4724static void
4725s_arm_unwind_save_mixed (long range, long mask_range)
4726{
4727  while (mask_range)
4728    {
4729      long mask_bit = mask_range & -mask_range;
4730      long subrange = range & (mask_bit - 1);
4731
4732      if (subrange)
4733	s_arm_unwind_save_core (subrange);
4734
4735      s_arm_unwind_save_pseudo (mask_bit);
4736      range &= ~subrange;
4737      mask_range &= ~mask_bit;
4738    }
4739
4740  if (range)
4741    s_arm_unwind_save_core (range);
4742}
4743
4744/* Parse an unwind_save directive.
4745   If the argument is non-zero, this is a .vsave directive.  */
4746
4747static void
4748s_arm_unwind_save (int arch_v6)
4749{
4750  char *peek, *mask_peek;
4751  long range, mask_range;
4752  struct reg_entry *reg;
4753  bool had_brace = false;
4754
4755  if (!unwind.proc_start)
4756    as_bad (MISSING_FNSTART);
4757
4758  /* Figure out what sort of save we have.  */
4759  peek = mask_peek = input_line_pointer;
4760
4761  if (*peek == '{')
4762    {
4763      had_brace = true;
4764      peek++;
4765    }
4766
4767  reg = arm_reg_parse_multi (&peek);
4768
4769  if (!reg)
4770    {
4771      as_bad (_("register expected"));
4772      ignore_rest_of_line ();
4773      return;
4774    }
4775
4776  switch (reg->type)
4777    {
4778    case REG_TYPE_FN:
4779      if (had_brace)
4780	{
4781	  as_bad (_("FPA .unwind_save does not take a register list"));
4782	  ignore_rest_of_line ();
4783	  return;
4784	}
4785      input_line_pointer = peek;
4786      s_arm_unwind_save_fpa (reg->number);
4787      return;
4788
4789    case REG_TYPE_PSEUDO:
4790    case REG_TYPE_RN:
4791      mask_range = parse_reg_list (&mask_peek, REGLIST_PSEUDO);
4792      range = parse_reg_list (&input_line_pointer, REGLIST_RN);
4793
4794      if (range == FAIL || mask_range == FAIL)
4795	{
4796	  as_bad (_("expected register list"));
4797	  ignore_rest_of_line ();
4798	  return;
4799	}
4800
4801      demand_empty_rest_of_line ();
4802
4803      s_arm_unwind_save_mixed (range, mask_range);
4804      return;
4805
4806    case REG_TYPE_VFD:
4807      if (arch_v6)
4808	s_arm_unwind_save_vfp_armv6 ();
4809      else
4810	s_arm_unwind_save_vfp ();
4811      return;
4812
4813    case REG_TYPE_MMXWR:
4814      s_arm_unwind_save_mmxwr ();
4815      return;
4816
4817    case REG_TYPE_MMXWCG:
4818      s_arm_unwind_save_mmxwcg ();
4819      return;
4820
4821    default:
4822      as_bad (_(".unwind_save does not support this kind of register"));
4823      ignore_rest_of_line ();
4824    }
4825}
4826
4827
4828/* Parse an unwind_movsp directive.  */
4829
4830static void
4831s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4832{
4833  int reg;
4834  valueT op;
4835  int offset;
4836
4837  if (!unwind.proc_start)
4838    as_bad (MISSING_FNSTART);
4839
4840  reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4841  if (reg == FAIL)
4842    {
4843      as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
4844      ignore_rest_of_line ();
4845      return;
4846    }
4847
4848  /* Optional constant.	 */
4849  if (skip_past_comma (&input_line_pointer) != FAIL)
4850    {
4851      if (immediate_for_directive (&offset) == FAIL)
4852	return;
4853    }
4854  else
4855    offset = 0;
4856
4857  demand_empty_rest_of_line ();
4858
4859  if (reg == REG_SP || reg == REG_PC)
4860    {
4861      as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4862      return;
4863    }
4864
4865  if (unwind.fp_reg != REG_SP)
4866    as_bad (_("unexpected .unwind_movsp directive"));
4867
4868  /* Generate opcode to restore the value.  */
4869  op = 0x90 | reg;
4870  add_unwind_opcode (op, 1);
4871
4872  /* Record the information for later.	*/
4873  unwind.fp_reg = reg;
4874  unwind.fp_offset = unwind.frame_size - offset;
4875  unwind.sp_restored = 1;
4876}
4877
4878/* Parse an unwind_pad directive.  */
4879
4880static void
4881s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
4882{
4883  int offset;
4884
4885  if (!unwind.proc_start)
4886    as_bad (MISSING_FNSTART);
4887
4888  if (immediate_for_directive (&offset) == FAIL)
4889    return;
4890
4891  if (offset & 3)
4892    {
4893      as_bad (_("stack increment must be multiple of 4"));
4894      ignore_rest_of_line ();
4895      return;
4896    }
4897
4898  /* Don't generate any opcodes, just record the details for later.  */
4899  unwind.frame_size += offset;
4900  unwind.pending_offset += offset;
4901
4902  demand_empty_rest_of_line ();
4903}
4904
4905/* Parse an unwind_setfp directive.  */
4906
4907static void
4908s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
4909{
4910  int sp_reg;
4911  int fp_reg;
4912  int offset;
4913
4914  if (!unwind.proc_start)
4915    as_bad (MISSING_FNSTART);
4916
4917  fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4918  if (skip_past_comma (&input_line_pointer) == FAIL)
4919    sp_reg = FAIL;
4920  else
4921    sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
4922
4923  if (fp_reg == FAIL || sp_reg == FAIL)
4924    {
4925      as_bad (_("expected <reg>, <reg>"));
4926      ignore_rest_of_line ();
4927      return;
4928    }
4929
4930  /* Optional constant.	 */
4931  if (skip_past_comma (&input_line_pointer) != FAIL)
4932    {
4933      if (immediate_for_directive (&offset) == FAIL)
4934	return;
4935    }
4936  else
4937    offset = 0;
4938
4939  demand_empty_rest_of_line ();
4940
4941  if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
4942    {
4943      as_bad (_("register must be either sp or set by a previous"
4944		"unwind_movsp directive"));
4945      return;
4946    }
4947
4948  /* Don't generate any opcodes, just record the information for later.	 */
4949  unwind.fp_reg = fp_reg;
4950  unwind.fp_used = 1;
4951  if (sp_reg == REG_SP)
4952    unwind.fp_offset = unwind.frame_size - offset;
4953  else
4954    unwind.fp_offset -= offset;
4955}
4956
4957/* Parse an unwind_raw directive.  */
4958
4959static void
4960s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
4961{
4962  expressionS exp;
4963  /* This is an arbitrary limit.	 */
4964  unsigned char op[16];
4965  int count;
4966
4967  if (!unwind.proc_start)
4968    as_bad (MISSING_FNSTART);
4969
4970  expression (&exp);
4971  if (exp.X_op == O_constant
4972      && skip_past_comma (&input_line_pointer) != FAIL)
4973    {
4974      unwind.frame_size += exp.X_add_number;
4975      expression (&exp);
4976    }
4977  else
4978    exp.X_op = O_illegal;
4979
4980  if (exp.X_op != O_constant)
4981    {
4982      as_bad (_("expected <offset>, <opcode>"));
4983      ignore_rest_of_line ();
4984      return;
4985    }
4986
4987  count = 0;
4988
4989  /* Parse the opcode.	*/
4990  for (;;)
4991    {
4992      if (count >= 16)
4993	{
4994	  as_bad (_("unwind opcode too long"));
4995	  ignore_rest_of_line ();
4996	}
4997      if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
4998	{
4999	  as_bad (_("invalid unwind opcode"));
5000	  ignore_rest_of_line ();
5001	  return;
5002	}
5003      op[count++] = exp.X_add_number;
5004
5005      /* Parse the next byte.  */
5006      if (skip_past_comma (&input_line_pointer) == FAIL)
5007	break;
5008
5009      expression (&exp);
5010    }
5011
5012  /* Add the opcode bytes in reverse order.  */
5013  while (count--)
5014    add_unwind_opcode (op[count], 1);
5015
5016  demand_empty_rest_of_line ();
5017}
5018
5019
5020/* Parse a .eabi_attribute directive.  */
5021
5022static void
5023s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
5024{
5025  int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
5026
5027  if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES)
5028    attributes_set_explicitly[tag] = 1;
5029}
5030
5031/* Emit a tls fix for the symbol.  */
5032
5033static void
5034s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
5035{
5036  char *p;
5037  expressionS exp;
5038#ifdef md_flush_pending_output
5039  md_flush_pending_output ();
5040#endif
5041
5042#ifdef md_cons_align
5043  md_cons_align (4);
5044#endif
5045
5046  /* Since we're just labelling the code, there's no need to define a
5047     mapping symbol.  */
5048  expression (&exp);
5049  p = obstack_next_free (&frchain_now->frch_obstack);
5050  fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
5051	       thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5052	       : BFD_RELOC_ARM_TLS_DESCSEQ);
5053}
5054#endif /* OBJ_ELF */
5055
5056static void s_arm_arch (int);
5057static void s_arm_object_arch (int);
5058static void s_arm_cpu (int);
5059static void s_arm_fpu (int);
5060static void s_arm_arch_extension (int);
5061
5062#ifdef TE_PE
5063
5064static void
5065pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
5066{
5067  expressionS exp;
5068
5069  do
5070    {
5071      expression (&exp);
5072      if (exp.X_op == O_symbol)
5073	exp.X_op = O_secrel;
5074
5075      emit_expr (&exp, 4);
5076    }
5077  while (*input_line_pointer++ == ',');
5078
5079  input_line_pointer--;
5080  demand_empty_rest_of_line ();
5081}
5082#endif /* TE_PE */
5083
5084int
5085arm_is_largest_exponent_ok (int precision)
5086{
5087  /* precision == 1 ensures that this will only return
5088     true for 16 bit floats.  */
5089  return (precision == 1) && (fp16_format == ARM_FP16_FORMAT_ALTERNATIVE);
5090}
5091
5092static void
5093set_fp16_format (int dummy ATTRIBUTE_UNUSED)
5094{
5095  char saved_char;
5096  char* name;
5097  enum fp_16bit_format new_format;
5098
5099  new_format = ARM_FP16_FORMAT_DEFAULT;
5100
5101  name = input_line_pointer;
5102  while (*input_line_pointer && !ISSPACE (*input_line_pointer))
5103    input_line_pointer++;
5104
5105  saved_char = *input_line_pointer;
5106  *input_line_pointer = 0;
5107
5108  if (strcasecmp (name, "ieee") == 0)
5109    new_format = ARM_FP16_FORMAT_IEEE;
5110  else if (strcasecmp (name, "alternative") == 0)
5111    new_format = ARM_FP16_FORMAT_ALTERNATIVE;
5112  else
5113    {
5114      as_bad (_("unrecognised float16 format \"%s\""), name);
5115      goto cleanup;
5116    }
5117
5118  /* Only set fp16_format if it is still the default (aka not already
5119     been set yet).  */
5120  if (fp16_format == ARM_FP16_FORMAT_DEFAULT)
5121    fp16_format = new_format;
5122  else
5123    {
5124      if (new_format != fp16_format)
5125	as_warn (_("float16 format cannot be set more than once, ignoring."));
5126    }
5127
5128 cleanup:
5129  *input_line_pointer = saved_char;
5130  ignore_rest_of_line ();
5131}
5132
5133/* This table describes all the machine specific pseudo-ops the assembler
5134   has to support.  The fields are:
5135     pseudo-op name without dot
5136     function to call to execute this pseudo-op
5137     Integer arg to pass to the function.  */
5138
5139const pseudo_typeS md_pseudo_table[] =
5140{
5141  /* Never called because '.req' does not start a line.	 */
5142  { "req",	   s_req,	  0 },
5143  /* Following two are likewise never called.  */
5144  { "dn",	   s_dn,          0 },
5145  { "qn",          s_qn,          0 },
5146  { "unreq",	   s_unreq,	  0 },
5147  { "bss",	   s_bss,	  0 },
5148  { "align",	   s_align_ptwo,  2 },
5149  { "arm",	   s_arm,	  0 },
5150  { "thumb",	   s_thumb,	  0 },
5151  { "code",	   s_code,	  0 },
5152  { "force_thumb", s_force_thumb, 0 },
5153  { "thumb_func",  s_thumb_func,  0 },
5154  { "thumb_set",   s_thumb_set,	  0 },
5155  { "even",	   s_even,	  0 },
5156  { "ltorg",	   s_ltorg,	  0 },
5157  { "pool",	   s_ltorg,	  0 },
5158  { "syntax",	   s_syntax,	  0 },
5159  { "cpu",	   s_arm_cpu,	  0 },
5160  { "arch",	   s_arm_arch,	  0 },
5161  { "object_arch", s_arm_object_arch,	0 },
5162  { "fpu",	   s_arm_fpu,	  0 },
5163  { "arch_extension", s_arm_arch_extension, 0 },
5164#ifdef OBJ_ELF
5165  { "word",	        s_arm_elf_cons, 4 },
5166  { "long",	        s_arm_elf_cons, 4 },
5167  { "inst.n",           s_arm_elf_inst, 2 },
5168  { "inst.w",           s_arm_elf_inst, 4 },
5169  { "inst",             s_arm_elf_inst, 0 },
5170  { "rel31",	        s_arm_rel31,	  0 },
5171  { "fnstart",		s_arm_unwind_fnstart,	0 },
5172  { "fnend",		s_arm_unwind_fnend,	0 },
5173  { "cantunwind",	s_arm_unwind_cantunwind, 0 },
5174  { "personality",	s_arm_unwind_personality, 0 },
5175  { "personalityindex",	s_arm_unwind_personalityindex, 0 },
5176  { "handlerdata",	s_arm_unwind_handlerdata, 0 },
5177  { "save",		s_arm_unwind_save,	0 },
5178  { "vsave",		s_arm_unwind_save,	1 },
5179  { "movsp",		s_arm_unwind_movsp,	0 },
5180  { "pad",		s_arm_unwind_pad,	0 },
5181  { "setfp",		s_arm_unwind_setfp,	0 },
5182  { "unwind_raw",	s_arm_unwind_raw,	0 },
5183  { "eabi_attribute",	s_arm_eabi_attribute,	0 },
5184  { "tlsdescseq",	s_arm_tls_descseq,      0 },
5185#else
5186  { "word",	   cons, 4},
5187
5188  /* These are used for dwarf.  */
5189  {"2byte", cons, 2},
5190  {"4byte", cons, 4},
5191  {"8byte", cons, 8},
5192  /* These are used for dwarf2.  */
5193  { "file", dwarf2_directive_file, 0 },
5194  { "loc",  dwarf2_directive_loc,  0 },
5195  { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
5196#endif
5197  { "extend",	   float_cons, 'x' },
5198  { "ldouble",	   float_cons, 'x' },
5199  { "packed",	   float_cons, 'p' },
5200  { "bfloat16",	   float_cons, 'b' },
5201#ifdef TE_PE
5202  {"secrel32", pe_directive_secrel, 0},
5203#endif
5204
5205  /* These are for compatibility with CodeComposer Studio.  */
5206  {"ref",          s_ccs_ref,        0},
5207  {"def",          s_ccs_def,        0},
5208  {"asmfunc",      s_ccs_asmfunc,    0},
5209  {"endasmfunc",   s_ccs_endasmfunc, 0},
5210
5211  {"float16", float_cons, 'h' },
5212  {"float16_format", set_fp16_format, 0 },
5213
5214  { 0, 0, 0 }
5215};
5216
5217/* Parser functions used exclusively in instruction operands.  */
5218
5219/* Generic immediate-value read function for use in insn parsing.
5220   STR points to the beginning of the immediate (the leading #);
5221   VAL receives the value; if the value is outside [MIN, MAX]
5222   issue an error.  PREFIX_OPT is true if the immediate prefix is
5223   optional.  */
5224
5225static int
5226parse_immediate (char **str, int *val, int min, int max,
5227		 bool prefix_opt)
5228{
5229  expressionS exp;
5230
5231  my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
5232  if (exp.X_op != O_constant)
5233    {
5234      inst.error = _("constant expression required");
5235      return FAIL;
5236    }
5237
5238  if (exp.X_add_number < min || exp.X_add_number > max)
5239    {
5240      inst.error = _("immediate value out of range");
5241      return FAIL;
5242    }
5243
5244  *val = exp.X_add_number;
5245  return SUCCESS;
5246}
5247
5248/* Less-generic immediate-value read function with the possibility of loading a
5249   big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5250   instructions. Puts the result directly in inst.operands[i].  */
5251
5252static int
5253parse_big_immediate (char **str, int i, expressionS *in_exp,
5254		     bool allow_symbol_p)
5255{
5256  expressionS exp;
5257  expressionS *exp_p = in_exp ? in_exp : &exp;
5258  char *ptr = *str;
5259
5260  my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5261
5262  if (exp_p->X_op == O_constant)
5263    {
5264      inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
5265      /* If we're on a 64-bit host, then a 64-bit number can be returned using
5266	 O_constant.  We have to be careful not to break compilation for
5267	 32-bit X_add_number, though.  */
5268      if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
5269	{
5270	  /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4.  */
5271	  inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5272				  & 0xffffffff);
5273	  inst.operands[i].regisimm = 1;
5274	}
5275    }
5276  else if (exp_p->X_op == O_big
5277	   && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5278    {
5279      unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
5280
5281      /* Bignums have their least significant bits in
5282	 generic_bignum[0]. Make sure we put 32 bits in imm and
5283	 32 bits in reg,  in a (hopefully) portable way.  */
5284      gas_assert (parts != 0);
5285
5286      /* Make sure that the number is not too big.
5287	 PR 11972: Bignums can now be sign-extended to the
5288	 size of a .octa so check that the out of range bits
5289	 are all zero or all one.  */
5290      if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
5291	{
5292	  LITTLENUM_TYPE m = -1;
5293
5294	  if (generic_bignum[parts * 2] != 0
5295	      && generic_bignum[parts * 2] != m)
5296	    return FAIL;
5297
5298	  for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
5299	    if (generic_bignum[j] != generic_bignum[j-1])
5300	      return FAIL;
5301	}
5302
5303      inst.operands[i].imm = 0;
5304      for (j = 0; j < parts; j++, idx++)
5305	inst.operands[i].imm |= ((unsigned) generic_bignum[idx]
5306				 << (LITTLENUM_NUMBER_OF_BITS * j));
5307      inst.operands[i].reg = 0;
5308      for (j = 0; j < parts; j++, idx++)
5309	inst.operands[i].reg |= ((unsigned) generic_bignum[idx]
5310				 << (LITTLENUM_NUMBER_OF_BITS * j));
5311      inst.operands[i].regisimm = 1;
5312    }
5313  else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5314    return FAIL;
5315
5316  *str = ptr;
5317
5318  return SUCCESS;
5319}
5320
5321/* Returns the pseudo-register number of an FPA immediate constant,
5322   or FAIL if there isn't a valid constant here.  */
5323
5324static int
5325parse_fpa_immediate (char ** str)
5326{
5327  LITTLENUM_TYPE words[MAX_LITTLENUMS];
5328  char *	 save_in;
5329  expressionS	 exp;
5330  int		 i;
5331  int		 j;
5332
5333  /* First try and match exact strings, this is to guarantee
5334     that some formats will work even for cross assembly.  */
5335
5336  for (i = 0; fp_const[i]; i++)
5337    {
5338      if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
5339	{
5340	  char *start = *str;
5341
5342	  *str += strlen (fp_const[i]);
5343	  if (is_end_of_line[(unsigned char) **str])
5344	    return i + 8;
5345	  *str = start;
5346	}
5347    }
5348
5349  /* Just because we didn't get a match doesn't mean that the constant
5350     isn't valid, just that it is in a format that we don't
5351     automatically recognize.  Try parsing it with the standard
5352     expression routines.  */
5353
5354  memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
5355
5356  /* Look for a raw floating point number.  */
5357  if ((save_in = atof_ieee (*str, 'x', words)) != NULL
5358      && is_end_of_line[(unsigned char) *save_in])
5359    {
5360      for (i = 0; i < NUM_FLOAT_VALS; i++)
5361	{
5362	  for (j = 0; j < MAX_LITTLENUMS; j++)
5363	    {
5364	      if (words[j] != fp_values[i][j])
5365		break;
5366	    }
5367
5368	  if (j == MAX_LITTLENUMS)
5369	    {
5370	      *str = save_in;
5371	      return i + 8;
5372	    }
5373	}
5374    }
5375
5376  /* Try and parse a more complex expression, this will probably fail
5377     unless the code uses a floating point prefix (eg "0f").  */
5378  save_in = input_line_pointer;
5379  input_line_pointer = *str;
5380  if (expression (&exp) == absolute_section
5381      && exp.X_op == O_big
5382      && exp.X_add_number < 0)
5383    {
5384      /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5385	 Ditto for 15.	*/
5386#define X_PRECISION 5
5387#define E_PRECISION 15L
5388      if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
5389	{
5390	  for (i = 0; i < NUM_FLOAT_VALS; i++)
5391	    {
5392	      for (j = 0; j < MAX_LITTLENUMS; j++)
5393		{
5394		  if (words[j] != fp_values[i][j])
5395		    break;
5396		}
5397
5398	      if (j == MAX_LITTLENUMS)
5399		{
5400		  *str = input_line_pointer;
5401		  input_line_pointer = save_in;
5402		  return i + 8;
5403		}
5404	    }
5405	}
5406    }
5407
5408  *str = input_line_pointer;
5409  input_line_pointer = save_in;
5410  inst.error = _("invalid FPA immediate expression");
5411  return FAIL;
5412}
5413
5414/* Returns 1 if a number has "quarter-precision" float format
5415   0baBbbbbbc defgh000 00000000 00000000.  */
5416
5417static int
5418is_quarter_float (unsigned imm)
5419{
5420  int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
5421  return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5422}
5423
5424
5425/* Detect the presence of a floating point or integer zero constant,
5426   i.e. #0.0 or #0.  */
5427
5428static bool
5429parse_ifimm_zero (char **in)
5430{
5431  int error_code;
5432
5433  if (!is_immediate_prefix (**in))
5434    {
5435      /* In unified syntax, all prefixes are optional.  */
5436      if (!unified_syntax)
5437	return false;
5438    }
5439  else
5440    ++*in;
5441
5442  /* Accept #0x0 as a synonym for #0.  */
5443  if (startswith (*in, "0x"))
5444    {
5445      int val;
5446      if (parse_immediate (in, &val, 0, 0, true) == FAIL)
5447        return false;
5448      return true;
5449    }
5450
5451  error_code = atof_generic (in, ".", EXP_CHARS,
5452                             &generic_floating_point_number);
5453
5454  if (!error_code
5455      && generic_floating_point_number.sign == '+'
5456      && (generic_floating_point_number.low
5457          > generic_floating_point_number.leader))
5458    return true;
5459
5460  return false;
5461}
5462
5463/* Parse an 8-bit "quarter-precision" floating point number of the form:
5464   0baBbbbbbc defgh000 00000000 00000000.
5465   The zero and minus-zero cases need special handling, since they can't be
5466   encoded in the "quarter-precision" float format, but can nonetheless be
5467   loaded as integer constants.  */
5468
5469static unsigned
5470parse_qfloat_immediate (char **ccp, int *immed)
5471{
5472  char *str = *ccp;
5473  char *fpnum;
5474  LITTLENUM_TYPE words[MAX_LITTLENUMS];
5475  int found_fpchar = 0;
5476
5477  skip_past_char (&str, '#');
5478
5479  /* We must not accidentally parse an integer as a floating-point number. Make
5480     sure that the value we parse is not an integer by checking for special
5481     characters '.' or 'e'.
5482     FIXME: This is a horrible hack, but doing better is tricky because type
5483     information isn't in a very usable state at parse time.  */
5484  fpnum = str;
5485  skip_whitespace (fpnum);
5486
5487  if (startswith (fpnum, "0x"))
5488    return FAIL;
5489  else
5490    {
5491      for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
5492	if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5493	  {
5494	    found_fpchar = 1;
5495	    break;
5496	  }
5497
5498      if (!found_fpchar)
5499	return FAIL;
5500    }
5501
5502  if ((str = atof_ieee (str, 's', words)) != NULL)
5503    {
5504      unsigned fpword = 0;
5505      int i;
5506
5507      /* Our FP word must be 32 bits (single-precision FP).  */
5508      for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
5509	{
5510	  fpword <<= LITTLENUM_NUMBER_OF_BITS;
5511	  fpword |= words[i];
5512	}
5513
5514      if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
5515	*immed = fpword;
5516      else
5517	return FAIL;
5518
5519      *ccp = str;
5520
5521      return SUCCESS;
5522    }
5523
5524  return FAIL;
5525}
5526
5527/* Shift operands.  */
5528enum shift_kind
5529{
5530  SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
5531};
5532
5533struct asm_shift_name
5534{
5535  const char	  *name;
5536  enum shift_kind  kind;
5537};
5538
5539/* Third argument to parse_shift.  */
5540enum parse_shift_mode
5541{
5542  NO_SHIFT_RESTRICT,		/* Any kind of shift is accepted.  */
5543  SHIFT_IMMEDIATE,		/* Shift operand must be an immediate.	*/
5544  SHIFT_LSL_OR_ASR_IMMEDIATE,	/* Shift must be LSL or ASR immediate.	*/
5545  SHIFT_ASR_IMMEDIATE,		/* Shift must be ASR immediate.	 */
5546  SHIFT_LSL_IMMEDIATE,		/* Shift must be LSL immediate.	 */
5547  SHIFT_UXTW_IMMEDIATE		/* Shift must be UXTW immediate.  */
5548};
5549
5550/* Parse a <shift> specifier on an ARM data processing instruction.
5551   This has three forms:
5552
5553     (LSL|LSR|ASL|ASR|ROR) Rs
5554     (LSL|LSR|ASL|ASR|ROR) #imm
5555     RRX
5556
5557   Note that ASL is assimilated to LSL in the instruction encoding, and
5558   RRX to ROR #0 (which cannot be written as such).  */
5559
5560static int
5561parse_shift (char **str, int i, enum parse_shift_mode mode)
5562{
5563  const struct asm_shift_name *shift_name;
5564  enum shift_kind shift;
5565  char *s = *str;
5566  char *p = s;
5567  int reg;
5568
5569  for (p = *str; ISALPHA (*p); p++)
5570    ;
5571
5572  if (p == *str)
5573    {
5574      inst.error = _("shift expression expected");
5575      return FAIL;
5576    }
5577
5578  shift_name
5579    = (const struct asm_shift_name *) str_hash_find_n (arm_shift_hsh, *str,
5580						       p - *str);
5581
5582  if (shift_name == NULL)
5583    {
5584      inst.error = _("shift expression expected");
5585      return FAIL;
5586    }
5587
5588  shift = shift_name->kind;
5589
5590  switch (mode)
5591    {
5592    case NO_SHIFT_RESTRICT:
5593    case SHIFT_IMMEDIATE:
5594      if (shift == SHIFT_UXTW)
5595	{
5596	  inst.error = _("'UXTW' not allowed here");
5597	  return FAIL;
5598	}
5599      break;
5600
5601    case SHIFT_LSL_OR_ASR_IMMEDIATE:
5602      if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5603	{
5604	  inst.error = _("'LSL' or 'ASR' required");
5605	  return FAIL;
5606	}
5607      break;
5608
5609    case SHIFT_LSL_IMMEDIATE:
5610      if (shift != SHIFT_LSL)
5611	{
5612	  inst.error = _("'LSL' required");
5613	  return FAIL;
5614	}
5615      break;
5616
5617    case SHIFT_ASR_IMMEDIATE:
5618      if (shift != SHIFT_ASR)
5619	{
5620	  inst.error = _("'ASR' required");
5621	  return FAIL;
5622	}
5623      break;
5624    case SHIFT_UXTW_IMMEDIATE:
5625      if (shift != SHIFT_UXTW)
5626	{
5627	  inst.error = _("'UXTW' required");
5628	  return FAIL;
5629	}
5630      break;
5631
5632    default: abort ();
5633    }
5634
5635  if (shift != SHIFT_RRX)
5636    {
5637      /* Whitespace can appear here if the next thing is a bare digit.	*/
5638      skip_whitespace (p);
5639
5640      if (mode == NO_SHIFT_RESTRICT
5641	  && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5642	{
5643	  inst.operands[i].imm = reg;
5644	  inst.operands[i].immisreg = 1;
5645	}
5646      else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
5647	return FAIL;
5648    }
5649  inst.operands[i].shift_kind = shift;
5650  inst.operands[i].shifted = 1;
5651  *str = p;
5652  return SUCCESS;
5653}
5654
5655/* Parse a <shifter_operand> for an ARM data processing instruction:
5656
5657      #<immediate>
5658      #<immediate>, <rotate>
5659      <Rm>
5660      <Rm>, <shift>
5661
5662   where <shift> is defined by parse_shift above, and <rotate> is a
5663   multiple of 2 between 0 and 30.  Validation of immediate operands
5664   is deferred to md_apply_fix.  */
5665
5666static int
5667parse_shifter_operand (char **str, int i)
5668{
5669  int value;
5670  expressionS exp;
5671
5672  if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
5673    {
5674      inst.operands[i].reg = value;
5675      inst.operands[i].isreg = 1;
5676
5677      /* parse_shift will override this if appropriate */
5678      inst.relocs[0].exp.X_op = O_constant;
5679      inst.relocs[0].exp.X_add_number = 0;
5680
5681      if (skip_past_comma (str) == FAIL)
5682	return SUCCESS;
5683
5684      /* Shift operation on register.  */
5685      return parse_shift (str, i, NO_SHIFT_RESTRICT);
5686    }
5687
5688  if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
5689    return FAIL;
5690
5691  if (skip_past_comma (str) == SUCCESS)
5692    {
5693      /* #x, y -- ie explicit rotation by Y.  */
5694      if (my_get_expression (&exp, str, GE_NO_PREFIX))
5695	return FAIL;
5696
5697      if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
5698	{
5699	  inst.error = _("constant expression expected");
5700	  return FAIL;
5701	}
5702
5703      value = exp.X_add_number;
5704      if (value < 0 || value > 30 || value % 2 != 0)
5705	{
5706	  inst.error = _("invalid rotation");
5707	  return FAIL;
5708	}
5709      if (inst.relocs[0].exp.X_add_number < 0
5710	  || inst.relocs[0].exp.X_add_number > 255)
5711	{
5712	  inst.error = _("invalid constant");
5713	  return FAIL;
5714	}
5715
5716      /* Encode as specified.  */
5717      inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
5718      return SUCCESS;
5719    }
5720
5721  inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5722  inst.relocs[0].pc_rel = 0;
5723  return SUCCESS;
5724}
5725
5726/* Group relocation information.  Each entry in the table contains the
5727   textual name of the relocation as may appear in assembler source
5728   and must end with a colon.
5729   Along with this textual name are the relocation codes to be used if
5730   the corresponding instruction is an ALU instruction (ADD or SUB only),
5731   an LDR, an LDRS, or an LDC.  */
5732
5733struct group_reloc_table_entry
5734{
5735  const char *name;
5736  int alu_code;
5737  int ldr_code;
5738  int ldrs_code;
5739  int ldc_code;
5740};
5741
5742typedef enum
5743{
5744  /* Varieties of non-ALU group relocation.  */
5745
5746  GROUP_LDR,
5747  GROUP_LDRS,
5748  GROUP_LDC,
5749  GROUP_MVE
5750} group_reloc_type;
5751
5752static struct group_reloc_table_entry group_reloc_table[] =
5753  { /* Program counter relative: */
5754    { "pc_g0_nc",
5755      BFD_RELOC_ARM_ALU_PC_G0_NC,	/* ALU */
5756      0,				/* LDR */
5757      0,				/* LDRS */
5758      0 },				/* LDC */
5759    { "pc_g0",
5760      BFD_RELOC_ARM_ALU_PC_G0,		/* ALU */
5761      BFD_RELOC_ARM_LDR_PC_G0,		/* LDR */
5762      BFD_RELOC_ARM_LDRS_PC_G0,		/* LDRS */
5763      BFD_RELOC_ARM_LDC_PC_G0 },	/* LDC */
5764    { "pc_g1_nc",
5765      BFD_RELOC_ARM_ALU_PC_G1_NC,	/* ALU */
5766      0,				/* LDR */
5767      0,				/* LDRS */
5768      0 },				/* LDC */
5769    { "pc_g1",
5770      BFD_RELOC_ARM_ALU_PC_G1,		/* ALU */
5771      BFD_RELOC_ARM_LDR_PC_G1, 		/* LDR */
5772      BFD_RELOC_ARM_LDRS_PC_G1,		/* LDRS */
5773      BFD_RELOC_ARM_LDC_PC_G1 },	/* LDC */
5774    { "pc_g2",
5775      BFD_RELOC_ARM_ALU_PC_G2,		/* ALU */
5776      BFD_RELOC_ARM_LDR_PC_G2,		/* LDR */
5777      BFD_RELOC_ARM_LDRS_PC_G2,		/* LDRS */
5778      BFD_RELOC_ARM_LDC_PC_G2 },	/* LDC */
5779    /* Section base relative */
5780    { "sb_g0_nc",
5781      BFD_RELOC_ARM_ALU_SB_G0_NC,	/* ALU */
5782      0,				/* LDR */
5783      0,				/* LDRS */
5784      0 },				/* LDC */
5785    { "sb_g0",
5786      BFD_RELOC_ARM_ALU_SB_G0,		/* ALU */
5787      BFD_RELOC_ARM_LDR_SB_G0,		/* LDR */
5788      BFD_RELOC_ARM_LDRS_SB_G0,		/* LDRS */
5789      BFD_RELOC_ARM_LDC_SB_G0 },	/* LDC */
5790    { "sb_g1_nc",
5791      BFD_RELOC_ARM_ALU_SB_G1_NC,	/* ALU */
5792      0,				/* LDR */
5793      0,				/* LDRS */
5794      0 },				/* LDC */
5795    { "sb_g1",
5796      BFD_RELOC_ARM_ALU_SB_G1,		/* ALU */
5797      BFD_RELOC_ARM_LDR_SB_G1, 		/* LDR */
5798      BFD_RELOC_ARM_LDRS_SB_G1,		/* LDRS */
5799      BFD_RELOC_ARM_LDC_SB_G1 },	/* LDC */
5800    { "sb_g2",
5801      BFD_RELOC_ARM_ALU_SB_G2,		/* ALU */
5802      BFD_RELOC_ARM_LDR_SB_G2,		/* LDR */
5803      BFD_RELOC_ARM_LDRS_SB_G2,		/* LDRS */
5804      BFD_RELOC_ARM_LDC_SB_G2 },	/* LDC */
5805    /* Absolute thumb alu relocations.  */
5806    { "lower0_7",
5807      BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU.  */
5808      0,				/* LDR.  */
5809      0,				/* LDRS.  */
5810      0 },				/* LDC.  */
5811    { "lower8_15",
5812      BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU.  */
5813      0,				/* LDR.  */
5814      0,				/* LDRS.  */
5815      0 },				/* LDC.  */
5816    { "upper0_7",
5817      BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU.  */
5818      0,				/* LDR.  */
5819      0,				/* LDRS.  */
5820      0 },				/* LDC.  */
5821    { "upper8_15",
5822      BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU.  */
5823      0,				/* LDR.  */
5824      0,				/* LDRS.  */
5825      0 } };				/* LDC.  */
5826
5827/* Given the address of a pointer pointing to the textual name of a group
5828   relocation as may appear in assembler source, attempt to find its details
5829   in group_reloc_table.  The pointer will be updated to the character after
5830   the trailing colon.  On failure, FAIL will be returned; SUCCESS
5831   otherwise.  On success, *entry will be updated to point at the relevant
5832   group_reloc_table entry. */
5833
5834static int
5835find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5836{
5837  unsigned int i;
5838  for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5839    {
5840      int length = strlen (group_reloc_table[i].name);
5841
5842      if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5843	  && (*str)[length] == ':')
5844	{
5845	  *out = &group_reloc_table[i];
5846	  *str += (length + 1);
5847	  return SUCCESS;
5848	}
5849    }
5850
5851  return FAIL;
5852}
5853
5854/* Parse a <shifter_operand> for an ARM data processing instruction
5855   (as for parse_shifter_operand) where group relocations are allowed:
5856
5857      #<immediate>
5858      #<immediate>, <rotate>
5859      #:<group_reloc>:<expression>
5860      <Rm>
5861      <Rm>, <shift>
5862
5863   where <group_reloc> is one of the strings defined in group_reloc_table.
5864   The hashes are optional.
5865
5866   Everything else is as for parse_shifter_operand.  */
5867
5868static parse_operand_result
5869parse_shifter_operand_group_reloc (char **str, int i)
5870{
5871  /* Determine if we have the sequence of characters #: or just :
5872     coming next.  If we do, then we check for a group relocation.
5873     If we don't, punt the whole lot to parse_shifter_operand.  */
5874
5875  if (((*str)[0] == '#' && (*str)[1] == ':')
5876      || (*str)[0] == ':')
5877    {
5878      struct group_reloc_table_entry *entry;
5879
5880      if ((*str)[0] == '#')
5881	(*str) += 2;
5882      else
5883	(*str)++;
5884
5885      /* Try to parse a group relocation.  Anything else is an error.  */
5886      if (find_group_reloc_table_entry (str, &entry) == FAIL)
5887	{
5888	  inst.error = _("unknown group relocation");
5889	  return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5890	}
5891
5892      /* We now have the group relocation table entry corresponding to
5893	 the name in the assembler source.  Next, we parse the expression.  */
5894      if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
5895	return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5896
5897      /* Record the relocation type (always the ALU variant here).  */
5898      inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5899      gas_assert (inst.relocs[0].type != 0);
5900
5901      return PARSE_OPERAND_SUCCESS;
5902    }
5903  else
5904    return parse_shifter_operand (str, i) == SUCCESS
5905	   ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
5906
5907  /* Never reached.  */
5908}
5909
5910/* Parse a Neon alignment expression.  Information is written to
5911   inst.operands[i].  We assume the initial ':' has been skipped.
5912
5913   align	.imm = align << 8, .immisalign=1, .preind=0  */
5914static parse_operand_result
5915parse_neon_alignment (char **str, int i)
5916{
5917  char *p = *str;
5918  expressionS exp;
5919
5920  my_get_expression (&exp, &p, GE_NO_PREFIX);
5921
5922  if (exp.X_op != O_constant)
5923    {
5924      inst.error = _("alignment must be constant");
5925      return PARSE_OPERAND_FAIL;
5926    }
5927
5928  inst.operands[i].imm = exp.X_add_number << 8;
5929  inst.operands[i].immisalign = 1;
5930  /* Alignments are not pre-indexes.  */
5931  inst.operands[i].preind = 0;
5932
5933  *str = p;
5934  return PARSE_OPERAND_SUCCESS;
5935}
5936
5937/* Parse all forms of an ARM address expression.  Information is written
5938   to inst.operands[i] and/or inst.relocs[0].
5939
5940   Preindexed addressing (.preind=1):
5941
5942   [Rn, #offset]       .reg=Rn .relocs[0].exp=offset
5943   [Rn, +/-Rm]	       .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5944   [Rn, +/-Rm, shift]  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5945		       .shift_kind=shift .relocs[0].exp=shift_imm
5946
5947   These three may have a trailing ! which causes .writeback to be set also.
5948
5949   Postindexed addressing (.postind=1, .writeback=1):
5950
5951   [Rn], #offset       .reg=Rn .relocs[0].exp=offset
5952   [Rn], +/-Rm	       .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5953   [Rn], +/-Rm, shift  .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5954		       .shift_kind=shift .relocs[0].exp=shift_imm
5955
5956   Unindexed addressing (.preind=0, .postind=0):
5957
5958   [Rn], {option}      .reg=Rn .imm=option .immisreg=0
5959
5960   Other:
5961
5962   [Rn]{!}	       shorthand for [Rn,#0]{!}
5963   =immediate	       .isreg=0 .relocs[0].exp=immediate
5964   label	       .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5965
5966  It is the caller's responsibility to check for addressing modes not
5967  supported by the instruction, and to set inst.relocs[0].type.  */
5968
5969static parse_operand_result
5970parse_address_main (char **str, int i, int group_relocations,
5971		    group_reloc_type group_type)
5972{
5973  char *p = *str;
5974  int reg;
5975
5976  if (skip_past_char (&p, '[') == FAIL)
5977    {
5978      if (group_type == GROUP_MVE
5979	  && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
5980	{
5981	  /* [r0-r15] expected as argument but receiving r0-r15 without
5982	     [] brackets.  */
5983	  inst.error = BAD_SYNTAX;
5984	  return PARSE_OPERAND_FAIL;
5985	}
5986      else if (skip_past_char (&p, '=') == FAIL)
5987	{
5988	  /* Bare address - translate to PC-relative offset.  */
5989	  inst.relocs[0].pc_rel = 1;
5990	  inst.operands[i].reg = REG_PC;
5991	  inst.operands[i].isreg = 1;
5992	  inst.operands[i].preind = 1;
5993
5994	  if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
5995	    return PARSE_OPERAND_FAIL;
5996	}
5997      else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
5998				    /*allow_symbol_p=*/true))
5999	return PARSE_OPERAND_FAIL;
6000
6001      *str = p;
6002      return PARSE_OPERAND_SUCCESS;
6003    }
6004
6005  /* PR gas/14887: Allow for whitespace after the opening bracket.  */
6006  skip_whitespace (p);
6007
6008  if (group_type == GROUP_MVE)
6009    {
6010      enum arm_reg_type rtype = REG_TYPE_MQ;
6011      struct neon_type_el et;
6012      if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6013	{
6014	  inst.operands[i].isquad = 1;
6015	}
6016      else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6017	{
6018	  inst.error = BAD_ADDR_MODE;
6019	  return PARSE_OPERAND_FAIL;
6020	}
6021    }
6022  else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6023    {
6024      if (group_type == GROUP_MVE)
6025	inst.error = BAD_ADDR_MODE;
6026      else
6027	inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6028      return PARSE_OPERAND_FAIL;
6029    }
6030  inst.operands[i].reg = reg;
6031  inst.operands[i].isreg = 1;
6032
6033  if (skip_past_comma (&p) == SUCCESS)
6034    {
6035      inst.operands[i].preind = 1;
6036
6037      if (*p == '+') p++;
6038      else if (*p == '-') p++, inst.operands[i].negative = 1;
6039
6040      enum arm_reg_type rtype = REG_TYPE_MQ;
6041      struct neon_type_el et;
6042      if (group_type == GROUP_MVE
6043	  && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6044	{
6045	  inst.operands[i].immisreg = 2;
6046	  inst.operands[i].imm = reg;
6047
6048	  if (skip_past_comma (&p) == SUCCESS)
6049	    {
6050	      if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
6051		{
6052		  inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
6053		  inst.relocs[0].exp.X_add_number = 0;
6054		}
6055	      else
6056		return PARSE_OPERAND_FAIL;
6057	    }
6058	}
6059      else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
6060	{
6061	  inst.operands[i].imm = reg;
6062	  inst.operands[i].immisreg = 1;
6063
6064	  if (skip_past_comma (&p) == SUCCESS)
6065	    if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
6066	      return PARSE_OPERAND_FAIL;
6067	}
6068      else if (skip_past_char (&p, ':') == SUCCESS)
6069	{
6070	  /* FIXME: '@' should be used here, but it's filtered out by generic
6071	     code before we get to see it here. This may be subject to
6072	     change.  */
6073	  parse_operand_result result = parse_neon_alignment (&p, i);
6074
6075	  if (result != PARSE_OPERAND_SUCCESS)
6076	    return result;
6077	}
6078      else
6079	{
6080	  if (inst.operands[i].negative)
6081	    {
6082	      inst.operands[i].negative = 0;
6083	      p--;
6084	    }
6085
6086	  if (group_relocations
6087	      && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
6088	    {
6089	      struct group_reloc_table_entry *entry;
6090
6091	      /* Skip over the #: or : sequence.  */
6092	      if (*p == '#')
6093		p += 2;
6094	      else
6095		p++;
6096
6097	      /* Try to parse a group relocation.  Anything else is an
6098		 error.  */
6099	      if (find_group_reloc_table_entry (&p, &entry) == FAIL)
6100		{
6101		  inst.error = _("unknown group relocation");
6102		  return PARSE_OPERAND_FAIL_NO_BACKTRACK;
6103		}
6104
6105	      /* We now have the group relocation table entry corresponding to
6106		 the name in the assembler source.  Next, we parse the
6107		 expression.  */
6108	      if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
6109		return PARSE_OPERAND_FAIL_NO_BACKTRACK;
6110
6111	      /* Record the relocation type.  */
6112	      switch (group_type)
6113		{
6114		  case GROUP_LDR:
6115		    inst.relocs[0].type
6116			= (bfd_reloc_code_real_type) entry->ldr_code;
6117		    break;
6118
6119		  case GROUP_LDRS:
6120		    inst.relocs[0].type
6121			= (bfd_reloc_code_real_type) entry->ldrs_code;
6122		    break;
6123
6124		  case GROUP_LDC:
6125		    inst.relocs[0].type
6126			= (bfd_reloc_code_real_type) entry->ldc_code;
6127		    break;
6128
6129		  default:
6130		    gas_assert (0);
6131		}
6132
6133	      if (inst.relocs[0].type == 0)
6134		{
6135		  inst.error = _("this group relocation is not allowed on this instruction");
6136		  return PARSE_OPERAND_FAIL_NO_BACKTRACK;
6137		}
6138	    }
6139	  else
6140	    {
6141	      char *q = p;
6142
6143	      if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6144		return PARSE_OPERAND_FAIL;
6145	      /* If the offset is 0, find out if it's a +0 or -0.  */
6146	      if (inst.relocs[0].exp.X_op == O_constant
6147		  && inst.relocs[0].exp.X_add_number == 0)
6148		{
6149		  skip_whitespace (q);
6150		  if (*q == '#')
6151		    {
6152		      q++;
6153		      skip_whitespace (q);
6154		    }
6155		  if (*q == '-')
6156		    inst.operands[i].negative = 1;
6157		}
6158	    }
6159	}
6160    }
6161  else if (skip_past_char (&p, ':') == SUCCESS)
6162    {
6163      /* FIXME: '@' should be used here, but it's filtered out by generic code
6164	 before we get to see it here. This may be subject to change.  */
6165      parse_operand_result result = parse_neon_alignment (&p, i);
6166
6167      if (result != PARSE_OPERAND_SUCCESS)
6168	return result;
6169    }
6170
6171  if (skip_past_char (&p, ']') == FAIL)
6172    {
6173      inst.error = _("']' expected");
6174      return PARSE_OPERAND_FAIL;
6175    }
6176
6177  if (skip_past_char (&p, '!') == SUCCESS)
6178    inst.operands[i].writeback = 1;
6179
6180  else if (skip_past_comma (&p) == SUCCESS)
6181    {
6182      if (skip_past_char (&p, '{') == SUCCESS)
6183	{
6184	  /* [Rn], {expr} - unindexed, with option */
6185	  if (parse_immediate (&p, &inst.operands[i].imm,
6186			       0, 255, true) == FAIL)
6187	    return PARSE_OPERAND_FAIL;
6188
6189	  if (skip_past_char (&p, '}') == FAIL)
6190	    {
6191	      inst.error = _("'}' expected at end of 'option' field");
6192	      return PARSE_OPERAND_FAIL;
6193	    }
6194	  if (inst.operands[i].preind)
6195	    {
6196	      inst.error = _("cannot combine index with option");
6197	      return PARSE_OPERAND_FAIL;
6198	    }
6199	  *str = p;
6200	  return PARSE_OPERAND_SUCCESS;
6201	}
6202      else
6203	{
6204	  inst.operands[i].postind = 1;
6205	  inst.operands[i].writeback = 1;
6206
6207	  if (inst.operands[i].preind)
6208	    {
6209	      inst.error = _("cannot combine pre- and post-indexing");
6210	      return PARSE_OPERAND_FAIL;
6211	    }
6212
6213	  if (*p == '+') p++;
6214	  else if (*p == '-') p++, inst.operands[i].negative = 1;
6215
6216	  enum arm_reg_type rtype = REG_TYPE_MQ;
6217	  struct neon_type_el et;
6218	  if (group_type == GROUP_MVE
6219	      && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6220	    {
6221	      inst.operands[i].immisreg = 2;
6222	      inst.operands[i].imm = reg;
6223	    }
6224	  else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
6225	    {
6226	      /* We might be using the immediate for alignment already. If we
6227		 are, OR the register number into the low-order bits.  */
6228	      if (inst.operands[i].immisalign)
6229		inst.operands[i].imm |= reg;
6230	      else
6231		inst.operands[i].imm = reg;
6232	      inst.operands[i].immisreg = 1;
6233
6234	      if (skip_past_comma (&p) == SUCCESS)
6235		if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
6236		  return PARSE_OPERAND_FAIL;
6237	    }
6238	  else
6239	    {
6240	      char *q = p;
6241
6242	      if (inst.operands[i].negative)
6243		{
6244		  inst.operands[i].negative = 0;
6245		  p--;
6246		}
6247	      if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
6248		return PARSE_OPERAND_FAIL;
6249	      /* If the offset is 0, find out if it's a +0 or -0.  */
6250	      if (inst.relocs[0].exp.X_op == O_constant
6251		  && inst.relocs[0].exp.X_add_number == 0)
6252		{
6253		  skip_whitespace (q);
6254		  if (*q == '#')
6255		    {
6256		      q++;
6257		      skip_whitespace (q);
6258		    }
6259		  if (*q == '-')
6260		    inst.operands[i].negative = 1;
6261		}
6262	    }
6263	}
6264    }
6265
6266  /* If at this point neither .preind nor .postind is set, we have a
6267     bare [Rn]{!}, which is shorthand for [Rn,#0]{!}.  */
6268  if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6269    {
6270      inst.operands[i].preind = 1;
6271      inst.relocs[0].exp.X_op = O_constant;
6272      inst.relocs[0].exp.X_add_number = 0;
6273    }
6274  *str = p;
6275  return PARSE_OPERAND_SUCCESS;
6276}
6277
6278static int
6279parse_address (char **str, int i)
6280{
6281  return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
6282	 ? SUCCESS : FAIL;
6283}
6284
6285static parse_operand_result
6286parse_address_group_reloc (char **str, int i, group_reloc_type type)
6287{
6288  return parse_address_main (str, i, 1, type);
6289}
6290
6291/* Parse an operand for a MOVW or MOVT instruction.  */
6292static int
6293parse_half (char **str)
6294{
6295  char * p;
6296
6297  p = *str;
6298  skip_past_char (&p, '#');
6299  if (strncasecmp (p, ":lower16:", 9) == 0)
6300    inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
6301  else if (strncasecmp (p, ":upper16:", 9) == 0)
6302    inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
6303
6304  if (inst.relocs[0].type != BFD_RELOC_UNUSED)
6305    {
6306      p += 9;
6307      skip_whitespace (p);
6308    }
6309
6310  if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
6311    return FAIL;
6312
6313  if (inst.relocs[0].type == BFD_RELOC_UNUSED)
6314    {
6315      if (inst.relocs[0].exp.X_op != O_constant)
6316	{
6317	  inst.error = _("constant expression expected");
6318	  return FAIL;
6319	}
6320      if (inst.relocs[0].exp.X_add_number < 0
6321	  || inst.relocs[0].exp.X_add_number > 0xffff)
6322	{
6323	  inst.error = _("immediate value out of range");
6324	  return FAIL;
6325	}
6326    }
6327  *str = p;
6328  return SUCCESS;
6329}
6330
6331/* Miscellaneous. */
6332
6333/* Parse a PSR flag operand.  The value returned is FAIL on syntax error,
6334   or a bitmask suitable to be or-ed into the ARM msr instruction.  */
6335static int
6336parse_psr (char **str, bool lhs)
6337{
6338  char *p;
6339  unsigned long psr_field;
6340  const struct asm_psr *psr;
6341  char *start;
6342  bool is_apsr = false;
6343  bool m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
6344
6345  /* PR gas/12698:  If the user has specified -march=all then m_profile will
6346     be TRUE, but we want to ignore it in this case as we are building for any
6347     CPU type, including non-m variants.  */
6348  if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
6349    m_profile = false;
6350
6351  /* CPSR's and SPSR's can now be lowercase.  This is just a convenience
6352     feature for ease of use and backwards compatibility.  */
6353  p = *str;
6354  if (strncasecmp (p, "SPSR", 4) == 0)
6355    {
6356      if (m_profile)
6357	goto unsupported_psr;
6358
6359      psr_field = SPSR_BIT;
6360    }
6361  else if (strncasecmp (p, "CPSR", 4) == 0)
6362    {
6363      if (m_profile)
6364	goto unsupported_psr;
6365
6366      psr_field = 0;
6367    }
6368  else if (strncasecmp (p, "APSR", 4) == 0)
6369    {
6370      /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6371	 and ARMv7-R architecture CPUs.  */
6372      is_apsr = true;
6373      psr_field = 0;
6374    }
6375  else if (m_profile)
6376    {
6377      start = p;
6378      do
6379	p++;
6380      while (ISALNUM (*p) || *p == '_');
6381
6382      if (strncasecmp (start, "iapsr", 5) == 0
6383	  || strncasecmp (start, "eapsr", 5) == 0
6384	  || strncasecmp (start, "xpsr", 4) == 0
6385	  || strncasecmp (start, "psr", 3) == 0)
6386	p = start + strcspn (start, "rR") + 1;
6387
6388      psr = (const struct asm_psr *) str_hash_find_n (arm_v7m_psr_hsh, start,
6389						      p - start);
6390
6391      if (!psr)
6392	return FAIL;
6393
6394      /* If APSR is being written, a bitfield may be specified.  Note that
6395	 APSR itself is handled above.  */
6396      if (psr->field <= 3)
6397	{
6398	  psr_field = psr->field;
6399	  is_apsr = true;
6400	  goto check_suffix;
6401	}
6402
6403      *str = p;
6404      /* M-profile MSR instructions have the mask field set to "10", except
6405	 *PSR variants which modify APSR, which may use a different mask (and
6406	 have been handled already).  Do that by setting the PSR_f field
6407	 here.  */
6408      return psr->field | (lhs ? PSR_f : 0);
6409    }
6410  else
6411    goto unsupported_psr;
6412
6413  p += 4;
6414 check_suffix:
6415  if (*p == '_')
6416    {
6417      /* A suffix follows.  */
6418      p++;
6419      start = p;
6420
6421      do
6422	p++;
6423      while (ISALNUM (*p) || *p == '_');
6424
6425      if (is_apsr)
6426	{
6427	  /* APSR uses a notation for bits, rather than fields.  */
6428	  unsigned int nzcvq_bits = 0;
6429	  unsigned int g_bit = 0;
6430	  char *bit;
6431
6432	  for (bit = start; bit != p; bit++)
6433	    {
6434	      switch (TOLOWER (*bit))
6435		{
6436		case 'n':
6437		  nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
6438		  break;
6439
6440		case 'z':
6441		  nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
6442		  break;
6443
6444		case 'c':
6445		  nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
6446		  break;
6447
6448		case 'v':
6449		  nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
6450		  break;
6451
6452		case 'q':
6453		  nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
6454		  break;
6455
6456		case 'g':
6457		  g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
6458		  break;
6459
6460		default:
6461		  inst.error = _("unexpected bit specified after APSR");
6462		  return FAIL;
6463		}
6464	    }
6465
6466	  if (nzcvq_bits == 0x1f)
6467	    psr_field |= PSR_f;
6468
6469	  if (g_bit == 0x1)
6470	    {
6471	      if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
6472		{
6473		  inst.error = _("selected processor does not "
6474				 "support DSP extension");
6475		  return FAIL;
6476		}
6477
6478	      psr_field |= PSR_s;
6479	    }
6480
6481	  if ((nzcvq_bits & 0x20) != 0
6482	      || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
6483	      || (g_bit & 0x2) != 0)
6484	    {
6485	      inst.error = _("bad bitmask specified after APSR");
6486	      return FAIL;
6487	    }
6488	}
6489      else
6490	{
6491	  psr = (const struct asm_psr *) str_hash_find_n (arm_psr_hsh, start,
6492							  p - start);
6493	  if (!psr)
6494	    goto error;
6495
6496	  psr_field |= psr->field;
6497	}
6498    }
6499  else
6500    {
6501      if (ISALNUM (*p))
6502	goto error;    /* Garbage after "[CS]PSR".  */
6503
6504      /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes).  This
6505	 is deprecated, but allow it anyway.  */
6506      if (is_apsr && lhs)
6507	{
6508	  psr_field |= PSR_f;
6509	  as_tsktsk (_("writing to APSR without specifying a bitmask is "
6510		       "deprecated"));
6511	}
6512      else if (!m_profile)
6513	/* These bits are never right for M-profile devices: don't set them
6514	   (only code paths which read/write APSR reach here).  */
6515	psr_field |= (PSR_c | PSR_f);
6516    }
6517  *str = p;
6518  return psr_field;
6519
6520 unsupported_psr:
6521  inst.error = _("selected processor does not support requested special "
6522		 "purpose register");
6523  return FAIL;
6524
6525 error:
6526  inst.error = _("flag for {c}psr instruction expected");
6527  return FAIL;
6528}
6529
6530static int
6531parse_sys_vldr_vstr (char **str)
6532{
6533  unsigned i;
6534  int val = FAIL;
6535  struct {
6536    const char *name;
6537    int regl;
6538    int regh;
6539  } sysregs[] = {
6540    {"FPSCR",		0x1, 0x0},
6541    {"FPSCR_nzcvqc",	0x2, 0x0},
6542    {"VPR",		0x4, 0x1},
6543    {"P0",		0x5, 0x1},
6544    {"FPCXTNS",		0x6, 0x1},
6545    {"FPCXT_NS",	0x6, 0x1},
6546    {"fpcxtns",		0x6, 0x1},
6547    {"fpcxt_ns",	0x6, 0x1},
6548    {"FPCXTS",		0x7, 0x1},
6549    {"FPCXT_S",		0x7, 0x1},
6550    {"fpcxts",		0x7, 0x1},
6551    {"fpcxt_s",		0x7, 0x1}
6552  };
6553  char *op_end = strchr (*str, ',');
6554  size_t op_strlen = op_end - *str;
6555
6556  for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
6557    {
6558      if (!strncmp (*str, sysregs[i].name, op_strlen))
6559	{
6560	  val = sysregs[i].regl | (sysregs[i].regh << 3);
6561	  *str = op_end;
6562	  break;
6563	}
6564    }
6565
6566  return val;
6567}
6568
6569/* Parse the flags argument to CPSI[ED].  Returns FAIL on error, or a
6570   value suitable for splatting into the AIF field of the instruction.	*/
6571
6572static int
6573parse_cps_flags (char **str)
6574{
6575  int val = 0;
6576  int saw_a_flag = 0;
6577  char *s = *str;
6578
6579  for (;;)
6580    switch (*s++)
6581      {
6582      case '\0': case ',':
6583	goto done;
6584
6585      case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6586      case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6587      case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
6588
6589      default:
6590	inst.error = _("unrecognized CPS flag");
6591	return FAIL;
6592      }
6593
6594 done:
6595  if (saw_a_flag == 0)
6596    {
6597      inst.error = _("missing CPS flags");
6598      return FAIL;
6599    }
6600
6601  *str = s - 1;
6602  return val;
6603}
6604
6605/* Parse an endian specifier ("BE" or "LE", case insensitive);
6606   returns 0 for big-endian, 1 for little-endian, FAIL for an error.  */
6607
6608static int
6609parse_endian_specifier (char **str)
6610{
6611  int little_endian;
6612  char *s = *str;
6613
6614  if (strncasecmp (s, "BE", 2))
6615    little_endian = 0;
6616  else if (strncasecmp (s, "LE", 2))
6617    little_endian = 1;
6618  else
6619    {
6620      inst.error = _("valid endian specifiers are be or le");
6621      return FAIL;
6622    }
6623
6624  if (ISALNUM (s[2]) || s[2] == '_')
6625    {
6626      inst.error = _("valid endian specifiers are be or le");
6627      return FAIL;
6628    }
6629
6630  *str = s + 2;
6631  return little_endian;
6632}
6633
6634/* Parse a rotation specifier: ROR #0, #8, #16, #24.  *val receives a
6635   value suitable for poking into the rotate field of an sxt or sxta
6636   instruction, or FAIL on error.  */
6637
6638static int
6639parse_ror (char **str)
6640{
6641  int rot;
6642  char *s = *str;
6643
6644  if (strncasecmp (s, "ROR", 3) == 0)
6645    s += 3;
6646  else
6647    {
6648      inst.error = _("missing rotation field after comma");
6649      return FAIL;
6650    }
6651
6652  if (parse_immediate (&s, &rot, 0, 24, false) == FAIL)
6653    return FAIL;
6654
6655  switch (rot)
6656    {
6657    case  0: *str = s; return 0x0;
6658    case  8: *str = s; return 0x1;
6659    case 16: *str = s; return 0x2;
6660    case 24: *str = s; return 0x3;
6661
6662    default:
6663      inst.error = _("rotation can only be 0, 8, 16, or 24");
6664      return FAIL;
6665    }
6666}
6667
6668/* Parse a conditional code (from conds[] below).  The value returned is in the
6669   range 0 .. 14, or FAIL.  */
6670static int
6671parse_cond (char **str)
6672{
6673  char *q;
6674  const struct asm_cond *c;
6675  int n;
6676  /* Condition codes are always 2 characters, so matching up to
6677     3 characters is sufficient.  */
6678  char cond[3];
6679
6680  q = *str;
6681  n = 0;
6682  while (ISALPHA (*q) && n < 3)
6683    {
6684      cond[n] = TOLOWER (*q);
6685      q++;
6686      n++;
6687    }
6688
6689  c = (const struct asm_cond *) str_hash_find_n (arm_cond_hsh, cond, n);
6690  if (!c)
6691    {
6692      inst.error = _("condition required");
6693      return FAIL;
6694    }
6695
6696  *str = q;
6697  return c->value;
6698}
6699
6700/* Parse an option for a barrier instruction.  Returns the encoding for the
6701   option, or FAIL.  */
6702static int
6703parse_barrier (char **str)
6704{
6705  char *p, *q;
6706  const struct asm_barrier_opt *o;
6707
6708  p = q = *str;
6709  while (ISALPHA (*q))
6710    q++;
6711
6712  o = (const struct asm_barrier_opt *) str_hash_find_n (arm_barrier_opt_hsh, p,
6713							q - p);
6714  if (!o)
6715    return FAIL;
6716
6717  if (!mark_feature_used (&o->arch))
6718    return FAIL;
6719
6720  *str = q;
6721  return o->value;
6722}
6723
6724/* Parse the operands of a table branch instruction.  Similar to a memory
6725   operand.  */
6726static int
6727parse_tb (char **str)
6728{
6729  char * p = *str;
6730  int reg;
6731
6732  if (skip_past_char (&p, '[') == FAIL)
6733    {
6734      inst.error = _("'[' expected");
6735      return FAIL;
6736    }
6737
6738  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6739    {
6740      inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6741      return FAIL;
6742    }
6743  inst.operands[0].reg = reg;
6744
6745  if (skip_past_comma (&p) == FAIL)
6746    {
6747      inst.error = _("',' expected");
6748      return FAIL;
6749    }
6750
6751  if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
6752    {
6753      inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6754      return FAIL;
6755    }
6756  inst.operands[0].imm = reg;
6757
6758  if (skip_past_comma (&p) == SUCCESS)
6759    {
6760      if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6761	return FAIL;
6762      if (inst.relocs[0].exp.X_add_number != 1)
6763	{
6764	  inst.error = _("invalid shift");
6765	  return FAIL;
6766	}
6767      inst.operands[0].shifted = 1;
6768    }
6769
6770  if (skip_past_char (&p, ']') == FAIL)
6771    {
6772      inst.error = _("']' expected");
6773      return FAIL;
6774    }
6775  *str = p;
6776  return SUCCESS;
6777}
6778
6779/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6780   information on the types the operands can take and how they are encoded.
6781   Up to four operands may be read; this function handles setting the
6782   ".present" field for each read operand itself.
6783   Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6784   else returns FAIL.  */
6785
6786static int
6787parse_neon_mov (char **str, int *which_operand)
6788{
6789  int i = *which_operand, val;
6790  enum arm_reg_type rtype;
6791  char *ptr = *str;
6792  struct neon_type_el optype;
6793
6794   if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6795    {
6796      /* Cases 17 or 19.  */
6797      inst.operands[i].reg = val;
6798      inst.operands[i].isvec = 1;
6799      inst.operands[i].isscalar = 2;
6800      inst.operands[i].vectype = optype;
6801      inst.operands[i++].present = 1;
6802
6803      if (skip_past_comma (&ptr) == FAIL)
6804	goto wanted_comma;
6805
6806      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6807	{
6808	  /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt>  */
6809	  inst.operands[i].reg = val;
6810	  inst.operands[i].isreg = 1;
6811	  inst.operands[i].present = 1;
6812	}
6813      else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6814	{
6815	  /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>  */
6816	  inst.operands[i].reg = val;
6817	  inst.operands[i].isvec = 1;
6818	  inst.operands[i].isscalar = 2;
6819	  inst.operands[i].vectype = optype;
6820	  inst.operands[i++].present = 1;
6821
6822	  if (skip_past_comma (&ptr) == FAIL)
6823	    goto wanted_comma;
6824
6825	  if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6826	    goto wanted_arm;
6827
6828	  inst.operands[i].reg = val;
6829	  inst.operands[i].isreg = 1;
6830	  inst.operands[i++].present = 1;
6831
6832	  if (skip_past_comma (&ptr) == FAIL)
6833	    goto wanted_comma;
6834
6835	  if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6836	    goto wanted_arm;
6837
6838	  inst.operands[i].reg = val;
6839	  inst.operands[i].isreg = 1;
6840	  inst.operands[i].present = 1;
6841	}
6842      else
6843	{
6844	  first_error (_("expected ARM or MVE vector register"));
6845	  return FAIL;
6846	}
6847    }
6848   else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6849    {
6850      /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>.  */
6851      inst.operands[i].reg = val;
6852      inst.operands[i].isscalar = 1;
6853      inst.operands[i].vectype = optype;
6854      inst.operands[i++].present = 1;
6855
6856      if (skip_past_comma (&ptr) == FAIL)
6857	goto wanted_comma;
6858
6859      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6860	goto wanted_arm;
6861
6862      inst.operands[i].reg = val;
6863      inst.operands[i].isreg = 1;
6864      inst.operands[i].present = 1;
6865    }
6866  else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6867	    != FAIL)
6868	   || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype))
6869	       != FAIL))
6870    {
6871      /* Cases 0, 1, 2, 3, 5 (D only).  */
6872      if (skip_past_comma (&ptr) == FAIL)
6873	goto wanted_comma;
6874
6875      inst.operands[i].reg = val;
6876      inst.operands[i].isreg = 1;
6877      inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6878      inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6879      inst.operands[i].isvec = 1;
6880      inst.operands[i].vectype = optype;
6881      inst.operands[i++].present = 1;
6882
6883      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6884	{
6885	  /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6886	     Case 13: VMOV <Sd>, <Rm>  */
6887	  inst.operands[i].reg = val;
6888	  inst.operands[i].isreg = 1;
6889	  inst.operands[i].present = 1;
6890
6891	  if (rtype == REG_TYPE_NQ)
6892	    {
6893	      first_error (_("can't use Neon quad register here"));
6894	      return FAIL;
6895	    }
6896	  else if (rtype != REG_TYPE_VFS)
6897	    {
6898	      i++;
6899	      if (skip_past_comma (&ptr) == FAIL)
6900		goto wanted_comma;
6901	      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6902		goto wanted_arm;
6903	      inst.operands[i].reg = val;
6904	      inst.operands[i].isreg = 1;
6905	      inst.operands[i].present = 1;
6906	    }
6907	}
6908      else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6909		&optype)) != FAIL)
6910	       || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype,
6911		   &optype)) != FAIL))
6912	{
6913	  /* Case 0: VMOV<c><q> <Qd>, <Qm>
6914	     Case 1: VMOV<c><q> <Dd>, <Dm>
6915	     Case 8: VMOV.F32 <Sd>, <Sm>
6916	     Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm>  */
6917
6918	  inst.operands[i].reg = val;
6919	  inst.operands[i].isreg = 1;
6920	  inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6921	  inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6922	  inst.operands[i].isvec = 1;
6923	  inst.operands[i].vectype = optype;
6924	  inst.operands[i].present = 1;
6925
6926	  if (skip_past_comma (&ptr) == SUCCESS)
6927	    {
6928	      /* Case 15.  */
6929	      i++;
6930
6931	      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6932		goto wanted_arm;
6933
6934	      inst.operands[i].reg = val;
6935	      inst.operands[i].isreg = 1;
6936	      inst.operands[i++].present = 1;
6937
6938	      if (skip_past_comma (&ptr) == FAIL)
6939		goto wanted_comma;
6940
6941	      if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6942		goto wanted_arm;
6943
6944	      inst.operands[i].reg = val;
6945	      inst.operands[i].isreg = 1;
6946	      inst.operands[i].present = 1;
6947	    }
6948	}
6949      else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
6950	  /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6951	     Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6952	     Case 10: VMOV.F32 <Sd>, #<imm>
6953	     Case 11: VMOV.F64 <Dd>, #<imm>  */
6954	inst.operands[i].immisfloat = 1;
6955      else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/false)
6956	       == SUCCESS)
6957	  /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6958	     Case 3: VMOV<c><q>.<dt> <Dd>, #<imm>  */
6959	;
6960      else
6961	{
6962	  first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6963	  return FAIL;
6964	}
6965    }
6966  else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6967    {
6968      /* Cases 6, 7, 16, 18.  */
6969      inst.operands[i].reg = val;
6970      inst.operands[i].isreg = 1;
6971      inst.operands[i++].present = 1;
6972
6973      if (skip_past_comma (&ptr) == FAIL)
6974	goto wanted_comma;
6975
6976      if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6977	{
6978	  /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]>  */
6979	  inst.operands[i].reg = val;
6980	  inst.operands[i].isscalar = 2;
6981	  inst.operands[i].present = 1;
6982	  inst.operands[i].vectype = optype;
6983	}
6984      else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
6985	{
6986	  /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]>  */
6987	  inst.operands[i].reg = val;
6988	  inst.operands[i].isscalar = 1;
6989	  inst.operands[i].present = 1;
6990	  inst.operands[i].vectype = optype;
6991	}
6992      else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6993	{
6994	  inst.operands[i].reg = val;
6995	  inst.operands[i].isreg = 1;
6996	  inst.operands[i++].present = 1;
6997
6998	  if (skip_past_comma (&ptr) == FAIL)
6999	    goto wanted_comma;
7000
7001	  if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
7002	      != FAIL)
7003	    {
7004	      /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm>  */
7005
7006	      inst.operands[i].reg = val;
7007	      inst.operands[i].isreg = 1;
7008	      inst.operands[i].isvec = 1;
7009	      inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
7010	      inst.operands[i].vectype = optype;
7011	      inst.operands[i].present = 1;
7012
7013	      if (rtype == REG_TYPE_VFS)
7014		{
7015		  /* Case 14.  */
7016		  i++;
7017		  if (skip_past_comma (&ptr) == FAIL)
7018		    goto wanted_comma;
7019		  if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
7020						  &optype)) == FAIL)
7021		    {
7022		      first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
7023		      return FAIL;
7024		    }
7025		  inst.operands[i].reg = val;
7026		  inst.operands[i].isreg = 1;
7027		  inst.operands[i].isvec = 1;
7028		  inst.operands[i].issingle = 1;
7029		  inst.operands[i].vectype = optype;
7030		  inst.operands[i].present = 1;
7031		}
7032	    }
7033	  else
7034	    {
7035	      if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
7036		       != FAIL)
7037		{
7038		  /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>  */
7039		  inst.operands[i].reg = val;
7040		  inst.operands[i].isvec = 1;
7041		  inst.operands[i].isscalar = 2;
7042		  inst.operands[i].vectype = optype;
7043		  inst.operands[i++].present = 1;
7044
7045		  if (skip_past_comma (&ptr) == FAIL)
7046		    goto wanted_comma;
7047
7048		  if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
7049		      == FAIL)
7050		    {
7051		      first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
7052		      return FAIL;
7053		    }
7054		  inst.operands[i].reg = val;
7055		  inst.operands[i].isvec = 1;
7056		  inst.operands[i].isscalar = 2;
7057		  inst.operands[i].vectype = optype;
7058		  inst.operands[i].present = 1;
7059		}
7060	      else
7061		{
7062		  first_error (_("VFP single, double or MVE vector register"
7063			       " expected"));
7064		  return FAIL;
7065		}
7066	    }
7067	}
7068      else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
7069	       != FAIL)
7070	{
7071	  /* Case 13.  */
7072	  inst.operands[i].reg = val;
7073	  inst.operands[i].isreg = 1;
7074	  inst.operands[i].isvec = 1;
7075	  inst.operands[i].issingle = 1;
7076	  inst.operands[i].vectype = optype;
7077	  inst.operands[i].present = 1;
7078	}
7079    }
7080  else
7081    {
7082      first_error (_("parse error"));
7083      return FAIL;
7084    }
7085
7086  /* Successfully parsed the operands. Update args.  */
7087  *which_operand = i;
7088  *str = ptr;
7089  return SUCCESS;
7090
7091 wanted_comma:
7092  first_error (_("expected comma"));
7093  return FAIL;
7094
7095 wanted_arm:
7096  first_error (_(reg_expected_msgs[REG_TYPE_RN]));
7097  return FAIL;
7098}
7099
7100/* Use this macro when the operand constraints are different
7101   for ARM and THUMB (e.g. ldrd).  */
7102#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7103	((arm_operand) | ((thumb_operand) << 16))
7104
7105/* Matcher codes for parse_operands.  */
7106enum operand_parse_code
7107{
7108  OP_stop,	/* end of line */
7109
7110  OP_RR,	/* ARM register */
7111  OP_RRnpc,	/* ARM register, not r15 */
7112  OP_RRnpcsp,	/* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7113  OP_RRnpcb,	/* ARM register, not r15, in square brackets */
7114  OP_RRnpctw,	/* ARM register, not r15 in Thumb-state or with writeback,
7115		   optional trailing ! */
7116  OP_RRw,	/* ARM register, not r15, optional trailing ! */
7117  OP_RCP,	/* Coprocessor number */
7118  OP_RCN,	/* Coprocessor register */
7119  OP_RF,	/* FPA register */
7120  OP_RVS,	/* VFP single precision register */
7121  OP_RVD,	/* VFP double precision register (0..15) */
7122  OP_RND,       /* Neon double precision register (0..31) */
7123  OP_RNDMQ,     /* Neon double precision (0..31) or MVE vector register.  */
7124  OP_RNDMQR,    /* Neon double precision (0..31), MVE vector or ARM register.
7125		 */
7126  OP_RNSDMQR,    /* Neon single or double precision, MVE vector or ARM register.
7127		 */
7128  OP_RNQ,	/* Neon quad precision register */
7129  OP_RNQMQ,	/* Neon quad or MVE vector register.  */
7130  OP_RVSD,	/* VFP single or double precision register */
7131  OP_RVSD_COND,	/* VFP single, double precision register or condition code.  */
7132  OP_RVSDMQ,	/* VFP single, double precision or MVE vector register.  */
7133  OP_RNSD,      /* Neon single or double precision register */
7134  OP_RNDQ,      /* Neon double or quad precision register */
7135  OP_RNDQMQ,     /* Neon double, quad or MVE vector register.  */
7136  OP_RNDQMQR,   /* Neon double, quad, MVE vector or ARM register.  */
7137  OP_RNSDQ,	/* Neon single, double or quad precision register */
7138  OP_RNSC,      /* Neon scalar D[X] */
7139  OP_RVC,	/* VFP control register */
7140  OP_RMF,	/* Maverick F register */
7141  OP_RMD,	/* Maverick D register */
7142  OP_RMFX,	/* Maverick FX register */
7143  OP_RMDX,	/* Maverick DX register */
7144  OP_RMAX,	/* Maverick AX register */
7145  OP_RMDS,	/* Maverick DSPSC register */
7146  OP_RIWR,	/* iWMMXt wR register */
7147  OP_RIWC,	/* iWMMXt wC register */
7148  OP_RIWG,	/* iWMMXt wCG register */
7149  OP_RXA,	/* XScale accumulator register */
7150
7151  OP_RNSDMQ,	/* Neon single, double or MVE vector register */
7152  OP_RNSDQMQ,	/* Neon single, double or quad register or MVE vector register
7153		 */
7154  OP_RNSDQMQR,	/* Neon single, double or quad register, MVE vector register or
7155		   GPR (no SP/SP)  */
7156  OP_RMQ,	/* MVE vector register.  */
7157  OP_RMQRZ,	/* MVE vector or ARM register including ZR.  */
7158  OP_RMQRR,     /* MVE vector or ARM register.  */
7159
7160  /* New operands for Armv8.1-M Mainline.  */
7161  OP_LR,	/* ARM LR register */
7162  OP_SP,	/* ARM SP register */
7163  OP_R12,
7164  OP_RRe,	/* ARM register, only even numbered.  */
7165  OP_RRo,	/* ARM register, only odd numbered, not r13 or r15.  */
7166  OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
7167  OP_RR_ZR,	/* ARM register or ZR but no PC */
7168
7169  OP_REGLST,	/* ARM register list */
7170  OP_CLRMLST,	/* CLRM register list */
7171  OP_VRSLST,	/* VFP single-precision register list */
7172  OP_VRDLST,	/* VFP double-precision register list */
7173  OP_VRSDLST,   /* VFP single or double-precision register list (& quad) */
7174  OP_NRDLST,    /* Neon double-precision register list (d0-d31, qN aliases) */
7175  OP_NSTRLST,   /* Neon element/structure list */
7176  OP_VRSDVLST,  /* VFP single or double-precision register list and VPR */
7177  OP_MSTRLST2,	/* MVE vector list with two elements.  */
7178  OP_MSTRLST4,	/* MVE vector list with four elements.  */
7179
7180  OP_RNDQ_I0,   /* Neon D or Q reg, or immediate zero.  */
7181  OP_RVSD_I0,	/* VFP S or D reg, or immediate zero.  */
7182  OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero.  */
7183  OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate
7184		    zero.  */
7185  OP_RR_RNSC,   /* ARM reg or Neon scalar.  */
7186  OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar.  */
7187  OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar.  */
7188  OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7189		     */
7190  OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7191			  scalar, or ARM register.  */
7192  OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar.  */
7193  OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register.  */
7194  OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7195			register.  */
7196  OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar.  */
7197  OP_RND_RNSC,  /* Neon D reg, or Neon scalar.  */
7198  OP_VMOV,      /* Neon VMOV operands.  */
7199  OP_RNDQ_Ibig,	/* Neon D or Q reg, or big immediate for logic and VMVN.  */
7200  /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN.  */
7201  OP_RNDQMQ_Ibig,
7202  OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift.  */
7203  OP_RNDQMQ_I63b_RR, /* Neon D or Q reg, immediate for shift, MVE vector or
7204			ARM register.  */
7205  OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2.  */
7206  OP_VLDR,	/* VLDR operand.  */
7207
7208  OP_I0,        /* immediate zero */
7209  OP_I7,	/* immediate value 0 .. 7 */
7210  OP_I15,	/*		   0 .. 15 */
7211  OP_I16,	/*		   1 .. 16 */
7212  OP_I16z,      /*                 0 .. 16 */
7213  OP_I31,	/*		   0 .. 31 */
7214  OP_I31w,	/*		   0 .. 31, optional trailing ! */
7215  OP_I32,	/*		   1 .. 32 */
7216  OP_I32z,	/*		   0 .. 32 */
7217  OP_I48_I64,	/*		   48 or 64 */
7218  OP_I63,	/*		   0 .. 63 */
7219  OP_I63s,	/*		 -64 .. 63 */
7220  OP_I64,	/*		   1 .. 64 */
7221  OP_I64z,	/*		   0 .. 64 */
7222  OP_I127,	/*		   0 .. 127 */
7223  OP_I255,	/*		   0 .. 255 */
7224  OP_I511,	/*		   0 .. 511 */
7225  OP_I4095,	/*		   0 .. 4095 */
7226  OP_I8191,	/*		   0 .. 8191 */
7227  OP_I4b,	/* immediate, prefix optional, 1 .. 4 */
7228  OP_I7b,	/*			       0 .. 7 */
7229  OP_I15b,	/*			       0 .. 15 */
7230  OP_I31b,	/*			       0 .. 31 */
7231
7232  OP_SH,	/* shifter operand */
7233  OP_SHG,	/* shifter operand with possible group relocation */
7234  OP_ADDR,	/* Memory address expression (any mode) */
7235  OP_ADDRMVE,	/* Memory address expression for MVE's VSTR/VLDR.  */
7236  OP_ADDRGLDR,	/* Mem addr expr (any mode) with possible LDR group reloc */
7237  OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
7238  OP_ADDRGLDC,  /* Mem addr expr (any mode) with possible LDC group reloc */
7239  OP_EXP,	/* arbitrary expression */
7240  OP_EXPi,	/* same, with optional immediate prefix */
7241  OP_EXPr,	/* same, with optional relocation suffix */
7242  OP_EXPs,	/* same, with optional non-first operand relocation suffix */
7243  OP_HALF,	/* 0 .. 65535 or low/high reloc.  */
7244  OP_IROT1,	/* VCADD rotate immediate: 90, 270.  */
7245  OP_IROT2,	/* VCMLA rotate immediate: 0, 90, 180, 270.  */
7246
7247  OP_CPSF,	/* CPS flags */
7248  OP_ENDI,	/* Endianness specifier */
7249  OP_wPSR,	/* CPSR/SPSR/APSR mask for msr (writing).  */
7250  OP_rPSR,	/* CPSR/SPSR/APSR mask for msr (reading).  */
7251  OP_COND,	/* conditional code */
7252  OP_TB,	/* Table branch.  */
7253
7254  OP_APSR_RR,   /* ARM register or "APSR_nzcv".  */
7255
7256  OP_RRnpc_I0,	/* ARM register or literal 0 */
7257  OP_RR_EXr,	/* ARM register or expression with opt. reloc stuff. */
7258  OP_RR_EXi,	/* ARM register or expression with imm prefix */
7259  OP_RF_IF,	/* FPA register or immediate */
7260  OP_RIWR_RIWC, /* iWMMXt R or C reg */
7261  OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
7262
7263  /* Optional operands.	 */
7264  OP_oI7b,	 /* immediate, prefix optional, 0 .. 7 */
7265  OP_oI31b,	 /*				0 .. 31 */
7266  OP_oI32b,      /*                             1 .. 32 */
7267  OP_oI32z,      /*                             0 .. 32 */
7268  OP_oIffffb,	 /*				0 .. 65535 */
7269  OP_oI255c,	 /*	  curly-brace enclosed, 0 .. 255 */
7270
7271  OP_oRR,	 /* ARM register */
7272  OP_oLR,	 /* ARM LR register */
7273  OP_oRRnpc,	 /* ARM register, not the PC */
7274  OP_oRRnpcsp,	 /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7275  OP_oRRw,	 /* ARM register, not r15, optional trailing ! */
7276  OP_oRND,       /* Optional Neon double precision register */
7277  OP_oRNQ,       /* Optional Neon quad precision register */
7278  OP_oRNDQMQ,     /* Optional Neon double, quad or MVE vector register.  */
7279  OP_oRNDQ,      /* Optional Neon double or quad precision register */
7280  OP_oRNSDQ,	 /* Optional single, double or quad precision vector register */
7281  OP_oRNSDQMQ,	 /* Optional single, double or quad register or MVE vector
7282		    register.  */
7283  OP_oRNSDMQ,	 /* Optional single, double register or MVE vector
7284		    register.  */
7285  OP_oSHll,	 /* LSL immediate */
7286  OP_oSHar,	 /* ASR immediate */
7287  OP_oSHllar,	 /* LSL or ASR immediate */
7288  OP_oROR,	 /* ROR 0/8/16/24 */
7289  OP_oBARRIER_I15, /* Option argument for a barrier instruction.  */
7290
7291  OP_oRMQRZ,	/* optional MVE vector or ARM register including ZR.  */
7292
7293  /* Some pre-defined mixed (ARM/THUMB) operands.  */
7294  OP_RR_npcsp		= MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
7295  OP_RRnpc_npcsp	= MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
7296  OP_oRRnpc_npcsp	= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
7297
7298  OP_FIRST_OPTIONAL = OP_oI7b
7299};
7300
7301/* Generic instruction operand parser.	This does no encoding and no
7302   semantic validation; it merely squirrels values away in the inst
7303   structure.  Returns SUCCESS or FAIL depending on whether the
7304   specified grammar matched.  */
7305static int
7306parse_operands (char *str, const unsigned int *pattern, bool thumb)
7307{
7308  unsigned const int *upat = pattern;
7309  char *backtrack_pos = 0;
7310  const char *backtrack_error = 0;
7311  int i, val = 0, backtrack_index = 0;
7312  enum arm_reg_type rtype;
7313  parse_operand_result result;
7314  unsigned int op_parse_code;
7315  bool partial_match;
7316
7317#define po_char_or_fail(chr)			\
7318  do						\
7319    {						\
7320      if (skip_past_char (&str, chr) == FAIL)	\
7321	goto bad_args;				\
7322    }						\
7323  while (0)
7324
7325#define po_reg_or_fail(regtype)					\
7326  do								\
7327    {								\
7328      val = arm_typed_reg_parse (& str, regtype, & rtype,	\
7329				 & inst.operands[i].vectype);	\
7330      if (val == FAIL)						\
7331	{							\
7332	  first_error (_(reg_expected_msgs[regtype]));		\
7333	  goto failure;						\
7334	}							\
7335      inst.operands[i].reg = val;				\
7336      inst.operands[i].isreg = 1;				\
7337      inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\
7338      inst.operands[i].issingle = (rtype == REG_TYPE_VFS);	\
7339      inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\
7340			     || rtype == REG_TYPE_VFD		\
7341			     || rtype == REG_TYPE_NQ);		\
7342      inst.operands[i].iszr = (rtype == REG_TYPE_ZR);		\
7343    }								\
7344  while (0)
7345
7346#define po_reg_or_goto(regtype, label)				\
7347  do								\
7348    {								\
7349      val = arm_typed_reg_parse (& str, regtype, & rtype,	\
7350				 & inst.operands[i].vectype);	\
7351      if (val == FAIL)						\
7352	goto label;						\
7353								\
7354      inst.operands[i].reg = val;				\
7355      inst.operands[i].isreg = 1;				\
7356      inst.operands[i].isquad = (rtype == REG_TYPE_NQ);		\
7357      inst.operands[i].issingle = (rtype == REG_TYPE_VFS);	\
7358      inst.operands[i].isvec = (rtype == REG_TYPE_VFS		\
7359			     || rtype == REG_TYPE_VFD		\
7360			     || rtype == REG_TYPE_NQ);		\
7361      inst.operands[i].iszr = (rtype == REG_TYPE_ZR);		\
7362    }								\
7363  while (0)
7364
7365#define po_imm_or_fail(min, max, popt)				\
7366  do								\
7367    {								\
7368      if (parse_immediate (&str, &val, min, max, popt) == FAIL)	\
7369	goto failure;						\
7370      inst.operands[i].imm = val;				\
7371    }								\
7372  while (0)
7373
7374#define po_imm1_or_imm2_or_fail(imm1, imm2, popt)		\
7375  do								\
7376    {								\
7377      expressionS exp;						\
7378      my_get_expression (&exp, &str, popt);			\
7379      if (exp.X_op != O_constant)				\
7380	{							\
7381	  inst.error = _("constant expression required");	\
7382	  goto failure;						\
7383	}							\
7384      if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7385	{							\
7386	  inst.error = _("immediate value 48 or 64 expected");	\
7387	  goto failure;						\
7388	}							\
7389      inst.operands[i].imm = exp.X_add_number;			\
7390    }								\
7391  while (0)
7392
7393#define po_scalar_or_goto(elsz, label, reg_type)			\
7394  do									\
7395    {									\
7396      val = parse_scalar (& str, elsz, & inst.operands[i].vectype,	\
7397			  reg_type);					\
7398      if (val == FAIL)							\
7399	goto label;							\
7400      inst.operands[i].reg = val;					\
7401      inst.operands[i].isscalar = 1;					\
7402    }									\
7403  while (0)
7404
7405#define po_misc_or_fail(expr)			\
7406  do						\
7407    {						\
7408      if (expr)					\
7409	goto failure;				\
7410    }						\
7411  while (0)
7412
7413#define po_misc_or_fail_no_backtrack(expr)		\
7414  do							\
7415    {							\
7416      result = expr;					\
7417      if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)	\
7418	backtrack_pos = 0;				\
7419      if (result != PARSE_OPERAND_SUCCESS)		\
7420	goto failure;					\
7421    }							\
7422  while (0)
7423
7424#define po_barrier_or_imm(str)				   \
7425  do							   \
7426    {						 	   \
7427      val = parse_barrier (&str);			   \
7428      if (val == FAIL && ! ISALPHA (*str))		   \
7429	goto immediate;					   \
7430      if (val == FAIL					   \
7431	  /* ISB can only take SY as an option.  */	   \
7432	  || ((inst.instruction & 0xf0) == 0x60		   \
7433	       && val != 0xf))				   \
7434	{						   \
7435	   inst.error = _("invalid barrier type");	   \
7436	   backtrack_pos = 0;				   \
7437	   goto failure;				   \
7438	}						   \
7439    }							   \
7440  while (0)
7441
7442  skip_whitespace (str);
7443
7444  for (i = 0; upat[i] != OP_stop; i++)
7445    {
7446      op_parse_code = upat[i];
7447      if (op_parse_code >= 1<<16)
7448	op_parse_code = thumb ? (op_parse_code >> 16)
7449				: (op_parse_code & ((1<<16)-1));
7450
7451      if (op_parse_code >= OP_FIRST_OPTIONAL)
7452	{
7453	  /* Remember where we are in case we need to backtrack.  */
7454	  backtrack_pos = str;
7455	  backtrack_error = inst.error;
7456	  backtrack_index = i;
7457	}
7458
7459      if (i > 0 && (i > 1 || inst.operands[0].present))
7460	po_char_or_fail (',');
7461
7462      switch (op_parse_code)
7463	{
7464	  /* Registers */
7465	case OP_oRRnpc:
7466	case OP_oRRnpcsp:
7467	case OP_RRnpc:
7468	case OP_RRnpcsp:
7469	case OP_oRR:
7470	case OP_RRe:
7471	case OP_RRo:
7472	case OP_LR:
7473	case OP_oLR:
7474	case OP_SP:
7475	case OP_R12:
7476	case OP_RR:    po_reg_or_fail (REG_TYPE_RN);	  break;
7477	case OP_RCP:   po_reg_or_fail (REG_TYPE_CP);	  break;
7478	case OP_RCN:   po_reg_or_fail (REG_TYPE_CN);	  break;
7479	case OP_RF:    po_reg_or_fail (REG_TYPE_FN);	  break;
7480	case OP_RVS:   po_reg_or_fail (REG_TYPE_VFS);	  break;
7481	case OP_RVD:   po_reg_or_fail (REG_TYPE_VFD);	  break;
7482	case OP_oRND:
7483	case OP_RNSDMQR:
7484	  po_reg_or_goto (REG_TYPE_VFS, try_rndmqr);
7485	  break;
7486	try_rndmqr:
7487	case OP_RNDMQR:
7488	  po_reg_or_goto (REG_TYPE_RN, try_rndmq);
7489	  break;
7490	try_rndmq:
7491	case OP_RNDMQ:
7492	  po_reg_or_goto (REG_TYPE_MQ, try_rnd);
7493	  break;
7494	try_rnd:
7495	case OP_RND:   po_reg_or_fail (REG_TYPE_VFD);	  break;
7496	case OP_RVC:
7497	  po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
7498	  break;
7499	  /* Also accept generic coprocessor regs for unknown registers.  */
7500	  coproc_reg:
7501	  po_reg_or_goto (REG_TYPE_CN, vpr_po);
7502	  break;
7503	  /* Also accept P0 or p0 for VPR.P0.  Since P0 is already an
7504	     existing register with a value of 0, this seems like the
7505	     best way to parse P0.  */
7506	  vpr_po:
7507	  if (strncasecmp (str, "P0", 2) == 0)
7508	    {
7509	      str += 2;
7510	      inst.operands[i].isreg = 1;
7511	      inst.operands[i].reg = 13;
7512	    }
7513	  else
7514	    goto failure;
7515	  break;
7516	case OP_RMF:   po_reg_or_fail (REG_TYPE_MVF);	  break;
7517	case OP_RMD:   po_reg_or_fail (REG_TYPE_MVD);	  break;
7518	case OP_RMFX:  po_reg_or_fail (REG_TYPE_MVFX);	  break;
7519	case OP_RMDX:  po_reg_or_fail (REG_TYPE_MVDX);	  break;
7520	case OP_RMAX:  po_reg_or_fail (REG_TYPE_MVAX);	  break;
7521	case OP_RMDS:  po_reg_or_fail (REG_TYPE_DSPSC);	  break;
7522	case OP_RIWR:  po_reg_or_fail (REG_TYPE_MMXWR);	  break;
7523	case OP_RIWC:  po_reg_or_fail (REG_TYPE_MMXWC);	  break;
7524	case OP_RIWG:  po_reg_or_fail (REG_TYPE_MMXWCG);  break;
7525	case OP_RXA:   po_reg_or_fail (REG_TYPE_XSCALE);  break;
7526	case OP_oRNQ:
7527	case OP_RNQMQ:
7528	  po_reg_or_goto (REG_TYPE_MQ, try_nq);
7529	  break;
7530	try_nq:
7531	case OP_RNQ:   po_reg_or_fail (REG_TYPE_NQ);      break;
7532	case OP_RNSD:  po_reg_or_fail (REG_TYPE_NSD);     break;
7533	case OP_RNDQMQR:
7534	  po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
7535	  break;
7536	try_rndqmq:
7537	case OP_oRNDQMQ:
7538	case OP_RNDQMQ:
7539	  po_reg_or_goto (REG_TYPE_MQ, try_rndq);
7540	  break;
7541	try_rndq:
7542	case OP_oRNDQ:
7543	case OP_RNDQ:  po_reg_or_fail (REG_TYPE_NDQ);     break;
7544	case OP_RVSDMQ:
7545	  po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
7546	  break;
7547	try_rvsd:
7548	case OP_RVSD:  po_reg_or_fail (REG_TYPE_VFSD);    break;
7549	case OP_RVSD_COND:
7550	  po_reg_or_goto (REG_TYPE_VFSD, try_cond);
7551	  break;
7552	case OP_oRNSDMQ:
7553	case OP_RNSDMQ:
7554	  po_reg_or_goto (REG_TYPE_NSD, try_mq2);
7555	  break;
7556	  try_mq2:
7557	  po_reg_or_fail (REG_TYPE_MQ);
7558	  break;
7559	case OP_oRNSDQ:
7560	case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ);    break;
7561	case OP_RNSDQMQR:
7562	  po_reg_or_goto (REG_TYPE_RN, try_mq);
7563	  break;
7564	  try_mq:
7565	case OP_oRNSDQMQ:
7566	case OP_RNSDQMQ:
7567	  po_reg_or_goto (REG_TYPE_MQ, try_nsdq2);
7568	  break;
7569	  try_nsdq2:
7570	  po_reg_or_fail (REG_TYPE_NSDQ);
7571	  inst.error = 0;
7572	  break;
7573	case OP_RMQRR:
7574	  po_reg_or_goto (REG_TYPE_RN, try_rmq);
7575	  break;
7576	try_rmq:
7577	case OP_RMQ:
7578	  po_reg_or_fail (REG_TYPE_MQ);
7579	  break;
7580	/* Neon scalar. Using an element size of 8 means that some invalid
7581	   scalars are accepted here, so deal with those in later code.  */
7582	case OP_RNSC:  po_scalar_or_goto (8, failure, REG_TYPE_VFD);    break;
7583
7584	case OP_RNDQ_I0:
7585	  {
7586	    po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
7587	    break;
7588	    try_imm0:
7589	    po_imm_or_fail (0, 0, true);
7590	  }
7591	  break;
7592
7593	case OP_RVSD_I0:
7594	  po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
7595	  break;
7596
7597	case OP_RSVDMQ_FI0:
7598	  po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0);
7599	  break;
7600	try_rsvd_fi0:
7601	case OP_RSVD_FI0:
7602	  {
7603	    po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
7604	    break;
7605	    try_ifimm0:
7606	    if (parse_ifimm_zero (&str))
7607	      inst.operands[i].imm = 0;
7608	    else
7609	    {
7610	      inst.error
7611	        = _("only floating point zero is allowed as immediate value");
7612	      goto failure;
7613	    }
7614	  }
7615	  break;
7616
7617	case OP_RR_RNSC:
7618	  {
7619	    po_scalar_or_goto (8, try_rr, REG_TYPE_VFD);
7620	    break;
7621	    try_rr:
7622	    po_reg_or_fail (REG_TYPE_RN);
7623	  }
7624	  break;
7625
7626	case OP_RNSDQ_RNSC_MQ_RR:
7627	  po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq);
7628	  break;
7629	try_rnsdq_rnsc_mq:
7630	case OP_RNSDQ_RNSC_MQ:
7631	  po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
7632	  break;
7633	try_rnsdq_rnsc:
7634	case OP_RNSDQ_RNSC:
7635	  {
7636	    po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD);
7637	    inst.error = 0;
7638	    break;
7639	    try_nsdq:
7640	    po_reg_or_fail (REG_TYPE_NSDQ);
7641	    inst.error = 0;
7642	  }
7643	  break;
7644
7645	case OP_RNSD_RNSC:
7646	  {
7647	    po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD);
7648	    break;
7649	    try_s_scalar:
7650	    po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS);
7651	    break;
7652	    try_nsd:
7653	    po_reg_or_fail (REG_TYPE_NSD);
7654	  }
7655	  break;
7656
7657	case OP_RNDQMQ_RNSC_RR:
7658	  po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr);
7659	  break;
7660	try_rndq_rnsc_rr:
7661	case OP_RNDQ_RNSC_RR:
7662	  po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc);
7663	  break;
7664	case OP_RNDQMQ_RNSC:
7665	  po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
7666	  break;
7667	try_rndq_rnsc:
7668	case OP_RNDQ_RNSC:
7669	  {
7670	    po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
7671	    break;
7672	    try_ndq:
7673	    po_reg_or_fail (REG_TYPE_NDQ);
7674	  }
7675	  break;
7676
7677	case OP_RND_RNSC:
7678	  {
7679	    po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD);
7680	    break;
7681	    try_vfd:
7682	    po_reg_or_fail (REG_TYPE_VFD);
7683	  }
7684	  break;
7685
7686	case OP_VMOV:
7687	  /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7688	     not careful then bad things might happen.  */
7689	  po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
7690	  break;
7691
7692	case OP_RNDQMQ_Ibig:
7693	  po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
7694	  break;
7695	try_rndq_ibig:
7696	case OP_RNDQ_Ibig:
7697	  {
7698	    po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
7699	    break;
7700	    try_immbig:
7701	    /* There's a possibility of getting a 64-bit immediate here, so
7702	       we need special handling.  */
7703	    if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/false)
7704		== FAIL)
7705	      {
7706		inst.error = _("immediate value is out of range");
7707		goto failure;
7708	      }
7709	  }
7710	  break;
7711
7712	case OP_RNDQMQ_I63b_RR:
7713	  po_reg_or_goto (REG_TYPE_MQ, try_rndq_i63b_rr);
7714	  break;
7715	try_rndq_i63b_rr:
7716	  po_reg_or_goto (REG_TYPE_RN, try_rndq_i63b);
7717	  break;
7718	try_rndq_i63b:
7719	case OP_RNDQ_I63b:
7720	  {
7721	    po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
7722	    break;
7723	    try_shimm:
7724	    po_imm_or_fail (0, 63, true);
7725	  }
7726	  break;
7727
7728	case OP_RRnpcb:
7729	  po_char_or_fail ('[');
7730	  po_reg_or_fail  (REG_TYPE_RN);
7731	  po_char_or_fail (']');
7732	  break;
7733
7734	case OP_RRnpctw:
7735	case OP_RRw:
7736	case OP_oRRw:
7737	  po_reg_or_fail (REG_TYPE_RN);
7738	  if (skip_past_char (&str, '!') == SUCCESS)
7739	    inst.operands[i].writeback = 1;
7740	  break;
7741
7742	  /* Immediates */
7743	case OP_I7:	 po_imm_or_fail (  0,	   7, false);	break;
7744	case OP_I15:	 po_imm_or_fail (  0,	  15, false);	break;
7745	case OP_I16:	 po_imm_or_fail (  1,	  16, false);	break;
7746	case OP_I16z:	 po_imm_or_fail (  0,     16, false);   break;
7747	case OP_I31:	 po_imm_or_fail (  0,	  31, false);	break;
7748	case OP_I32:	 po_imm_or_fail (  1,	  32, false);	break;
7749	case OP_I32z:	 po_imm_or_fail (  0,     32, false);   break;
7750	case OP_I48_I64: po_imm1_or_imm2_or_fail (48, 64, false); break;
7751	case OP_I63s:	 po_imm_or_fail (-64,	  63, false);	break;
7752	case OP_I63:	 po_imm_or_fail (  0,     63, false);   break;
7753	case OP_I64:	 po_imm_or_fail (  1,     64, false);   break;
7754	case OP_I64z:	 po_imm_or_fail (  0,     64, false);   break;
7755	case OP_I127:	 po_imm_or_fail (  0,	 127, false);	break;
7756	case OP_I255:	 po_imm_or_fail (  0,	 255, false);	break;
7757	case OP_I511:	 po_imm_or_fail (  0,	 511, false);	break;
7758	case OP_I4095:	 po_imm_or_fail (  0,	 4095, false);	break;
7759	case OP_I8191:   po_imm_or_fail (  0,	 8191, false);	break;
7760	case OP_I4b:	 po_imm_or_fail (  1,	   4, true);	break;
7761	case OP_oI7b:
7762	case OP_I7b:	 po_imm_or_fail (  0,	   7, true);	break;
7763	case OP_I15b:	 po_imm_or_fail (  0,	  15, true);	break;
7764	case OP_oI31b:
7765	case OP_I31b:	 po_imm_or_fail (  0,	  31, true);	break;
7766	case OP_oI32b:   po_imm_or_fail (  1,     32, true);    break;
7767	case OP_oI32z:   po_imm_or_fail (  0,     32, true);    break;
7768	case OP_oIffffb: po_imm_or_fail (  0, 0xffff, true);	break;
7769
7770	  /* Immediate variants */
7771	case OP_oI255c:
7772	  po_char_or_fail ('{');
7773	  po_imm_or_fail (0, 255, true);
7774	  po_char_or_fail ('}');
7775	  break;
7776
7777	case OP_I31w:
7778	  /* The expression parser chokes on a trailing !, so we have
7779	     to find it first and zap it.  */
7780	  {
7781	    char *s = str;
7782	    while (*s && *s != ',')
7783	      s++;
7784	    if (s[-1] == '!')
7785	      {
7786		s[-1] = '\0';
7787		inst.operands[i].writeback = 1;
7788	      }
7789	    po_imm_or_fail (0, 31, true);
7790	    if (str == s - 1)
7791	      str = s;
7792	  }
7793	  break;
7794
7795	  /* Expressions */
7796	case OP_EXPi:	EXPi:
7797	  po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7798					      GE_OPT_PREFIX));
7799	  break;
7800
7801	case OP_EXP:
7802	  po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7803					      GE_NO_PREFIX));
7804	  break;
7805
7806	case OP_EXPr:	EXPr:
7807	  po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
7808					      GE_NO_PREFIX));
7809	  if (inst.relocs[0].exp.X_op == O_symbol)
7810	    {
7811	      val = parse_reloc (&str);
7812	      if (val == -1)
7813		{
7814		  inst.error = _("unrecognized relocation suffix");
7815		  goto failure;
7816		}
7817	      else if (val != BFD_RELOC_UNUSED)
7818		{
7819		  inst.operands[i].imm = val;
7820		  inst.operands[i].hasreloc = 1;
7821		}
7822	    }
7823	  break;
7824
7825	case OP_EXPs:
7826	  po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7827					      GE_NO_PREFIX));
7828	  if (inst.relocs[i].exp.X_op == O_symbol)
7829	    {
7830	      inst.operands[i].hasreloc = 1;
7831	    }
7832	  else if (inst.relocs[i].exp.X_op == O_constant)
7833	    {
7834	      inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7835	      inst.operands[i].hasreloc = 0;
7836	    }
7837	  break;
7838
7839	  /* Operand for MOVW or MOVT.  */
7840	case OP_HALF:
7841	  po_misc_or_fail (parse_half (&str));
7842	  break;
7843
7844	  /* Register or expression.  */
7845	case OP_RR_EXr:	  po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7846	case OP_RR_EXi:	  po_reg_or_goto (REG_TYPE_RN, EXPi); break;
7847
7848	  /* Register or immediate.  */
7849	case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0);   break;
7850	I0:		  po_imm_or_fail (0, 0, false);	      break;
7851
7852	case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32);	break;
7853	I32:		     po_imm_or_fail (1, 32, false);	break;
7854
7855	case OP_RF_IF:    po_reg_or_goto (REG_TYPE_FN, IF);   break;
7856	IF:
7857	  if (!is_immediate_prefix (*str))
7858	    goto bad_args;
7859	  str++;
7860	  val = parse_fpa_immediate (&str);
7861	  if (val == FAIL)
7862	    goto failure;
7863	  /* FPA immediates are encoded as registers 8-15.
7864	     parse_fpa_immediate has already applied the offset.  */
7865	  inst.operands[i].reg = val;
7866	  inst.operands[i].isreg = 1;
7867	  break;
7868
7869	case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7870	I32z:		  po_imm_or_fail (0, 32, false);	  break;
7871
7872	  /* Two kinds of register.  */
7873	case OP_RIWR_RIWC:
7874	  {
7875	    struct reg_entry *rege = arm_reg_parse_multi (&str);
7876	    if (!rege
7877		|| (rege->type != REG_TYPE_MMXWR
7878		    && rege->type != REG_TYPE_MMXWC
7879		    && rege->type != REG_TYPE_MMXWCG))
7880	      {
7881		inst.error = _("iWMMXt data or control register expected");
7882		goto failure;
7883	      }
7884	    inst.operands[i].reg = rege->number;
7885	    inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7886	  }
7887	  break;
7888
7889	case OP_RIWC_RIWG:
7890	  {
7891	    struct reg_entry *rege = arm_reg_parse_multi (&str);
7892	    if (!rege
7893		|| (rege->type != REG_TYPE_MMXWC
7894		    && rege->type != REG_TYPE_MMXWCG))
7895	      {
7896		inst.error = _("iWMMXt control register expected");
7897		goto failure;
7898	      }
7899	    inst.operands[i].reg = rege->number;
7900	    inst.operands[i].isreg = 1;
7901	  }
7902	  break;
7903
7904	  /* Misc */
7905	case OP_CPSF:	 val = parse_cps_flags (&str);		break;
7906	case OP_ENDI:	 val = parse_endian_specifier (&str);	break;
7907	case OP_oROR:	 val = parse_ror (&str);		break;
7908	try_cond:
7909	case OP_COND:	 val = parse_cond (&str);		break;
7910	case OP_oBARRIER_I15:
7911	  po_barrier_or_imm (str); break;
7912	  immediate:
7913	  if (parse_immediate (&str, &val, 0, 15, true) == FAIL)
7914	    goto failure;
7915	  break;
7916
7917	case OP_wPSR:
7918	case OP_rPSR:
7919	  po_reg_or_goto (REG_TYPE_RNB, try_psr);
7920	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7921	    {
7922	      inst.error = _("Banked registers are not available with this "
7923			     "architecture.");
7924	      goto failure;
7925	    }
7926	  break;
7927	  try_psr:
7928	  val = parse_psr (&str, op_parse_code == OP_wPSR);
7929	  break;
7930
7931	case OP_VLDR:
7932	  po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
7933	  break;
7934	try_sysreg:
7935	  val = parse_sys_vldr_vstr (&str);
7936	  break;
7937
7938	case OP_APSR_RR:
7939	  po_reg_or_goto (REG_TYPE_RN, try_apsr);
7940	  break;
7941	  try_apsr:
7942	  /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7943	     instruction).  */
7944	  if (strncasecmp (str, "APSR_", 5) == 0)
7945	    {
7946	      unsigned found = 0;
7947	      str += 5;
7948	      while (found < 15)
7949		switch (*str++)
7950		  {
7951		  case 'c': found = (found & 1) ? 16 : found | 1; break;
7952		  case 'n': found = (found & 2) ? 16 : found | 2; break;
7953		  case 'z': found = (found & 4) ? 16 : found | 4; break;
7954		  case 'v': found = (found & 8) ? 16 : found | 8; break;
7955		  default: found = 16;
7956		  }
7957	      if (found != 15)
7958		goto failure;
7959	      inst.operands[i].isvec = 1;
7960	      /* APSR_nzcv is encoded in instructions as if it were the REG_PC.  */
7961	      inst.operands[i].reg = REG_PC;
7962	    }
7963	  else
7964	    goto failure;
7965	  break;
7966
7967	case OP_TB:
7968	  po_misc_or_fail (parse_tb (&str));
7969	  break;
7970
7971	  /* Register lists.  */
7972	case OP_REGLST:
7973	  val = parse_reg_list (&str, REGLIST_RN);
7974	  if (*str == '^')
7975	    {
7976	      inst.operands[i].writeback = 1;
7977	      str++;
7978	    }
7979	  break;
7980
7981	case OP_CLRMLST:
7982	  val = parse_reg_list (&str, REGLIST_CLRM);
7983	  break;
7984
7985	case OP_VRSLST:
7986	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7987				    &partial_match);
7988	  break;
7989
7990	case OP_VRDLST:
7991	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7992				    &partial_match);
7993	  break;
7994
7995	case OP_VRSDLST:
7996	  /* Allow Q registers too.  */
7997	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7998				    REGLIST_NEON_D, &partial_match);
7999	  if (val == FAIL)
8000	    {
8001	      inst.error = NULL;
8002	      val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
8003					REGLIST_VFP_S, &partial_match);
8004	      inst.operands[i].issingle = 1;
8005	    }
8006	  break;
8007
8008	case OP_VRSDVLST:
8009	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
8010				    REGLIST_VFP_D_VPR, &partial_match);
8011	  if (val == FAIL && !partial_match)
8012	    {
8013	      inst.error = NULL;
8014	      val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
8015					REGLIST_VFP_S_VPR, &partial_match);
8016	      inst.operands[i].issingle = 1;
8017	    }
8018	  break;
8019
8020	case OP_NRDLST:
8021	  val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
8022				    REGLIST_NEON_D, &partial_match);
8023	  break;
8024
8025	case OP_MSTRLST4:
8026	case OP_MSTRLST2:
8027	  val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
8028					   1, &inst.operands[i].vectype);
8029	  if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
8030	    goto failure;
8031	  break;
8032	case OP_NSTRLST:
8033	  val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
8034					   0, &inst.operands[i].vectype);
8035	  break;
8036
8037	  /* Addressing modes */
8038	case OP_ADDRMVE:
8039	  po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
8040	  break;
8041
8042	case OP_ADDR:
8043	  po_misc_or_fail (parse_address (&str, i));
8044	  break;
8045
8046	case OP_ADDRGLDR:
8047	  po_misc_or_fail_no_backtrack (
8048	    parse_address_group_reloc (&str, i, GROUP_LDR));
8049	  break;
8050
8051	case OP_ADDRGLDRS:
8052	  po_misc_or_fail_no_backtrack (
8053	    parse_address_group_reloc (&str, i, GROUP_LDRS));
8054	  break;
8055
8056	case OP_ADDRGLDC:
8057	  po_misc_or_fail_no_backtrack (
8058	    parse_address_group_reloc (&str, i, GROUP_LDC));
8059	  break;
8060
8061	case OP_SH:
8062	  po_misc_or_fail (parse_shifter_operand (&str, i));
8063	  break;
8064
8065	case OP_SHG:
8066	  po_misc_or_fail_no_backtrack (
8067	    parse_shifter_operand_group_reloc (&str, i));
8068	  break;
8069
8070	case OP_oSHll:
8071	  po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
8072	  break;
8073
8074	case OP_oSHar:
8075	  po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
8076	  break;
8077
8078	case OP_oSHllar:
8079	  po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
8080	  break;
8081
8082	case OP_RMQRZ:
8083	case OP_oRMQRZ:
8084	  po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
8085	  break;
8086
8087	case OP_RR_ZR:
8088	try_rr_zr:
8089	  po_reg_or_goto (REG_TYPE_RN, ZR);
8090	  break;
8091	ZR:
8092	  po_reg_or_fail (REG_TYPE_ZR);
8093	  break;
8094
8095	default:
8096	  as_fatal (_("unhandled operand code %d"), op_parse_code);
8097	}
8098
8099      /* Various value-based sanity checks and shared operations.  We
8100	 do not signal immediate failures for the register constraints;
8101	 this allows a syntax error to take precedence.	 */
8102      switch (op_parse_code)
8103	{
8104	case OP_oRRnpc:
8105	case OP_RRnpc:
8106	case OP_RRnpcb:
8107	case OP_RRw:
8108	case OP_oRRw:
8109	case OP_RRnpc_I0:
8110	  if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
8111	    inst.error = BAD_PC;
8112	  break;
8113
8114	case OP_oRRnpcsp:
8115	case OP_RRnpcsp:
8116	case OP_RRnpcsp_I32:
8117	  if (inst.operands[i].isreg)
8118	    {
8119	      if (inst.operands[i].reg == REG_PC)
8120		inst.error = BAD_PC;
8121	      else if (inst.operands[i].reg == REG_SP
8122		       /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8123			  relaxed since ARMv8-A.  */
8124		       && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8125		{
8126		  gas_assert (thumb);
8127		  inst.error = BAD_SP;
8128		}
8129	    }
8130	  break;
8131
8132	case OP_RRnpctw:
8133	  if (inst.operands[i].isreg
8134	      && inst.operands[i].reg == REG_PC
8135	      && (inst.operands[i].writeback || thumb))
8136	    inst.error = BAD_PC;
8137	  break;
8138
8139	case OP_RVSD_COND:
8140	case OP_VLDR:
8141	  if (inst.operands[i].isreg)
8142	    break;
8143	/* fall through.  */
8144
8145	case OP_CPSF:
8146	case OP_ENDI:
8147	case OP_oROR:
8148	case OP_wPSR:
8149	case OP_rPSR:
8150	case OP_COND:
8151	case OP_oBARRIER_I15:
8152	case OP_REGLST:
8153	case OP_CLRMLST:
8154	case OP_VRSLST:
8155	case OP_VRDLST:
8156	case OP_VRSDLST:
8157	case OP_VRSDVLST:
8158	case OP_NRDLST:
8159	case OP_NSTRLST:
8160	case OP_MSTRLST2:
8161	case OP_MSTRLST4:
8162	  if (val == FAIL)
8163	    goto failure;
8164	  inst.operands[i].imm = val;
8165	  break;
8166
8167	case OP_LR:
8168	case OP_oLR:
8169	  if (inst.operands[i].reg != REG_LR)
8170	    inst.error = _("operand must be LR register");
8171	  break;
8172
8173	case OP_SP:
8174	  if (inst.operands[i].reg != REG_SP)
8175	    inst.error = _("operand must be SP register");
8176	  break;
8177
8178	case OP_R12:
8179	  if (inst.operands[i].reg != REG_R12)
8180	    inst.error = _("operand must be r12");
8181	  break;
8182
8183	case OP_RMQRZ:
8184	case OP_oRMQRZ:
8185	case OP_RR_ZR:
8186	  if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
8187	    inst.error = BAD_PC;
8188	  break;
8189
8190	case OP_RRe:
8191	  if (inst.operands[i].isreg
8192	      && (inst.operands[i].reg & 0x00000001) != 0)
8193	    inst.error = BAD_ODD;
8194	  break;
8195
8196	case OP_RRo:
8197	  if (inst.operands[i].isreg)
8198	    {
8199	      if ((inst.operands[i].reg & 0x00000001) != 1)
8200		inst.error = BAD_EVEN;
8201	      else if (inst.operands[i].reg == REG_SP)
8202		as_tsktsk (MVE_BAD_SP);
8203	      else if (inst.operands[i].reg == REG_PC)
8204		inst.error = BAD_PC;
8205	    }
8206	  break;
8207
8208	default:
8209	  break;
8210	}
8211
8212      /* If we get here, this operand was successfully parsed.	*/
8213      inst.operands[i].present = 1;
8214      continue;
8215
8216    bad_args:
8217      inst.error = BAD_ARGS;
8218
8219    failure:
8220      if (!backtrack_pos)
8221	{
8222	  /* The parse routine should already have set inst.error, but set a
8223	     default here just in case.  */
8224	  if (!inst.error)
8225	    inst.error = BAD_SYNTAX;
8226	  return FAIL;
8227	}
8228
8229      /* Do not backtrack over a trailing optional argument that
8230	 absorbed some text.  We will only fail again, with the
8231	 'garbage following instruction' error message, which is
8232	 probably less helpful than the current one.  */
8233      if (backtrack_index == i && backtrack_pos != str
8234	  && upat[i+1] == OP_stop)
8235	{
8236	  if (!inst.error)
8237	    inst.error = BAD_SYNTAX;
8238	  return FAIL;
8239	}
8240
8241      /* Try again, skipping the optional argument at backtrack_pos.  */
8242      str = backtrack_pos;
8243      inst.error = backtrack_error;
8244      inst.operands[backtrack_index].present = 0;
8245      i = backtrack_index;
8246      backtrack_pos = 0;
8247    }
8248
8249  /* Check that we have parsed all the arguments.  */
8250  if (*str != '\0' && !inst.error)
8251    inst.error = _("garbage following instruction");
8252
8253  return inst.error ? FAIL : SUCCESS;
8254}
8255
8256#undef po_char_or_fail
8257#undef po_reg_or_fail
8258#undef po_reg_or_goto
8259#undef po_imm_or_fail
8260#undef po_scalar_or_fail
8261#undef po_barrier_or_imm
8262
8263/* Shorthand macro for instruction encoding functions issuing errors.  */
8264#define constraint(expr, err)			\
8265  do						\
8266    {						\
8267      if (expr)					\
8268	{					\
8269	  inst.error = err;			\
8270	  return;				\
8271	}					\
8272    }						\
8273  while (0)
8274
8275/* Reject "bad registers" for Thumb-2 instructions.  Many Thumb-2
8276   instructions are unpredictable if these registers are used.  This
8277   is the BadReg predicate in ARM's Thumb-2 documentation.
8278
8279   Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8280   places, while the restriction on REG_SP was relaxed since ARMv8-A.  */
8281#define reject_bad_reg(reg)					\
8282  do								\
8283   if (reg == REG_PC)						\
8284     {								\
8285       inst.error = BAD_PC;					\
8286       return;							\
8287     }								\
8288   else if (reg == REG_SP					\
8289	    && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))	\
8290     {								\
8291       inst.error = BAD_SP;					\
8292       return;							\
8293     }								\
8294  while (0)
8295
8296/* If REG is R13 (the stack pointer), warn that its use is
8297   deprecated.  */
8298#define warn_deprecated_sp(reg)			\
8299  do						\
8300    if (warn_on_deprecated && reg == REG_SP)	\
8301       as_tsktsk (_("use of r13 is deprecated"));	\
8302  while (0)
8303
8304/* Functions for operand encoding.  ARM, then Thumb.  */
8305
8306#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8307
8308/* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8309
8310   The only binary encoding difference is the Coprocessor number.  Coprocessor
8311   9 is used for half-precision calculations or conversions.  The format of the
8312   instruction is the same as the equivalent Coprocessor 10 instruction that
8313   exists for Single-Precision operation.  */
8314
8315static void
8316do_scalar_fp16_v82_encode (void)
8317{
8318  if (inst.cond < COND_ALWAYS)
8319    as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8320	       " the behaviour is UNPREDICTABLE"));
8321  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
8322	      _(BAD_FP16));
8323
8324  inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
8325  mark_feature_used (&arm_ext_fp16);
8326}
8327
8328/* If VAL can be encoded in the immediate field of an ARM instruction,
8329   return the encoded form.  Otherwise, return FAIL.  */
8330
8331static unsigned int
8332encode_arm_immediate (unsigned int val)
8333{
8334  unsigned int a, i;
8335
8336  if (val <= 0xff)
8337    return val;
8338
8339  for (i = 2; i < 32; i += 2)
8340    if ((a = rotate_left (val, i)) <= 0xff)
8341      return a | (i << 7); /* 12-bit pack: [shift-cnt,const].  */
8342
8343  return FAIL;
8344}
8345
8346/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8347   return the encoded form.  Otherwise, return FAIL.  */
8348static unsigned int
8349encode_thumb32_immediate (unsigned int val)
8350{
8351  unsigned int a, i;
8352
8353  if (val <= 0xff)
8354    return val;
8355
8356  for (i = 1; i <= 24; i++)
8357    {
8358      a = val >> i;
8359      if ((val & ~(0xffU << i)) == 0)
8360	return ((val >> i) & 0x7f) | ((32 - i) << 7);
8361    }
8362
8363  a = val & 0xff;
8364  if (val == ((a << 16) | a))
8365    return 0x100 | a;
8366  if (val == ((a << 24) | (a << 16) | (a << 8) | a))
8367    return 0x300 | a;
8368
8369  a = val & 0xff00;
8370  if (val == ((a << 16) | a))
8371    return 0x200 | (a >> 8);
8372
8373  return FAIL;
8374}
8375/* Encode a VFP SP or DP register number into inst.instruction.  */
8376
8377static void
8378encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
8379{
8380  if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
8381      && reg > 15)
8382    {
8383      if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
8384	{
8385	  if (thumb_mode)
8386	    ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8387				    fpu_vfp_ext_d32);
8388	  else
8389	    ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8390				    fpu_vfp_ext_d32);
8391	}
8392      else
8393	{
8394	  first_error (_("D register out of range for selected VFP version"));
8395	  return;
8396	}
8397    }
8398
8399  switch (pos)
8400    {
8401    case VFP_REG_Sd:
8402      inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8403      break;
8404
8405    case VFP_REG_Sn:
8406      inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8407      break;
8408
8409    case VFP_REG_Sm:
8410      inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8411      break;
8412
8413    case VFP_REG_Dd:
8414      inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8415      break;
8416
8417    case VFP_REG_Dn:
8418      inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8419      break;
8420
8421    case VFP_REG_Dm:
8422      inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8423      break;
8424
8425    default:
8426      abort ();
8427    }
8428}
8429
8430/* Encode a <shift> in an ARM-format instruction.  The immediate,
8431   if any, is handled by md_apply_fix.	 */
8432static void
8433encode_arm_shift (int i)
8434{
8435  /* register-shifted register.  */
8436  if (inst.operands[i].immisreg)
8437    {
8438      int op_index;
8439      for (op_index = 0; op_index <= i; ++op_index)
8440	{
8441	  /* Check the operand only when it's presented.  In pre-UAL syntax,
8442	     if the destination register is the same as the first operand, two
8443	     register form of the instruction can be used.  */
8444	  if (inst.operands[op_index].present && inst.operands[op_index].isreg
8445	      && inst.operands[op_index].reg == REG_PC)
8446	    as_warn (UNPRED_REG ("r15"));
8447	}
8448
8449      if (inst.operands[i].imm == REG_PC)
8450	as_warn (UNPRED_REG ("r15"));
8451    }
8452
8453  if (inst.operands[i].shift_kind == SHIFT_RRX)
8454    inst.instruction |= SHIFT_ROR << 5;
8455  else
8456    {
8457      inst.instruction |= inst.operands[i].shift_kind << 5;
8458      if (inst.operands[i].immisreg)
8459	{
8460	  inst.instruction |= SHIFT_BY_REG;
8461	  inst.instruction |= inst.operands[i].imm << 8;
8462	}
8463      else
8464	inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8465    }
8466}
8467
8468static void
8469encode_arm_shifter_operand (int i)
8470{
8471  if (inst.operands[i].isreg)
8472    {
8473      inst.instruction |= inst.operands[i].reg;
8474      encode_arm_shift (i);
8475    }
8476  else
8477    {
8478      inst.instruction |= INST_IMMEDIATE;
8479      if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
8480	inst.instruction |= inst.operands[i].imm;
8481    }
8482}
8483
8484/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3.  */
8485static void
8486encode_arm_addr_mode_common (int i, bool is_t)
8487{
8488  /* PR 14260:
8489     Generate an error if the operand is not a register.  */
8490  constraint (!inst.operands[i].isreg,
8491	      _("Instruction does not support =N addresses"));
8492
8493  inst.instruction |= inst.operands[i].reg << 16;
8494
8495  if (inst.operands[i].preind)
8496    {
8497      if (is_t)
8498	{
8499	  inst.error = _("instruction does not accept preindexed addressing");
8500	  return;
8501	}
8502      inst.instruction |= PRE_INDEX;
8503      if (inst.operands[i].writeback)
8504	inst.instruction |= WRITE_BACK;
8505
8506    }
8507  else if (inst.operands[i].postind)
8508    {
8509      gas_assert (inst.operands[i].writeback);
8510      if (is_t)
8511	inst.instruction |= WRITE_BACK;
8512    }
8513  else /* unindexed - only for coprocessor */
8514    {
8515      inst.error = _("instruction does not accept unindexed addressing");
8516      return;
8517    }
8518
8519  if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8520      && (((inst.instruction & 0x000f0000) >> 16)
8521	  == ((inst.instruction & 0x0000f000) >> 12)))
8522    as_warn ((inst.instruction & LOAD_BIT)
8523	     ? _("destination register same as write-back base")
8524	     : _("source register same as write-back base"));
8525}
8526
8527/* inst.operands[i] was set up by parse_address.  Encode it into an
8528   ARM-format mode 2 load or store instruction.	 If is_t is true,
8529   reject forms that cannot be used with a T instruction (i.e. not
8530   post-indexed).  */
8531static void
8532encode_arm_addr_mode_2 (int i, bool is_t)
8533{
8534  const bool is_pc = (inst.operands[i].reg == REG_PC);
8535
8536  encode_arm_addr_mode_common (i, is_t);
8537
8538  if (inst.operands[i].immisreg)
8539    {
8540      constraint ((inst.operands[i].imm == REG_PC
8541		   || (is_pc && inst.operands[i].writeback)),
8542		  BAD_PC_ADDRESSING);
8543      inst.instruction |= INST_IMMEDIATE;  /* yes, this is backwards */
8544      inst.instruction |= inst.operands[i].imm;
8545      if (!inst.operands[i].negative)
8546	inst.instruction |= INDEX_UP;
8547      if (inst.operands[i].shifted)
8548	{
8549	  if (inst.operands[i].shift_kind == SHIFT_RRX)
8550	    inst.instruction |= SHIFT_ROR << 5;
8551	  else
8552	    {
8553	      inst.instruction |= inst.operands[i].shift_kind << 5;
8554	      inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
8555	    }
8556	}
8557    }
8558  else /* immediate offset in inst.relocs[0] */
8559    {
8560      if (is_pc && !inst.relocs[0].pc_rel)
8561	{
8562	  const bool is_load = ((inst.instruction & LOAD_BIT) != 0);
8563
8564	  /* If is_t is TRUE, it's called from do_ldstt.  ldrt/strt
8565	     cannot use PC in addressing.
8566	     PC cannot be used in writeback addressing, either.  */
8567	  constraint ((is_t || inst.operands[i].writeback),
8568		      BAD_PC_ADDRESSING);
8569
8570	  /* Use of PC in str is deprecated for ARMv7.  */
8571	  if (warn_on_deprecated
8572	      && !is_load
8573	      && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
8574	    as_tsktsk (_("use of PC in this instruction is deprecated"));
8575	}
8576
8577      if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8578	{
8579	  /* Prefer + for zero encoded value.  */
8580	  if (!inst.operands[i].negative)
8581	    inst.instruction |= INDEX_UP;
8582	  inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
8583	}
8584    }
8585}
8586
8587/* inst.operands[i] was set up by parse_address.  Encode it into an
8588   ARM-format mode 3 load or store instruction.	 Reject forms that
8589   cannot be used with such instructions.  If is_t is true, reject
8590   forms that cannot be used with a T instruction (i.e. not
8591   post-indexed).  */
8592static void
8593encode_arm_addr_mode_3 (int i, bool is_t)
8594{
8595  if (inst.operands[i].immisreg && inst.operands[i].shifted)
8596    {
8597      inst.error = _("instruction does not accept scaled register index");
8598      return;
8599    }
8600
8601  encode_arm_addr_mode_common (i, is_t);
8602
8603  if (inst.operands[i].immisreg)
8604    {
8605      constraint ((inst.operands[i].imm == REG_PC
8606		   || (is_t && inst.operands[i].reg == REG_PC)),
8607		  BAD_PC_ADDRESSING);
8608      constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8609		  BAD_PC_WRITEBACK);
8610      inst.instruction |= inst.operands[i].imm;
8611      if (!inst.operands[i].negative)
8612	inst.instruction |= INDEX_UP;
8613    }
8614  else /* immediate offset in inst.relocs[0] */
8615    {
8616      constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
8617		   && inst.operands[i].writeback),
8618		  BAD_PC_WRITEBACK);
8619      inst.instruction |= HWOFFSET_IMM;
8620      if (inst.relocs[0].type == BFD_RELOC_UNUSED)
8621	{
8622	  /* Prefer + for zero encoded value.  */
8623	  if (!inst.operands[i].negative)
8624	    inst.instruction |= INDEX_UP;
8625
8626	  inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
8627	}
8628    }
8629}
8630
8631/* Write immediate bits [7:0] to the following locations:
8632
8633  |28/24|23     19|18 16|15                    4|3     0|
8634  |  a  |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8635
8636  This function is used by VMOV/VMVN/VORR/VBIC.  */
8637
8638static void
8639neon_write_immbits (unsigned immbits)
8640{
8641  inst.instruction |= immbits & 0xf;
8642  inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8643  inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8644}
8645
8646/* Invert low-order SIZE bits of XHI:XLO.  */
8647
8648static void
8649neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
8650{
8651  unsigned immlo = xlo ? *xlo : 0;
8652  unsigned immhi = xhi ? *xhi : 0;
8653
8654  switch (size)
8655    {
8656    case 8:
8657      immlo = (~immlo) & 0xff;
8658      break;
8659
8660    case 16:
8661      immlo = (~immlo) & 0xffff;
8662      break;
8663
8664    case 64:
8665      immhi = (~immhi) & 0xffffffff;
8666      /* fall through.  */
8667
8668    case 32:
8669      immlo = (~immlo) & 0xffffffff;
8670      break;
8671
8672    default:
8673      abort ();
8674    }
8675
8676  if (xlo)
8677    *xlo = immlo;
8678
8679  if (xhi)
8680    *xhi = immhi;
8681}
8682
8683/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8684   A, B, C, D.  */
8685
8686static int
8687neon_bits_same_in_bytes (unsigned imm)
8688{
8689  return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
8690	 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
8691	 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
8692	 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
8693}
8694
8695/* For immediate of above form, return 0bABCD.  */
8696
8697static unsigned
8698neon_squash_bits (unsigned imm)
8699{
8700  return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
8701	 | ((imm & 0x01000000) >> 21);
8702}
8703
8704/* Compress quarter-float representation to 0b...000 abcdefgh.  */
8705
8706static unsigned
8707neon_qfloat_bits (unsigned imm)
8708{
8709  return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
8710}
8711
8712/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8713   the instruction. *OP is passed as the initial value of the op field, and
8714   may be set to a different value depending on the constant (i.e.
8715   "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8716   MVN).  If the immediate looks like a repeated pattern then also
8717   try smaller element sizes.  */
8718
8719static int
8720neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
8721			 unsigned *immbits, int *op, int size,
8722			 enum neon_el_type type)
8723{
8724  /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8725     float.  */
8726  if (type == NT_float && !float_p)
8727    return FAIL;
8728
8729  if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
8730    {
8731      if (size != 32 || *op == 1)
8732	return FAIL;
8733      *immbits = neon_qfloat_bits (immlo);
8734      return 0xf;
8735    }
8736
8737  if (size == 64)
8738    {
8739      if (neon_bits_same_in_bytes (immhi)
8740	  && neon_bits_same_in_bytes (immlo))
8741	{
8742	  if (*op == 1)
8743	    return FAIL;
8744	  *immbits = (neon_squash_bits (immhi) << 4)
8745		     | neon_squash_bits (immlo);
8746	  *op = 1;
8747	  return 0xe;
8748	}
8749
8750      if (immhi != immlo)
8751	return FAIL;
8752    }
8753
8754  if (size >= 32)
8755    {
8756      if (immlo == (immlo & 0x000000ff))
8757	{
8758	  *immbits = immlo;
8759	  return 0x0;
8760	}
8761      else if (immlo == (immlo & 0x0000ff00))
8762	{
8763	  *immbits = immlo >> 8;
8764	  return 0x2;
8765	}
8766      else if (immlo == (immlo & 0x00ff0000))
8767	{
8768	  *immbits = immlo >> 16;
8769	  return 0x4;
8770	}
8771      else if (immlo == (immlo & 0xff000000))
8772	{
8773	  *immbits = immlo >> 24;
8774	  return 0x6;
8775	}
8776      else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
8777	{
8778	  *immbits = (immlo >> 8) & 0xff;
8779	  return 0xc;
8780	}
8781      else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
8782	{
8783	  *immbits = (immlo >> 16) & 0xff;
8784	  return 0xd;
8785	}
8786
8787      if ((immlo & 0xffff) != (immlo >> 16))
8788	return FAIL;
8789      immlo &= 0xffff;
8790    }
8791
8792  if (size >= 16)
8793    {
8794      if (immlo == (immlo & 0x000000ff))
8795	{
8796	  *immbits = immlo;
8797	  return 0x8;
8798	}
8799      else if (immlo == (immlo & 0x0000ff00))
8800	{
8801	  *immbits = immlo >> 8;
8802	  return 0xa;
8803	}
8804
8805      if ((immlo & 0xff) != (immlo >> 8))
8806	return FAIL;
8807      immlo &= 0xff;
8808    }
8809
8810  if (immlo == (immlo & 0x000000ff))
8811    {
8812      /* Don't allow MVN with 8-bit immediate.  */
8813      if (*op == 1)
8814	return FAIL;
8815      *immbits = immlo;
8816      return 0xe;
8817    }
8818
8819  return FAIL;
8820}
8821
8822/* Returns TRUE if double precision value V may be cast
8823   to single precision without loss of accuracy.  */
8824
8825static bool
8826is_double_a_single (uint64_t v)
8827{
8828  int exp = (v >> 52) & 0x7FF;
8829  uint64_t mantissa = v & 0xFFFFFFFFFFFFFULL;
8830
8831  return ((exp == 0 || exp == 0x7FF
8832	   || (exp >= 1023 - 126 && exp <= 1023 + 127))
8833	  && (mantissa & 0x1FFFFFFFL) == 0);
8834}
8835
8836/* Returns a double precision value casted to single precision
8837   (ignoring the least significant bits in exponent and mantissa).  */
8838
8839static int
8840double_to_single (uint64_t v)
8841{
8842  unsigned int sign = (v >> 63) & 1;
8843  int exp = (v >> 52) & 0x7FF;
8844  uint64_t mantissa = v & 0xFFFFFFFFFFFFFULL;
8845
8846  if (exp == 0x7FF)
8847    exp = 0xFF;
8848  else
8849    {
8850      exp = exp - 1023 + 127;
8851      if (exp >= 0xFF)
8852	{
8853	  /* Infinity.  */
8854	  exp = 0x7F;
8855	  mantissa = 0;
8856	}
8857      else if (exp < 0)
8858	{
8859	  /* No denormalized numbers.  */
8860	  exp = 0;
8861	  mantissa = 0;
8862	}
8863    }
8864  mantissa >>= 29;
8865  return (sign << 31) | (exp << 23) | mantissa;
8866}
8867
8868enum lit_type
8869{
8870  CONST_THUMB,
8871  CONST_ARM,
8872  CONST_VEC
8873};
8874
8875static void do_vfp_nsyn_opcode (const char *);
8876
8877/* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8878   Determine whether it can be performed with a move instruction; if
8879   it can, convert inst.instruction to that move instruction and
8880   return true; if it can't, convert inst.instruction to a literal-pool
8881   load and return FALSE.  If this is not a valid thing to do in the
8882   current context, set inst.error and return TRUE.
8883
8884   inst.operands[i] describes the destination register.	 */
8885
8886static bool
8887move_or_literal_pool (int i, enum lit_type t, bool mode_3)
8888{
8889  unsigned long tbit;
8890  bool thumb_p = (t == CONST_THUMB);
8891  bool arm_p   = (t == CONST_ARM);
8892
8893  if (thumb_p)
8894    tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8895  else
8896    tbit = LOAD_BIT;
8897
8898  if ((inst.instruction & tbit) == 0)
8899    {
8900      inst.error = _("invalid pseudo operation");
8901      return true;
8902    }
8903
8904  if (inst.relocs[0].exp.X_op != O_constant
8905      && inst.relocs[0].exp.X_op != O_symbol
8906      && inst.relocs[0].exp.X_op != O_big)
8907    {
8908      inst.error = _("constant expression expected");
8909      return true;
8910    }
8911
8912  if (inst.relocs[0].exp.X_op == O_constant
8913      || inst.relocs[0].exp.X_op == O_big)
8914    {
8915      uint64_t v;
8916      if (inst.relocs[0].exp.X_op == O_big)
8917	{
8918	  LITTLENUM_TYPE w[X_PRECISION];
8919	  LITTLENUM_TYPE * l;
8920
8921	  if (inst.relocs[0].exp.X_add_number == -1)
8922	    {
8923	      gen_to_words (w, X_PRECISION, E_PRECISION);
8924	      l = w;
8925	      /* FIXME: Should we check words w[2..5] ?  */
8926	    }
8927	  else
8928	    l = generic_bignum;
8929
8930	  v = l[3] & LITTLENUM_MASK;
8931	  v <<= LITTLENUM_NUMBER_OF_BITS;
8932	  v |= l[2] & LITTLENUM_MASK;
8933	  v <<= LITTLENUM_NUMBER_OF_BITS;
8934	  v |= l[1] & LITTLENUM_MASK;
8935	  v <<= LITTLENUM_NUMBER_OF_BITS;
8936	  v |= l[0] & LITTLENUM_MASK;
8937	}
8938      else
8939	v = inst.relocs[0].exp.X_add_number;
8940
8941      if (!inst.operands[i].issingle)
8942	{
8943	  if (thumb_p)
8944	    {
8945	      /* LDR should not use lead in a flag-setting instruction being
8946		 chosen so we do not check whether movs can be used.  */
8947
8948	      if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
8949		  || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8950		  && inst.operands[i].reg != 13
8951		  && inst.operands[i].reg != 15)
8952		{
8953		  /* Check if on thumb2 it can be done with a mov.w, mvn or
8954		     movw instruction.  */
8955		  unsigned int newimm;
8956		  bool isNegated = false;
8957
8958		  newimm = encode_thumb32_immediate (v);
8959		  if (newimm == (unsigned int) FAIL)
8960		    {
8961		      newimm = encode_thumb32_immediate (~v);
8962		      isNegated = true;
8963		    }
8964
8965		  /* The number can be loaded with a mov.w or mvn
8966		     instruction.  */
8967		  if (newimm != (unsigned int) FAIL
8968		      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
8969		    {
8970		      inst.instruction = (0xf04f0000  /*  MOV.W.  */
8971					  | (inst.operands[i].reg << 8));
8972		      /* Change to MOVN.  */
8973		      inst.instruction |= (isNegated ? 0x200000 : 0);
8974		      inst.instruction |= (newimm & 0x800) << 15;
8975		      inst.instruction |= (newimm & 0x700) << 4;
8976		      inst.instruction |= (newimm & 0x0ff);
8977		      return true;
8978		    }
8979		  /* The number can be loaded with a movw instruction.  */
8980		  else if ((v & ~0xFFFF) == 0
8981			   && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
8982		    {
8983		      int imm = v & 0xFFFF;
8984
8985		      inst.instruction = 0xf2400000;  /* MOVW.  */
8986		      inst.instruction |= (inst.operands[i].reg << 8);
8987		      inst.instruction |= (imm & 0xf000) << 4;
8988		      inst.instruction |= (imm & 0x0800) << 15;
8989		      inst.instruction |= (imm & 0x0700) << 4;
8990		      inst.instruction |= (imm & 0x00ff);
8991		      /*  In case this replacement is being done on Armv8-M
8992			  Baseline we need to make sure to disable the
8993			  instruction size check, as otherwise GAS will reject
8994			  the use of this T32 instruction.  */
8995		      inst.size_req = 0;
8996		      return true;
8997		    }
8998		}
8999	    }
9000	  else if (arm_p)
9001	    {
9002	      int value = encode_arm_immediate (v);
9003
9004	      if (value != FAIL)
9005		{
9006		  /* This can be done with a mov instruction.  */
9007		  inst.instruction &= LITERAL_MASK;
9008		  inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
9009		  inst.instruction |= value & 0xfff;
9010		  return true;
9011		}
9012
9013	      value = encode_arm_immediate (~ v);
9014	      if (value != FAIL)
9015		{
9016		  /* This can be done with a mvn instruction.  */
9017		  inst.instruction &= LITERAL_MASK;
9018		  inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
9019		  inst.instruction |= value & 0xfff;
9020		  return true;
9021		}
9022	    }
9023	  else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
9024	    {
9025	      int op = 0;
9026	      unsigned immbits = 0;
9027	      unsigned immlo = inst.operands[1].imm;
9028	      unsigned immhi = inst.operands[1].regisimm
9029		? inst.operands[1].reg
9030		: inst.relocs[0].exp.X_unsigned
9031		? 0
9032		: (int64_t) (int) immlo >> 32;
9033	      int cmode = neon_cmode_for_move_imm (immlo, immhi, false, &immbits,
9034						   &op, 64, NT_invtype);
9035
9036	      if (cmode == FAIL)
9037		{
9038		  neon_invert_size (&immlo, &immhi, 64);
9039		  op = !op;
9040		  cmode = neon_cmode_for_move_imm (immlo, immhi, false, &immbits,
9041						   &op, 64, NT_invtype);
9042		}
9043
9044	      if (cmode != FAIL)
9045		{
9046		  inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
9047		    | (1 << 23)
9048		    | (cmode << 8)
9049		    | (op << 5)
9050		    | (1 << 4);
9051
9052		  /* Fill other bits in vmov encoding for both thumb and arm.  */
9053		  if (thumb_mode)
9054		    inst.instruction |= (0x7U << 29) | (0xF << 24);
9055		  else
9056		    inst.instruction |= (0xFU << 28) | (0x1 << 25);
9057		  neon_write_immbits (immbits);
9058		  return true;
9059		}
9060	    }
9061	}
9062
9063      if (t == CONST_VEC)
9064	{
9065	  /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant.  */
9066	  if (inst.operands[i].issingle
9067	      && is_quarter_float (inst.operands[1].imm)
9068	      && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
9069	    {
9070	      inst.operands[1].imm =
9071		neon_qfloat_bits (v);
9072	      do_vfp_nsyn_opcode ("fconsts");
9073	      return true;
9074	    }
9075
9076	  /* If our host does not support a 64-bit type then we cannot perform
9077	     the following optimization.  This mean that there will be a
9078	     discrepancy between the output produced by an assembler built for
9079	     a 32-bit-only host and the output produced from a 64-bit host, but
9080	     this cannot be helped.  */
9081	  else if (!inst.operands[1].issingle
9082		   && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
9083	    {
9084	      if (is_double_a_single (v)
9085		  && is_quarter_float (double_to_single (v)))
9086		{
9087		  inst.operands[1].imm =
9088		    neon_qfloat_bits (double_to_single (v));
9089		  do_vfp_nsyn_opcode ("fconstd");
9090		  return true;
9091		}
9092	    }
9093	}
9094    }
9095
9096  if (add_to_lit_pool ((!inst.operands[i].isvec
9097			|| inst.operands[i].issingle) ? 4 : 8) == FAIL)
9098    return true;
9099
9100  inst.operands[1].reg = REG_PC;
9101  inst.operands[1].isreg = 1;
9102  inst.operands[1].preind = 1;
9103  inst.relocs[0].pc_rel = 1;
9104  inst.relocs[0].type = (thumb_p
9105		     ? BFD_RELOC_ARM_THUMB_OFFSET
9106		     : (mode_3
9107			? BFD_RELOC_ARM_HWLITERAL
9108			: BFD_RELOC_ARM_LITERAL));
9109  return false;
9110}
9111
9112/* inst.operands[i] was set up by parse_address.  Encode it into an
9113   ARM-format instruction.  Reject all forms which cannot be encoded
9114   into a coprocessor load/store instruction.  If wb_ok is false,
9115   reject use of writeback; if unind_ok is false, reject use of
9116   unindexed addressing.  If reloc_override is not 0, use it instead
9117   of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9118   (in which case it is preserved).  */
9119
9120static int
9121encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
9122{
9123  if (!inst.operands[i].isreg)
9124    {
9125      /* PR 18256 */
9126      if (! inst.operands[0].isvec)
9127	{
9128	  inst.error = _("invalid co-processor operand");
9129	  return FAIL;
9130	}
9131      if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/false))
9132	return SUCCESS;
9133    }
9134
9135  inst.instruction |= inst.operands[i].reg << 16;
9136
9137  gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
9138
9139  if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
9140    {
9141      gas_assert (!inst.operands[i].writeback);
9142      if (!unind_ok)
9143	{
9144	  inst.error = _("instruction does not support unindexed addressing");
9145	  return FAIL;
9146	}
9147      inst.instruction |= inst.operands[i].imm;
9148      inst.instruction |= INDEX_UP;
9149      return SUCCESS;
9150    }
9151
9152  if (inst.operands[i].preind)
9153    inst.instruction |= PRE_INDEX;
9154
9155  if (inst.operands[i].writeback)
9156    {
9157      if (inst.operands[i].reg == REG_PC)
9158	{
9159	  inst.error = _("pc may not be used with write-back");
9160	  return FAIL;
9161	}
9162      if (!wb_ok)
9163	{
9164	  inst.error = _("instruction does not support writeback");
9165	  return FAIL;
9166	}
9167      inst.instruction |= WRITE_BACK;
9168    }
9169
9170  if (reloc_override)
9171    inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
9172  else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
9173	    || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
9174	   && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
9175    {
9176      if (thumb_mode)
9177	inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
9178      else
9179	inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
9180    }
9181
9182  /* Prefer + for zero encoded value.  */
9183  if (!inst.operands[i].negative)
9184    inst.instruction |= INDEX_UP;
9185
9186  return SUCCESS;
9187}
9188
9189/* Functions for instruction encoding, sorted by sub-architecture.
9190   First some generics; their names are taken from the conventional
9191   bit positions for register arguments in ARM format instructions.  */
9192
9193static void
9194do_noargs (void)
9195{
9196}
9197
9198static void
9199do_rd (void)
9200{
9201  inst.instruction |= inst.operands[0].reg << 12;
9202}
9203
9204static void
9205do_rn (void)
9206{
9207  inst.instruction |= inst.operands[0].reg << 16;
9208}
9209
9210static void
9211do_rd_rm (void)
9212{
9213  inst.instruction |= inst.operands[0].reg << 12;
9214  inst.instruction |= inst.operands[1].reg;
9215}
9216
9217static void
9218do_rm_rn (void)
9219{
9220  inst.instruction |= inst.operands[0].reg;
9221  inst.instruction |= inst.operands[1].reg << 16;
9222}
9223
9224static void
9225do_rd_rn (void)
9226{
9227  inst.instruction |= inst.operands[0].reg << 12;
9228  inst.instruction |= inst.operands[1].reg << 16;
9229}
9230
9231static void
9232do_rn_rd (void)
9233{
9234  inst.instruction |= inst.operands[0].reg << 16;
9235  inst.instruction |= inst.operands[1].reg << 12;
9236}
9237
9238static void
9239do_tt (void)
9240{
9241  inst.instruction |= inst.operands[0].reg << 8;
9242  inst.instruction |= inst.operands[1].reg << 16;
9243}
9244
9245static bool
9246check_obsolete (const arm_feature_set *feature, const char *msg)
9247{
9248  if (ARM_CPU_IS_ANY (cpu_variant))
9249    {
9250      as_tsktsk ("%s", msg);
9251      return true;
9252    }
9253  else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
9254    {
9255      as_bad ("%s", msg);
9256      return true;
9257    }
9258
9259  return false;
9260}
9261
9262static void
9263do_rd_rm_rn (void)
9264{
9265  unsigned Rn = inst.operands[2].reg;
9266  /* Enforce restrictions on SWP instruction.  */
9267  if ((inst.instruction & 0x0fbfffff) == 0x01000090)
9268    {
9269      constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
9270		  _("Rn must not overlap other operands"));
9271
9272      /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9273       */
9274      if (!check_obsolete (&arm_ext_v8,
9275			   _("swp{b} use is obsoleted for ARMv8 and later"))
9276	  && warn_on_deprecated
9277	  && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
9278	as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9279    }
9280
9281  inst.instruction |= inst.operands[0].reg << 12;
9282  inst.instruction |= inst.operands[1].reg;
9283  inst.instruction |= Rn << 16;
9284}
9285
9286static void
9287do_rd_rn_rm (void)
9288{
9289  inst.instruction |= inst.operands[0].reg << 12;
9290  inst.instruction |= inst.operands[1].reg << 16;
9291  inst.instruction |= inst.operands[2].reg;
9292}
9293
9294static void
9295do_rm_rd_rn (void)
9296{
9297  constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
9298  constraint (((inst.relocs[0].exp.X_op != O_constant
9299		&& inst.relocs[0].exp.X_op != O_illegal)
9300	       || inst.relocs[0].exp.X_add_number != 0),
9301	      BAD_ADDR_MODE);
9302  inst.instruction |= inst.operands[0].reg;
9303  inst.instruction |= inst.operands[1].reg << 12;
9304  inst.instruction |= inst.operands[2].reg << 16;
9305}
9306
9307static void
9308do_imm0 (void)
9309{
9310  inst.instruction |= inst.operands[0].imm;
9311}
9312
9313static void
9314do_rd_cpaddr (void)
9315{
9316  inst.instruction |= inst.operands[0].reg << 12;
9317  encode_arm_cp_address (1, true, true, 0);
9318}
9319
9320/* ARM instructions, in alphabetical order by function name (except
9321   that wrapper functions appear immediately after the function they
9322   wrap).  */
9323
9324/* This is a pseudo-op of the form "adr rd, label" to be converted
9325   into a relative address of the form "add rd, pc, #label-.-8".  */
9326
9327static void
9328do_adr (void)
9329{
9330  inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */
9331
9332  /* Frag hacking will turn this into a sub instruction if the offset turns
9333     out to be negative.  */
9334  inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9335  inst.relocs[0].pc_rel = 1;
9336  inst.relocs[0].exp.X_add_number -= 8;
9337
9338  if (support_interwork
9339      && inst.relocs[0].exp.X_op == O_symbol
9340      && inst.relocs[0].exp.X_add_symbol != NULL
9341      && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9342      && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9343    inst.relocs[0].exp.X_add_number |= 1;
9344}
9345
9346/* This is a pseudo-op of the form "adrl rd, label" to be converted
9347   into a relative address of the form:
9348   add rd, pc, #low(label-.-8)"
9349   add rd, rd, #high(label-.-8)"  */
9350
9351static void
9352do_adrl (void)
9353{
9354  inst.instruction |= (inst.operands[0].reg << 12);  /* Rd */
9355
9356  /* Frag hacking will turn this into a sub instruction if the offset turns
9357     out to be negative.  */
9358  inst.relocs[0].type	       = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9359  inst.relocs[0].pc_rel	       = 1;
9360  inst.size		       = INSN_SIZE * 2;
9361  inst.relocs[0].exp.X_add_number -= 8;
9362
9363  if (support_interwork
9364      && inst.relocs[0].exp.X_op == O_symbol
9365      && inst.relocs[0].exp.X_add_symbol != NULL
9366      && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9367      && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9368    inst.relocs[0].exp.X_add_number |= 1;
9369}
9370
9371static void
9372do_arit (void)
9373{
9374  constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9375	      && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
9376	      THUMB1_RELOC_ONLY);
9377  if (!inst.operands[1].present)
9378    inst.operands[1].reg = inst.operands[0].reg;
9379  inst.instruction |= inst.operands[0].reg << 12;
9380  inst.instruction |= inst.operands[1].reg << 16;
9381  encode_arm_shifter_operand (2);
9382}
9383
9384static void
9385do_barrier (void)
9386{
9387  if (inst.operands[0].present)
9388    inst.instruction |= inst.operands[0].imm;
9389  else
9390    inst.instruction |= 0xf;
9391}
9392
9393static void
9394do_bfc (void)
9395{
9396  unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9397  constraint (msb > 32, _("bit-field extends past end of register"));
9398  /* The instruction encoding stores the LSB and MSB,
9399     not the LSB and width.  */
9400  inst.instruction |= inst.operands[0].reg << 12;
9401  inst.instruction |= inst.operands[1].imm << 7;
9402  inst.instruction |= (msb - 1) << 16;
9403}
9404
9405static void
9406do_bfi (void)
9407{
9408  unsigned int msb;
9409
9410  /* #0 in second position is alternative syntax for bfc, which is
9411     the same instruction but with REG_PC in the Rm field.  */
9412  if (!inst.operands[1].isreg)
9413    inst.operands[1].reg = REG_PC;
9414
9415  msb = inst.operands[2].imm + inst.operands[3].imm;
9416  constraint (msb > 32, _("bit-field extends past end of register"));
9417  /* The instruction encoding stores the LSB and MSB,
9418     not the LSB and width.  */
9419  inst.instruction |= inst.operands[0].reg << 12;
9420  inst.instruction |= inst.operands[1].reg;
9421  inst.instruction |= inst.operands[2].imm << 7;
9422  inst.instruction |= (msb - 1) << 16;
9423}
9424
9425static void
9426do_bfx (void)
9427{
9428  constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9429	      _("bit-field extends past end of register"));
9430  inst.instruction |= inst.operands[0].reg << 12;
9431  inst.instruction |= inst.operands[1].reg;
9432  inst.instruction |= inst.operands[2].imm << 7;
9433  inst.instruction |= (inst.operands[3].imm - 1) << 16;
9434}
9435
9436/* ARM V5 breakpoint instruction (argument parse)
9437     BKPT <16 bit unsigned immediate>
9438     Instruction is not conditional.
9439	The bit pattern given in insns[] has the COND_ALWAYS condition,
9440	and it is an error if the caller tried to override that.  */
9441
9442static void
9443do_bkpt (void)
9444{
9445  /* Top 12 of 16 bits to bits 19:8.  */
9446  inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
9447
9448  /* Bottom 4 of 16 bits to bits 3:0.  */
9449  inst.instruction |= inst.operands[0].imm & 0xf;
9450}
9451
9452static void
9453encode_branch (int default_reloc)
9454{
9455  if (inst.operands[0].hasreloc)
9456    {
9457      constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9458		  && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9459		  _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9460      inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
9461	? BFD_RELOC_ARM_PLT32
9462	: thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
9463    }
9464  else
9465    inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9466  inst.relocs[0].pc_rel = 1;
9467}
9468
9469static void
9470do_branch (void)
9471{
9472#ifdef OBJ_ELF
9473  if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9474    encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9475  else
9476#endif
9477    encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9478}
9479
9480static void
9481do_bl (void)
9482{
9483#ifdef OBJ_ELF
9484  if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9485    {
9486      if (inst.cond == COND_ALWAYS)
9487	encode_branch (BFD_RELOC_ARM_PCREL_CALL);
9488      else
9489	encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9490    }
9491  else
9492#endif
9493    encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9494}
9495
9496/* ARM V5 branch-link-exchange instruction (argument parse)
9497     BLX <target_addr>		ie BLX(1)
9498     BLX{<condition>} <Rm>	ie BLX(2)
9499   Unfortunately, there are two different opcodes for this mnemonic.
9500   So, the insns[].value is not used, and the code here zaps values
9501	into inst.instruction.
9502   Also, the <target_addr> can be 25 bits, hence has its own reloc.  */
9503
9504static void
9505do_blx (void)
9506{
9507  if (inst.operands[0].isreg)
9508    {
9509      /* Arg is a register; the opcode provided by insns[] is correct.
9510	 It is not illegal to do "blx pc", just useless.  */
9511      if (inst.operands[0].reg == REG_PC)
9512	as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9513
9514      inst.instruction |= inst.operands[0].reg;
9515    }
9516  else
9517    {
9518      /* Arg is an address; this instruction cannot be executed
9519	 conditionally, and the opcode must be adjusted.
9520	 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9521	 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead.  */
9522      constraint (inst.cond != COND_ALWAYS, BAD_COND);
9523      inst.instruction = 0xfa000000;
9524      encode_branch (BFD_RELOC_ARM_PCREL_BLX);
9525    }
9526}
9527
9528static void
9529do_bx (void)
9530{
9531  bool want_reloc;
9532
9533  if (inst.operands[0].reg == REG_PC)
9534    as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9535
9536  inst.instruction |= inst.operands[0].reg;
9537  /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9538     it is for ARMv4t or earlier.  */
9539  want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
9540  if (!ARM_FEATURE_ZERO (selected_object_arch)
9541      && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
9542      want_reloc = true;
9543
9544#ifdef OBJ_ELF
9545  if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
9546#endif
9547    want_reloc = false;
9548
9549  if (want_reloc)
9550    inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
9551}
9552
9553
9554/* ARM v5TEJ.  Jump to Jazelle code.  */
9555
9556static void
9557do_bxj (void)
9558{
9559  if (inst.operands[0].reg == REG_PC)
9560    as_tsktsk (_("use of r15 in bxj is not really useful"));
9561
9562  inst.instruction |= inst.operands[0].reg;
9563}
9564
9565/* Co-processor data operation:
9566      CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9567      CDP2	<coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}	 */
9568static void
9569do_cdp (void)
9570{
9571  inst.instruction |= inst.operands[0].reg << 8;
9572  inst.instruction |= inst.operands[1].imm << 20;
9573  inst.instruction |= inst.operands[2].reg << 12;
9574  inst.instruction |= inst.operands[3].reg << 16;
9575  inst.instruction |= inst.operands[4].reg;
9576  inst.instruction |= inst.operands[5].imm << 5;
9577}
9578
9579static void
9580do_cmp (void)
9581{
9582  inst.instruction |= inst.operands[0].reg << 16;
9583  encode_arm_shifter_operand (1);
9584}
9585
9586/* Transfer between coprocessor and ARM registers.
9587   MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9588   MRC2
9589   MCR{cond}
9590   MCR2
9591
9592   No special properties.  */
9593
9594struct deprecated_coproc_regs_s
9595{
9596  unsigned cp;
9597  int opc1;
9598  unsigned crn;
9599  unsigned crm;
9600  int opc2;
9601  arm_feature_set deprecated;
9602  arm_feature_set obsoleted;
9603  const char *dep_msg;
9604  const char *obs_msg;
9605};
9606
9607#define DEPR_ACCESS_V8 \
9608  N_("This coprocessor register access is deprecated in ARMv8")
9609
9610/* Table of all deprecated coprocessor registers.  */
9611static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
9612{
9613    {15, 0, 7, 10, 5,					/* CP15DMB.  */
9614     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9615     DEPR_ACCESS_V8, NULL},
9616    {15, 0, 7, 10, 4,					/* CP15DSB.  */
9617     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9618     DEPR_ACCESS_V8, NULL},
9619    {15, 0, 7,  5, 4,					/* CP15ISB.  */
9620     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9621     DEPR_ACCESS_V8, NULL},
9622    {14, 6, 1,  0, 0,					/* TEEHBR.  */
9623     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9624     DEPR_ACCESS_V8, NULL},
9625    {14, 6, 0,  0, 0,					/* TEECR.  */
9626     ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
9627     DEPR_ACCESS_V8, NULL},
9628};
9629
9630#undef DEPR_ACCESS_V8
9631
9632static const size_t deprecated_coproc_reg_count =
9633  sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
9634
9635static void
9636do_co_reg (void)
9637{
9638  unsigned Rd;
9639  size_t i;
9640
9641  Rd = inst.operands[2].reg;
9642  if (thumb_mode)
9643    {
9644      if (inst.instruction == 0xee000010
9645	  || inst.instruction == 0xfe000010)
9646	/* MCR, MCR2  */
9647	reject_bad_reg (Rd);
9648      else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9649	/* MRC, MRC2  */
9650	constraint (Rd == REG_SP, BAD_SP);
9651    }
9652  else
9653    {
9654      /* MCR */
9655      if (inst.instruction == 0xe000010)
9656	constraint (Rd == REG_PC, BAD_PC);
9657    }
9658
9659    for (i = 0; i < deprecated_coproc_reg_count; ++i)
9660      {
9661	const struct deprecated_coproc_regs_s *r =
9662	  deprecated_coproc_regs + i;
9663
9664	if (inst.operands[0].reg == r->cp
9665	    && inst.operands[1].imm == r->opc1
9666	    && inst.operands[3].reg == r->crn
9667	    && inst.operands[4].reg == r->crm
9668	    && inst.operands[5].imm == r->opc2)
9669	  {
9670	    if (! ARM_CPU_IS_ANY (cpu_variant)
9671		&& warn_on_deprecated
9672		&& ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
9673	      as_tsktsk ("%s", r->dep_msg);
9674	  }
9675      }
9676
9677  inst.instruction |= inst.operands[0].reg << 8;
9678  inst.instruction |= inst.operands[1].imm << 21;
9679  inst.instruction |= Rd << 12;
9680  inst.instruction |= inst.operands[3].reg << 16;
9681  inst.instruction |= inst.operands[4].reg;
9682  inst.instruction |= inst.operands[5].imm << 5;
9683}
9684
9685/* Transfer between coprocessor register and pair of ARM registers.
9686   MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9687   MCRR2
9688   MRRC{cond}
9689   MRRC2
9690
9691   Two XScale instructions are special cases of these:
9692
9693     MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9694     MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9695
9696   Result unpredictable if Rd or Rn is R15.  */
9697
9698static void
9699do_co_reg2c (void)
9700{
9701  unsigned Rd, Rn;
9702
9703  Rd = inst.operands[2].reg;
9704  Rn = inst.operands[3].reg;
9705
9706  if (thumb_mode)
9707    {
9708      reject_bad_reg (Rd);
9709      reject_bad_reg (Rn);
9710    }
9711  else
9712    {
9713      constraint (Rd == REG_PC, BAD_PC);
9714      constraint (Rn == REG_PC, BAD_PC);
9715    }
9716
9717  /* Only check the MRRC{2} variants.  */
9718  if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9719    {
9720       /* If Rd == Rn, error that the operation is
9721	  unpredictable (example MRRC p3,#1,r1,r1,c4).  */
9722       constraint (Rd == Rn, BAD_OVERLAP);
9723    }
9724
9725  inst.instruction |= inst.operands[0].reg << 8;
9726  inst.instruction |= inst.operands[1].imm << 4;
9727  inst.instruction |= Rd << 12;
9728  inst.instruction |= Rn << 16;
9729  inst.instruction |= inst.operands[4].reg;
9730}
9731
9732static void
9733do_cpsi (void)
9734{
9735  inst.instruction |= inst.operands[0].imm << 6;
9736  if (inst.operands[1].present)
9737    {
9738      inst.instruction |= CPSI_MMOD;
9739      inst.instruction |= inst.operands[1].imm;
9740    }
9741}
9742
9743static void
9744do_dbg (void)
9745{
9746  inst.instruction |= inst.operands[0].imm;
9747}
9748
9749static void
9750do_div (void)
9751{
9752  unsigned Rd, Rn, Rm;
9753
9754  Rd = inst.operands[0].reg;
9755  Rn = (inst.operands[1].present
9756	? inst.operands[1].reg : Rd);
9757  Rm = inst.operands[2].reg;
9758
9759  constraint ((Rd == REG_PC), BAD_PC);
9760  constraint ((Rn == REG_PC), BAD_PC);
9761  constraint ((Rm == REG_PC), BAD_PC);
9762
9763  inst.instruction |= Rd << 16;
9764  inst.instruction |= Rn << 0;
9765  inst.instruction |= Rm << 8;
9766}
9767
9768static void
9769do_it (void)
9770{
9771  /* There is no IT instruction in ARM mode.  We
9772     process it to do the validation as if in
9773     thumb mode, just in case the code gets
9774     assembled for thumb using the unified syntax.  */
9775
9776  inst.size = 0;
9777  if (unified_syntax)
9778    {
9779      set_pred_insn_type (IT_INSN);
9780      now_pred.mask = (inst.instruction & 0xf) | 0x10;
9781      now_pred.cc = inst.operands[0].imm;
9782    }
9783}
9784
9785/* If there is only one register in the register list,
9786   then return its register number.  Otherwise return -1.  */
9787static int
9788only_one_reg_in_list (int range)
9789{
9790  int i = ffs (range) - 1;
9791  return (i > 15 || range != (1 << i)) ? -1 : i;
9792}
9793
9794static void
9795encode_ldmstm(int from_push_pop_mnem)
9796{
9797  int base_reg = inst.operands[0].reg;
9798  int range = inst.operands[1].imm;
9799  int one_reg;
9800
9801  inst.instruction |= base_reg << 16;
9802  inst.instruction |= range;
9803
9804  if (inst.operands[1].writeback)
9805    inst.instruction |= LDM_TYPE_2_OR_3;
9806
9807  if (inst.operands[0].writeback)
9808    {
9809      inst.instruction |= WRITE_BACK;
9810      /* Check for unpredictable uses of writeback.  */
9811      if (inst.instruction & LOAD_BIT)
9812	{
9813	  /* Not allowed in LDM type 2.	 */
9814	  if ((inst.instruction & LDM_TYPE_2_OR_3)
9815	      && ((range & (1 << REG_PC)) == 0))
9816	    as_warn (_("writeback of base register is UNPREDICTABLE"));
9817	  /* Only allowed if base reg not in list for other types.  */
9818	  else if (range & (1 << base_reg))
9819	    as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9820	}
9821      else /* STM.  */
9822	{
9823	  /* Not allowed for type 2.  */
9824	  if (inst.instruction & LDM_TYPE_2_OR_3)
9825	    as_warn (_("writeback of base register is UNPREDICTABLE"));
9826	  /* Only allowed if base reg not in list, or first in list.  */
9827	  else if ((range & (1 << base_reg))
9828		   && (range & ((1 << base_reg) - 1)))
9829	    as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9830	}
9831    }
9832
9833  /* If PUSH/POP has only one register, then use the A2 encoding.  */
9834  one_reg = only_one_reg_in_list (range);
9835  if (from_push_pop_mnem && one_reg >= 0)
9836    {
9837      int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9838
9839      if (is_push && one_reg == 13 /* SP */)
9840	/* PR 22483: The A2 encoding cannot be used when
9841	   pushing the stack pointer as this is UNPREDICTABLE.  */
9842	return;
9843
9844      inst.instruction &= A_COND_MASK;
9845      inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9846      inst.instruction |= one_reg << 12;
9847    }
9848}
9849
9850static void
9851do_ldmstm (void)
9852{
9853  encode_ldmstm (/*from_push_pop_mnem=*/false);
9854}
9855
9856/* ARMv5TE load-consecutive (argument parse)
9857   Mode is like LDRH.
9858
9859     LDRccD R, mode
9860     STRccD R, mode.  */
9861
9862static void
9863do_ldrd (void)
9864{
9865  constraint (inst.operands[0].reg % 2 != 0,
9866	      _("first transfer register must be even"));
9867  constraint (inst.operands[1].present
9868	      && inst.operands[1].reg != inst.operands[0].reg + 1,
9869	      _("can only transfer two consecutive registers"));
9870  constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9871  constraint (!inst.operands[2].isreg, _("'[' expected"));
9872
9873  if (!inst.operands[1].present)
9874    inst.operands[1].reg = inst.operands[0].reg + 1;
9875
9876  /* encode_arm_addr_mode_3 will diagnose overlap between the base
9877     register and the first register written; we have to diagnose
9878     overlap between the base and the second register written here.  */
9879
9880  if (inst.operands[2].reg == inst.operands[1].reg
9881      && (inst.operands[2].writeback || inst.operands[2].postind))
9882    as_warn (_("base register written back, and overlaps "
9883	       "second transfer register"));
9884
9885  if (!(inst.instruction & V4_STR_BIT))
9886    {
9887      /* For an index-register load, the index register must not overlap the
9888	destination (even if not write-back).  */
9889      if (inst.operands[2].immisreg
9890	      && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9891	      || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9892	as_warn (_("index register overlaps transfer register"));
9893    }
9894  inst.instruction |= inst.operands[0].reg << 12;
9895  encode_arm_addr_mode_3 (2, /*is_t=*/false);
9896}
9897
9898static void
9899do_ldrex (void)
9900{
9901  constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9902	      || inst.operands[1].postind || inst.operands[1].writeback
9903	      || inst.operands[1].immisreg || inst.operands[1].shifted
9904	      || inst.operands[1].negative
9905	      /* This can arise if the programmer has written
9906		   strex rN, rM, foo
9907		 or if they have mistakenly used a register name as the last
9908		 operand,  eg:
9909		   strex rN, rM, rX
9910		 It is very difficult to distinguish between these two cases
9911		 because "rX" might actually be a label. ie the register
9912		 name has been occluded by a symbol of the same name. So we
9913		 just generate a general 'bad addressing mode' type error
9914		 message and leave it up to the programmer to discover the
9915		 true cause and fix their mistake.  */
9916	      || (inst.operands[1].reg == REG_PC),
9917	      BAD_ADDR_MODE);
9918
9919  constraint (inst.relocs[0].exp.X_op != O_constant
9920	      || inst.relocs[0].exp.X_add_number != 0,
9921	      _("offset must be zero in ARM encoding"));
9922
9923  constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9924
9925  inst.instruction |= inst.operands[0].reg << 12;
9926  inst.instruction |= inst.operands[1].reg << 16;
9927  inst.relocs[0].type = BFD_RELOC_UNUSED;
9928}
9929
9930static void
9931do_ldrexd (void)
9932{
9933  constraint (inst.operands[0].reg % 2 != 0,
9934	      _("even register required"));
9935  constraint (inst.operands[1].present
9936	      && inst.operands[1].reg != inst.operands[0].reg + 1,
9937	      _("can only load two consecutive registers"));
9938  /* If op 1 were present and equal to PC, this function wouldn't
9939     have been called in the first place.  */
9940  constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9941
9942  inst.instruction |= inst.operands[0].reg << 12;
9943  inst.instruction |= inst.operands[2].reg << 16;
9944}
9945
9946/* In both ARM and thumb state 'ldr pc, #imm'  with an immediate
9947   which is not a multiple of four is UNPREDICTABLE.  */
9948static void
9949check_ldr_r15_aligned (void)
9950{
9951  constraint (!(inst.operands[1].immisreg)
9952	      && (inst.operands[0].reg == REG_PC
9953	      && inst.operands[1].reg == REG_PC
9954	      && (inst.relocs[0].exp.X_add_number & 0x3)),
9955	      _("ldr to register 15 must be 4-byte aligned"));
9956}
9957
9958static void
9959do_ldst (void)
9960{
9961  inst.instruction |= inst.operands[0].reg << 12;
9962  if (!inst.operands[1].isreg)
9963    if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/false))
9964      return;
9965  encode_arm_addr_mode_2 (1, /*is_t=*/false);
9966  check_ldr_r15_aligned ();
9967}
9968
9969static void
9970do_ldstt (void)
9971{
9972  /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
9973     reject [Rn,...].  */
9974  if (inst.operands[1].preind)
9975    {
9976      constraint (inst.relocs[0].exp.X_op != O_constant
9977		  || inst.relocs[0].exp.X_add_number != 0,
9978		  _("this instruction requires a post-indexed address"));
9979
9980      inst.operands[1].preind = 0;
9981      inst.operands[1].postind = 1;
9982      inst.operands[1].writeback = 1;
9983    }
9984  inst.instruction |= inst.operands[0].reg << 12;
9985  encode_arm_addr_mode_2 (1, /*is_t=*/true);
9986}
9987
9988/* Halfword and signed-byte load/store operations.  */
9989
9990static void
9991do_ldstv4 (void)
9992{
9993  constraint (inst.operands[0].reg == REG_PC, BAD_PC);
9994  inst.instruction |= inst.operands[0].reg << 12;
9995  if (!inst.operands[1].isreg)
9996    if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/true))
9997      return;
9998  encode_arm_addr_mode_3 (1, /*is_t=*/false);
9999}
10000
10001static void
10002do_ldsttv4 (void)
10003{
10004  /* ldrt/strt always use post-indexed addressing.  Turn [Rn] into [Rn]! and
10005     reject [Rn,...].  */
10006  if (inst.operands[1].preind)
10007    {
10008      constraint (inst.relocs[0].exp.X_op != O_constant
10009		  || inst.relocs[0].exp.X_add_number != 0,
10010		  _("this instruction requires a post-indexed address"));
10011
10012      inst.operands[1].preind = 0;
10013      inst.operands[1].postind = 1;
10014      inst.operands[1].writeback = 1;
10015    }
10016  inst.instruction |= inst.operands[0].reg << 12;
10017  encode_arm_addr_mode_3 (1, /*is_t=*/true);
10018}
10019
10020/* Co-processor register load/store.
10021   Format: <LDC|STC>{cond}[L] CP#,CRd,<address>	 */
10022static void
10023do_lstc (void)
10024{
10025  inst.instruction |= inst.operands[0].reg << 8;
10026  inst.instruction |= inst.operands[1].reg << 12;
10027  encode_arm_cp_address (2, true, true, 0);
10028}
10029
10030static void
10031do_mlas (void)
10032{
10033  /* This restriction does not apply to mls (nor to mla in v6 or later).  */
10034  if (inst.operands[0].reg == inst.operands[1].reg
10035      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
10036      && !(inst.instruction & 0x00400000))
10037    as_tsktsk (_("Rd and Rm should be different in mla"));
10038
10039  inst.instruction |= inst.operands[0].reg << 16;
10040  inst.instruction |= inst.operands[1].reg;
10041  inst.instruction |= inst.operands[2].reg << 8;
10042  inst.instruction |= inst.operands[3].reg << 12;
10043}
10044
10045static void
10046do_mov (void)
10047{
10048  constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10049	      && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
10050	      THUMB1_RELOC_ONLY);
10051  inst.instruction |= inst.operands[0].reg << 12;
10052  encode_arm_shifter_operand (1);
10053}
10054
10055/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>.	 */
10056static void
10057do_mov16 (void)
10058{
10059  bfd_vma imm;
10060  bool top;
10061
10062  top = (inst.instruction & 0x00400000) != 0;
10063  constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
10064	      _(":lower16: not allowed in this instruction"));
10065  constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
10066	      _(":upper16: not allowed in this instruction"));
10067  inst.instruction |= inst.operands[0].reg << 12;
10068  if (inst.relocs[0].type == BFD_RELOC_UNUSED)
10069    {
10070      imm = inst.relocs[0].exp.X_add_number;
10071      /* The value is in two pieces: 0:11, 16:19.  */
10072      inst.instruction |= (imm & 0x00000fff);
10073      inst.instruction |= (imm & 0x0000f000) << 4;
10074    }
10075}
10076
10077static int
10078do_vfp_nsyn_mrs (void)
10079{
10080  if (inst.operands[0].isvec)
10081    {
10082      if (inst.operands[1].reg != 1)
10083	first_error (_("operand 1 must be FPSCR"));
10084      memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
10085      memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
10086      do_vfp_nsyn_opcode ("fmstat");
10087    }
10088  else if (inst.operands[1].isvec)
10089    do_vfp_nsyn_opcode ("fmrx");
10090  else
10091    return FAIL;
10092
10093  return SUCCESS;
10094}
10095
10096static int
10097do_vfp_nsyn_msr (void)
10098{
10099  if (inst.operands[0].isvec)
10100    do_vfp_nsyn_opcode ("fmxr");
10101  else
10102    return FAIL;
10103
10104  return SUCCESS;
10105}
10106
10107static void
10108do_vmrs (void)
10109{
10110  unsigned Rt = inst.operands[0].reg;
10111
10112  if (thumb_mode && Rt == REG_SP)
10113    {
10114      inst.error = BAD_SP;
10115      return;
10116    }
10117
10118  switch (inst.operands[1].reg)
10119    {
10120    /* MVFR2 is only valid for Armv8-A.  */
10121    case 5:
10122      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
10123		  _(BAD_FPU));
10124      break;
10125
10126    /* Check for new Armv8.1-M Mainline changes to <spec_reg>.  */
10127    case 1: /* fpscr.  */
10128      constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10129		    || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10130		  _(BAD_FPU));
10131      break;
10132
10133    case 14: /* fpcxt_ns, fpcxtns, FPCXT_NS, FPCXTNS.  */
10134    case 15: /* fpcxt_s, fpcxts, FPCXT_S, FPCXTS.  */
10135      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
10136		  _("selected processor does not support instruction"));
10137      break;
10138
10139    case  2: /* fpscr_nzcvqc.  */
10140    case 12: /* vpr.  */
10141    case 13: /* p0.  */
10142      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
10143		  || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10144		      && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10145		  _("selected processor does not support instruction"));
10146      if (inst.operands[0].reg != 2
10147	  && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
10148	as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10149      break;
10150
10151    default:
10152      break;
10153    }
10154
10155  /* APSR_ sets isvec. All other refs to PC are illegal.  */
10156  if (!inst.operands[0].isvec && Rt == REG_PC)
10157    {
10158      inst.error = BAD_PC;
10159      return;
10160    }
10161
10162  /* If we get through parsing the register name, we just insert the number
10163     generated into the instruction without further validation.  */
10164  inst.instruction |= (inst.operands[1].reg << 16);
10165  inst.instruction |= (Rt << 12);
10166}
10167
10168static void
10169do_vmsr (void)
10170{
10171  unsigned Rt = inst.operands[1].reg;
10172
10173  if (thumb_mode)
10174    reject_bad_reg (Rt);
10175  else if (Rt == REG_PC)
10176    {
10177      inst.error = BAD_PC;
10178      return;
10179    }
10180
10181  switch (inst.operands[0].reg)
10182    {
10183    /* MVFR2 is only valid for Armv8-A.  */
10184    case 5:
10185      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
10186		  _(BAD_FPU));
10187      break;
10188
10189    /* Check for new Armv8.1-M Mainline changes to <spec_reg>.  */
10190    case  1: /* fpcr.  */
10191      constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10192		    || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10193		  _(BAD_FPU));
10194      break;
10195
10196    case 14: /* fpcxt_ns.  */
10197    case 15: /* fpcxt_s.  */
10198      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
10199		  _("selected processor does not support instruction"));
10200      break;
10201
10202    case  2: /* fpscr_nzcvqc.  */
10203    case 12: /* vpr.  */
10204    case 13: /* p0.  */
10205      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
10206		  || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10207		      && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10208		  _("selected processor does not support instruction"));
10209      if (inst.operands[0].reg != 2
10210	  && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
10211	as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10212      break;
10213
10214    default:
10215      break;
10216    }
10217
10218  /* If we get through parsing the register name, we just insert the number
10219     generated into the instruction without further validation.  */
10220  inst.instruction |= (inst.operands[0].reg << 16);
10221  inst.instruction |= (Rt << 12);
10222}
10223
10224static void
10225do_mrs (void)
10226{
10227  unsigned br;
10228
10229  if (do_vfp_nsyn_mrs () == SUCCESS)
10230    return;
10231
10232  constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10233  inst.instruction |= inst.operands[0].reg << 12;
10234
10235  if (inst.operands[1].isreg)
10236    {
10237      br = inst.operands[1].reg;
10238      if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
10239	as_bad (_("bad register for mrs"));
10240    }
10241  else
10242    {
10243      /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all.  */
10244      constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
10245		  != (PSR_c|PSR_f),
10246		  _("'APSR', 'CPSR' or 'SPSR' expected"));
10247      br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
10248    }
10249
10250  inst.instruction |= br;
10251}
10252
10253/* Two possible forms:
10254      "{C|S}PSR_<field>, Rm",
10255      "{C|S}PSR_f, #expression".  */
10256
10257static void
10258do_msr (void)
10259{
10260  if (do_vfp_nsyn_msr () == SUCCESS)
10261    return;
10262
10263  inst.instruction |= inst.operands[0].imm;
10264  if (inst.operands[1].isreg)
10265    inst.instruction |= inst.operands[1].reg;
10266  else
10267    {
10268      inst.instruction |= INST_IMMEDIATE;
10269      inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
10270      inst.relocs[0].pc_rel = 0;
10271    }
10272}
10273
10274static void
10275do_mul (void)
10276{
10277  constraint (inst.operands[2].reg == REG_PC, BAD_PC);
10278
10279  if (!inst.operands[2].present)
10280    inst.operands[2].reg = inst.operands[0].reg;
10281  inst.instruction |= inst.operands[0].reg << 16;
10282  inst.instruction |= inst.operands[1].reg;
10283  inst.instruction |= inst.operands[2].reg << 8;
10284
10285  if (inst.operands[0].reg == inst.operands[1].reg
10286      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
10287    as_tsktsk (_("Rd and Rm should be different in mul"));
10288}
10289
10290/* Long Multiply Parser
10291   UMULL RdLo, RdHi, Rm, Rs
10292   SMULL RdLo, RdHi, Rm, Rs
10293   UMLAL RdLo, RdHi, Rm, Rs
10294   SMLAL RdLo, RdHi, Rm, Rs.  */
10295
10296static void
10297do_mull (void)
10298{
10299  inst.instruction |= inst.operands[0].reg << 12;
10300  inst.instruction |= inst.operands[1].reg << 16;
10301  inst.instruction |= inst.operands[2].reg;
10302  inst.instruction |= inst.operands[3].reg << 8;
10303
10304  /* rdhi and rdlo must be different.  */
10305  if (inst.operands[0].reg == inst.operands[1].reg)
10306    as_tsktsk (_("rdhi and rdlo must be different"));
10307
10308  /* rdhi, rdlo and rm must all be different before armv6.  */
10309  if ((inst.operands[0].reg == inst.operands[2].reg
10310      || inst.operands[1].reg == inst.operands[2].reg)
10311      && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
10312    as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10313}
10314
10315static void
10316do_nop (void)
10317{
10318  if (inst.operands[0].present
10319      || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
10320    {
10321      /* Architectural NOP hints are CPSR sets with no bits selected.  */
10322      inst.instruction &= 0xf0000000;
10323      inst.instruction |= 0x0320f000;
10324      if (inst.operands[0].present)
10325	inst.instruction |= inst.operands[0].imm;
10326    }
10327}
10328
10329/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10330   PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10331   Condition defaults to COND_ALWAYS.
10332   Error if Rd, Rn or Rm are R15.  */
10333
10334static void
10335do_pkhbt (void)
10336{
10337  inst.instruction |= inst.operands[0].reg << 12;
10338  inst.instruction |= inst.operands[1].reg << 16;
10339  inst.instruction |= inst.operands[2].reg;
10340  if (inst.operands[3].present)
10341    encode_arm_shift (3);
10342}
10343
10344/* ARM V6 PKHTB (Argument Parse).  */
10345
10346static void
10347do_pkhtb (void)
10348{
10349  if (!inst.operands[3].present)
10350    {
10351      /* If the shift specifier is omitted, turn the instruction
10352	 into pkhbt rd, rm, rn. */
10353      inst.instruction &= 0xfff00010;
10354      inst.instruction |= inst.operands[0].reg << 12;
10355      inst.instruction |= inst.operands[1].reg;
10356      inst.instruction |= inst.operands[2].reg << 16;
10357    }
10358  else
10359    {
10360      inst.instruction |= inst.operands[0].reg << 12;
10361      inst.instruction |= inst.operands[1].reg << 16;
10362      inst.instruction |= inst.operands[2].reg;
10363      encode_arm_shift (3);
10364    }
10365}
10366
10367/* ARMv5TE: Preload-Cache
10368   MP Extensions: Preload for write
10369
10370    PLD(W) <addr_mode>
10371
10372  Syntactically, like LDR with B=1, W=0, L=1.  */
10373
10374static void
10375do_pld (void)
10376{
10377  constraint (!inst.operands[0].isreg,
10378	      _("'[' expected after PLD mnemonic"));
10379  constraint (inst.operands[0].postind,
10380	      _("post-indexed expression used in preload instruction"));
10381  constraint (inst.operands[0].writeback,
10382	      _("writeback used in preload instruction"));
10383  constraint (!inst.operands[0].preind,
10384	      _("unindexed addressing used in preload instruction"));
10385  encode_arm_addr_mode_2 (0, /*is_t=*/false);
10386}
10387
10388/* ARMv7: PLI <addr_mode>  */
10389static void
10390do_pli (void)
10391{
10392  constraint (!inst.operands[0].isreg,
10393	      _("'[' expected after PLI mnemonic"));
10394  constraint (inst.operands[0].postind,
10395	      _("post-indexed expression used in preload instruction"));
10396  constraint (inst.operands[0].writeback,
10397	      _("writeback used in preload instruction"));
10398  constraint (!inst.operands[0].preind,
10399	      _("unindexed addressing used in preload instruction"));
10400  encode_arm_addr_mode_2 (0, /*is_t=*/false);
10401  inst.instruction &= ~PRE_INDEX;
10402}
10403
10404static void
10405do_push_pop (void)
10406{
10407  constraint (inst.operands[0].writeback,
10408	      _("push/pop do not support {reglist}^"));
10409  inst.operands[1] = inst.operands[0];
10410  memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10411  inst.operands[0].isreg = 1;
10412  inst.operands[0].writeback = 1;
10413  inst.operands[0].reg = REG_SP;
10414  encode_ldmstm (/*from_push_pop_mnem=*/true);
10415}
10416
10417/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10418   word at the specified address and the following word
10419   respectively.
10420   Unconditionally executed.
10421   Error if Rn is R15.	*/
10422
10423static void
10424do_rfe (void)
10425{
10426  inst.instruction |= inst.operands[0].reg << 16;
10427  if (inst.operands[0].writeback)
10428    inst.instruction |= WRITE_BACK;
10429}
10430
10431/* ARM V6 ssat (argument parse).  */
10432
10433static void
10434do_ssat (void)
10435{
10436  inst.instruction |= inst.operands[0].reg << 12;
10437  inst.instruction |= (inst.operands[1].imm - 1) << 16;
10438  inst.instruction |= inst.operands[2].reg;
10439
10440  if (inst.operands[3].present)
10441    encode_arm_shift (3);
10442}
10443
10444/* ARM V6 usat (argument parse).  */
10445
10446static void
10447do_usat (void)
10448{
10449  inst.instruction |= inst.operands[0].reg << 12;
10450  inst.instruction |= inst.operands[1].imm << 16;
10451  inst.instruction |= inst.operands[2].reg;
10452
10453  if (inst.operands[3].present)
10454    encode_arm_shift (3);
10455}
10456
10457/* ARM V6 ssat16 (argument parse).  */
10458
10459static void
10460do_ssat16 (void)
10461{
10462  inst.instruction |= inst.operands[0].reg << 12;
10463  inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10464  inst.instruction |= inst.operands[2].reg;
10465}
10466
10467static void
10468do_usat16 (void)
10469{
10470  inst.instruction |= inst.operands[0].reg << 12;
10471  inst.instruction |= inst.operands[1].imm << 16;
10472  inst.instruction |= inst.operands[2].reg;
10473}
10474
10475/* ARM V6 SETEND (argument parse).  Sets the E bit in the CPSR while
10476   preserving the other bits.
10477
10478   setend <endian_specifier>, where <endian_specifier> is either
10479   BE or LE.  */
10480
10481static void
10482do_setend (void)
10483{
10484  if (warn_on_deprecated
10485      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
10486      as_tsktsk (_("setend use is deprecated for ARMv8"));
10487
10488  if (inst.operands[0].imm)
10489    inst.instruction |= 0x200;
10490}
10491
10492static void
10493do_shift (void)
10494{
10495  unsigned int Rm = (inst.operands[1].present
10496		     ? inst.operands[1].reg
10497		     : inst.operands[0].reg);
10498
10499  inst.instruction |= inst.operands[0].reg << 12;
10500  inst.instruction |= Rm;
10501  if (inst.operands[2].isreg)  /* Rd, {Rm,} Rs */
10502    {
10503      inst.instruction |= inst.operands[2].reg << 8;
10504      inst.instruction |= SHIFT_BY_REG;
10505      /* PR 12854: Error on extraneous shifts.  */
10506      constraint (inst.operands[2].shifted,
10507		  _("extraneous shift as part of operand to shift insn"));
10508    }
10509  else
10510    inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
10511}
10512
10513static void
10514do_smc (void)
10515{
10516  unsigned int value = inst.relocs[0].exp.X_add_number;
10517  constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
10518
10519  inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10520  inst.relocs[0].pc_rel = 0;
10521}
10522
10523static void
10524do_hvc (void)
10525{
10526  inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10527  inst.relocs[0].pc_rel = 0;
10528}
10529
10530static void
10531do_swi (void)
10532{
10533  inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10534  inst.relocs[0].pc_rel = 0;
10535}
10536
10537static void
10538do_setpan (void)
10539{
10540  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10541	      _("selected processor does not support SETPAN instruction"));
10542
10543  inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10544}
10545
10546static void
10547do_t_setpan (void)
10548{
10549  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10550	      _("selected processor does not support SETPAN instruction"));
10551
10552  inst.instruction |= (inst.operands[0].imm << 3);
10553}
10554
10555/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10556   SMLAxy{cond} Rd,Rm,Rs,Rn
10557   SMLAWy{cond} Rd,Rm,Rs,Rn
10558   Error if any register is R15.  */
10559
10560static void
10561do_smla (void)
10562{
10563  inst.instruction |= inst.operands[0].reg << 16;
10564  inst.instruction |= inst.operands[1].reg;
10565  inst.instruction |= inst.operands[2].reg << 8;
10566  inst.instruction |= inst.operands[3].reg << 12;
10567}
10568
10569/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10570   SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10571   Error if any register is R15.
10572   Warning if Rdlo == Rdhi.  */
10573
10574static void
10575do_smlal (void)
10576{
10577  inst.instruction |= inst.operands[0].reg << 12;
10578  inst.instruction |= inst.operands[1].reg << 16;
10579  inst.instruction |= inst.operands[2].reg;
10580  inst.instruction |= inst.operands[3].reg << 8;
10581
10582  if (inst.operands[0].reg == inst.operands[1].reg)
10583    as_tsktsk (_("rdhi and rdlo must be different"));
10584}
10585
10586/* ARM V5E (El Segundo) signed-multiply (argument parse)
10587   SMULxy{cond} Rd,Rm,Rs
10588   Error if any register is R15.  */
10589
10590static void
10591do_smul (void)
10592{
10593  inst.instruction |= inst.operands[0].reg << 16;
10594  inst.instruction |= inst.operands[1].reg;
10595  inst.instruction |= inst.operands[2].reg << 8;
10596}
10597
10598/* ARM V6 srs (argument parse).  The variable fields in the encoding are
10599   the same for both ARM and Thumb-2.  */
10600
10601static void
10602do_srs (void)
10603{
10604  int reg;
10605
10606  if (inst.operands[0].present)
10607    {
10608      reg = inst.operands[0].reg;
10609      constraint (reg != REG_SP, _("SRS base register must be r13"));
10610    }
10611  else
10612    reg = REG_SP;
10613
10614  inst.instruction |= reg << 16;
10615  inst.instruction |= inst.operands[1].imm;
10616  if (inst.operands[0].writeback || inst.operands[1].writeback)
10617    inst.instruction |= WRITE_BACK;
10618}
10619
10620/* ARM V6 strex (argument parse).  */
10621
10622static void
10623do_strex (void)
10624{
10625  constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10626	      || inst.operands[2].postind || inst.operands[2].writeback
10627	      || inst.operands[2].immisreg || inst.operands[2].shifted
10628	      || inst.operands[2].negative
10629	      /* See comment in do_ldrex().  */
10630	      || (inst.operands[2].reg == REG_PC),
10631	      BAD_ADDR_MODE);
10632
10633  constraint (inst.operands[0].reg == inst.operands[1].reg
10634	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10635
10636  constraint (inst.relocs[0].exp.X_op != O_constant
10637	      || inst.relocs[0].exp.X_add_number != 0,
10638	      _("offset must be zero in ARM encoding"));
10639
10640  inst.instruction |= inst.operands[0].reg << 12;
10641  inst.instruction |= inst.operands[1].reg;
10642  inst.instruction |= inst.operands[2].reg << 16;
10643  inst.relocs[0].type = BFD_RELOC_UNUSED;
10644}
10645
10646static void
10647do_t_strexbh (void)
10648{
10649  constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10650	      || inst.operands[2].postind || inst.operands[2].writeback
10651	      || inst.operands[2].immisreg || inst.operands[2].shifted
10652	      || inst.operands[2].negative,
10653	      BAD_ADDR_MODE);
10654
10655  constraint (inst.operands[0].reg == inst.operands[1].reg
10656	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10657
10658  do_rm_rd_rn ();
10659}
10660
10661static void
10662do_strexd (void)
10663{
10664  constraint (inst.operands[1].reg % 2 != 0,
10665	      _("even register required"));
10666  constraint (inst.operands[2].present
10667	      && inst.operands[2].reg != inst.operands[1].reg + 1,
10668	      _("can only store two consecutive registers"));
10669  /* If op 2 were present and equal to PC, this function wouldn't
10670     have been called in the first place.  */
10671  constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
10672
10673  constraint (inst.operands[0].reg == inst.operands[1].reg
10674	      || inst.operands[0].reg == inst.operands[1].reg + 1
10675	      || inst.operands[0].reg == inst.operands[3].reg,
10676	      BAD_OVERLAP);
10677
10678  inst.instruction |= inst.operands[0].reg << 12;
10679  inst.instruction |= inst.operands[1].reg;
10680  inst.instruction |= inst.operands[3].reg << 16;
10681}
10682
10683/* ARM V8 STRL.  */
10684static void
10685do_stlex (void)
10686{
10687  constraint (inst.operands[0].reg == inst.operands[1].reg
10688	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10689
10690  do_rd_rm_rn ();
10691}
10692
10693static void
10694do_t_stlex (void)
10695{
10696  constraint (inst.operands[0].reg == inst.operands[1].reg
10697	      || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10698
10699  do_rm_rd_rn ();
10700}
10701
10702/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10703   extends it to 32-bits, and adds the result to a value in another
10704   register.  You can specify a rotation by 0, 8, 16, or 24 bits
10705   before extracting the 16-bit value.
10706   SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10707   Condition defaults to COND_ALWAYS.
10708   Error if any register uses R15.  */
10709
10710static void
10711do_sxtah (void)
10712{
10713  inst.instruction |= inst.operands[0].reg << 12;
10714  inst.instruction |= inst.operands[1].reg << 16;
10715  inst.instruction |= inst.operands[2].reg;
10716  inst.instruction |= inst.operands[3].imm << 10;
10717}
10718
10719/* ARM V6 SXTH.
10720
10721   SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10722   Condition defaults to COND_ALWAYS.
10723   Error if any register uses R15.  */
10724
10725static void
10726do_sxth (void)
10727{
10728  inst.instruction |= inst.operands[0].reg << 12;
10729  inst.instruction |= inst.operands[1].reg;
10730  inst.instruction |= inst.operands[2].imm << 10;
10731}
10732
10733/* VFP instructions.  In a logical order: SP variant first, monad
10734   before dyad, arithmetic then move then load/store.  */
10735
10736static void
10737do_vfp_sp_monadic (void)
10738{
10739  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10740	      && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10741	      _(BAD_FPU));
10742
10743  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10744  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10745}
10746
10747static void
10748do_vfp_sp_dyadic (void)
10749{
10750  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10751  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10752  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10753}
10754
10755static void
10756do_vfp_sp_compare_z (void)
10757{
10758  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10759}
10760
10761static void
10762do_vfp_dp_sp_cvt (void)
10763{
10764  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10765  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
10766}
10767
10768static void
10769do_vfp_sp_dp_cvt (void)
10770{
10771  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10772  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10773}
10774
10775static void
10776do_vfp_reg_from_sp (void)
10777{
10778  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10779	     && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10780	     _(BAD_FPU));
10781
10782  inst.instruction |= inst.operands[0].reg << 12;
10783  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10784}
10785
10786static void
10787do_vfp_reg2_from_sp2 (void)
10788{
10789  constraint (inst.operands[2].imm != 2,
10790	      _("only two consecutive VFP SP registers allowed here"));
10791  inst.instruction |= inst.operands[0].reg << 12;
10792  inst.instruction |= inst.operands[1].reg << 16;
10793  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
10794}
10795
10796static void
10797do_vfp_sp_from_reg (void)
10798{
10799  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10800	     && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10801	     _(BAD_FPU));
10802
10803  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
10804  inst.instruction |= inst.operands[1].reg << 12;
10805}
10806
10807static void
10808do_vfp_sp2_from_reg2 (void)
10809{
10810  constraint (inst.operands[0].imm != 2,
10811	      _("only two consecutive VFP SP registers allowed here"));
10812  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
10813  inst.instruction |= inst.operands[1].reg << 12;
10814  inst.instruction |= inst.operands[2].reg << 16;
10815}
10816
10817static void
10818do_vfp_sp_ldst (void)
10819{
10820  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10821  encode_arm_cp_address (1, false, true, 0);
10822}
10823
10824static void
10825do_vfp_dp_ldst (void)
10826{
10827  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10828  encode_arm_cp_address (1, false, true, 0);
10829}
10830
10831
10832static void
10833vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
10834{
10835  if (inst.operands[0].writeback)
10836    inst.instruction |= WRITE_BACK;
10837  else
10838    constraint (ldstm_type != VFP_LDSTMIA,
10839		_("this addressing mode requires base-register writeback"));
10840  inst.instruction |= inst.operands[0].reg << 16;
10841  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
10842  inst.instruction |= inst.operands[1].imm;
10843}
10844
10845static void
10846vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
10847{
10848  int count;
10849
10850  if (inst.operands[0].writeback)
10851    inst.instruction |= WRITE_BACK;
10852  else
10853    constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
10854		_("this addressing mode requires base-register writeback"));
10855
10856  inst.instruction |= inst.operands[0].reg << 16;
10857  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10858
10859  count = inst.operands[1].imm << 1;
10860  if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
10861    count += 1;
10862
10863  inst.instruction |= count;
10864}
10865
10866static void
10867do_vfp_sp_ldstmia (void)
10868{
10869  vfp_sp_ldstm (VFP_LDSTMIA);
10870}
10871
10872static void
10873do_vfp_sp_ldstmdb (void)
10874{
10875  vfp_sp_ldstm (VFP_LDSTMDB);
10876}
10877
10878static void
10879do_vfp_dp_ldstmia (void)
10880{
10881  vfp_dp_ldstm (VFP_LDSTMIA);
10882}
10883
10884static void
10885do_vfp_dp_ldstmdb (void)
10886{
10887  vfp_dp_ldstm (VFP_LDSTMDB);
10888}
10889
10890static void
10891do_vfp_xp_ldstmia (void)
10892{
10893  vfp_dp_ldstm (VFP_LDSTMIAX);
10894}
10895
10896static void
10897do_vfp_xp_ldstmdb (void)
10898{
10899  vfp_dp_ldstm (VFP_LDSTMDBX);
10900}
10901
10902static void
10903do_vfp_dp_rd_rm (void)
10904{
10905  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
10906	      && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10907	      _(BAD_FPU));
10908
10909  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10910  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10911}
10912
10913static void
10914do_vfp_dp_rn_rd (void)
10915{
10916  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10917  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10918}
10919
10920static void
10921do_vfp_dp_rd_rn (void)
10922{
10923  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10924  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10925}
10926
10927static void
10928do_vfp_dp_rd_rn_rm (void)
10929{
10930  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10931	      && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10932	      _(BAD_FPU));
10933
10934  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10935  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10936  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10937}
10938
10939static void
10940do_vfp_dp_rd (void)
10941{
10942  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10943}
10944
10945static void
10946do_vfp_dp_rm_rd_rn (void)
10947{
10948  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10949	      && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10950	      _(BAD_FPU));
10951
10952  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10953  encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10954  encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10955}
10956
10957/* VFPv3 instructions.  */
10958static void
10959do_vfp_sp_const (void)
10960{
10961  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10962  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10963  inst.instruction |= (inst.operands[1].imm & 0x0f);
10964}
10965
10966static void
10967do_vfp_dp_const (void)
10968{
10969  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10970  inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10971  inst.instruction |= (inst.operands[1].imm & 0x0f);
10972}
10973
10974static void
10975vfp_conv (int srcsize)
10976{
10977  int immbits = srcsize - inst.operands[1].imm;
10978
10979  if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
10980    {
10981      /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10982	 i.e. immbits must be in range 0 - 16.  */
10983      inst.error = _("immediate value out of range, expected range [0, 16]");
10984      return;
10985    }
10986  else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
10987    {
10988      /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10989	 i.e. immbits must be in range 0 - 31.  */
10990      inst.error = _("immediate value out of range, expected range [1, 32]");
10991      return;
10992    }
10993
10994  inst.instruction |= (immbits & 1) << 5;
10995  inst.instruction |= (immbits >> 1);
10996}
10997
10998static void
10999do_vfp_sp_conv_16 (void)
11000{
11001  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
11002  vfp_conv (16);
11003}
11004
11005static void
11006do_vfp_dp_conv_16 (void)
11007{
11008  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
11009  vfp_conv (16);
11010}
11011
11012static void
11013do_vfp_sp_conv_32 (void)
11014{
11015  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
11016  vfp_conv (32);
11017}
11018
11019static void
11020do_vfp_dp_conv_32 (void)
11021{
11022  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
11023  vfp_conv (32);
11024}
11025
11026/* FPA instructions.  Also in a logical order.	*/
11027
11028static void
11029do_fpa_cmp (void)
11030{
11031  inst.instruction |= inst.operands[0].reg << 16;
11032  inst.instruction |= inst.operands[1].reg;
11033}
11034
11035static void
11036do_fpa_ldmstm (void)
11037{
11038  inst.instruction |= inst.operands[0].reg << 12;
11039  switch (inst.operands[1].imm)
11040    {
11041    case 1: inst.instruction |= CP_T_X;		 break;
11042    case 2: inst.instruction |= CP_T_Y;		 break;
11043    case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
11044    case 4:					 break;
11045    default: abort ();
11046    }
11047
11048  if (inst.instruction & (PRE_INDEX | INDEX_UP))
11049    {
11050      /* The instruction specified "ea" or "fd", so we can only accept
11051	 [Rn]{!}.  The instruction does not really support stacking or
11052	 unstacking, so we have to emulate these by setting appropriate
11053	 bits and offsets.  */
11054      constraint (inst.relocs[0].exp.X_op != O_constant
11055		  || inst.relocs[0].exp.X_add_number != 0,
11056		  _("this instruction does not support indexing"));
11057
11058      if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
11059	inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
11060
11061      if (!(inst.instruction & INDEX_UP))
11062	inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
11063
11064      if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
11065	{
11066	  inst.operands[2].preind = 0;
11067	  inst.operands[2].postind = 1;
11068	}
11069    }
11070
11071  encode_arm_cp_address (2, true, true, 0);
11072}
11073
11074/* iWMMXt instructions: strictly in alphabetical order.	 */
11075
11076static void
11077do_iwmmxt_tandorc (void)
11078{
11079  constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
11080}
11081
11082static void
11083do_iwmmxt_textrc (void)
11084{
11085  inst.instruction |= inst.operands[0].reg << 12;
11086  inst.instruction |= inst.operands[1].imm;
11087}
11088
11089static void
11090do_iwmmxt_textrm (void)
11091{
11092  inst.instruction |= inst.operands[0].reg << 12;
11093  inst.instruction |= inst.operands[1].reg << 16;
11094  inst.instruction |= inst.operands[2].imm;
11095}
11096
11097static void
11098do_iwmmxt_tinsr (void)
11099{
11100  inst.instruction |= inst.operands[0].reg << 16;
11101  inst.instruction |= inst.operands[1].reg << 12;
11102  inst.instruction |= inst.operands[2].imm;
11103}
11104
11105static void
11106do_iwmmxt_tmia (void)
11107{
11108  inst.instruction |= inst.operands[0].reg << 5;
11109  inst.instruction |= inst.operands[1].reg;
11110  inst.instruction |= inst.operands[2].reg << 12;
11111}
11112
11113static void
11114do_iwmmxt_waligni (void)
11115{
11116  inst.instruction |= inst.operands[0].reg << 12;
11117  inst.instruction |= inst.operands[1].reg << 16;
11118  inst.instruction |= inst.operands[2].reg;
11119  inst.instruction |= inst.operands[3].imm << 20;
11120}
11121
11122static void
11123do_iwmmxt_wmerge (void)
11124{
11125  inst.instruction |= inst.operands[0].reg << 12;
11126  inst.instruction |= inst.operands[1].reg << 16;
11127  inst.instruction |= inst.operands[2].reg;
11128  inst.instruction |= inst.operands[3].imm << 21;
11129}
11130
11131static void
11132do_iwmmxt_wmov (void)
11133{
11134  /* WMOV rD, rN is an alias for WOR rD, rN, rN.  */
11135  inst.instruction |= inst.operands[0].reg << 12;
11136  inst.instruction |= inst.operands[1].reg << 16;
11137  inst.instruction |= inst.operands[1].reg;
11138}
11139
11140static void
11141do_iwmmxt_wldstbh (void)
11142{
11143  int reloc;
11144  inst.instruction |= inst.operands[0].reg << 12;
11145  if (thumb_mode)
11146    reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
11147  else
11148    reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
11149  encode_arm_cp_address (1, true, false, reloc);
11150}
11151
11152static void
11153do_iwmmxt_wldstw (void)
11154{
11155  /* RIWR_RIWC clears .isreg for a control register.  */
11156  if (!inst.operands[0].isreg)
11157    {
11158      constraint (inst.cond != COND_ALWAYS, BAD_COND);
11159      inst.instruction |= 0xf0000000;
11160    }
11161
11162  inst.instruction |= inst.operands[0].reg << 12;
11163  encode_arm_cp_address (1, true, true, 0);
11164}
11165
11166static void
11167do_iwmmxt_wldstd (void)
11168{
11169  inst.instruction |= inst.operands[0].reg << 12;
11170  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
11171      && inst.operands[1].immisreg)
11172    {
11173      inst.instruction &= ~0x1a000ff;
11174      inst.instruction |= (0xfU << 28);
11175      if (inst.operands[1].preind)
11176	inst.instruction |= PRE_INDEX;
11177      if (!inst.operands[1].negative)
11178	inst.instruction |= INDEX_UP;
11179      if (inst.operands[1].writeback)
11180	inst.instruction |= WRITE_BACK;
11181      inst.instruction |= inst.operands[1].reg << 16;
11182      inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
11183      inst.instruction |= inst.operands[1].imm;
11184    }
11185  else
11186    encode_arm_cp_address (1, true, false, 0);
11187}
11188
11189static void
11190do_iwmmxt_wshufh (void)
11191{
11192  inst.instruction |= inst.operands[0].reg << 12;
11193  inst.instruction |= inst.operands[1].reg << 16;
11194  inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
11195  inst.instruction |= (inst.operands[2].imm & 0x0f);
11196}
11197
11198static void
11199do_iwmmxt_wzero (void)
11200{
11201  /* WZERO reg is an alias for WANDN reg, reg, reg.  */
11202  inst.instruction |= inst.operands[0].reg;
11203  inst.instruction |= inst.operands[0].reg << 12;
11204  inst.instruction |= inst.operands[0].reg << 16;
11205}
11206
11207static void
11208do_iwmmxt_wrwrwr_or_imm5 (void)
11209{
11210  if (inst.operands[2].isreg)
11211    do_rd_rn_rm ();
11212  else {
11213    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
11214		_("immediate operand requires iWMMXt2"));
11215    do_rd_rn ();
11216    if (inst.operands[2].imm == 0)
11217      {
11218	switch ((inst.instruction >> 20) & 0xf)
11219	  {
11220	  case 4:
11221	  case 5:
11222	  case 6:
11223	  case 7:
11224	    /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16.  */
11225	    inst.operands[2].imm = 16;
11226	    inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
11227	    break;
11228	  case 8:
11229	  case 9:
11230	  case 10:
11231	  case 11:
11232	    /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32.  */
11233	    inst.operands[2].imm = 32;
11234	    inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
11235	    break;
11236	  case 12:
11237	  case 13:
11238	  case 14:
11239	  case 15:
11240	    {
11241	      /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn.  */
11242	      unsigned long wrn;
11243	      wrn = (inst.instruction >> 16) & 0xf;
11244	      inst.instruction &= 0xff0fff0f;
11245	      inst.instruction |= wrn;
11246	      /* Bail out here; the instruction is now assembled.  */
11247	      return;
11248	    }
11249	  }
11250      }
11251    /* Map 32 -> 0, etc.  */
11252    inst.operands[2].imm &= 0x1f;
11253    inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
11254  }
11255}
11256
11257/* Cirrus Maverick instructions.  Simple 2-, 3-, and 4-register
11258   operations first, then control, shift, and load/store.  */
11259
11260/* Insns like "foo X,Y,Z".  */
11261
11262static void
11263do_mav_triple (void)
11264{
11265  inst.instruction |= inst.operands[0].reg << 16;
11266  inst.instruction |= inst.operands[1].reg;
11267  inst.instruction |= inst.operands[2].reg << 12;
11268}
11269
11270/* Insns like "foo W,X,Y,Z".
11271    where W=MVAX[0:3] and X,Y,Z=MVFX[0:15].  */
11272
11273static void
11274do_mav_quad (void)
11275{
11276  inst.instruction |= inst.operands[0].reg << 5;
11277  inst.instruction |= inst.operands[1].reg << 12;
11278  inst.instruction |= inst.operands[2].reg << 16;
11279  inst.instruction |= inst.operands[3].reg;
11280}
11281
11282/* cfmvsc32<cond> DSPSC,MVDX[15:0].  */
11283static void
11284do_mav_dspsc (void)
11285{
11286  inst.instruction |= inst.operands[1].reg << 12;
11287}
11288
11289/* Maverick shift immediate instructions.
11290   cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11291   cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0].  */
11292
11293static void
11294do_mav_shift (void)
11295{
11296  int imm = inst.operands[2].imm;
11297
11298  inst.instruction |= inst.operands[0].reg << 12;
11299  inst.instruction |= inst.operands[1].reg << 16;
11300
11301  /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11302     Bits 5-7 of the insn should have bits 4-6 of the immediate.
11303     Bit 4 should be 0.	 */
11304  imm = (imm & 0xf) | ((imm & 0x70) << 1);
11305
11306  inst.instruction |= imm;
11307}
11308
11309/* XScale instructions.	 Also sorted arithmetic before move.  */
11310
11311/* Xscale multiply-accumulate (argument parse)
11312     MIAcc   acc0,Rm,Rs
11313     MIAPHcc acc0,Rm,Rs
11314     MIAxycc acc0,Rm,Rs.  */
11315
11316static void
11317do_xsc_mia (void)
11318{
11319  inst.instruction |= inst.operands[1].reg;
11320  inst.instruction |= inst.operands[2].reg << 12;
11321}
11322
11323/* Xscale move-accumulator-register (argument parse)
11324
11325     MARcc   acc0,RdLo,RdHi.  */
11326
11327static void
11328do_xsc_mar (void)
11329{
11330  inst.instruction |= inst.operands[1].reg << 12;
11331  inst.instruction |= inst.operands[2].reg << 16;
11332}
11333
11334/* Xscale move-register-accumulator (argument parse)
11335
11336     MRAcc   RdLo,RdHi,acc0.  */
11337
11338static void
11339do_xsc_mra (void)
11340{
11341  constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
11342  inst.instruction |= inst.operands[0].reg << 12;
11343  inst.instruction |= inst.operands[1].reg << 16;
11344}
11345
11346/* Encoding functions relevant only to Thumb.  */
11347
11348/* inst.operands[i] is a shifted-register operand; encode
11349   it into inst.instruction in the format used by Thumb32.  */
11350
11351static void
11352encode_thumb32_shifted_operand (int i)
11353{
11354  unsigned int value = inst.relocs[0].exp.X_add_number;
11355  unsigned int shift = inst.operands[i].shift_kind;
11356
11357  constraint (inst.operands[i].immisreg,
11358	      _("shift by register not allowed in thumb mode"));
11359  inst.instruction |= inst.operands[i].reg;
11360  if (shift == SHIFT_RRX)
11361    inst.instruction |= SHIFT_ROR << 4;
11362  else
11363    {
11364      constraint (inst.relocs[0].exp.X_op != O_constant,
11365		  _("expression too complex"));
11366
11367      constraint (value > 32
11368		  || (value == 32 && (shift == SHIFT_LSL
11369				      || shift == SHIFT_ROR)),
11370		  _("shift expression is too large"));
11371
11372      if (value == 0)
11373	shift = SHIFT_LSL;
11374      else if (value == 32)
11375	value = 0;
11376
11377      inst.instruction |= shift << 4;
11378      inst.instruction |= (value & 0x1c) << 10;
11379      inst.instruction |= (value & 0x03) << 6;
11380    }
11381}
11382
11383
11384/* inst.operands[i] was set up by parse_address.  Encode it into a
11385   Thumb32 format load or store instruction.  Reject forms that cannot
11386   be used with such instructions.  If is_t is true, reject forms that
11387   cannot be used with a T instruction; if is_d is true, reject forms
11388   that cannot be used with a D instruction.  If it is a store insn,
11389   reject PC in Rn.  */
11390
11391static void
11392encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
11393{
11394  const bool is_pc = (inst.operands[i].reg == REG_PC);
11395
11396  constraint (!inst.operands[i].isreg,
11397	      _("Instruction does not support =N addresses"));
11398
11399  inst.instruction |= inst.operands[i].reg << 16;
11400  if (inst.operands[i].immisreg)
11401    {
11402      constraint (is_pc, BAD_PC_ADDRESSING);
11403      constraint (is_t || is_d, _("cannot use register index with this instruction"));
11404      constraint (inst.operands[i].negative,
11405		  _("Thumb does not support negative register indexing"));
11406      constraint (inst.operands[i].postind,
11407		  _("Thumb does not support register post-indexing"));
11408      constraint (inst.operands[i].writeback,
11409		  _("Thumb does not support register indexing with writeback"));
11410      constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11411		  _("Thumb supports only LSL in shifted register indexing"));
11412
11413      inst.instruction |= inst.operands[i].imm;
11414      if (inst.operands[i].shifted)
11415	{
11416	  constraint (inst.relocs[0].exp.X_op != O_constant,
11417		      _("expression too complex"));
11418	  constraint (inst.relocs[0].exp.X_add_number < 0
11419		      || inst.relocs[0].exp.X_add_number > 3,
11420		      _("shift out of range"));
11421	  inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
11422	}
11423      inst.relocs[0].type = BFD_RELOC_UNUSED;
11424    }
11425  else if (inst.operands[i].preind)
11426    {
11427      constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
11428      constraint (is_t && inst.operands[i].writeback,
11429		  _("cannot use writeback with this instruction"));
11430      constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11431		  BAD_PC_ADDRESSING);
11432
11433      if (is_d)
11434	{
11435	  inst.instruction |= 0x01000000;
11436	  if (inst.operands[i].writeback)
11437	    inst.instruction |= 0x00200000;
11438	}
11439      else
11440	{
11441	  inst.instruction |= 0x00000c00;
11442	  if (inst.operands[i].writeback)
11443	    inst.instruction |= 0x00000100;
11444	}
11445      inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11446    }
11447  else if (inst.operands[i].postind)
11448    {
11449      gas_assert (inst.operands[i].writeback);
11450      constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
11451      constraint (is_t, _("cannot use post-indexing with this instruction"));
11452
11453      if (is_d)
11454	inst.instruction |= 0x00200000;
11455      else
11456	inst.instruction |= 0x00000900;
11457      inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
11458    }
11459  else /* unindexed - only for coprocessor */
11460    inst.error = _("instruction does not accept unindexed addressing");
11461}
11462
11463/* Table of Thumb instructions which exist in 16- and/or 32-bit
11464   encodings (the latter only in post-V6T2 cores).  The index is the
11465   value used in the insns table below.  When there is more than one
11466   possible 16-bit encoding for the instruction, this table always
11467   holds variant (1).
11468   Also contains several pseudo-instructions used during relaxation.  */
11469#define T16_32_TAB				\
11470  X(_adc,   4140, eb400000),			\
11471  X(_adcs,  4140, eb500000),			\
11472  X(_add,   1c00, eb000000),			\
11473  X(_adds,  1c00, eb100000),			\
11474  X(_addi,  0000, f1000000),			\
11475  X(_addis, 0000, f1100000),			\
11476  X(_add_pc,000f, f20f0000),			\
11477  X(_add_sp,000d, f10d0000),			\
11478  X(_adr,   000f, f20f0000),			\
11479  X(_and,   4000, ea000000),			\
11480  X(_ands,  4000, ea100000),			\
11481  X(_asr,   1000, fa40f000),			\
11482  X(_asrs,  1000, fa50f000),			\
11483  X(_aut,   0000, f3af802d),			\
11484  X(_autg,   0000, fb500f00),			\
11485  X(_b,     e000, f000b000),			\
11486  X(_bcond, d000, f0008000),			\
11487  X(_bf,    0000, f040e001),			\
11488  X(_bfcsel,0000, f000e001),			\
11489  X(_bfx,   0000, f060e001),			\
11490  X(_bfl,   0000, f000c001),			\
11491  X(_bflx,  0000, f070e001),			\
11492  X(_bic,   4380, ea200000),			\
11493  X(_bics,  4380, ea300000),			\
11494  X(_bxaut, 0000, fb500f10),			\
11495  X(_cinc,  0000, ea509000),			\
11496  X(_cinv,  0000, ea50a000),			\
11497  X(_cmn,   42c0, eb100f00),			\
11498  X(_cmp,   2800, ebb00f00),			\
11499  X(_cneg,  0000, ea50b000),			\
11500  X(_cpsie, b660, f3af8400),			\
11501  X(_cpsid, b670, f3af8600),			\
11502  X(_cpy,   4600, ea4f0000),			\
11503  X(_csel,  0000, ea508000),			\
11504  X(_cset,  0000, ea5f900f),			\
11505  X(_csetm, 0000, ea5fa00f),			\
11506  X(_csinc, 0000, ea509000),			\
11507  X(_csinv, 0000, ea50a000),			\
11508  X(_csneg, 0000, ea50b000),			\
11509  X(_dec_sp,80dd, f1ad0d00),			\
11510  X(_dls,   0000, f040e001),			\
11511  X(_dlstp, 0000, f000e001),			\
11512  X(_eor,   4040, ea800000),			\
11513  X(_eors,  4040, ea900000),			\
11514  X(_inc_sp,00dd, f10d0d00),			\
11515  X(_lctp,  0000, f00fe001),			\
11516  X(_ldmia, c800, e8900000),			\
11517  X(_ldr,   6800, f8500000),			\
11518  X(_ldrb,  7800, f8100000),			\
11519  X(_ldrh,  8800, f8300000),			\
11520  X(_ldrsb, 5600, f9100000),			\
11521  X(_ldrsh, 5e00, f9300000),			\
11522  X(_ldr_pc,4800, f85f0000),			\
11523  X(_ldr_pc2,4800, f85f0000),			\
11524  X(_ldr_sp,9800, f85d0000),			\
11525  X(_le,    0000, f00fc001),			\
11526  X(_letp,  0000, f01fc001),			\
11527  X(_lsl,   0000, fa00f000),			\
11528  X(_lsls,  0000, fa10f000),			\
11529  X(_lsr,   0800, fa20f000),			\
11530  X(_lsrs,  0800, fa30f000),			\
11531  X(_mov,   2000, ea4f0000),			\
11532  X(_movs,  2000, ea5f0000),			\
11533  X(_mul,   4340, fb00f000),                     \
11534  X(_muls,  4340, ffffffff), /* no 32b muls */	\
11535  X(_mvn,   43c0, ea6f0000),			\
11536  X(_mvns,  43c0, ea7f0000),			\
11537  X(_neg,   4240, f1c00000), /* rsb #0 */	\
11538  X(_negs,  4240, f1d00000), /* rsbs #0 */	\
11539  X(_orr,   4300, ea400000),			\
11540  X(_orrs,  4300, ea500000),			\
11541  X(_pac,   0000, f3af801d),			\
11542  X(_pacbti, 0000, f3af800d),			\
11543  X(_pacg,  0000, fb60f000),			\
11544  X(_pop,   bc00, e8bd0000), /* ldmia sp!,... */	\
11545  X(_push,  b400, e92d0000), /* stmdb sp!,... */	\
11546  X(_rev,   ba00, fa90f080),			\
11547  X(_rev16, ba40, fa90f090),			\
11548  X(_revsh, bac0, fa90f0b0),			\
11549  X(_ror,   41c0, fa60f000),			\
11550  X(_rors,  41c0, fa70f000),			\
11551  X(_sbc,   4180, eb600000),			\
11552  X(_sbcs,  4180, eb700000),			\
11553  X(_stmia, c000, e8800000),			\
11554  X(_str,   6000, f8400000),			\
11555  X(_strb,  7000, f8000000),			\
11556  X(_strh,  8000, f8200000),			\
11557  X(_str_sp,9000, f84d0000),			\
11558  X(_sub,   1e00, eba00000),			\
11559  X(_subs,  1e00, ebb00000),			\
11560  X(_subi,  8000, f1a00000),			\
11561  X(_subis, 8000, f1b00000),			\
11562  X(_sxtb,  b240, fa4ff080),			\
11563  X(_sxth,  b200, fa0ff080),			\
11564  X(_tst,   4200, ea100f00),			\
11565  X(_uxtb,  b2c0, fa5ff080),			\
11566  X(_uxth,  b280, fa1ff080),			\
11567  X(_nop,   bf00, f3af8000),			\
11568  X(_yield, bf10, f3af8001),			\
11569  X(_wfe,   bf20, f3af8002),			\
11570  X(_wfi,   bf30, f3af8003),			\
11571  X(_wls,   0000, f040c001),			\
11572  X(_wlstp, 0000, f000c001),			\
11573  X(_sev,   bf40, f3af8004),                    \
11574  X(_sevl,  bf50, f3af8005),			\
11575  X(_udf,   de00, f7f0a000)
11576
11577/* To catch errors in encoding functions, the codes are all offset by
11578   0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11579   as 16-bit instructions.  */
11580#define X(a,b,c) T_MNEM##a
11581enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
11582#undef X
11583
11584#define X(a,b,c) 0x##b
11585static const unsigned short thumb_op16[] = { T16_32_TAB };
11586#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11587#undef X
11588
11589#define X(a,b,c) 0x##c
11590static const unsigned int thumb_op32[] = { T16_32_TAB };
11591#define THUMB_OP32(n)        (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11592#define THUMB_SETS_FLAGS(n)  (THUMB_OP32 (n) & 0x00100000)
11593#undef X
11594#undef T16_32_TAB
11595
11596/* Thumb instruction encoders, in alphabetical order.  */
11597
11598/* ADDW or SUBW.  */
11599
11600static void
11601do_t_add_sub_w (void)
11602{
11603  int Rd, Rn;
11604
11605  Rd = inst.operands[0].reg;
11606  Rn = inst.operands[1].reg;
11607
11608  /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11609     is the SP-{plus,minus}-immediate form of the instruction.  */
11610  if (Rn == REG_SP)
11611    constraint (Rd == REG_PC, BAD_PC);
11612  else
11613    reject_bad_reg (Rd);
11614
11615  inst.instruction |= (Rn << 16) | (Rd << 8);
11616  inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11617}
11618
11619/* Parse an add or subtract instruction.  We get here with inst.instruction
11620   equaling any of THUMB_OPCODE_add, adds, sub, or subs.  */
11621
11622static void
11623do_t_add_sub (void)
11624{
11625  int Rd, Rs, Rn;
11626
11627  Rd = inst.operands[0].reg;
11628  Rs = (inst.operands[1].present
11629	? inst.operands[1].reg    /* Rd, Rs, foo */
11630	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
11631
11632  if (Rd == REG_PC)
11633    set_pred_insn_type_last ();
11634
11635  if (unified_syntax)
11636    {
11637      bool flags;
11638      bool narrow;
11639      int opcode;
11640
11641      flags = (inst.instruction == T_MNEM_adds
11642	       || inst.instruction == T_MNEM_subs);
11643      if (flags)
11644	narrow = !in_pred_block ();
11645      else
11646	narrow = in_pred_block ();
11647      if (!inst.operands[2].isreg)
11648	{
11649	  int add;
11650
11651	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11652	    constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11653
11654	  add = (inst.instruction == T_MNEM_add
11655		 || inst.instruction == T_MNEM_adds);
11656	  opcode = 0;
11657	  if (inst.size_req != 4)
11658	    {
11659	      /* Attempt to use a narrow opcode, with relaxation if
11660		 appropriate.  */
11661	      if (Rd == REG_SP && Rs == REG_SP && !flags)
11662		opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
11663	      else if (Rd <= 7 && Rs == REG_SP && add && !flags)
11664		opcode = T_MNEM_add_sp;
11665	      else if (Rd <= 7 && Rs == REG_PC && add && !flags)
11666		opcode = T_MNEM_add_pc;
11667	      else if (Rd <= 7 && Rs <= 7 && narrow)
11668		{
11669		  if (flags)
11670		    opcode = add ? T_MNEM_addis : T_MNEM_subis;
11671		  else
11672		    opcode = add ? T_MNEM_addi : T_MNEM_subi;
11673		}
11674	      if (opcode)
11675		{
11676		  inst.instruction = THUMB_OP16(opcode);
11677		  inst.instruction |= (Rd << 4) | Rs;
11678		  if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11679		      || (inst.relocs[0].type
11680			  > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
11681		  {
11682		    if (inst.size_req == 2)
11683		      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11684		    else
11685		      inst.relax = opcode;
11686		  }
11687		}
11688	      else
11689		constraint (inst.size_req == 2, _("cannot honor width suffix"));
11690	    }
11691	  if (inst.size_req == 4
11692	      || (inst.size_req != 2 && !opcode))
11693	    {
11694	      constraint ((inst.relocs[0].type
11695			   >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
11696			  && (inst.relocs[0].type
11697			      <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
11698			  THUMB1_RELOC_ONLY);
11699	      if (Rd == REG_PC)
11700		{
11701		  constraint (add, BAD_PC);
11702		  constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11703			     _("only SUBS PC, LR, #const allowed"));
11704		  constraint (inst.relocs[0].exp.X_op != O_constant,
11705			      _("expression too complex"));
11706		  constraint (inst.relocs[0].exp.X_add_number < 0
11707			      || inst.relocs[0].exp.X_add_number > 0xff,
11708			     _("immediate value out of range"));
11709		  inst.instruction = T2_SUBS_PC_LR
11710				     | inst.relocs[0].exp.X_add_number;
11711		  inst.relocs[0].type = BFD_RELOC_UNUSED;
11712		  return;
11713		}
11714	      else if (Rs == REG_PC)
11715		{
11716		  /* Always use addw/subw.  */
11717		  inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
11718		  inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
11719		}
11720	      else
11721		{
11722		  inst.instruction = THUMB_OP32 (inst.instruction);
11723		  inst.instruction = (inst.instruction & 0xe1ffffff)
11724				     | 0x10000000;
11725		  if (flags)
11726		    inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11727		  else
11728		    inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
11729		}
11730	      inst.instruction |= Rd << 8;
11731	      inst.instruction |= Rs << 16;
11732	    }
11733	}
11734      else
11735	{
11736	  unsigned int value = inst.relocs[0].exp.X_add_number;
11737	  unsigned int shift = inst.operands[2].shift_kind;
11738
11739	  Rn = inst.operands[2].reg;
11740	  /* See if we can do this with a 16-bit instruction.  */
11741	  if (!inst.operands[2].shifted && inst.size_req != 4)
11742	    {
11743	      if (Rd > 7 || Rs > 7 || Rn > 7)
11744		narrow = false;
11745
11746	      if (narrow)
11747		{
11748		  inst.instruction = ((inst.instruction == T_MNEM_adds
11749				       || inst.instruction == T_MNEM_add)
11750				      ? T_OPCODE_ADD_R3
11751				      : T_OPCODE_SUB_R3);
11752		  inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11753		  return;
11754		}
11755
11756	      if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
11757		{
11758		  /* Thumb-1 cores (except v6-M) require at least one high
11759		     register in a narrow non flag setting add.  */
11760		  if (Rd > 7 || Rn > 7
11761		      || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
11762		      || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
11763		    {
11764		      if (Rd == Rn)
11765			{
11766			  Rn = Rs;
11767			  Rs = Rd;
11768			}
11769		      inst.instruction = T_OPCODE_ADD_HI;
11770		      inst.instruction |= (Rd & 8) << 4;
11771		      inst.instruction |= (Rd & 7);
11772		      inst.instruction |= Rn << 3;
11773		      return;
11774		    }
11775		}
11776	    }
11777
11778	  constraint (Rd == REG_PC, BAD_PC);
11779	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11780	    constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
11781	  constraint (Rs == REG_PC, BAD_PC);
11782	  reject_bad_reg (Rn);
11783
11784	  /* If we get here, it can't be done in 16 bits.  */
11785	  constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11786		      _("shift must be constant"));
11787	  inst.instruction = THUMB_OP32 (inst.instruction);
11788	  inst.instruction |= Rd << 8;
11789	  inst.instruction |= Rs << 16;
11790	  constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
11791		      _("shift value over 3 not allowed in thumb mode"));
11792	  constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
11793		      _("only LSL shift allowed in thumb mode"));
11794	  encode_thumb32_shifted_operand (2);
11795	}
11796    }
11797  else
11798    {
11799      constraint (inst.instruction == T_MNEM_adds
11800		  || inst.instruction == T_MNEM_subs,
11801		  BAD_THUMB32);
11802
11803      if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
11804	{
11805	  constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
11806		      || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
11807		      BAD_HIREG);
11808
11809	  inst.instruction = (inst.instruction == T_MNEM_add
11810			      ? 0x0000 : 0x8000);
11811	  inst.instruction |= (Rd << 4) | Rs;
11812	  inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11813	  return;
11814	}
11815
11816      Rn = inst.operands[2].reg;
11817      constraint (inst.operands[2].shifted, _("unshifted register required"));
11818
11819      /* We now have Rd, Rs, and Rn set to registers.  */
11820      if (Rd > 7 || Rs > 7 || Rn > 7)
11821	{
11822	  /* Can't do this for SUB.	 */
11823	  constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11824	  inst.instruction = T_OPCODE_ADD_HI;
11825	  inst.instruction |= (Rd & 8) << 4;
11826	  inst.instruction |= (Rd & 7);
11827	  if (Rs == Rd)
11828	    inst.instruction |= Rn << 3;
11829	  else if (Rn == Rd)
11830	    inst.instruction |= Rs << 3;
11831	  else
11832	    constraint (1, _("dest must overlap one source register"));
11833	}
11834      else
11835	{
11836	  inst.instruction = (inst.instruction == T_MNEM_add
11837			      ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
11838	  inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11839	}
11840    }
11841}
11842
11843static void
11844do_t_adr (void)
11845{
11846  unsigned Rd;
11847
11848  Rd = inst.operands[0].reg;
11849  reject_bad_reg (Rd);
11850
11851  if (unified_syntax && inst.size_req == 0 && Rd <= 7)
11852    {
11853      /* Defer to section relaxation.  */
11854      inst.relax = inst.instruction;
11855      inst.instruction = THUMB_OP16 (inst.instruction);
11856      inst.instruction |= Rd << 4;
11857    }
11858  else if (unified_syntax && inst.size_req != 2)
11859    {
11860      /* Generate a 32-bit opcode.  */
11861      inst.instruction = THUMB_OP32 (inst.instruction);
11862      inst.instruction |= Rd << 8;
11863      inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11864      inst.relocs[0].pc_rel = 1;
11865    }
11866  else
11867    {
11868      /* Generate a 16-bit opcode.  */
11869      inst.instruction = THUMB_OP16 (inst.instruction);
11870      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11871      inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust.  */
11872      inst.relocs[0].pc_rel = 1;
11873      inst.instruction |= Rd << 4;
11874    }
11875
11876  if (inst.relocs[0].exp.X_op == O_symbol
11877      && inst.relocs[0].exp.X_add_symbol != NULL
11878      && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11879      && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11880    inst.relocs[0].exp.X_add_number += 1;
11881}
11882
11883/* Arithmetic instructions for which there is just one 16-bit
11884   instruction encoding, and it allows only two low registers.
11885   For maximal compatibility with ARM syntax, we allow three register
11886   operands even when Thumb-32 instructions are not available, as long
11887   as the first two are identical.  For instance, both "sbc r0,r1" and
11888   "sbc r0,r0,r1" are allowed.  */
11889static void
11890do_t_arit3 (void)
11891{
11892  int Rd, Rs, Rn;
11893
11894  Rd = inst.operands[0].reg;
11895  Rs = (inst.operands[1].present
11896	? inst.operands[1].reg    /* Rd, Rs, foo */
11897	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
11898  Rn = inst.operands[2].reg;
11899
11900  reject_bad_reg (Rd);
11901  reject_bad_reg (Rs);
11902  if (inst.operands[2].isreg)
11903    reject_bad_reg (Rn);
11904
11905  if (unified_syntax)
11906    {
11907      if (!inst.operands[2].isreg)
11908	{
11909	  /* For an immediate, we always generate a 32-bit opcode;
11910	     section relaxation will shrink it later if possible.  */
11911	  inst.instruction = THUMB_OP32 (inst.instruction);
11912	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11913	  inst.instruction |= Rd << 8;
11914	  inst.instruction |= Rs << 16;
11915	  inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
11916	}
11917      else
11918	{
11919	  bool narrow;
11920
11921	  /* See if we can do this with a 16-bit instruction.  */
11922	  if (THUMB_SETS_FLAGS (inst.instruction))
11923	    narrow = !in_pred_block ();
11924	  else
11925	    narrow = in_pred_block ();
11926
11927	  if (Rd > 7 || Rn > 7 || Rs > 7)
11928	    narrow = false;
11929	  if (inst.operands[2].shifted)
11930	    narrow = false;
11931	  if (inst.size_req == 4)
11932	    narrow = false;
11933
11934	  if (narrow
11935	      && Rd == Rs)
11936	    {
11937	      inst.instruction = THUMB_OP16 (inst.instruction);
11938	      inst.instruction |= Rd;
11939	      inst.instruction |= Rn << 3;
11940	      return;
11941	    }
11942
11943	  /* If we get here, it can't be done in 16 bits.  */
11944	  constraint (inst.operands[2].shifted
11945		      && inst.operands[2].immisreg,
11946		      _("shift must be constant"));
11947	  inst.instruction = THUMB_OP32 (inst.instruction);
11948	  inst.instruction |= Rd << 8;
11949	  inst.instruction |= Rs << 16;
11950	  encode_thumb32_shifted_operand (2);
11951	}
11952    }
11953  else
11954    {
11955      /* On its face this is a lie - the instruction does set the
11956	 flags.  However, the only supported mnemonic in this mode
11957	 says it doesn't.  */
11958      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11959
11960      constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11961		  _("unshifted register required"));
11962      constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11963      constraint (Rd != Rs,
11964		  _("dest and source1 must be the same register"));
11965
11966      inst.instruction = THUMB_OP16 (inst.instruction);
11967      inst.instruction |= Rd;
11968      inst.instruction |= Rn << 3;
11969    }
11970}
11971
11972/* Similarly, but for instructions where the arithmetic operation is
11973   commutative, so we can allow either of them to be different from
11974   the destination operand in a 16-bit instruction.  For instance, all
11975   three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11976   accepted.  */
11977static void
11978do_t_arit3c (void)
11979{
11980  int Rd, Rs, Rn;
11981
11982  Rd = inst.operands[0].reg;
11983  Rs = (inst.operands[1].present
11984	? inst.operands[1].reg    /* Rd, Rs, foo */
11985	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
11986  Rn = inst.operands[2].reg;
11987
11988  reject_bad_reg (Rd);
11989  reject_bad_reg (Rs);
11990  if (inst.operands[2].isreg)
11991    reject_bad_reg (Rn);
11992
11993  if (unified_syntax)
11994    {
11995      if (!inst.operands[2].isreg)
11996	{
11997	  /* For an immediate, we always generate a 32-bit opcode;
11998	     section relaxation will shrink it later if possible.  */
11999	  inst.instruction = THUMB_OP32 (inst.instruction);
12000	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12001	  inst.instruction |= Rd << 8;
12002	  inst.instruction |= Rs << 16;
12003	  inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
12004	}
12005      else
12006	{
12007	  bool narrow;
12008
12009	  /* See if we can do this with a 16-bit instruction.  */
12010	  if (THUMB_SETS_FLAGS (inst.instruction))
12011	    narrow = !in_pred_block ();
12012	  else
12013	    narrow = in_pred_block ();
12014
12015	  if (Rd > 7 || Rn > 7 || Rs > 7)
12016	    narrow = false;
12017	  if (inst.operands[2].shifted)
12018	    narrow = false;
12019	  if (inst.size_req == 4)
12020	    narrow = false;
12021
12022	  if (narrow)
12023	    {
12024	      if (Rd == Rs)
12025		{
12026		  inst.instruction = THUMB_OP16 (inst.instruction);
12027		  inst.instruction |= Rd;
12028		  inst.instruction |= Rn << 3;
12029		  return;
12030		}
12031	      if (Rd == Rn)
12032		{
12033		  inst.instruction = THUMB_OP16 (inst.instruction);
12034		  inst.instruction |= Rd;
12035		  inst.instruction |= Rs << 3;
12036		  return;
12037		}
12038	    }
12039
12040	  /* If we get here, it can't be done in 16 bits.  */
12041	  constraint (inst.operands[2].shifted
12042		      && inst.operands[2].immisreg,
12043		      _("shift must be constant"));
12044	  inst.instruction = THUMB_OP32 (inst.instruction);
12045	  inst.instruction |= Rd << 8;
12046	  inst.instruction |= Rs << 16;
12047	  encode_thumb32_shifted_operand (2);
12048	}
12049    }
12050  else
12051    {
12052      /* On its face this is a lie - the instruction does set the
12053	 flags.  However, the only supported mnemonic in this mode
12054	 says it doesn't.  */
12055      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12056
12057      constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
12058		  _("unshifted register required"));
12059      constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
12060
12061      inst.instruction = THUMB_OP16 (inst.instruction);
12062      inst.instruction |= Rd;
12063
12064      if (Rd == Rs)
12065	inst.instruction |= Rn << 3;
12066      else if (Rd == Rn)
12067	inst.instruction |= Rs << 3;
12068      else
12069	constraint (1, _("dest must overlap one source register"));
12070    }
12071}
12072
12073static void
12074do_t_bfc (void)
12075{
12076  unsigned Rd;
12077  unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
12078  constraint (msb > 32, _("bit-field extends past end of register"));
12079  /* The instruction encoding stores the LSB and MSB,
12080     not the LSB and width.  */
12081  Rd = inst.operands[0].reg;
12082  reject_bad_reg (Rd);
12083  inst.instruction |= Rd << 8;
12084  inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
12085  inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
12086  inst.instruction |= msb - 1;
12087}
12088
12089static void
12090do_t_bfi (void)
12091{
12092  int Rd, Rn;
12093  unsigned int msb;
12094
12095  Rd = inst.operands[0].reg;
12096  reject_bad_reg (Rd);
12097
12098  /* #0 in second position is alternative syntax for bfc, which is
12099     the same instruction but with REG_PC in the Rm field.  */
12100  if (!inst.operands[1].isreg)
12101    Rn = REG_PC;
12102  else
12103    {
12104      Rn = inst.operands[1].reg;
12105      reject_bad_reg (Rn);
12106    }
12107
12108  msb = inst.operands[2].imm + inst.operands[3].imm;
12109  constraint (msb > 32, _("bit-field extends past end of register"));
12110  /* The instruction encoding stores the LSB and MSB,
12111     not the LSB and width.  */
12112  inst.instruction |= Rd << 8;
12113  inst.instruction |= Rn << 16;
12114  inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
12115  inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
12116  inst.instruction |= msb - 1;
12117}
12118
12119static void
12120do_t_bfx (void)
12121{
12122  unsigned Rd, Rn;
12123
12124  Rd = inst.operands[0].reg;
12125  Rn = inst.operands[1].reg;
12126
12127  reject_bad_reg (Rd);
12128  reject_bad_reg (Rn);
12129
12130  constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
12131	      _("bit-field extends past end of register"));
12132  inst.instruction |= Rd << 8;
12133  inst.instruction |= Rn << 16;
12134  inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
12135  inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
12136  inst.instruction |= inst.operands[3].imm - 1;
12137}
12138
12139/* ARM V5 Thumb BLX (argument parse)
12140	BLX <target_addr>	which is BLX(1)
12141	BLX <Rm>		which is BLX(2)
12142   Unfortunately, there are two different opcodes for this mnemonic.
12143   So, the insns[].value is not used, and the code here zaps values
12144	into inst.instruction.
12145
12146   ??? How to take advantage of the additional two bits of displacement
12147   available in Thumb32 mode?  Need new relocation?  */
12148
12149static void
12150do_t_blx (void)
12151{
12152  set_pred_insn_type_last ();
12153
12154  if (inst.operands[0].isreg)
12155    {
12156      constraint (inst.operands[0].reg == REG_PC, BAD_PC);
12157      /* We have a register, so this is BLX(2).  */
12158      inst.instruction |= inst.operands[0].reg << 3;
12159    }
12160  else
12161    {
12162      /* No register.  This must be BLX(1).  */
12163      inst.instruction = 0xf000e800;
12164      encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
12165    }
12166}
12167
12168static void
12169do_t_branch (void)
12170{
12171  int opcode;
12172  int cond;
12173  bfd_reloc_code_real_type reloc;
12174
12175  cond = inst.cond;
12176  set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);
12177
12178  if (in_pred_block ())
12179    {
12180      /* Conditional branches inside IT blocks are encoded as unconditional
12181	 branches.  */
12182      cond = COND_ALWAYS;
12183    }
12184  else
12185    cond = inst.cond;
12186
12187  if (cond != COND_ALWAYS)
12188    opcode = T_MNEM_bcond;
12189  else
12190    opcode = inst.instruction;
12191
12192  if (unified_syntax
12193      && (inst.size_req == 4
12194	  || (inst.size_req != 2
12195	      && (inst.operands[0].hasreloc
12196		  || inst.relocs[0].exp.X_op == O_constant))))
12197    {
12198      inst.instruction = THUMB_OP32(opcode);
12199      if (cond == COND_ALWAYS)
12200	reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
12201      else
12202	{
12203	  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
12204		      _("selected architecture does not support "
12205			"wide conditional branch instruction"));
12206
12207	  gas_assert (cond != 0xF);
12208	  inst.instruction |= cond << 22;
12209	  reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
12210	}
12211    }
12212  else
12213    {
12214      inst.instruction = THUMB_OP16(opcode);
12215      if (cond == COND_ALWAYS)
12216	reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
12217      else
12218	{
12219	  inst.instruction |= cond << 8;
12220	  reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
12221	}
12222      /* Allow section relaxation.  */
12223      if (unified_syntax && inst.size_req != 2)
12224	inst.relax = opcode;
12225    }
12226  inst.relocs[0].type = reloc;
12227  inst.relocs[0].pc_rel = 1;
12228}
12229
12230/* Actually do the work for Thumb state bkpt and hlt.  The only difference
12231   between the two is the maximum immediate allowed - which is passed in
12232   RANGE.  */
12233static void
12234do_t_bkpt_hlt1 (int range)
12235{
12236  constraint (inst.cond != COND_ALWAYS,
12237	      _("instruction is always unconditional"));
12238  if (inst.operands[0].present)
12239    {
12240      constraint (inst.operands[0].imm > range,
12241		  _("immediate value out of range"));
12242      inst.instruction |= inst.operands[0].imm;
12243    }
12244
12245  set_pred_insn_type (NEUTRAL_IT_INSN);
12246}
12247
12248static void
12249do_t_hlt (void)
12250{
12251  do_t_bkpt_hlt1 (63);
12252}
12253
12254static void
12255do_t_bkpt (void)
12256{
12257  do_t_bkpt_hlt1 (255);
12258}
12259
12260static void
12261do_t_branch23 (void)
12262{
12263  set_pred_insn_type_last ();
12264  encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
12265
12266  /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12267     this file.  We used to simply ignore the PLT reloc type here --
12268     the branch encoding is now needed to deal with TLSCALL relocs.
12269     So if we see a PLT reloc now, put it back to how it used to be to
12270     keep the preexisting behaviour.  */
12271  if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
12272    inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
12273
12274#if defined(OBJ_COFF)
12275  /* If the destination of the branch is a defined symbol which does not have
12276     the THUMB_FUNC attribute, then we must be calling a function which has
12277     the (interfacearm) attribute.  We look for the Thumb entry point to that
12278     function and change the branch to refer to that function instead.	*/
12279  if (	 inst.relocs[0].exp.X_op == O_symbol
12280      && inst.relocs[0].exp.X_add_symbol != NULL
12281      && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
12282      && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
12283    inst.relocs[0].exp.X_add_symbol
12284      = find_real_start (inst.relocs[0].exp.X_add_symbol);
12285#endif
12286}
12287
12288static void
12289do_t_bx (void)
12290{
12291  set_pred_insn_type_last ();
12292  inst.instruction |= inst.operands[0].reg << 3;
12293  /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC.	 The reloc
12294     should cause the alignment to be checked once it is known.	 This is
12295     because BX PC only works if the instruction is word aligned.  */
12296}
12297
12298static void
12299do_t_bxj (void)
12300{
12301  int Rm;
12302
12303  set_pred_insn_type_last ();
12304  Rm = inst.operands[0].reg;
12305  reject_bad_reg (Rm);
12306  inst.instruction |= Rm << 16;
12307}
12308
12309static void
12310do_t_clz (void)
12311{
12312  unsigned Rd;
12313  unsigned Rm;
12314
12315  Rd = inst.operands[0].reg;
12316  Rm = inst.operands[1].reg;
12317
12318  reject_bad_reg (Rd);
12319  reject_bad_reg (Rm);
12320
12321  inst.instruction |= Rd << 8;
12322  inst.instruction |= Rm << 16;
12323  inst.instruction |= Rm;
12324}
12325
12326/* For the Armv8.1-M conditional instructions.  */
12327static void
12328do_t_cond (void)
12329{
12330  unsigned Rd, Rn, Rm;
12331  signed int cond;
12332
12333  constraint (inst.cond != COND_ALWAYS, BAD_COND);
12334
12335  Rd = inst.operands[0].reg;
12336  switch (inst.instruction)
12337    {
12338      case T_MNEM_csinc:
12339      case T_MNEM_csinv:
12340      case T_MNEM_csneg:
12341      case T_MNEM_csel:
12342	Rn = inst.operands[1].reg;
12343	Rm = inst.operands[2].reg;
12344	cond = inst.operands[3].imm;
12345	constraint (Rn == REG_SP, BAD_SP);
12346	constraint (Rm == REG_SP, BAD_SP);
12347	break;
12348
12349      case T_MNEM_cinc:
12350      case T_MNEM_cinv:
12351      case T_MNEM_cneg:
12352	Rn = inst.operands[1].reg;
12353	cond = inst.operands[2].imm;
12354	/* Invert the last bit to invert the cond.  */
12355	cond = TOGGLE_BIT (cond, 0);
12356	constraint (Rn == REG_SP, BAD_SP);
12357	Rm = Rn;
12358	break;
12359
12360      case T_MNEM_csetm:
12361      case T_MNEM_cset:
12362	cond = inst.operands[1].imm;
12363	/* Invert the last bit to invert the cond.  */
12364	cond = TOGGLE_BIT (cond, 0);
12365	Rn = REG_PC;
12366	Rm = REG_PC;
12367	break;
12368
12369      default: abort ();
12370    }
12371
12372  set_pred_insn_type (OUTSIDE_PRED_INSN);
12373  inst.instruction = THUMB_OP32 (inst.instruction);
12374  inst.instruction |= Rd << 8;
12375  inst.instruction |= Rn << 16;
12376  inst.instruction |= Rm;
12377  inst.instruction |= cond << 4;
12378}
12379
12380static void
12381do_t_csdb (void)
12382{
12383  set_pred_insn_type (OUTSIDE_PRED_INSN);
12384}
12385
12386static void
12387do_t_cps (void)
12388{
12389  set_pred_insn_type (OUTSIDE_PRED_INSN);
12390  inst.instruction |= inst.operands[0].imm;
12391}
12392
12393static void
12394do_t_cpsi (void)
12395{
12396  set_pred_insn_type (OUTSIDE_PRED_INSN);
12397  if (unified_syntax
12398      && (inst.operands[1].present || inst.size_req == 4)
12399      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
12400    {
12401      unsigned int imod = (inst.instruction & 0x0030) >> 4;
12402      inst.instruction = 0xf3af8000;
12403      inst.instruction |= imod << 9;
12404      inst.instruction |= inst.operands[0].imm << 5;
12405      if (inst.operands[1].present)
12406	inst.instruction |= 0x100 | inst.operands[1].imm;
12407    }
12408  else
12409    {
12410      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
12411		  && (inst.operands[0].imm & 4),
12412		  _("selected processor does not support 'A' form "
12413		    "of this instruction"));
12414      constraint (inst.operands[1].present || inst.size_req == 4,
12415		  _("Thumb does not support the 2-argument "
12416		    "form of this instruction"));
12417      inst.instruction |= inst.operands[0].imm;
12418    }
12419}
12420
12421/* THUMB CPY instruction (argument parse).  */
12422
12423static void
12424do_t_cpy (void)
12425{
12426  if (inst.size_req == 4)
12427    {
12428      inst.instruction = THUMB_OP32 (T_MNEM_mov);
12429      inst.instruction |= inst.operands[0].reg << 8;
12430      inst.instruction |= inst.operands[1].reg;
12431    }
12432  else
12433    {
12434      inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
12435      inst.instruction |= (inst.operands[0].reg & 0x7);
12436      inst.instruction |= inst.operands[1].reg << 3;
12437    }
12438}
12439
12440static void
12441do_t_cbz (void)
12442{
12443  set_pred_insn_type (OUTSIDE_PRED_INSN);
12444  constraint (inst.operands[0].reg > 7, BAD_HIREG);
12445  inst.instruction |= inst.operands[0].reg;
12446  inst.relocs[0].pc_rel = 1;
12447  inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
12448}
12449
12450static void
12451do_t_dbg (void)
12452{
12453  inst.instruction |= inst.operands[0].imm;
12454}
12455
12456static void
12457do_t_div (void)
12458{
12459  unsigned Rd, Rn, Rm;
12460
12461  Rd = inst.operands[0].reg;
12462  Rn = (inst.operands[1].present
12463	? inst.operands[1].reg : Rd);
12464  Rm = inst.operands[2].reg;
12465
12466  reject_bad_reg (Rd);
12467  reject_bad_reg (Rn);
12468  reject_bad_reg (Rm);
12469
12470  inst.instruction |= Rd << 8;
12471  inst.instruction |= Rn << 16;
12472  inst.instruction |= Rm;
12473}
12474
12475static void
12476do_t_hint (void)
12477{
12478  if (unified_syntax && inst.size_req == 4)
12479    inst.instruction = THUMB_OP32 (inst.instruction);
12480  else
12481    inst.instruction = THUMB_OP16 (inst.instruction);
12482}
12483
12484static void
12485do_t_it (void)
12486{
12487  unsigned int cond = inst.operands[0].imm;
12488
12489  set_pred_insn_type (IT_INSN);
12490  now_pred.mask = (inst.instruction & 0xf) | 0x10;
12491  now_pred.cc = cond;
12492  now_pred.warn_deprecated = false;
12493  now_pred.type = SCALAR_PRED;
12494
12495  /* If the condition is a negative condition, invert the mask.  */
12496  if ((cond & 0x1) == 0x0)
12497    {
12498      unsigned int mask = inst.instruction & 0x000f;
12499
12500      if ((mask & 0x7) == 0)
12501	{
12502	  /* No conversion needed.  */
12503	  now_pred.block_length = 1;
12504	}
12505      else if ((mask & 0x3) == 0)
12506	{
12507	  mask ^= 0x8;
12508	  now_pred.block_length = 2;
12509	}
12510      else if ((mask & 0x1) == 0)
12511	{
12512	  mask ^= 0xC;
12513	  now_pred.block_length = 3;
12514	}
12515      else
12516	{
12517	  mask ^= 0xE;
12518	  now_pred.block_length = 4;
12519	}
12520
12521      inst.instruction &= 0xfff0;
12522      inst.instruction |= mask;
12523    }
12524
12525  inst.instruction |= cond << 4;
12526}
12527
12528/* Helper function used for both push/pop and ldm/stm.  */
12529static void
12530encode_thumb2_multi (bool do_io, int base, unsigned mask,
12531		     bool writeback)
12532{
12533  bool load, store;
12534
12535  gas_assert (base != -1 || !do_io);
12536  load = do_io && ((inst.instruction & (1 << 20)) != 0);
12537  store = do_io && !load;
12538
12539  if (mask & (1 << 13))
12540    inst.error =  _("SP not allowed in register list");
12541
12542  if (do_io && (mask & (1 << base)) != 0
12543      && writeback)
12544    inst.error = _("having the base register in the register list when "
12545		   "using write back is UNPREDICTABLE");
12546
12547  if (load)
12548    {
12549      if (mask & (1 << 15))
12550	{
12551	  if (mask & (1 << 14))
12552	    inst.error = _("LR and PC should not both be in register list");
12553	  else
12554	    set_pred_insn_type_last ();
12555	}
12556    }
12557  else if (store)
12558    {
12559      if (mask & (1 << 15))
12560	inst.error = _("PC not allowed in register list");
12561    }
12562
12563  if (do_io && ((mask & (mask - 1)) == 0))
12564    {
12565      /* Single register transfers implemented as str/ldr.  */
12566      if (writeback)
12567	{
12568	  if (inst.instruction & (1 << 23))
12569	    inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12570	  else
12571	    inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12572	}
12573      else
12574	{
12575	  if (inst.instruction & (1 << 23))
12576	    inst.instruction = 0x00800000; /* ia -> [base] */
12577	  else
12578	    inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12579	}
12580
12581      inst.instruction |= 0xf8400000;
12582      if (load)
12583	inst.instruction |= 0x00100000;
12584
12585      mask = ffs (mask) - 1;
12586      mask <<= 12;
12587    }
12588  else if (writeback)
12589    inst.instruction |= WRITE_BACK;
12590
12591  inst.instruction |= mask;
12592  if (do_io)
12593    inst.instruction |= base << 16;
12594}
12595
12596static void
12597do_t_ldmstm (void)
12598{
12599  /* This really doesn't seem worth it.  */
12600  constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
12601	      _("expression too complex"));
12602  constraint (inst.operands[1].writeback,
12603	      _("Thumb load/store multiple does not support {reglist}^"));
12604
12605  if (unified_syntax)
12606    {
12607      bool narrow;
12608      unsigned mask;
12609
12610      narrow = false;
12611      /* See if we can use a 16-bit instruction.  */
12612      if (inst.instruction < 0xffff /* not ldmdb/stmdb */
12613	  && inst.size_req != 4
12614	  && !(inst.operands[1].imm & ~0xff))
12615	{
12616	  mask = 1 << inst.operands[0].reg;
12617
12618	  if (inst.operands[0].reg <= 7)
12619	    {
12620	      if (inst.instruction == T_MNEM_stmia
12621		  ? inst.operands[0].writeback
12622		  : (inst.operands[0].writeback
12623		     == !(inst.operands[1].imm & mask)))
12624		{
12625		  if (inst.instruction == T_MNEM_stmia
12626		      && (inst.operands[1].imm & mask)
12627		      && (inst.operands[1].imm & (mask - 1)))
12628		    as_warn (_("value stored for r%d is UNKNOWN"),
12629			     inst.operands[0].reg);
12630
12631		  inst.instruction = THUMB_OP16 (inst.instruction);
12632		  inst.instruction |= inst.operands[0].reg << 8;
12633		  inst.instruction |= inst.operands[1].imm;
12634		  narrow = true;
12635		}
12636	      else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12637		{
12638		  /* This means 1 register in reg list one of 3 situations:
12639		     1. Instruction is stmia, but without writeback.
12640		     2. lmdia without writeback, but with Rn not in
12641			reglist.
12642		     3. ldmia with writeback, but with Rn in reglist.
12643		     Case 3 is UNPREDICTABLE behaviour, so we handle
12644		     case 1 and 2 which can be converted into a 16-bit
12645		     str or ldr. The SP cases are handled below.  */
12646		  unsigned long opcode;
12647		  /* First, record an error for Case 3.  */
12648		  if (inst.operands[1].imm & mask
12649		      && inst.operands[0].writeback)
12650		    inst.error =
12651			_("having the base register in the register list when "
12652			  "using write back is UNPREDICTABLE");
12653
12654		  opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
12655							     : T_MNEM_ldr);
12656		  inst.instruction = THUMB_OP16 (opcode);
12657		  inst.instruction |= inst.operands[0].reg << 3;
12658		  inst.instruction |= (ffs (inst.operands[1].imm)-1);
12659		  narrow = true;
12660		}
12661	    }
12662	  else if (inst.operands[0] .reg == REG_SP)
12663	    {
12664	      if (inst.operands[0].writeback)
12665		{
12666		  inst.instruction =
12667			THUMB_OP16 (inst.instruction == T_MNEM_stmia
12668				    ? T_MNEM_push : T_MNEM_pop);
12669		  inst.instruction |= inst.operands[1].imm;
12670		  narrow = true;
12671		}
12672	      else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12673		{
12674		  inst.instruction =
12675			THUMB_OP16 (inst.instruction == T_MNEM_stmia
12676				    ? T_MNEM_str_sp : T_MNEM_ldr_sp);
12677		  inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
12678		  narrow = true;
12679		}
12680	    }
12681	}
12682
12683      if (!narrow)
12684	{
12685	  if (inst.instruction < 0xffff)
12686	    inst.instruction = THUMB_OP32 (inst.instruction);
12687
12688	  encode_thumb2_multi (true /* do_io */, inst.operands[0].reg,
12689			       inst.operands[1].imm,
12690			       inst.operands[0].writeback);
12691	}
12692    }
12693  else
12694    {
12695      constraint (inst.operands[0].reg > 7
12696		  || (inst.operands[1].imm & ~0xff), BAD_HIREG);
12697      constraint (inst.instruction != T_MNEM_ldmia
12698		  && inst.instruction != T_MNEM_stmia,
12699		  _("Thumb-2 instruction only valid in unified syntax"));
12700      if (inst.instruction == T_MNEM_stmia)
12701	{
12702	  if (!inst.operands[0].writeback)
12703	    as_warn (_("this instruction will write back the base register"));
12704	  if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12705	      && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
12706	    as_warn (_("value stored for r%d is UNKNOWN"),
12707		     inst.operands[0].reg);
12708	}
12709      else
12710	{
12711	  if (!inst.operands[0].writeback
12712	      && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12713	    as_warn (_("this instruction will write back the base register"));
12714	  else if (inst.operands[0].writeback
12715		   && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12716	    as_warn (_("this instruction will not write back the base register"));
12717	}
12718
12719      inst.instruction = THUMB_OP16 (inst.instruction);
12720      inst.instruction |= inst.operands[0].reg << 8;
12721      inst.instruction |= inst.operands[1].imm;
12722    }
12723}
12724
12725static void
12726do_t_ldrex (void)
12727{
12728  constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12729	      || inst.operands[1].postind || inst.operands[1].writeback
12730	      || inst.operands[1].immisreg || inst.operands[1].shifted
12731	      || inst.operands[1].negative,
12732	      BAD_ADDR_MODE);
12733
12734  constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12735
12736  inst.instruction |= inst.operands[0].reg << 12;
12737  inst.instruction |= inst.operands[1].reg << 16;
12738  inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
12739}
12740
12741static void
12742do_t_ldrexd (void)
12743{
12744  if (!inst.operands[1].present)
12745    {
12746      constraint (inst.operands[0].reg == REG_LR,
12747		  _("r14 not allowed as first register "
12748		    "when second register is omitted"));
12749      inst.operands[1].reg = inst.operands[0].reg + 1;
12750    }
12751  constraint (inst.operands[0].reg == inst.operands[1].reg,
12752	      BAD_OVERLAP);
12753
12754  inst.instruction |= inst.operands[0].reg << 12;
12755  inst.instruction |= inst.operands[1].reg << 8;
12756  inst.instruction |= inst.operands[2].reg << 16;
12757}
12758
12759static void
12760do_t_ldst (void)
12761{
12762  unsigned long opcode;
12763  int Rn;
12764
12765  if (inst.operands[0].isreg
12766      && !inst.operands[0].preind
12767      && inst.operands[0].reg == REG_PC)
12768    set_pred_insn_type_last ();
12769
12770  opcode = inst.instruction;
12771  if (unified_syntax)
12772    {
12773      if (!inst.operands[1].isreg)
12774	{
12775	  if (opcode <= 0xffff)
12776	    inst.instruction = THUMB_OP32 (opcode);
12777	  if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/false))
12778	    return;
12779	}
12780      if (inst.operands[1].isreg
12781	  && !inst.operands[1].writeback
12782	  && !inst.operands[1].shifted && !inst.operands[1].postind
12783	  && !inst.operands[1].negative && inst.operands[0].reg <= 7
12784	  && opcode <= 0xffff
12785	  && inst.size_req != 4)
12786	{
12787	  /* Insn may have a 16-bit form.  */
12788	  Rn = inst.operands[1].reg;
12789	  if (inst.operands[1].immisreg)
12790	    {
12791	      inst.instruction = THUMB_OP16 (opcode);
12792	      /* [Rn, Rik] */
12793	      if (Rn <= 7 && inst.operands[1].imm <= 7)
12794		goto op16;
12795	      else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
12796		reject_bad_reg (inst.operands[1].imm);
12797	    }
12798	  else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12799		    && opcode != T_MNEM_ldrsb)
12800		   || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12801		   || (Rn == REG_SP && opcode == T_MNEM_str))
12802	    {
12803	      /* [Rn, #const] */
12804	      if (Rn > 7)
12805		{
12806		  if (Rn == REG_PC)
12807		    {
12808		      if (inst.relocs[0].pc_rel)
12809			opcode = T_MNEM_ldr_pc2;
12810		      else
12811			opcode = T_MNEM_ldr_pc;
12812		    }
12813		  else
12814		    {
12815		      if (opcode == T_MNEM_ldr)
12816			opcode = T_MNEM_ldr_sp;
12817		      else
12818			opcode = T_MNEM_str_sp;
12819		    }
12820		  inst.instruction = inst.operands[0].reg << 8;
12821		}
12822	      else
12823		{
12824		  inst.instruction = inst.operands[0].reg;
12825		  inst.instruction |= inst.operands[1].reg << 3;
12826		}
12827	      inst.instruction |= THUMB_OP16 (opcode);
12828	      if (inst.size_req == 2)
12829		inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12830	      else
12831		inst.relax = opcode;
12832	      return;
12833	    }
12834	}
12835      /* Definitely a 32-bit variant.  */
12836
12837      /* Warning for Erratum 752419.  */
12838      if (opcode == T_MNEM_ldr
12839	  && inst.operands[0].reg == REG_SP
12840	  && inst.operands[1].writeback == 1
12841	  && !inst.operands[1].immisreg)
12842	{
12843	  if (no_cpu_selected ()
12844	      || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
12845		  && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
12846		  && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
12847	    as_warn (_("This instruction may be unpredictable "
12848		       "if executed on M-profile cores "
12849		       "with interrupts enabled."));
12850	}
12851
12852      /* Do some validations regarding addressing modes.  */
12853      if (inst.operands[1].immisreg)
12854	reject_bad_reg (inst.operands[1].imm);
12855
12856      constraint (inst.operands[1].writeback == 1
12857		  && inst.operands[0].reg == inst.operands[1].reg,
12858		  BAD_OVERLAP);
12859
12860      inst.instruction = THUMB_OP32 (opcode);
12861      inst.instruction |= inst.operands[0].reg << 12;
12862      encode_thumb32_addr_mode (1, /*is_t=*/false, /*is_d=*/false);
12863      check_ldr_r15_aligned ();
12864      return;
12865    }
12866
12867  constraint (inst.operands[0].reg > 7, BAD_HIREG);
12868
12869  if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
12870    {
12871      /* Only [Rn,Rm] is acceptable.  */
12872      constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12873      constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12874		  || inst.operands[1].postind || inst.operands[1].shifted
12875		  || inst.operands[1].negative,
12876		  _("Thumb does not support this addressing mode"));
12877      inst.instruction = THUMB_OP16 (inst.instruction);
12878      goto op16;
12879    }
12880
12881  inst.instruction = THUMB_OP16 (inst.instruction);
12882  if (!inst.operands[1].isreg)
12883    if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/false))
12884      return;
12885
12886  constraint (!inst.operands[1].preind
12887	      || inst.operands[1].shifted
12888	      || inst.operands[1].writeback,
12889	      _("Thumb does not support this addressing mode"));
12890  if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
12891    {
12892      constraint (inst.instruction & 0x0600,
12893		  _("byte or halfword not valid for base register"));
12894      constraint (inst.operands[1].reg == REG_PC
12895		  && !(inst.instruction & THUMB_LOAD_BIT),
12896		  _("r15 based store not allowed"));
12897      constraint (inst.operands[1].immisreg,
12898		  _("invalid base register for register offset"));
12899
12900      if (inst.operands[1].reg == REG_PC)
12901	inst.instruction = T_OPCODE_LDR_PC;
12902      else if (inst.instruction & THUMB_LOAD_BIT)
12903	inst.instruction = T_OPCODE_LDR_SP;
12904      else
12905	inst.instruction = T_OPCODE_STR_SP;
12906
12907      inst.instruction |= inst.operands[0].reg << 8;
12908      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12909      return;
12910    }
12911
12912  constraint (inst.operands[1].reg > 7, BAD_HIREG);
12913  if (!inst.operands[1].immisreg)
12914    {
12915      /* Immediate offset.  */
12916      inst.instruction |= inst.operands[0].reg;
12917      inst.instruction |= inst.operands[1].reg << 3;
12918      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
12919      return;
12920    }
12921
12922  /* Register offset.  */
12923  constraint (inst.operands[1].imm > 7, BAD_HIREG);
12924  constraint (inst.operands[1].negative,
12925	      _("Thumb does not support this addressing mode"));
12926
12927 op16:
12928  switch (inst.instruction)
12929    {
12930    case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12931    case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12932    case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12933    case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12934    case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12935    case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12936    case 0x5600 /* ldrsb */:
12937    case 0x5e00 /* ldrsh */: break;
12938    default: abort ();
12939    }
12940
12941  inst.instruction |= inst.operands[0].reg;
12942  inst.instruction |= inst.operands[1].reg << 3;
12943  inst.instruction |= inst.operands[1].imm << 6;
12944}
12945
12946static void
12947do_t_ldstd (void)
12948{
12949  if (!inst.operands[1].present)
12950    {
12951      inst.operands[1].reg = inst.operands[0].reg + 1;
12952      constraint (inst.operands[0].reg == REG_LR,
12953		  _("r14 not allowed here"));
12954      constraint (inst.operands[0].reg == REG_R12,
12955		  _("r12 not allowed here"));
12956    }
12957
12958  if (inst.operands[2].writeback
12959      && (inst.operands[0].reg == inst.operands[2].reg
12960      || inst.operands[1].reg == inst.operands[2].reg))
12961    as_warn (_("base register written back, and overlaps "
12962	       "one of transfer registers"));
12963
12964  inst.instruction |= inst.operands[0].reg << 12;
12965  inst.instruction |= inst.operands[1].reg << 8;
12966  encode_thumb32_addr_mode (2, /*is_t=*/false, /*is_d=*/true);
12967}
12968
12969static void
12970do_t_ldstt (void)
12971{
12972  inst.instruction |= inst.operands[0].reg << 12;
12973  encode_thumb32_addr_mode (1, /*is_t=*/true, /*is_d=*/false);
12974}
12975
12976static void
12977do_t_mla (void)
12978{
12979  unsigned Rd, Rn, Rm, Ra;
12980
12981  Rd = inst.operands[0].reg;
12982  Rn = inst.operands[1].reg;
12983  Rm = inst.operands[2].reg;
12984  Ra = inst.operands[3].reg;
12985
12986  reject_bad_reg (Rd);
12987  reject_bad_reg (Rn);
12988  reject_bad_reg (Rm);
12989  reject_bad_reg (Ra);
12990
12991  inst.instruction |= Rd << 8;
12992  inst.instruction |= Rn << 16;
12993  inst.instruction |= Rm;
12994  inst.instruction |= Ra << 12;
12995}
12996
12997static void
12998do_t_mlal (void)
12999{
13000  unsigned RdLo, RdHi, Rn, Rm;
13001
13002  RdLo = inst.operands[0].reg;
13003  RdHi = inst.operands[1].reg;
13004  Rn = inst.operands[2].reg;
13005  Rm = inst.operands[3].reg;
13006
13007  reject_bad_reg (RdLo);
13008  reject_bad_reg (RdHi);
13009  reject_bad_reg (Rn);
13010  reject_bad_reg (Rm);
13011
13012  inst.instruction |= RdLo << 12;
13013  inst.instruction |= RdHi << 8;
13014  inst.instruction |= Rn << 16;
13015  inst.instruction |= Rm;
13016}
13017
13018static void
13019do_t_mov_cmp (void)
13020{
13021  unsigned Rn, Rm;
13022
13023  Rn = inst.operands[0].reg;
13024  Rm = inst.operands[1].reg;
13025
13026  if (Rn == REG_PC)
13027    set_pred_insn_type_last ();
13028
13029  if (unified_syntax)
13030    {
13031      int r0off = (inst.instruction == T_MNEM_mov
13032		   || inst.instruction == T_MNEM_movs) ? 8 : 16;
13033      unsigned long opcode;
13034      bool narrow;
13035      bool low_regs;
13036
13037      low_regs = (Rn <= 7 && Rm <= 7);
13038      opcode = inst.instruction;
13039      if (in_pred_block ())
13040	narrow = opcode != T_MNEM_movs;
13041      else
13042	narrow = opcode != T_MNEM_movs || low_regs;
13043      if (inst.size_req == 4
13044	  || inst.operands[1].shifted)
13045	narrow = false;
13046
13047      /* MOVS PC, LR is encoded as SUBS PC, LR, #0.  */
13048      if (opcode == T_MNEM_movs && inst.operands[1].isreg
13049	  && !inst.operands[1].shifted
13050	  && Rn == REG_PC
13051	  && Rm == REG_LR)
13052	{
13053	  inst.instruction = T2_SUBS_PC_LR;
13054	  return;
13055	}
13056
13057      if (opcode == T_MNEM_cmp)
13058	{
13059	  constraint (Rn == REG_PC, BAD_PC);
13060	  if (narrow)
13061	    {
13062	      /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13063		 but valid.  */
13064	      warn_deprecated_sp (Rm);
13065	      /* R15 was documented as a valid choice for Rm in ARMv6,
13066		 but as UNPREDICTABLE in ARMv7.  ARM's proprietary
13067		 tools reject R15, so we do too.  */
13068	      constraint (Rm == REG_PC, BAD_PC);
13069	    }
13070	  else
13071	    reject_bad_reg (Rm);
13072	}
13073      else if (opcode == T_MNEM_mov
13074	       || opcode == T_MNEM_movs)
13075	{
13076	  if (inst.operands[1].isreg)
13077	    {
13078	      if (opcode == T_MNEM_movs)
13079		{
13080		  reject_bad_reg (Rn);
13081		  reject_bad_reg (Rm);
13082		}
13083	      else if (narrow)
13084		{
13085		  /* This is mov.n.  */
13086		  if ((Rn == REG_SP || Rn == REG_PC)
13087		      && (Rm == REG_SP || Rm == REG_PC))
13088		    {
13089		      as_tsktsk (_("Use of r%u as a source register is "
13090				 "deprecated when r%u is the destination "
13091				 "register."), Rm, Rn);
13092		    }
13093		}
13094	      else
13095		{
13096		  /* This is mov.w.  */
13097		  constraint (Rn == REG_PC, BAD_PC);
13098		  constraint (Rm == REG_PC, BAD_PC);
13099		  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13100		    constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
13101		}
13102	    }
13103	  else
13104	    reject_bad_reg (Rn);
13105	}
13106
13107      if (!inst.operands[1].isreg)
13108	{
13109	  /* Immediate operand.  */
13110	  if (!in_pred_block () && opcode == T_MNEM_mov)
13111	    narrow = 0;
13112	  if (low_regs && narrow)
13113	    {
13114	      inst.instruction = THUMB_OP16 (opcode);
13115	      inst.instruction |= Rn << 8;
13116	      if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13117		  || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
13118		{
13119		  if (inst.size_req == 2)
13120		    inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
13121		  else
13122		    inst.relax = opcode;
13123		}
13124	    }
13125	  else
13126	    {
13127	      constraint ((inst.relocs[0].type
13128			   >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
13129			  && (inst.relocs[0].type
13130			      <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
13131			  THUMB1_RELOC_ONLY);
13132
13133	      inst.instruction = THUMB_OP32 (inst.instruction);
13134	      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13135	      inst.instruction |= Rn << r0off;
13136	      inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13137	    }
13138	}
13139      else if (inst.operands[1].shifted && inst.operands[1].immisreg
13140	       && (inst.instruction == T_MNEM_mov
13141		   || inst.instruction == T_MNEM_movs))
13142	{
13143	  /* Register shifts are encoded as separate shift instructions.  */
13144	  bool flags = (inst.instruction == T_MNEM_movs);
13145
13146	  if (in_pred_block ())
13147	    narrow = !flags;
13148	  else
13149	    narrow = flags;
13150
13151	  if (inst.size_req == 4)
13152	    narrow = false;
13153
13154	  if (!low_regs || inst.operands[1].imm > 7)
13155	    narrow = false;
13156
13157	  if (Rn != Rm)
13158	    narrow = false;
13159
13160	  switch (inst.operands[1].shift_kind)
13161	    {
13162	    case SHIFT_LSL:
13163	      opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
13164	      break;
13165	    case SHIFT_ASR:
13166	      opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
13167	      break;
13168	    case SHIFT_LSR:
13169	      opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
13170	      break;
13171	    case SHIFT_ROR:
13172	      opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
13173	      break;
13174	    default:
13175	      abort ();
13176	    }
13177
13178	  inst.instruction = opcode;
13179	  if (narrow)
13180	    {
13181	      inst.instruction |= Rn;
13182	      inst.instruction |= inst.operands[1].imm << 3;
13183	    }
13184	  else
13185	    {
13186	      if (flags)
13187		inst.instruction |= CONDS_BIT;
13188
13189	      inst.instruction |= Rn << 8;
13190	      inst.instruction |= Rm << 16;
13191	      inst.instruction |= inst.operands[1].imm;
13192	    }
13193	}
13194      else if (!narrow)
13195	{
13196	  /* Some mov with immediate shift have narrow variants.
13197	     Register shifts are handled above.  */
13198	  if (low_regs && inst.operands[1].shifted
13199	      && (inst.instruction == T_MNEM_mov
13200		  || inst.instruction == T_MNEM_movs))
13201	    {
13202	      if (in_pred_block ())
13203		narrow = (inst.instruction == T_MNEM_mov);
13204	      else
13205		narrow = (inst.instruction == T_MNEM_movs);
13206	    }
13207
13208	  if (narrow)
13209	    {
13210	      switch (inst.operands[1].shift_kind)
13211		{
13212		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13213		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13214		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13215		default: narrow = false; break;
13216		}
13217	    }
13218
13219	  if (narrow)
13220	    {
13221	      inst.instruction |= Rn;
13222	      inst.instruction |= Rm << 3;
13223	      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
13224	    }
13225	  else
13226	    {
13227	      inst.instruction = THUMB_OP32 (inst.instruction);
13228	      inst.instruction |= Rn << r0off;
13229	      encode_thumb32_shifted_operand (1);
13230	    }
13231	}
13232      else
13233	switch (inst.instruction)
13234	  {
13235	  case T_MNEM_mov:
13236	    /* In v4t or v5t a move of two lowregs produces unpredictable
13237	       results. Don't allow this.  */
13238	    if (low_regs)
13239	      {
13240		constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
13241			    "MOV Rd, Rs with two low registers is not "
13242			    "permitted on this architecture");
13243		ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
13244					arm_ext_v6);
13245	      }
13246
13247	    inst.instruction = T_OPCODE_MOV_HR;
13248	    inst.instruction |= (Rn & 0x8) << 4;
13249	    inst.instruction |= (Rn & 0x7);
13250	    inst.instruction |= Rm << 3;
13251	    break;
13252
13253	  case T_MNEM_movs:
13254	    /* We know we have low registers at this point.
13255	       Generate LSLS Rd, Rs, #0.  */
13256	    inst.instruction = T_OPCODE_LSL_I;
13257	    inst.instruction |= Rn;
13258	    inst.instruction |= Rm << 3;
13259	    break;
13260
13261	  case T_MNEM_cmp:
13262	    if (low_regs)
13263	      {
13264		inst.instruction = T_OPCODE_CMP_LR;
13265		inst.instruction |= Rn;
13266		inst.instruction |= Rm << 3;
13267	      }
13268	    else
13269	      {
13270		inst.instruction = T_OPCODE_CMP_HR;
13271		inst.instruction |= (Rn & 0x8) << 4;
13272		inst.instruction |= (Rn & 0x7);
13273		inst.instruction |= Rm << 3;
13274	      }
13275	    break;
13276	  }
13277      return;
13278    }
13279
13280  inst.instruction = THUMB_OP16 (inst.instruction);
13281
13282  /* PR 10443: Do not silently ignore shifted operands.  */
13283  constraint (inst.operands[1].shifted,
13284	      _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13285
13286  if (inst.operands[1].isreg)
13287    {
13288      if (Rn < 8 && Rm < 8)
13289	{
13290	  /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13291	     since a MOV instruction produces unpredictable results.  */
13292	  if (inst.instruction == T_OPCODE_MOV_I8)
13293	    inst.instruction = T_OPCODE_ADD_I3;
13294	  else
13295	    inst.instruction = T_OPCODE_CMP_LR;
13296
13297	  inst.instruction |= Rn;
13298	  inst.instruction |= Rm << 3;
13299	}
13300      else
13301	{
13302	  if (inst.instruction == T_OPCODE_MOV_I8)
13303	    inst.instruction = T_OPCODE_MOV_HR;
13304	  else
13305	    inst.instruction = T_OPCODE_CMP_HR;
13306	  do_t_cpy ();
13307	}
13308    }
13309  else
13310    {
13311      constraint (Rn > 7,
13312		  _("only lo regs allowed with immediate"));
13313      inst.instruction |= Rn << 8;
13314      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
13315    }
13316}
13317
13318static void
13319do_t_mov16 (void)
13320{
13321  unsigned Rd;
13322  bfd_vma imm;
13323  bool top;
13324
13325  top = (inst.instruction & 0x00800000) != 0;
13326  if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
13327    {
13328      constraint (top, _(":lower16: not allowed in this instruction"));
13329      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
13330    }
13331  else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
13332    {
13333      constraint (!top, _(":upper16: not allowed in this instruction"));
13334      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
13335    }
13336
13337  Rd = inst.operands[0].reg;
13338  reject_bad_reg (Rd);
13339
13340  inst.instruction |= Rd << 8;
13341  if (inst.relocs[0].type == BFD_RELOC_UNUSED)
13342    {
13343      imm = inst.relocs[0].exp.X_add_number;
13344      inst.instruction |= (imm & 0xf000) << 4;
13345      inst.instruction |= (imm & 0x0800) << 15;
13346      inst.instruction |= (imm & 0x0700) << 4;
13347      inst.instruction |= (imm & 0x00ff);
13348    }
13349}
13350
13351static void
13352do_t_mvn_tst (void)
13353{
13354  unsigned Rn, Rm;
13355
13356  Rn = inst.operands[0].reg;
13357  Rm = inst.operands[1].reg;
13358
13359  if (inst.instruction == T_MNEM_cmp
13360      || inst.instruction == T_MNEM_cmn)
13361    constraint (Rn == REG_PC, BAD_PC);
13362  else
13363    reject_bad_reg (Rn);
13364  reject_bad_reg (Rm);
13365
13366  if (unified_syntax)
13367    {
13368      int r0off = (inst.instruction == T_MNEM_mvn
13369		   || inst.instruction == T_MNEM_mvns) ? 8 : 16;
13370      bool narrow;
13371
13372      if (inst.size_req == 4
13373	  || inst.instruction > 0xffff
13374	  || inst.operands[1].shifted
13375	  || Rn > 7 || Rm > 7)
13376	narrow = false;
13377      else if (inst.instruction == T_MNEM_cmn
13378	       || inst.instruction == T_MNEM_tst)
13379	narrow = true;
13380      else if (THUMB_SETS_FLAGS (inst.instruction))
13381	narrow = !in_pred_block ();
13382      else
13383	narrow = in_pred_block ();
13384
13385      if (!inst.operands[1].isreg)
13386	{
13387	  /* For an immediate, we always generate a 32-bit opcode;
13388	     section relaxation will shrink it later if possible.  */
13389	  if (inst.instruction < 0xffff)
13390	    inst.instruction = THUMB_OP32 (inst.instruction);
13391	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13392	  inst.instruction |= Rn << r0off;
13393	  inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13394	}
13395      else
13396	{
13397	  /* See if we can do this with a 16-bit instruction.  */
13398	  if (narrow)
13399	    {
13400	      inst.instruction = THUMB_OP16 (inst.instruction);
13401	      inst.instruction |= Rn;
13402	      inst.instruction |= Rm << 3;
13403	    }
13404	  else
13405	    {
13406	      constraint (inst.operands[1].shifted
13407			  && inst.operands[1].immisreg,
13408			  _("shift must be constant"));
13409	      if (inst.instruction < 0xffff)
13410		inst.instruction = THUMB_OP32 (inst.instruction);
13411	      inst.instruction |= Rn << r0off;
13412	      encode_thumb32_shifted_operand (1);
13413	    }
13414	}
13415    }
13416  else
13417    {
13418      constraint (inst.instruction > 0xffff
13419		  || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
13420      constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
13421		  _("unshifted register required"));
13422      constraint (Rn > 7 || Rm > 7,
13423		  BAD_HIREG);
13424
13425      inst.instruction = THUMB_OP16 (inst.instruction);
13426      inst.instruction |= Rn;
13427      inst.instruction |= Rm << 3;
13428    }
13429}
13430
13431static void
13432do_t_mrs (void)
13433{
13434  unsigned Rd;
13435
13436  if (do_vfp_nsyn_mrs () == SUCCESS)
13437    return;
13438
13439  Rd = inst.operands[0].reg;
13440  reject_bad_reg (Rd);
13441  inst.instruction |= Rd << 8;
13442
13443  if (inst.operands[1].isreg)
13444    {
13445      unsigned br = inst.operands[1].reg;
13446      if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
13447	as_bad (_("bad register for mrs"));
13448
13449      inst.instruction |= br & (0xf << 16);
13450      inst.instruction |= (br & 0x300) >> 4;
13451      inst.instruction |= (br & SPSR_BIT) >> 2;
13452    }
13453  else
13454    {
13455      int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13456
13457      if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
13458	{
13459	  /* PR gas/12698:  The constraint is only applied for m_profile.
13460	     If the user has specified -march=all, we want to ignore it as
13461	     we are building for any CPU type, including non-m variants.  */
13462	  bool m_profile =
13463	    !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
13464	  constraint ((flags != 0) && m_profile, _("selected processor does "
13465						   "not support requested special purpose register"));
13466	}
13467      else
13468	/* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13469	   devices).  */
13470	constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
13471		    _("'APSR', 'CPSR' or 'SPSR' expected"));
13472
13473      inst.instruction |= (flags & SPSR_BIT) >> 2;
13474      inst.instruction |= inst.operands[1].imm & 0xff;
13475      inst.instruction |= 0xf0000;
13476    }
13477}
13478
13479static void
13480do_t_msr (void)
13481{
13482  int flags;
13483  unsigned Rn;
13484
13485  if (do_vfp_nsyn_msr () == SUCCESS)
13486    return;
13487
13488  constraint (!inst.operands[1].isreg,
13489	      _("Thumb encoding does not support an immediate here"));
13490
13491  if (inst.operands[0].isreg)
13492    flags = (int)(inst.operands[0].reg);
13493  else
13494    flags = inst.operands[0].imm;
13495
13496  if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
13497    {
13498      int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13499
13500      /* PR gas/12698:  The constraint is only applied for m_profile.
13501	 If the user has specified -march=all, we want to ignore it as
13502	 we are building for any CPU type, including non-m variants.  */
13503      bool m_profile =
13504	!ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
13505      constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13506	   && (bits & ~(PSR_s | PSR_f)) != 0)
13507	  || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13508	      && bits != PSR_f)) && m_profile,
13509	  _("selected processor does not support requested special "
13510	    "purpose register"));
13511    }
13512  else
13513     constraint ((flags & 0xff) != 0, _("selected processor does not support "
13514		 "requested special purpose register"));
13515
13516  Rn = inst.operands[1].reg;
13517  reject_bad_reg (Rn);
13518
13519  inst.instruction |= (flags & SPSR_BIT) >> 2;
13520  inst.instruction |= (flags & 0xf0000) >> 8;
13521  inst.instruction |= (flags & 0x300) >> 4;
13522  inst.instruction |= (flags & 0xff);
13523  inst.instruction |= Rn << 16;
13524}
13525
13526static void
13527do_t_mul (void)
13528{
13529  bool narrow;
13530  unsigned Rd, Rn, Rm;
13531
13532  if (!inst.operands[2].present)
13533    inst.operands[2].reg = inst.operands[0].reg;
13534
13535  Rd = inst.operands[0].reg;
13536  Rn = inst.operands[1].reg;
13537  Rm = inst.operands[2].reg;
13538
13539  if (unified_syntax)
13540    {
13541      if (inst.size_req == 4
13542	  || (Rd != Rn
13543	      && Rd != Rm)
13544	  || Rn > 7
13545	  || Rm > 7)
13546	narrow = false;
13547      else if (inst.instruction == T_MNEM_muls)
13548	narrow = !in_pred_block ();
13549      else
13550	narrow = in_pred_block ();
13551    }
13552  else
13553    {
13554      constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
13555      constraint (Rn > 7 || Rm > 7,
13556		  BAD_HIREG);
13557      narrow = true;
13558    }
13559
13560  if (narrow)
13561    {
13562      /* 16-bit MULS/Conditional MUL.  */
13563      inst.instruction = THUMB_OP16 (inst.instruction);
13564      inst.instruction |= Rd;
13565
13566      if (Rd == Rn)
13567	inst.instruction |= Rm << 3;
13568      else if (Rd == Rm)
13569	inst.instruction |= Rn << 3;
13570      else
13571	constraint (1, _("dest must overlap one source register"));
13572    }
13573  else
13574    {
13575      constraint (inst.instruction != T_MNEM_mul,
13576		  _("Thumb-2 MUL must not set flags"));
13577      /* 32-bit MUL.  */
13578      inst.instruction = THUMB_OP32 (inst.instruction);
13579      inst.instruction |= Rd << 8;
13580      inst.instruction |= Rn << 16;
13581      inst.instruction |= Rm << 0;
13582
13583      reject_bad_reg (Rd);
13584      reject_bad_reg (Rn);
13585      reject_bad_reg (Rm);
13586    }
13587}
13588
13589static void
13590do_t_mull (void)
13591{
13592  unsigned RdLo, RdHi, Rn, Rm;
13593
13594  RdLo = inst.operands[0].reg;
13595  RdHi = inst.operands[1].reg;
13596  Rn = inst.operands[2].reg;
13597  Rm = inst.operands[3].reg;
13598
13599  reject_bad_reg (RdLo);
13600  reject_bad_reg (RdHi);
13601  reject_bad_reg (Rn);
13602  reject_bad_reg (Rm);
13603
13604  inst.instruction |= RdLo << 12;
13605  inst.instruction |= RdHi << 8;
13606  inst.instruction |= Rn << 16;
13607  inst.instruction |= Rm;
13608
13609 if (RdLo == RdHi)
13610    as_tsktsk (_("rdhi and rdlo must be different"));
13611}
13612
13613static void
13614do_t_nop (void)
13615{
13616  set_pred_insn_type (NEUTRAL_IT_INSN);
13617
13618  if (unified_syntax)
13619    {
13620      if (inst.size_req == 4 || inst.operands[0].imm > 15)
13621	{
13622	  inst.instruction = THUMB_OP32 (inst.instruction);
13623	  inst.instruction |= inst.operands[0].imm;
13624	}
13625      else
13626	{
13627	  /* PR9722: Check for Thumb2 availability before
13628	     generating a thumb2 nop instruction.  */
13629	  if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
13630	    {
13631	      inst.instruction = THUMB_OP16 (inst.instruction);
13632	      inst.instruction |= inst.operands[0].imm << 4;
13633	    }
13634	  else
13635	    inst.instruction = 0x46c0;
13636	}
13637    }
13638  else
13639    {
13640      constraint (inst.operands[0].present,
13641		  _("Thumb does not support NOP with hints"));
13642      inst.instruction = 0x46c0;
13643    }
13644}
13645
13646static void
13647do_t_neg (void)
13648{
13649  if (unified_syntax)
13650    {
13651      bool narrow;
13652
13653      if (THUMB_SETS_FLAGS (inst.instruction))
13654	narrow = !in_pred_block ();
13655      else
13656	narrow = in_pred_block ();
13657      if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13658	narrow = false;
13659      if (inst.size_req == 4)
13660	narrow = false;
13661
13662      if (!narrow)
13663	{
13664	  inst.instruction = THUMB_OP32 (inst.instruction);
13665	  inst.instruction |= inst.operands[0].reg << 8;
13666	  inst.instruction |= inst.operands[1].reg << 16;
13667	}
13668      else
13669	{
13670	  inst.instruction = THUMB_OP16 (inst.instruction);
13671	  inst.instruction |= inst.operands[0].reg;
13672	  inst.instruction |= inst.operands[1].reg << 3;
13673	}
13674    }
13675  else
13676    {
13677      constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13678		  BAD_HIREG);
13679      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13680
13681      inst.instruction = THUMB_OP16 (inst.instruction);
13682      inst.instruction |= inst.operands[0].reg;
13683      inst.instruction |= inst.operands[1].reg << 3;
13684    }
13685}
13686
13687static void
13688do_t_orn (void)
13689{
13690  unsigned Rd, Rn;
13691
13692  Rd = inst.operands[0].reg;
13693  Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13694
13695  reject_bad_reg (Rd);
13696  /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN.  */
13697  reject_bad_reg (Rn);
13698
13699  inst.instruction |= Rd << 8;
13700  inst.instruction |= Rn << 16;
13701
13702  if (!inst.operands[2].isreg)
13703    {
13704      inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13705      inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13706    }
13707  else
13708    {
13709      unsigned Rm;
13710
13711      Rm = inst.operands[2].reg;
13712      reject_bad_reg (Rm);
13713
13714      constraint (inst.operands[2].shifted
13715		  && inst.operands[2].immisreg,
13716		  _("shift must be constant"));
13717      encode_thumb32_shifted_operand (2);
13718    }
13719}
13720
13721static void
13722do_t_pkhbt (void)
13723{
13724  unsigned Rd, Rn, Rm;
13725
13726  Rd = inst.operands[0].reg;
13727  Rn = inst.operands[1].reg;
13728  Rm = inst.operands[2].reg;
13729
13730  reject_bad_reg (Rd);
13731  reject_bad_reg (Rn);
13732  reject_bad_reg (Rm);
13733
13734  inst.instruction |= Rd << 8;
13735  inst.instruction |= Rn << 16;
13736  inst.instruction |= Rm;
13737  if (inst.operands[3].present)
13738    {
13739      unsigned int val = inst.relocs[0].exp.X_add_number;
13740      constraint (inst.relocs[0].exp.X_op != O_constant,
13741		  _("expression too complex"));
13742      inst.instruction |= (val & 0x1c) << 10;
13743      inst.instruction |= (val & 0x03) << 6;
13744    }
13745}
13746
13747static void
13748do_t_pkhtb (void)
13749{
13750  if (!inst.operands[3].present)
13751    {
13752      unsigned Rtmp;
13753
13754      inst.instruction &= ~0x00000020;
13755
13756      /* PR 10168.  Swap the Rm and Rn registers.  */
13757      Rtmp = inst.operands[1].reg;
13758      inst.operands[1].reg = inst.operands[2].reg;
13759      inst.operands[2].reg = Rtmp;
13760    }
13761  do_t_pkhbt ();
13762}
13763
13764static void
13765do_t_pld (void)
13766{
13767  if (inst.operands[0].immisreg)
13768    reject_bad_reg (inst.operands[0].imm);
13769
13770  encode_thumb32_addr_mode (0, /*is_t=*/false, /*is_d=*/false);
13771}
13772
13773static void
13774do_t_push_pop (void)
13775{
13776  unsigned mask;
13777
13778  constraint (inst.operands[0].writeback,
13779	      _("push/pop do not support {reglist}^"));
13780  constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
13781	      _("expression too complex"));
13782
13783  mask = inst.operands[0].imm;
13784  if (inst.size_req != 4 && (mask & ~0xff) == 0)
13785    inst.instruction = THUMB_OP16 (inst.instruction) | mask;
13786  else if (inst.size_req != 4
13787	   && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
13788				       ? REG_LR : REG_PC)))
13789    {
13790      inst.instruction = THUMB_OP16 (inst.instruction);
13791      inst.instruction |= THUMB_PP_PC_LR;
13792      inst.instruction |= mask & 0xff;
13793    }
13794  else if (unified_syntax)
13795    {
13796      inst.instruction = THUMB_OP32 (inst.instruction);
13797      encode_thumb2_multi (true /* do_io */, 13, mask, true);
13798    }
13799  else
13800    {
13801      inst.error = _("invalid register list to push/pop instruction");
13802      return;
13803    }
13804}
13805
13806static void
13807do_t_clrm (void)
13808{
13809  if (unified_syntax)
13810    encode_thumb2_multi (false /* do_io */, -1, inst.operands[0].imm, false);
13811  else
13812    {
13813      inst.error = _("invalid register list to push/pop instruction");
13814      return;
13815    }
13816}
13817
13818static void
13819do_t_vscclrm (void)
13820{
13821  if (inst.operands[0].issingle)
13822    {
13823      inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13824      inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13825      inst.instruction |= inst.operands[0].imm;
13826    }
13827  else
13828    {
13829      inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13830      inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13831      inst.instruction |= 1 << 8;
13832      inst.instruction |= inst.operands[0].imm << 1;
13833    }
13834}
13835
13836static void
13837do_t_rbit (void)
13838{
13839  unsigned Rd, Rm;
13840
13841  Rd = inst.operands[0].reg;
13842  Rm = inst.operands[1].reg;
13843
13844  reject_bad_reg (Rd);
13845  reject_bad_reg (Rm);
13846
13847  inst.instruction |= Rd << 8;
13848  inst.instruction |= Rm << 16;
13849  inst.instruction |= Rm;
13850}
13851
13852static void
13853do_t_rev (void)
13854{
13855  unsigned Rd, Rm;
13856
13857  Rd = inst.operands[0].reg;
13858  Rm = inst.operands[1].reg;
13859
13860  reject_bad_reg (Rd);
13861  reject_bad_reg (Rm);
13862
13863  if (Rd <= 7 && Rm <= 7
13864      && inst.size_req != 4)
13865    {
13866      inst.instruction = THUMB_OP16 (inst.instruction);
13867      inst.instruction |= Rd;
13868      inst.instruction |= Rm << 3;
13869    }
13870  else if (unified_syntax)
13871    {
13872      inst.instruction = THUMB_OP32 (inst.instruction);
13873      inst.instruction |= Rd << 8;
13874      inst.instruction |= Rm << 16;
13875      inst.instruction |= Rm;
13876    }
13877  else
13878    inst.error = BAD_HIREG;
13879}
13880
13881static void
13882do_t_rrx (void)
13883{
13884  unsigned Rd, Rm;
13885
13886  Rd = inst.operands[0].reg;
13887  Rm = inst.operands[1].reg;
13888
13889  reject_bad_reg (Rd);
13890  reject_bad_reg (Rm);
13891
13892  inst.instruction |= Rd << 8;
13893  inst.instruction |= Rm;
13894}
13895
13896static void
13897do_t_rsb (void)
13898{
13899  unsigned Rd, Rs;
13900
13901  Rd = inst.operands[0].reg;
13902  Rs = (inst.operands[1].present
13903	? inst.operands[1].reg    /* Rd, Rs, foo */
13904	: inst.operands[0].reg);  /* Rd, foo -> Rd, Rd, foo */
13905
13906  reject_bad_reg (Rd);
13907  reject_bad_reg (Rs);
13908  if (inst.operands[2].isreg)
13909    reject_bad_reg (inst.operands[2].reg);
13910
13911  inst.instruction |= Rd << 8;
13912  inst.instruction |= Rs << 16;
13913  if (!inst.operands[2].isreg)
13914    {
13915      bool narrow;
13916
13917      if ((inst.instruction & 0x00100000) != 0)
13918	narrow = !in_pred_block ();
13919      else
13920	narrow = in_pred_block ();
13921
13922      if (Rd > 7 || Rs > 7)
13923	narrow = false;
13924
13925      if (inst.size_req == 4 || !unified_syntax)
13926	narrow = false;
13927
13928      if (inst.relocs[0].exp.X_op != O_constant
13929	  || inst.relocs[0].exp.X_add_number != 0)
13930	narrow = false;
13931
13932      /* Turn rsb #0 into 16-bit neg.  We should probably do this via
13933	 relaxation, but it doesn't seem worth the hassle.  */
13934      if (narrow)
13935	{
13936	  inst.relocs[0].type = BFD_RELOC_UNUSED;
13937	  inst.instruction = THUMB_OP16 (T_MNEM_negs);
13938	  inst.instruction |= Rs << 3;
13939	  inst.instruction |= Rd;
13940	}
13941      else
13942	{
13943	  inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
13944	  inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
13945	}
13946    }
13947  else
13948    encode_thumb32_shifted_operand (2);
13949}
13950
13951static void
13952do_t_setend (void)
13953{
13954  if (warn_on_deprecated
13955      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
13956      as_tsktsk (_("setend use is deprecated for ARMv8"));
13957
13958  set_pred_insn_type (OUTSIDE_PRED_INSN);
13959  if (inst.operands[0].imm)
13960    inst.instruction |= 0x8;
13961}
13962
13963static void
13964do_t_shift (void)
13965{
13966  if (!inst.operands[1].present)
13967    inst.operands[1].reg = inst.operands[0].reg;
13968
13969  if (unified_syntax)
13970    {
13971      bool narrow;
13972      int shift_kind;
13973
13974      switch (inst.instruction)
13975	{
13976	case T_MNEM_asr:
13977	case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
13978	case T_MNEM_lsl:
13979	case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
13980	case T_MNEM_lsr:
13981	case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
13982	case T_MNEM_ror:
13983	case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
13984	default: abort ();
13985	}
13986
13987      if (THUMB_SETS_FLAGS (inst.instruction))
13988	narrow = !in_pred_block ();
13989      else
13990	narrow = in_pred_block ();
13991      if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13992	narrow = false;
13993      if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13994	narrow = false;
13995      if (inst.operands[2].isreg
13996	  && (inst.operands[1].reg != inst.operands[0].reg
13997	      || inst.operands[2].reg > 7))
13998	narrow = false;
13999      if (inst.size_req == 4)
14000	narrow = false;
14001
14002      reject_bad_reg (inst.operands[0].reg);
14003      reject_bad_reg (inst.operands[1].reg);
14004
14005      if (!narrow)
14006	{
14007	  if (inst.operands[2].isreg)
14008	    {
14009	      reject_bad_reg (inst.operands[2].reg);
14010	      inst.instruction = THUMB_OP32 (inst.instruction);
14011	      inst.instruction |= inst.operands[0].reg << 8;
14012	      inst.instruction |= inst.operands[1].reg << 16;
14013	      inst.instruction |= inst.operands[2].reg;
14014
14015	      /* PR 12854: Error on extraneous shifts.  */
14016	      constraint (inst.operands[2].shifted,
14017			  _("extraneous shift as part of operand to shift insn"));
14018	    }
14019	  else
14020	    {
14021	      inst.operands[1].shifted = 1;
14022	      inst.operands[1].shift_kind = shift_kind;
14023	      inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
14024					     ? T_MNEM_movs : T_MNEM_mov);
14025	      inst.instruction |= inst.operands[0].reg << 8;
14026	      encode_thumb32_shifted_operand (1);
14027	      /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup.  */
14028	      inst.relocs[0].type = BFD_RELOC_UNUSED;
14029	    }
14030	}
14031      else
14032	{
14033	  if (inst.operands[2].isreg)
14034	    {
14035	      switch (shift_kind)
14036		{
14037		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
14038		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
14039		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
14040		case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
14041		default: abort ();
14042		}
14043
14044	      inst.instruction |= inst.operands[0].reg;
14045	      inst.instruction |= inst.operands[2].reg << 3;
14046
14047	      /* PR 12854: Error on extraneous shifts.  */
14048	      constraint (inst.operands[2].shifted,
14049			  _("extraneous shift as part of operand to shift insn"));
14050	    }
14051	  else
14052	    {
14053	      switch (shift_kind)
14054		{
14055		case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
14056		case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
14057		case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
14058		default: abort ();
14059		}
14060	      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
14061	      inst.instruction |= inst.operands[0].reg;
14062	      inst.instruction |= inst.operands[1].reg << 3;
14063	    }
14064	}
14065    }
14066  else
14067    {
14068      constraint (inst.operands[0].reg > 7
14069		  || inst.operands[1].reg > 7, BAD_HIREG);
14070      constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
14071
14072      if (inst.operands[2].isreg)  /* Rd, {Rs,} Rn */
14073	{
14074	  constraint (inst.operands[2].reg > 7, BAD_HIREG);
14075	  constraint (inst.operands[0].reg != inst.operands[1].reg,
14076		      _("source1 and dest must be same register"));
14077
14078	  switch (inst.instruction)
14079	    {
14080	    case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
14081	    case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
14082	    case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
14083	    case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
14084	    default: abort ();
14085	    }
14086
14087	  inst.instruction |= inst.operands[0].reg;
14088	  inst.instruction |= inst.operands[2].reg << 3;
14089
14090	  /* PR 12854: Error on extraneous shifts.  */
14091	  constraint (inst.operands[2].shifted,
14092		      _("extraneous shift as part of operand to shift insn"));
14093	}
14094      else
14095	{
14096	  switch (inst.instruction)
14097	    {
14098	    case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
14099	    case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
14100	    case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
14101	    case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
14102	    default: abort ();
14103	    }
14104	  inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
14105	  inst.instruction |= inst.operands[0].reg;
14106	  inst.instruction |= inst.operands[1].reg << 3;
14107	}
14108    }
14109}
14110
14111static void
14112do_t_simd (void)
14113{
14114  unsigned Rd, Rn, Rm;
14115
14116  Rd = inst.operands[0].reg;
14117  Rn = inst.operands[1].reg;
14118  Rm = inst.operands[2].reg;
14119
14120  reject_bad_reg (Rd);
14121  reject_bad_reg (Rn);
14122  reject_bad_reg (Rm);
14123
14124  inst.instruction |= Rd << 8;
14125  inst.instruction |= Rn << 16;
14126  inst.instruction |= Rm;
14127}
14128
14129static void
14130do_t_simd2 (void)
14131{
14132  unsigned Rd, Rn, Rm;
14133
14134  Rd = inst.operands[0].reg;
14135  Rm = inst.operands[1].reg;
14136  Rn = inst.operands[2].reg;
14137
14138  reject_bad_reg (Rd);
14139  reject_bad_reg (Rn);
14140  reject_bad_reg (Rm);
14141
14142  inst.instruction |= Rd << 8;
14143  inst.instruction |= Rn << 16;
14144  inst.instruction |= Rm;
14145}
14146
14147static void
14148do_t_smc (void)
14149{
14150  unsigned int value = inst.relocs[0].exp.X_add_number;
14151  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
14152	      _("SMC is not permitted on this architecture"));
14153  constraint (inst.relocs[0].exp.X_op != O_constant,
14154	      _("expression too complex"));
14155  constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
14156
14157  inst.relocs[0].type = BFD_RELOC_UNUSED;
14158  inst.instruction |= (value & 0x000f) << 16;
14159
14160  /* PR gas/15623: SMC instructions must be last in an IT block.  */
14161  set_pred_insn_type_last ();
14162}
14163
14164static void
14165do_t_hvc (void)
14166{
14167  unsigned int value = inst.relocs[0].exp.X_add_number;
14168
14169  inst.relocs[0].type = BFD_RELOC_UNUSED;
14170  inst.instruction |= (value & 0x0fff);
14171  inst.instruction |= (value & 0xf000) << 4;
14172}
14173
14174static void
14175do_t_ssat_usat (int bias)
14176{
14177  unsigned Rd, Rn;
14178
14179  Rd = inst.operands[0].reg;
14180  Rn = inst.operands[2].reg;
14181
14182  reject_bad_reg (Rd);
14183  reject_bad_reg (Rn);
14184
14185  inst.instruction |= Rd << 8;
14186  inst.instruction |= inst.operands[1].imm - bias;
14187  inst.instruction |= Rn << 16;
14188
14189  if (inst.operands[3].present)
14190    {
14191      offsetT shift_amount = inst.relocs[0].exp.X_add_number;
14192
14193      inst.relocs[0].type = BFD_RELOC_UNUSED;
14194
14195      constraint (inst.relocs[0].exp.X_op != O_constant,
14196		  _("expression too complex"));
14197
14198      if (shift_amount != 0)
14199	{
14200	  constraint (shift_amount > 31,
14201		      _("shift expression is too large"));
14202
14203	  if (inst.operands[3].shift_kind == SHIFT_ASR)
14204	    inst.instruction |= 0x00200000;  /* sh bit.  */
14205
14206	  inst.instruction |= (shift_amount & 0x1c) << 10;
14207	  inst.instruction |= (shift_amount & 0x03) << 6;
14208	}
14209    }
14210}
14211
14212static void
14213do_t_ssat (void)
14214{
14215  do_t_ssat_usat (1);
14216}
14217
14218static void
14219do_t_ssat16 (void)
14220{
14221  unsigned Rd, Rn;
14222
14223  Rd = inst.operands[0].reg;
14224  Rn = inst.operands[2].reg;
14225
14226  reject_bad_reg (Rd);
14227  reject_bad_reg (Rn);
14228
14229  inst.instruction |= Rd << 8;
14230  inst.instruction |= inst.operands[1].imm - 1;
14231  inst.instruction |= Rn << 16;
14232}
14233
14234static void
14235do_t_strex (void)
14236{
14237  constraint (!inst.operands[2].isreg || !inst.operands[2].preind
14238	      || inst.operands[2].postind || inst.operands[2].writeback
14239	      || inst.operands[2].immisreg || inst.operands[2].shifted
14240	      || inst.operands[2].negative,
14241	      BAD_ADDR_MODE);
14242
14243  constraint (inst.operands[2].reg == REG_PC, BAD_PC);
14244
14245  inst.instruction |= inst.operands[0].reg << 8;
14246  inst.instruction |= inst.operands[1].reg << 12;
14247  inst.instruction |= inst.operands[2].reg << 16;
14248  inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
14249}
14250
14251static void
14252do_t_strexd (void)
14253{
14254  if (!inst.operands[2].present)
14255    inst.operands[2].reg = inst.operands[1].reg + 1;
14256
14257  constraint (inst.operands[0].reg == inst.operands[1].reg
14258	      || inst.operands[0].reg == inst.operands[2].reg
14259	      || inst.operands[0].reg == inst.operands[3].reg,
14260	      BAD_OVERLAP);
14261
14262  inst.instruction |= inst.operands[0].reg;
14263  inst.instruction |= inst.operands[1].reg << 12;
14264  inst.instruction |= inst.operands[2].reg << 8;
14265  inst.instruction |= inst.operands[3].reg << 16;
14266}
14267
14268static void
14269do_t_sxtah (void)
14270{
14271  unsigned Rd, Rn, Rm;
14272
14273  Rd = inst.operands[0].reg;
14274  Rn = inst.operands[1].reg;
14275  Rm = inst.operands[2].reg;
14276
14277  reject_bad_reg (Rd);
14278  reject_bad_reg (Rn);
14279  reject_bad_reg (Rm);
14280
14281  inst.instruction |= Rd << 8;
14282  inst.instruction |= Rn << 16;
14283  inst.instruction |= Rm;
14284  inst.instruction |= inst.operands[3].imm << 4;
14285}
14286
14287static void
14288do_t_sxth (void)
14289{
14290  unsigned Rd, Rm;
14291
14292  Rd = inst.operands[0].reg;
14293  Rm = inst.operands[1].reg;
14294
14295  reject_bad_reg (Rd);
14296  reject_bad_reg (Rm);
14297
14298  if (inst.instruction <= 0xffff
14299      && inst.size_req != 4
14300      && Rd <= 7 && Rm <= 7
14301      && (!inst.operands[2].present || inst.operands[2].imm == 0))
14302    {
14303      inst.instruction = THUMB_OP16 (inst.instruction);
14304      inst.instruction |= Rd;
14305      inst.instruction |= Rm << 3;
14306    }
14307  else if (unified_syntax)
14308    {
14309      if (inst.instruction <= 0xffff)
14310	inst.instruction = THUMB_OP32 (inst.instruction);
14311      inst.instruction |= Rd << 8;
14312      inst.instruction |= Rm;
14313      inst.instruction |= inst.operands[2].imm << 4;
14314    }
14315  else
14316    {
14317      constraint (inst.operands[2].present && inst.operands[2].imm != 0,
14318		  _("Thumb encoding does not support rotation"));
14319      constraint (1, BAD_HIREG);
14320    }
14321}
14322
14323static void
14324do_t_swi (void)
14325{
14326  inst.relocs[0].type = BFD_RELOC_ARM_SWI;
14327}
14328
14329static void
14330do_t_tb (void)
14331{
14332  unsigned Rn, Rm;
14333  int half;
14334
14335  half = (inst.instruction & 0x10) != 0;
14336  set_pred_insn_type_last ();
14337  constraint (inst.operands[0].immisreg,
14338	      _("instruction requires register index"));
14339
14340  Rn = inst.operands[0].reg;
14341  Rm = inst.operands[0].imm;
14342
14343  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
14344    constraint (Rn == REG_SP, BAD_SP);
14345  reject_bad_reg (Rm);
14346
14347  constraint (!half && inst.operands[0].shifted,
14348	      _("instruction does not allow shifted index"));
14349  inst.instruction |= (Rn << 16) | Rm;
14350}
14351
14352static void
14353do_t_udf (void)
14354{
14355  if (!inst.operands[0].present)
14356    inst.operands[0].imm = 0;
14357
14358  if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
14359    {
14360      constraint (inst.size_req == 2,
14361                  _("immediate value out of range"));
14362      inst.instruction = THUMB_OP32 (inst.instruction);
14363      inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
14364      inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
14365    }
14366  else
14367    {
14368      inst.instruction = THUMB_OP16 (inst.instruction);
14369      inst.instruction |= inst.operands[0].imm;
14370    }
14371
14372  set_pred_insn_type (NEUTRAL_IT_INSN);
14373}
14374
14375
14376static void
14377do_t_usat (void)
14378{
14379  do_t_ssat_usat (0);
14380}
14381
14382static void
14383do_t_usat16 (void)
14384{
14385  unsigned Rd, Rn;
14386
14387  Rd = inst.operands[0].reg;
14388  Rn = inst.operands[2].reg;
14389
14390  reject_bad_reg (Rd);
14391  reject_bad_reg (Rn);
14392
14393  inst.instruction |= Rd << 8;
14394  inst.instruction |= inst.operands[1].imm;
14395  inst.instruction |= Rn << 16;
14396}
14397
14398/* Checking the range of the branch offset (VAL) with NBITS bits
14399   and IS_SIGNED signedness.  Also checks the LSB to be 0.  */
14400static int
14401v8_1_branch_value_check (int val, int nbits, int is_signed)
14402{
14403  gas_assert (nbits > 0 && nbits <= 32);
14404  if (is_signed)
14405    {
14406      int cmp = (1 << (nbits - 1));
14407      if ((val < -cmp) || (val >= cmp) || (val & 0x01))
14408	return FAIL;
14409    }
14410  else
14411    {
14412      if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
14413	return FAIL;
14414    }
14415    return SUCCESS;
14416}
14417
14418/* For branches in Armv8.1-M Mainline.  */
14419static void
14420do_t_branch_future (void)
14421{
14422  unsigned long insn = inst.instruction;
14423
14424  inst.instruction = THUMB_OP32 (inst.instruction);
14425  if (inst.operands[0].hasreloc == 0)
14426    {
14427      if (v8_1_branch_value_check (inst.operands[0].imm, 5, false) == FAIL)
14428	as_bad (BAD_BRANCH_OFF);
14429
14430      inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
14431    }
14432  else
14433    {
14434      inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
14435      inst.relocs[0].pc_rel = 1;
14436    }
14437
14438  switch (insn)
14439    {
14440      case T_MNEM_bf:
14441	if (inst.operands[1].hasreloc == 0)
14442	  {
14443	    int val = inst.operands[1].imm;
14444	    if (v8_1_branch_value_check (inst.operands[1].imm, 17, true) == FAIL)
14445	      as_bad (BAD_BRANCH_OFF);
14446
14447	    int immA = (val & 0x0001f000) >> 12;
14448	    int immB = (val & 0x00000ffc) >> 2;
14449	    int immC = (val & 0x00000002) >> 1;
14450	    inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14451	  }
14452	else
14453	  {
14454	    inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
14455	    inst.relocs[1].pc_rel = 1;
14456	  }
14457	break;
14458
14459      case T_MNEM_bfl:
14460	if (inst.operands[1].hasreloc == 0)
14461	  {
14462	    int val = inst.operands[1].imm;
14463	    if (v8_1_branch_value_check (inst.operands[1].imm, 19, true) == FAIL)
14464	      as_bad (BAD_BRANCH_OFF);
14465
14466	    int immA = (val & 0x0007f000) >> 12;
14467	    int immB = (val & 0x00000ffc) >> 2;
14468	    int immC = (val & 0x00000002) >> 1;
14469	    inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14470	  }
14471	  else
14472	  {
14473	    inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14474	    inst.relocs[1].pc_rel = 1;
14475	  }
14476	break;
14477
14478      case T_MNEM_bfcsel:
14479	/* Operand 1.  */
14480	if (inst.operands[1].hasreloc == 0)
14481	  {
14482	    int val = inst.operands[1].imm;
14483	    int immA = (val & 0x00001000) >> 12;
14484	    int immB = (val & 0x00000ffc) >> 2;
14485	    int immC = (val & 0x00000002) >> 1;
14486	    inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14487	  }
14488	  else
14489	  {
14490	    inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14491	    inst.relocs[1].pc_rel = 1;
14492	  }
14493
14494	/* Operand 2.  */
14495	if (inst.operands[2].hasreloc == 0)
14496	  {
14497	      constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14498	      int val2 = inst.operands[2].imm;
14499	      int val0 = inst.operands[0].imm & 0x1f;
14500	      int diff = val2 - val0;
14501	      if (diff == 4)
14502		inst.instruction |= 1 << 17; /* T bit.  */
14503	      else if (diff != 2)
14504		as_bad (_("out of range label-relative fixup value"));
14505	  }
14506	else
14507	  {
14508	      constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14509	      inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14510	      inst.relocs[2].pc_rel = 1;
14511	  }
14512
14513	/* Operand 3.  */
14514	constraint (inst.cond != COND_ALWAYS, BAD_COND);
14515	inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14516	break;
14517
14518      case T_MNEM_bfx:
14519      case T_MNEM_bflx:
14520	inst.instruction |= inst.operands[1].reg << 16;
14521	break;
14522
14523      default: abort ();
14524    }
14525}
14526
14527/* Helper function for do_t_loloop to handle relocations.  */
14528static void
14529v8_1_loop_reloc (int is_le)
14530{
14531  if (inst.relocs[0].exp.X_op == O_constant)
14532    {
14533      int value = inst.relocs[0].exp.X_add_number;
14534      value = (is_le) ? -value : value;
14535
14536      if (v8_1_branch_value_check (value, 12, false) == FAIL)
14537	as_bad (BAD_BRANCH_OFF);
14538
14539      int imml, immh;
14540
14541      immh = (value & 0x00000ffc) >> 2;
14542      imml = (value & 0x00000002) >> 1;
14543
14544      inst.instruction |= (imml << 11) | (immh << 1);
14545    }
14546  else
14547    {
14548      inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14549      inst.relocs[0].pc_rel = 1;
14550    }
14551}
14552
14553/* For shifts with four operands in MVE.  */
14554static void
14555do_mve_scalar_shift1 (void)
14556{
14557  unsigned int value = inst.operands[2].imm;
14558
14559  inst.instruction |= inst.operands[0].reg << 16;
14560  inst.instruction |= inst.operands[1].reg << 8;
14561
14562  /* Setting the bit for saturation.  */
14563  inst.instruction |= ((value == 64) ? 0: 1) << 7;
14564
14565  /* Assuming Rm is already checked not to be 11x1.  */
14566  constraint (inst.operands[3].reg == inst.operands[0].reg, BAD_OVERLAP);
14567  constraint (inst.operands[3].reg == inst.operands[1].reg, BAD_OVERLAP);
14568  inst.instruction |= inst.operands[3].reg << 12;
14569}
14570
14571/* For shifts in MVE.  */
14572static void
14573do_mve_scalar_shift (void)
14574{
14575  if (!inst.operands[2].present)
14576    {
14577      inst.operands[2] = inst.operands[1];
14578      inst.operands[1].reg = 0xf;
14579    }
14580
14581  inst.instruction |= inst.operands[0].reg << 16;
14582  inst.instruction |= inst.operands[1].reg << 8;
14583
14584  if (inst.operands[2].isreg)
14585    {
14586      /* Assuming Rm is already checked not to be 11x1.  */
14587      constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
14588      constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
14589      inst.instruction |= inst.operands[2].reg << 12;
14590    }
14591  else
14592    {
14593      /* Assuming imm is already checked as [1,32].  */
14594      unsigned int value = inst.operands[2].imm;
14595      inst.instruction |= (value & 0x1c) << 10;
14596      inst.instruction |= (value & 0x03) << 6;
14597      /* Change last 4 bits from 0xd to 0xf.  */
14598      inst.instruction |= 0x2;
14599    }
14600}
14601
14602/* MVE instruction encoder helpers.  */
14603#define M_MNEM_vabav	0xee800f01
14604#define M_MNEM_vmladav	  0xeef00e00
14605#define M_MNEM_vmladava	  0xeef00e20
14606#define M_MNEM_vmladavx	  0xeef01e00
14607#define M_MNEM_vmladavax  0xeef01e20
14608#define M_MNEM_vmlsdav	  0xeef00e01
14609#define M_MNEM_vmlsdava	  0xeef00e21
14610#define M_MNEM_vmlsdavx	  0xeef01e01
14611#define M_MNEM_vmlsdavax  0xeef01e21
14612#define M_MNEM_vmullt	0xee011e00
14613#define M_MNEM_vmullb	0xee010e00
14614#define M_MNEM_vctp	0xf000e801
14615#define M_MNEM_vst20	0xfc801e00
14616#define M_MNEM_vst21	0xfc801e20
14617#define M_MNEM_vst40	0xfc801e01
14618#define M_MNEM_vst41	0xfc801e21
14619#define M_MNEM_vst42	0xfc801e41
14620#define M_MNEM_vst43	0xfc801e61
14621#define M_MNEM_vld20	0xfc901e00
14622#define M_MNEM_vld21	0xfc901e20
14623#define M_MNEM_vld40	0xfc901e01
14624#define M_MNEM_vld41	0xfc901e21
14625#define M_MNEM_vld42	0xfc901e41
14626#define M_MNEM_vld43	0xfc901e61
14627#define M_MNEM_vstrb	0xec000e00
14628#define M_MNEM_vstrh	0xec000e10
14629#define M_MNEM_vstrw	0xec000e40
14630#define M_MNEM_vstrd	0xec000e50
14631#define M_MNEM_vldrb	0xec100e00
14632#define M_MNEM_vldrh	0xec100e10
14633#define M_MNEM_vldrw	0xec100e40
14634#define M_MNEM_vldrd	0xec100e50
14635#define M_MNEM_vmovlt	0xeea01f40
14636#define M_MNEM_vmovlb	0xeea00f40
14637#define M_MNEM_vmovnt	0xfe311e81
14638#define M_MNEM_vmovnb	0xfe310e81
14639#define M_MNEM_vadc	0xee300f00
14640#define M_MNEM_vadci	0xee301f00
14641#define M_MNEM_vbrsr	0xfe011e60
14642#define M_MNEM_vaddlv	0xee890f00
14643#define M_MNEM_vaddlva	0xee890f20
14644#define M_MNEM_vaddv	0xeef10f00
14645#define M_MNEM_vaddva	0xeef10f20
14646#define M_MNEM_vddup	0xee011f6e
14647#define M_MNEM_vdwdup	0xee011f60
14648#define M_MNEM_vidup	0xee010f6e
14649#define M_MNEM_viwdup	0xee010f60
14650#define M_MNEM_vmaxv	0xeee20f00
14651#define M_MNEM_vmaxav	0xeee00f00
14652#define M_MNEM_vminv	0xeee20f80
14653#define M_MNEM_vminav	0xeee00f80
14654#define M_MNEM_vmlaldav	  0xee800e00
14655#define M_MNEM_vmlaldava  0xee800e20
14656#define M_MNEM_vmlaldavx  0xee801e00
14657#define M_MNEM_vmlaldavax 0xee801e20
14658#define M_MNEM_vmlsldav	  0xee800e01
14659#define M_MNEM_vmlsldava  0xee800e21
14660#define M_MNEM_vmlsldavx  0xee801e01
14661#define M_MNEM_vmlsldavax 0xee801e21
14662#define M_MNEM_vrmlaldavhx  0xee801f00
14663#define M_MNEM_vrmlaldavhax 0xee801f20
14664#define M_MNEM_vrmlsldavh   0xfe800e01
14665#define M_MNEM_vrmlsldavha  0xfe800e21
14666#define M_MNEM_vrmlsldavhx  0xfe801e01
14667#define M_MNEM_vrmlsldavhax 0xfe801e21
14668#define M_MNEM_vqmovnt	  0xee331e01
14669#define M_MNEM_vqmovnb	  0xee330e01
14670#define M_MNEM_vqmovunt	  0xee311e81
14671#define M_MNEM_vqmovunb	  0xee310e81
14672#define M_MNEM_vshrnt	    0xee801fc1
14673#define M_MNEM_vshrnb	    0xee800fc1
14674#define M_MNEM_vrshrnt	    0xfe801fc1
14675#define M_MNEM_vqshrnt	    0xee801f40
14676#define M_MNEM_vqshrnb	    0xee800f40
14677#define M_MNEM_vqshrunt	    0xee801fc0
14678#define M_MNEM_vqshrunb	    0xee800fc0
14679#define M_MNEM_vrshrnb	    0xfe800fc1
14680#define M_MNEM_vqrshrnt	    0xee801f41
14681#define M_MNEM_vqrshrnb	    0xee800f41
14682#define M_MNEM_vqrshrunt    0xfe801fc0
14683#define M_MNEM_vqrshrunb    0xfe800fc0
14684
14685/* Bfloat16 instruction encoder helpers.  */
14686#define B_MNEM_vfmat 0xfc300850
14687#define B_MNEM_vfmab 0xfc300810
14688
14689/* Neon instruction encoder helpers.  */
14690
14691/* Encodings for the different types for various Neon opcodes.  */
14692
14693/* An "invalid" code for the following tables.  */
14694#define N_INV -1u
14695
14696struct neon_tab_entry
14697{
14698  unsigned integer;
14699  unsigned float_or_poly;
14700  unsigned scalar_or_imm;
14701};
14702
14703/* Map overloaded Neon opcodes to their respective encodings.  */
14704#define NEON_ENC_TAB					\
14705  X(vabd,	0x0000700, 0x1200d00, N_INV),		\
14706  X(vabdl,	0x0800700, N_INV,     N_INV),		\
14707  X(vmax,	0x0000600, 0x0000f00, N_INV),		\
14708  X(vmin,	0x0000610, 0x0200f00, N_INV),		\
14709  X(vpadd,	0x0000b10, 0x1000d00, N_INV),		\
14710  X(vpmax,	0x0000a00, 0x1000f00, N_INV),		\
14711  X(vpmin,	0x0000a10, 0x1200f00, N_INV),		\
14712  X(vadd,	0x0000800, 0x0000d00, N_INV),		\
14713  X(vaddl,	0x0800000, N_INV,     N_INV),		\
14714  X(vsub,	0x1000800, 0x0200d00, N_INV),		\
14715  X(vsubl,	0x0800200, N_INV,     N_INV),		\
14716  X(vceq,	0x1000810, 0x0000e00, 0x1b10100),	\
14717  X(vcge,	0x0000310, 0x1000e00, 0x1b10080),	\
14718  X(vcgt,	0x0000300, 0x1200e00, 0x1b10000),	\
14719  /* Register variants of the following two instructions are encoded as
14720     vcge / vcgt with the operands reversed.  */  	\
14721  X(vclt,	0x0000300, 0x1200e00, 0x1b10200),	\
14722  X(vcle,	0x0000310, 0x1000e00, 0x1b10180),	\
14723  X(vfma,	N_INV, 0x0000c10, N_INV),		\
14724  X(vfms,	N_INV, 0x0200c10, N_INV),		\
14725  X(vmla,	0x0000900, 0x0000d10, 0x0800040),	\
14726  X(vmls,	0x1000900, 0x0200d10, 0x0800440),	\
14727  X(vmul,	0x0000910, 0x1000d10, 0x0800840),	\
14728  X(vmull,	0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float.  */ \
14729  X(vmlal,	0x0800800, N_INV,     0x0800240),	\
14730  X(vmlsl,	0x0800a00, N_INV,     0x0800640),	\
14731  X(vqdmlal,	0x0800900, N_INV,     0x0800340),	\
14732  X(vqdmlsl,	0x0800b00, N_INV,     0x0800740),	\
14733  X(vqdmull,	0x0800d00, N_INV,     0x0800b40),	\
14734  X(vqdmulh,    0x0000b00, N_INV,     0x0800c40),	\
14735  X(vqrdmulh,   0x1000b00, N_INV,     0x0800d40),	\
14736  X(vqrdmlah,   0x3000b10, N_INV,     0x0800e40),	\
14737  X(vqrdmlsh,   0x3000c10, N_INV,     0x0800f40),	\
14738  X(vshl,	0x0000400, N_INV,     0x0800510),	\
14739  X(vqshl,	0x0000410, N_INV,     0x0800710),	\
14740  X(vand,	0x0000110, N_INV,     0x0800030),	\
14741  X(vbic,	0x0100110, N_INV,     0x0800030),	\
14742  X(veor,	0x1000110, N_INV,     N_INV),		\
14743  X(vorn,	0x0300110, N_INV,     0x0800010),	\
14744  X(vorr,	0x0200110, N_INV,     0x0800010),	\
14745  X(vmvn,	0x1b00580, N_INV,     0x0800030),	\
14746  X(vshll,	0x1b20300, N_INV,     0x0800a10), /* max shift, immediate.  */ \
14747  X(vcvt,       0x1b30600, N_INV,     0x0800e10), /* integer, fixed-point.  */ \
14748  X(vdup,       0xe800b10, N_INV,     0x1b00c00), /* arm, scalar.  */ \
14749  X(vld1,       0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup.  */ \
14750  X(vst1,	0x0000000, 0x0800000, N_INV),		\
14751  X(vld2,	0x0200100, 0x0a00100, 0x0a00d00),	\
14752  X(vst2,	0x0000100, 0x0800100, N_INV),		\
14753  X(vld3,	0x0200200, 0x0a00200, 0x0a00e00),	\
14754  X(vst3,	0x0000200, 0x0800200, N_INV),		\
14755  X(vld4,	0x0200300, 0x0a00300, 0x0a00f00),	\
14756  X(vst4,	0x0000300, 0x0800300, N_INV),		\
14757  X(vmovn,	0x1b20200, N_INV,     N_INV),		\
14758  X(vtrn,	0x1b20080, N_INV,     N_INV),		\
14759  X(vqmovn,	0x1b20200, N_INV,     N_INV),		\
14760  X(vqmovun,	0x1b20240, N_INV,     N_INV),		\
14761  X(vnmul,      0xe200a40, 0xe200b40, N_INV),		\
14762  X(vnmla,      0xe100a40, 0xe100b40, N_INV),		\
14763  X(vnmls,      0xe100a00, 0xe100b00, N_INV),		\
14764  X(vfnma,      0xe900a40, 0xe900b40, N_INV),		\
14765  X(vfnms,      0xe900a00, 0xe900b00, N_INV),		\
14766  X(vcmp,	0xeb40a40, 0xeb40b40, N_INV),		\
14767  X(vcmpz,	0xeb50a40, 0xeb50b40, N_INV),		\
14768  X(vcmpe,	0xeb40ac0, 0xeb40bc0, N_INV),		\
14769  X(vcmpez,     0xeb50ac0, 0xeb50bc0, N_INV),		\
14770  X(vseleq,	0xe000a00, N_INV,     N_INV),		\
14771  X(vselvs,	0xe100a00, N_INV,     N_INV),		\
14772  X(vselge,	0xe200a00, N_INV,     N_INV),		\
14773  X(vselgt,	0xe300a00, N_INV,     N_INV),		\
14774  X(vmaxnm,	0xe800a00, 0x3000f10, N_INV),		\
14775  X(vminnm,	0xe800a40, 0x3200f10, N_INV),		\
14776  X(vcvta,	0xebc0a40, 0x3bb0000, N_INV),		\
14777  X(vrintr,	0xeb60a40, 0x3ba0400, N_INV),		\
14778  X(vrinta,	0xeb80a40, 0x3ba0400, N_INV),		\
14779  X(aes,	0x3b00300, N_INV,     N_INV),		\
14780  X(sha3op,	0x2000c00, N_INV,     N_INV),		\
14781  X(sha1h,	0x3b902c0, N_INV,     N_INV),           \
14782  X(sha2op,     0x3ba0380, N_INV,     N_INV)
14783
14784enum neon_opc
14785{
14786#define X(OPC,I,F,S) N_MNEM_##OPC
14787NEON_ENC_TAB
14788#undef X
14789};
14790
14791static const struct neon_tab_entry neon_enc_tab[] =
14792{
14793#define X(OPC,I,F,S) { (I), (F), (S) }
14794NEON_ENC_TAB
14795#undef X
14796};
14797
14798/* Do not use these macros; instead, use NEON_ENCODE defined below.  */
14799#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14800#define NEON_ENC_ARMREG_(X)  (neon_enc_tab[(X) & 0x0fffffff].integer)
14801#define NEON_ENC_POLY_(X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14802#define NEON_ENC_FLOAT_(X)   (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14803#define NEON_ENC_SCALAR_(X)  (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14804#define NEON_ENC_IMMED_(X)   (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14805#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14806#define NEON_ENC_LANE_(X)    (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14807#define NEON_ENC_DUP_(X)     (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14808#define NEON_ENC_SINGLE_(X) \
14809  ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14810#define NEON_ENC_DOUBLE_(X) \
14811  ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14812#define NEON_ENC_FPV8_(X) \
14813  ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14814
14815#define NEON_ENCODE(type, inst)					\
14816  do								\
14817    {								\
14818      inst.instruction = NEON_ENC_##type##_ (inst.instruction);	\
14819      inst.is_neon = 1;						\
14820    }								\
14821  while (0)
14822
14823#define check_neon_suffixes						\
14824  do									\
14825    {									\
14826      if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon)	\
14827	{								\
14828	  as_bad (_("invalid neon suffix for non neon instruction"));	\
14829	  return;							\
14830	}								\
14831    }									\
14832  while (0)
14833
14834/* Define shapes for instruction operands. The following mnemonic characters
14835   are used in this table:
14836
14837     F - VFP S<n> register
14838     D - Neon D<n> register
14839     Q - Neon Q<n> register
14840     I - Immediate
14841     S - Scalar
14842     R - ARM register
14843     L - D<n> register list
14844
14845   This table is used to generate various data:
14846     - enumerations of the form NS_DDR to be used as arguments to
14847       neon_select_shape.
14848     - a table classifying shapes into single, double, quad, mixed.
14849     - a table used to drive neon_select_shape.  */
14850
14851#define NEON_SHAPE_DEF			\
14852  X(4, (R, R, Q, Q), QUAD),		\
14853  X(4, (Q, R, R, I), QUAD),		\
14854  X(4, (R, R, S, S), QUAD),		\
14855  X(4, (S, S, R, R), QUAD),		\
14856  X(3, (Q, R, I), QUAD),		\
14857  X(3, (I, Q, Q), QUAD),		\
14858  X(3, (I, Q, R), QUAD),		\
14859  X(3, (R, Q, Q), QUAD),		\
14860  X(3, (D, D, D), DOUBLE),		\
14861  X(3, (Q, Q, Q), QUAD),		\
14862  X(3, (D, D, I), DOUBLE),		\
14863  X(3, (Q, Q, I), QUAD),		\
14864  X(3, (D, D, S), DOUBLE),		\
14865  X(3, (Q, Q, S), QUAD),		\
14866  X(3, (Q, Q, R), QUAD),		\
14867  X(3, (R, R, Q), QUAD),		\
14868  X(2, (R, Q),	  QUAD),		\
14869  X(2, (D, D), DOUBLE),			\
14870  X(2, (Q, Q), QUAD),			\
14871  X(2, (D, S), DOUBLE),			\
14872  X(2, (Q, S), QUAD),			\
14873  X(2, (D, R), DOUBLE),			\
14874  X(2, (Q, R), QUAD),			\
14875  X(2, (D, I), DOUBLE),			\
14876  X(2, (Q, I), QUAD),			\
14877  X(3, (P, F, I), SINGLE),		\
14878  X(3, (P, D, I), DOUBLE),		\
14879  X(3, (P, Q, I), QUAD),		\
14880  X(4, (P, F, F, I), SINGLE),		\
14881  X(4, (P, D, D, I), DOUBLE),		\
14882  X(4, (P, Q, Q, I), QUAD),		\
14883  X(5, (P, F, F, F, I), SINGLE),	\
14884  X(5, (P, D, D, D, I), DOUBLE),	\
14885  X(5, (P, Q, Q, Q, I), QUAD),		\
14886  X(3, (D, L, D), DOUBLE),		\
14887  X(2, (D, Q), MIXED),			\
14888  X(2, (Q, D), MIXED),			\
14889  X(3, (D, Q, I), MIXED),		\
14890  X(3, (Q, D, I), MIXED),		\
14891  X(3, (Q, D, D), MIXED),		\
14892  X(3, (D, Q, Q), MIXED),		\
14893  X(3, (Q, Q, D), MIXED),		\
14894  X(3, (Q, D, S), MIXED),		\
14895  X(3, (D, Q, S), MIXED),		\
14896  X(4, (D, D, D, I), DOUBLE),		\
14897  X(4, (Q, Q, Q, I), QUAD),		\
14898  X(4, (D, D, S, I), DOUBLE),		\
14899  X(4, (Q, Q, S, I), QUAD),		\
14900  X(2, (F, F), SINGLE),			\
14901  X(3, (F, F, F), SINGLE),		\
14902  X(2, (F, I), SINGLE),			\
14903  X(2, (F, D), MIXED),			\
14904  X(2, (D, F), MIXED),			\
14905  X(3, (F, F, I), MIXED),		\
14906  X(4, (R, R, F, F), SINGLE),		\
14907  X(4, (F, F, R, R), SINGLE),		\
14908  X(3, (D, R, R), DOUBLE),		\
14909  X(3, (R, R, D), DOUBLE),		\
14910  X(2, (S, R), SINGLE),			\
14911  X(2, (R, S), SINGLE),			\
14912  X(2, (F, R), SINGLE),			\
14913  X(2, (R, F), SINGLE),			\
14914/* Used for MVE tail predicated loop instructions.  */\
14915  X(2, (R, R), QUAD),			\
14916/* Half float shape supported so far.  */\
14917  X (2, (H, D), MIXED),			\
14918  X (2, (D, H), MIXED),			\
14919  X (2, (H, F), MIXED),			\
14920  X (2, (F, H), MIXED),			\
14921  X (2, (H, H), HALF),			\
14922  X (2, (H, R), HALF),			\
14923  X (2, (R, H), HALF),			\
14924  X (2, (H, I), HALF),			\
14925  X (3, (H, H, H), HALF),		\
14926  X (3, (H, F, I), MIXED),		\
14927  X (3, (F, H, I), MIXED),		\
14928  X (3, (D, H, H), MIXED),		\
14929  X (3, (D, H, S), MIXED)
14930
14931#define S2(A,B)		NS_##A##B
14932#define S3(A,B,C)	NS_##A##B##C
14933#define S4(A,B,C,D)	NS_##A##B##C##D
14934#define S5(A,B,C,D,E)	NS_##A##B##C##D##E
14935
14936#define X(N, L, C) S##N L
14937
14938enum neon_shape
14939{
14940  NEON_SHAPE_DEF,
14941  NS_NULL
14942};
14943
14944#undef X
14945#undef S2
14946#undef S3
14947#undef S4
14948#undef S5
14949
14950enum neon_shape_class
14951{
14952  SC_HALF,
14953  SC_SINGLE,
14954  SC_DOUBLE,
14955  SC_QUAD,
14956  SC_MIXED
14957};
14958
14959#define X(N, L, C) SC_##C
14960
14961static enum neon_shape_class neon_shape_class[] =
14962{
14963  NEON_SHAPE_DEF
14964};
14965
14966#undef X
14967
14968enum neon_shape_el
14969{
14970  SE_H,
14971  SE_F,
14972  SE_D,
14973  SE_Q,
14974  SE_I,
14975  SE_S,
14976  SE_R,
14977  SE_L,
14978  SE_P
14979};
14980
14981/* Register widths of above.  */
14982static unsigned neon_shape_el_size[] =
14983{
14984  16,
14985  32,
14986  64,
14987  128,
14988  0,
14989  32,
14990  32,
14991  0,
14992  0
14993};
14994
14995struct neon_shape_info
14996{
14997  unsigned els;
14998  enum neon_shape_el el[NEON_MAX_TYPE_ELS];
14999};
15000
15001#define S2(A,B)		{ SE_##A, SE_##B }
15002#define S3(A,B,C)	{ SE_##A, SE_##B, SE_##C }
15003#define S4(A,B,C,D)	{ SE_##A, SE_##B, SE_##C, SE_##D }
15004#define S5(A,B,C,D,E)	{ SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
15005
15006#define X(N, L, C) { N, S##N L }
15007
15008static struct neon_shape_info neon_shape_tab[] =
15009{
15010  NEON_SHAPE_DEF
15011};
15012
15013#undef X
15014#undef S2
15015#undef S3
15016#undef S4
15017#undef S5
15018
15019/* Bit masks used in type checking given instructions.
15020  'N_EQK' means the type must be the same as (or based on in some way) the key
15021   type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
15022   set, various other bits can be set as well in order to modify the meaning of
15023   the type constraint.  */
15024
15025enum neon_type_mask
15026{
15027  N_S8   = 0x0000001,
15028  N_S16  = 0x0000002,
15029  N_S32  = 0x0000004,
15030  N_S64  = 0x0000008,
15031  N_U8   = 0x0000010,
15032  N_U16  = 0x0000020,
15033  N_U32  = 0x0000040,
15034  N_U64  = 0x0000080,
15035  N_I8   = 0x0000100,
15036  N_I16  = 0x0000200,
15037  N_I32  = 0x0000400,
15038  N_I64  = 0x0000800,
15039  N_8    = 0x0001000,
15040  N_16   = 0x0002000,
15041  N_32   = 0x0004000,
15042  N_64   = 0x0008000,
15043  N_P8   = 0x0010000,
15044  N_P16  = 0x0020000,
15045  N_F16  = 0x0040000,
15046  N_F32  = 0x0080000,
15047  N_F64  = 0x0100000,
15048  N_P64	 = 0x0200000,
15049  N_BF16 = 0x0400000,
15050  N_KEY  = 0x1000000, /* Key element (main type specifier).  */
15051  N_EQK  = 0x2000000, /* Given operand has the same type & size as the key.  */
15052  N_VFP  = 0x4000000, /* VFP mode: operand size must match register width.  */
15053  N_UNT  = 0x8000000, /* Must be explicitly untyped.  */
15054  N_DBL  = 0x0000001, /* If N_EQK, this operand is twice the size.  */
15055  N_HLF  = 0x0000002, /* If N_EQK, this operand is half the size.  */
15056  N_SGN  = 0x0000004, /* If N_EQK, this operand is forced to be signed.  */
15057  N_UNS  = 0x0000008, /* If N_EQK, this operand is forced to be unsigned.  */
15058  N_INT  = 0x0000010, /* If N_EQK, this operand is forced to be integer.  */
15059  N_FLT  = 0x0000020, /* If N_EQK, this operand is forced to be float.  */
15060  N_SIZ  = 0x0000040, /* If N_EQK, this operand is forced to be size-only.  */
15061  N_UTYP = 0,
15062  N_MAX_NONSPECIAL = N_P64
15063};
15064
15065#define N_ALLMODS  (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15066
15067#define N_SU_ALL   (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15068#define N_SU_32    (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15069#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15070#define N_S_32     (N_S8 | N_S16 | N_S32)
15071#define N_F_16_32  (N_F16 | N_F32)
15072#define N_SUF_32   (N_SU_32 | N_F_16_32)
15073#define N_I_ALL    (N_I8 | N_I16 | N_I32 | N_I64)
15074#define N_IF_32    (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15075#define N_F_ALL    (N_F16 | N_F32 | N_F64)
15076#define N_I_MVE	   (N_I8 | N_I16 | N_I32)
15077#define N_F_MVE	   (N_F16 | N_F32)
15078#define N_SU_MVE   (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15079
15080/* Pass this as the first type argument to neon_check_type to ignore types
15081   altogether.  */
15082#define N_IGNORE_TYPE (N_KEY | N_EQK)
15083
15084/* Select a "shape" for the current instruction (describing register types or
15085   sizes) from a list of alternatives. Return NS_NULL if the current instruction
15086   doesn't fit. For non-polymorphic shapes, checking is usually done as a
15087   function of operand parsing, so this function doesn't need to be called.
15088   Shapes should be listed in order of decreasing length.  */
15089
15090static enum neon_shape
15091neon_select_shape (enum neon_shape shape, ...)
15092{
15093  va_list ap;
15094  enum neon_shape first_shape = shape;
15095
15096  /* Fix missing optional operands. FIXME: we don't know at this point how
15097     many arguments we should have, so this makes the assumption that we have
15098     > 1. This is true of all current Neon opcodes, I think, but may not be
15099     true in the future.  */
15100  if (!inst.operands[1].present)
15101    inst.operands[1] = inst.operands[0];
15102
15103  va_start (ap, shape);
15104
15105  for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
15106    {
15107      unsigned j;
15108      int matches = 1;
15109
15110      for (j = 0; j < neon_shape_tab[shape].els; j++)
15111	{
15112	  if (!inst.operands[j].present)
15113	    {
15114	      matches = 0;
15115	      break;
15116	    }
15117
15118	  switch (neon_shape_tab[shape].el[j])
15119	    {
15120	      /* If a  .f16,  .16,  .u16,  .s16 type specifier is given over
15121		 a VFP single precision register operand, it's essentially
15122		 means only half of the register is used.
15123
15124		 If the type specifier is given after the mnemonics, the
15125		 information is stored in inst.vectype.  If the type specifier
15126		 is given after register operand, the information is stored
15127		 in inst.operands[].vectype.
15128
15129		 When there is only one type specifier, and all the register
15130		 operands are the same type of hardware register, the type
15131		 specifier applies to all register operands.
15132
15133		 If no type specifier is given, the shape is inferred from
15134		 operand information.
15135
15136		 for example:
15137		 vadd.f16 s0, s1, s2:		NS_HHH
15138		 vabs.f16 s0, s1:		NS_HH
15139		 vmov.f16 s0, r1:		NS_HR
15140		 vmov.f16 r0, s1:		NS_RH
15141		 vcvt.f16 r0, s1:		NS_RH
15142		 vcvt.f16.s32	s2, s2, #29:	NS_HFI
15143		 vcvt.f16.s32	s2, s2:		NS_HF
15144	      */
15145	    case SE_H:
15146	      if (!(inst.operands[j].isreg
15147		    && inst.operands[j].isvec
15148		    && inst.operands[j].issingle
15149		    && !inst.operands[j].isquad
15150		    && ((inst.vectype.elems == 1
15151			 && inst.vectype.el[0].size == 16)
15152			|| (inst.vectype.elems > 1
15153			    && inst.vectype.el[j].size == 16)
15154			|| (inst.vectype.elems == 0
15155			    && inst.operands[j].vectype.type != NT_invtype
15156			    && inst.operands[j].vectype.size == 16))))
15157		matches = 0;
15158	      break;
15159
15160	    case SE_F:
15161	      if (!(inst.operands[j].isreg
15162		    && inst.operands[j].isvec
15163		    && inst.operands[j].issingle
15164		    && !inst.operands[j].isquad
15165		    && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
15166			|| (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
15167			|| (inst.vectype.elems == 0
15168			    && (inst.operands[j].vectype.size == 32
15169				|| inst.operands[j].vectype.type == NT_invtype)))))
15170		matches = 0;
15171	      break;
15172
15173	    case SE_D:
15174	      if (!(inst.operands[j].isreg
15175		    && inst.operands[j].isvec
15176		    && !inst.operands[j].isquad
15177		    && !inst.operands[j].issingle))
15178		matches = 0;
15179	      break;
15180
15181	    case SE_R:
15182	      if (!(inst.operands[j].isreg
15183		    && !inst.operands[j].isvec))
15184		matches = 0;
15185	      break;
15186
15187	    case SE_Q:
15188	      if (!(inst.operands[j].isreg
15189		    && inst.operands[j].isvec
15190		    && inst.operands[j].isquad
15191		    && !inst.operands[j].issingle))
15192		matches = 0;
15193	      break;
15194
15195	    case SE_I:
15196	      if (!(!inst.operands[j].isreg
15197		    && !inst.operands[j].isscalar))
15198		matches = 0;
15199	      break;
15200
15201	    case SE_S:
15202	      if (!(!inst.operands[j].isreg
15203		    && inst.operands[j].isscalar))
15204		matches = 0;
15205	      break;
15206
15207	    case SE_P:
15208	    case SE_L:
15209	      break;
15210	    }
15211	  if (!matches)
15212	    break;
15213	}
15214      if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
15215	/* We've matched all the entries in the shape table, and we don't
15216	   have any left over operands which have not been matched.  */
15217	break;
15218    }
15219
15220  va_end (ap);
15221
15222  if (shape == NS_NULL && first_shape != NS_NULL)
15223    first_error (_("invalid instruction shape"));
15224
15225  return shape;
15226}
15227
15228/* True if SHAPE is predominantly a quadword operation (most of the time, this
15229   means the Q bit should be set).  */
15230
15231static int
15232neon_quad (enum neon_shape shape)
15233{
15234  return neon_shape_class[shape] == SC_QUAD;
15235}
15236
15237static void
15238neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
15239		       unsigned *g_size)
15240{
15241  /* Allow modification to be made to types which are constrained to be
15242     based on the key element, based on bits set alongside N_EQK.  */
15243  if ((typebits & N_EQK) != 0)
15244    {
15245      if ((typebits & N_HLF) != 0)
15246	*g_size /= 2;
15247      else if ((typebits & N_DBL) != 0)
15248	*g_size *= 2;
15249      if ((typebits & N_SGN) != 0)
15250	*g_type = NT_signed;
15251      else if ((typebits & N_UNS) != 0)
15252	*g_type = NT_unsigned;
15253      else if ((typebits & N_INT) != 0)
15254	*g_type = NT_integer;
15255      else if ((typebits & N_FLT) != 0)
15256	*g_type = NT_float;
15257      else if ((typebits & N_SIZ) != 0)
15258	*g_type = NT_untyped;
15259    }
15260}
15261
15262/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15263   operand type, i.e. the single type specified in a Neon instruction when it
15264   is the only one given.  */
15265
15266static struct neon_type_el
15267neon_type_promote (struct neon_type_el *key, unsigned thisarg)
15268{
15269  struct neon_type_el dest = *key;
15270
15271  gas_assert ((thisarg & N_EQK) != 0);
15272
15273  neon_modify_type_size (thisarg, &dest.type, &dest.size);
15274
15275  return dest;
15276}
15277
15278/* Convert Neon type and size into compact bitmask representation.  */
15279
15280static enum neon_type_mask
15281type_chk_of_el_type (enum neon_el_type type, unsigned size)
15282{
15283  switch (type)
15284    {
15285    case NT_untyped:
15286      switch (size)
15287	{
15288	case 8:  return N_8;
15289	case 16: return N_16;
15290	case 32: return N_32;
15291	case 64: return N_64;
15292	default: ;
15293	}
15294      break;
15295
15296    case NT_integer:
15297      switch (size)
15298	{
15299	case 8:  return N_I8;
15300	case 16: return N_I16;
15301	case 32: return N_I32;
15302	case 64: return N_I64;
15303	default: ;
15304	}
15305      break;
15306
15307    case NT_float:
15308      switch (size)
15309	{
15310	case 16: return N_F16;
15311	case 32: return N_F32;
15312	case 64: return N_F64;
15313	default: ;
15314	}
15315      break;
15316
15317    case NT_poly:
15318      switch (size)
15319	{
15320	case 8:  return N_P8;
15321	case 16: return N_P16;
15322	case 64: return N_P64;
15323	default: ;
15324	}
15325      break;
15326
15327    case NT_signed:
15328      switch (size)
15329	{
15330	case 8:  return N_S8;
15331	case 16: return N_S16;
15332	case 32: return N_S32;
15333	case 64: return N_S64;
15334	default: ;
15335	}
15336      break;
15337
15338    case NT_unsigned:
15339      switch (size)
15340	{
15341	case 8:  return N_U8;
15342	case 16: return N_U16;
15343	case 32: return N_U32;
15344	case 64: return N_U64;
15345	default: ;
15346	}
15347      break;
15348
15349    case NT_bfloat:
15350      if (size == 16) return N_BF16;
15351      break;
15352
15353    default: ;
15354    }
15355
15356  return N_UTYP;
15357}
15358
15359/* Convert compact Neon bitmask type representation to a type and size. Only
15360   handles the case where a single bit is set in the mask.  */
15361
15362static int
15363el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
15364		     enum neon_type_mask mask)
15365{
15366  if ((mask & N_EQK) != 0)
15367    return FAIL;
15368
15369  if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
15370    *size = 8;
15371  else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16 | N_BF16))
15372	   != 0)
15373    *size = 16;
15374  else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
15375    *size = 32;
15376  else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
15377    *size = 64;
15378  else
15379    return FAIL;
15380
15381  if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
15382    *type = NT_signed;
15383  else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
15384    *type = NT_unsigned;
15385  else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
15386    *type = NT_integer;
15387  else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
15388    *type = NT_untyped;
15389  else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
15390    *type = NT_poly;
15391  else if ((mask & (N_F_ALL)) != 0)
15392    *type = NT_float;
15393  else if ((mask & (N_BF16)) != 0)
15394    *type = NT_bfloat;
15395  else
15396    return FAIL;
15397
15398  return SUCCESS;
15399}
15400
15401/* Modify a bitmask of allowed types. This is only needed for type
15402   relaxation.  */
15403
15404static unsigned
15405modify_types_allowed (unsigned allowed, unsigned mods)
15406{
15407  unsigned size;
15408  enum neon_el_type type;
15409  unsigned destmask;
15410  int i;
15411
15412  destmask = 0;
15413
15414  for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
15415    {
15416      if (el_type_of_type_chk (&type, &size,
15417			       (enum neon_type_mask) (allowed & i)) == SUCCESS)
15418	{
15419	  neon_modify_type_size (mods, &type, &size);
15420	  destmask |= type_chk_of_el_type (type, size);
15421	}
15422    }
15423
15424  return destmask;
15425}
15426
15427/* Check type and return type classification.
15428   The manual states (paraphrase): If one datatype is given, it indicates the
15429   type given in:
15430    - the second operand, if there is one
15431    - the operand, if there is no second operand
15432    - the result, if there are no operands.
15433   This isn't quite good enough though, so we use a concept of a "key" datatype
15434   which is set on a per-instruction basis, which is the one which matters when
15435   only one data type is written.
15436   Note: this function has side-effects (e.g. filling in missing operands). All
15437   Neon instructions should call it before performing bit encoding.  */
15438
15439static struct neon_type_el
15440neon_check_type (unsigned els, enum neon_shape ns, ...)
15441{
15442  va_list ap;
15443  unsigned i, pass, key_el = 0;
15444  unsigned types[NEON_MAX_TYPE_ELS];
15445  enum neon_el_type k_type = NT_invtype;
15446  unsigned k_size = -1u;
15447  struct neon_type_el badtype = {NT_invtype, -1};
15448  unsigned key_allowed = 0;
15449
15450  /* Optional registers in Neon instructions are always (not) in operand 1.
15451     Fill in the missing operand here, if it was omitted.  */
15452  if (els > 1 && !inst.operands[1].present)
15453    inst.operands[1] = inst.operands[0];
15454
15455  /* Suck up all the varargs.  */
15456  va_start (ap, ns);
15457  for (i = 0; i < els; i++)
15458    {
15459      unsigned thisarg = va_arg (ap, unsigned);
15460      if (thisarg == N_IGNORE_TYPE)
15461	{
15462	  va_end (ap);
15463	  return badtype;
15464	}
15465      types[i] = thisarg;
15466      if ((thisarg & N_KEY) != 0)
15467	key_el = i;
15468    }
15469  va_end (ap);
15470
15471  if (inst.vectype.elems > 0)
15472    for (i = 0; i < els; i++)
15473      if (inst.operands[i].vectype.type != NT_invtype)
15474	{
15475	  first_error (_("types specified in both the mnemonic and operands"));
15476	  return badtype;
15477	}
15478
15479  /* Duplicate inst.vectype elements here as necessary.
15480     FIXME: No idea if this is exactly the same as the ARM assembler,
15481     particularly when an insn takes one register and one non-register
15482     operand. */
15483  if (inst.vectype.elems == 1 && els > 1)
15484    {
15485      unsigned j;
15486      inst.vectype.elems = els;
15487      inst.vectype.el[key_el] = inst.vectype.el[0];
15488      for (j = 0; j < els; j++)
15489	if (j != key_el)
15490	  inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15491						  types[j]);
15492    }
15493  else if (inst.vectype.elems == 0 && els > 0)
15494    {
15495      unsigned j;
15496      /* No types were given after the mnemonic, so look for types specified
15497	 after each operand. We allow some flexibility here; as long as the
15498	 "key" operand has a type, we can infer the others.  */
15499      for (j = 0; j < els; j++)
15500	if (inst.operands[j].vectype.type != NT_invtype)
15501	  inst.vectype.el[j] = inst.operands[j].vectype;
15502
15503      if (inst.operands[key_el].vectype.type != NT_invtype)
15504	{
15505	  for (j = 0; j < els; j++)
15506	    if (inst.operands[j].vectype.type == NT_invtype)
15507	      inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15508						      types[j]);
15509	}
15510      else
15511	{
15512	  first_error (_("operand types can't be inferred"));
15513	  return badtype;
15514	}
15515    }
15516  else if (inst.vectype.elems != els)
15517    {
15518      first_error (_("type specifier has the wrong number of parts"));
15519      return badtype;
15520    }
15521
15522  for (pass = 0; pass < 2; pass++)
15523    {
15524      for (i = 0; i < els; i++)
15525	{
15526	  unsigned thisarg = types[i];
15527	  unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
15528	    ? modify_types_allowed (key_allowed, thisarg) : thisarg;
15529	  enum neon_el_type g_type = inst.vectype.el[i].type;
15530	  unsigned g_size = inst.vectype.el[i].size;
15531
15532	  /* Decay more-specific signed & unsigned types to sign-insensitive
15533	     integer types if sign-specific variants are unavailable.  */
15534	  if ((g_type == NT_signed || g_type == NT_unsigned)
15535	      && (types_allowed & N_SU_ALL) == 0)
15536	    g_type = NT_integer;
15537
15538	  /* If only untyped args are allowed, decay any more specific types to
15539	     them. Some instructions only care about signs for some element
15540	     sizes, so handle that properly.  */
15541	  if (((types_allowed & N_UNT) == 0)
15542	      && ((g_size == 8 && (types_allowed & N_8) != 0)
15543		  || (g_size == 16 && (types_allowed & N_16) != 0)
15544		  || (g_size == 32 && (types_allowed & N_32) != 0)
15545		  || (g_size == 64 && (types_allowed & N_64) != 0)))
15546	    g_type = NT_untyped;
15547
15548	  if (pass == 0)
15549	    {
15550	      if ((thisarg & N_KEY) != 0)
15551		{
15552		  k_type = g_type;
15553		  k_size = g_size;
15554		  key_allowed = thisarg & ~N_KEY;
15555
15556		  /* Check architecture constraint on FP16 extension.  */
15557		  if (k_size == 16
15558		      && k_type == NT_float
15559		      && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15560		    {
15561		      inst.error = _(BAD_FP16);
15562		      return badtype;
15563		    }
15564		}
15565	    }
15566	  else
15567	    {
15568	      if ((thisarg & N_VFP) != 0)
15569		{
15570		  enum neon_shape_el regshape;
15571		  unsigned regwidth, match;
15572
15573		  /* PR 11136: Catch the case where we are passed a shape of NS_NULL.  */
15574		  if (ns == NS_NULL)
15575		    {
15576		      first_error (_("invalid instruction shape"));
15577		      return badtype;
15578		    }
15579		  regshape = neon_shape_tab[ns].el[i];
15580		  regwidth = neon_shape_el_size[regshape];
15581
15582		  /* In VFP mode, operands must match register widths. If we
15583		     have a key operand, use its width, else use the width of
15584		     the current operand.  */
15585		  if (k_size != -1u)
15586		    match = k_size;
15587		  else
15588		    match = g_size;
15589
15590		  /* FP16 will use a single precision register.  */
15591		  if (regwidth == 32 && match == 16)
15592		    {
15593		      if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15594			match = regwidth;
15595		      else
15596			{
15597			  inst.error = _(BAD_FP16);
15598			  return badtype;
15599			}
15600		    }
15601
15602		  if (regwidth != match)
15603		    {
15604		      first_error (_("operand size must match register width"));
15605		      return badtype;
15606		    }
15607		}
15608
15609	      if ((thisarg & N_EQK) == 0)
15610		{
15611		  unsigned given_type = type_chk_of_el_type (g_type, g_size);
15612
15613		  if ((given_type & types_allowed) == 0)
15614		    {
15615		      first_error (BAD_SIMD_TYPE);
15616		      return badtype;
15617		    }
15618		}
15619	      else
15620		{
15621		  enum neon_el_type mod_k_type = k_type;
15622		  unsigned mod_k_size = k_size;
15623		  neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
15624		  if (g_type != mod_k_type || g_size != mod_k_size)
15625		    {
15626		      first_error (_("inconsistent types in Neon instruction"));
15627		      return badtype;
15628		    }
15629		}
15630	    }
15631	}
15632    }
15633
15634  return inst.vectype.el[key_el];
15635}
15636
15637/* Neon-style VFP instruction forwarding.  */
15638
15639/* Thumb VFP instructions have 0xE in the condition field.  */
15640
15641static void
15642do_vfp_cond_or_thumb (void)
15643{
15644  inst.is_neon = 1;
15645
15646  if (thumb_mode)
15647    inst.instruction |= 0xe0000000;
15648  else
15649    inst.instruction |= inst.cond << 28;
15650}
15651
15652/* Look up and encode a simple mnemonic, for use as a helper function for the
15653   Neon-style VFP syntax.  This avoids duplication of bits of the insns table,
15654   etc.  It is assumed that operand parsing has already been done, and that the
15655   operands are in the form expected by the given opcode (this isn't necessarily
15656   the same as the form in which they were parsed, hence some massaging must
15657   take place before this function is called).
15658   Checks current arch version against that in the looked-up opcode.  */
15659
15660static void
15661do_vfp_nsyn_opcode (const char *opname)
15662{
15663  const struct asm_opcode *opcode;
15664
15665  opcode = (const struct asm_opcode *) str_hash_find (arm_ops_hsh, opname);
15666
15667  if (!opcode)
15668    abort ();
15669
15670  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
15671		thumb_mode ? *opcode->tvariant : *opcode->avariant),
15672	      _(BAD_FPU));
15673
15674  inst.is_neon = 1;
15675
15676  if (thumb_mode)
15677    {
15678      inst.instruction = opcode->tvalue;
15679      opcode->tencode ();
15680    }
15681  else
15682    {
15683      inst.instruction = (inst.cond << 28) | opcode->avalue;
15684      opcode->aencode ();
15685    }
15686}
15687
15688static void
15689do_vfp_nsyn_add_sub (enum neon_shape rs)
15690{
15691  int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15692
15693  if (rs == NS_FFF || rs == NS_HHH)
15694    {
15695      if (is_add)
15696	do_vfp_nsyn_opcode ("fadds");
15697      else
15698	do_vfp_nsyn_opcode ("fsubs");
15699
15700      /* ARMv8.2 fp16 instruction.  */
15701      if (rs == NS_HHH)
15702	do_scalar_fp16_v82_encode ();
15703    }
15704  else
15705    {
15706      if (is_add)
15707	do_vfp_nsyn_opcode ("faddd");
15708      else
15709	do_vfp_nsyn_opcode ("fsubd");
15710    }
15711}
15712
15713/* Check operand types to see if this is a VFP instruction, and if so call
15714   PFN ().  */
15715
15716static int
15717try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
15718{
15719  enum neon_shape rs;
15720  struct neon_type_el et;
15721
15722  switch (args)
15723    {
15724    case 2:
15725      rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15726      et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15727      break;
15728
15729    case 3:
15730      rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15731      et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15732			    N_F_ALL | N_KEY | N_VFP);
15733      break;
15734
15735    default:
15736      abort ();
15737    }
15738
15739  if (et.type != NT_invtype)
15740    {
15741      pfn (rs);
15742      return SUCCESS;
15743    }
15744
15745  inst.error = NULL;
15746  return FAIL;
15747}
15748
15749static void
15750do_vfp_nsyn_mla_mls (enum neon_shape rs)
15751{
15752  int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
15753
15754  if (rs == NS_FFF || rs == NS_HHH)
15755    {
15756      if (is_mla)
15757	do_vfp_nsyn_opcode ("fmacs");
15758      else
15759	do_vfp_nsyn_opcode ("fnmacs");
15760
15761      /* ARMv8.2 fp16 instruction.  */
15762      if (rs == NS_HHH)
15763	do_scalar_fp16_v82_encode ();
15764    }
15765  else
15766    {
15767      if (is_mla)
15768	do_vfp_nsyn_opcode ("fmacd");
15769      else
15770	do_vfp_nsyn_opcode ("fnmacd");
15771    }
15772}
15773
15774static void
15775do_vfp_nsyn_fma_fms (enum neon_shape rs)
15776{
15777  int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15778
15779  if (rs == NS_FFF || rs == NS_HHH)
15780    {
15781      if (is_fma)
15782	do_vfp_nsyn_opcode ("ffmas");
15783      else
15784	do_vfp_nsyn_opcode ("ffnmas");
15785
15786      /* ARMv8.2 fp16 instruction.  */
15787      if (rs == NS_HHH)
15788	do_scalar_fp16_v82_encode ();
15789    }
15790  else
15791    {
15792      if (is_fma)
15793	do_vfp_nsyn_opcode ("ffmad");
15794      else
15795	do_vfp_nsyn_opcode ("ffnmad");
15796    }
15797}
15798
15799static void
15800do_vfp_nsyn_mul (enum neon_shape rs)
15801{
15802  if (rs == NS_FFF || rs == NS_HHH)
15803    {
15804      do_vfp_nsyn_opcode ("fmuls");
15805
15806      /* ARMv8.2 fp16 instruction.  */
15807      if (rs == NS_HHH)
15808	do_scalar_fp16_v82_encode ();
15809    }
15810  else
15811    do_vfp_nsyn_opcode ("fmuld");
15812}
15813
15814static void
15815do_vfp_nsyn_abs_neg (enum neon_shape rs)
15816{
15817  int is_neg = (inst.instruction & 0x80) != 0;
15818  neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
15819
15820  if (rs == NS_FF || rs == NS_HH)
15821    {
15822      if (is_neg)
15823	do_vfp_nsyn_opcode ("fnegs");
15824      else
15825	do_vfp_nsyn_opcode ("fabss");
15826
15827      /* ARMv8.2 fp16 instruction.  */
15828      if (rs == NS_HH)
15829	do_scalar_fp16_v82_encode ();
15830    }
15831  else
15832    {
15833      if (is_neg)
15834	do_vfp_nsyn_opcode ("fnegd");
15835      else
15836	do_vfp_nsyn_opcode ("fabsd");
15837    }
15838}
15839
15840/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15841   insns belong to Neon, and are handled elsewhere.  */
15842
15843static void
15844do_vfp_nsyn_ldm_stm (int is_dbmode)
15845{
15846  int is_ldm = (inst.instruction & (1 << 20)) != 0;
15847  if (is_ldm)
15848    {
15849      if (is_dbmode)
15850	do_vfp_nsyn_opcode ("fldmdbs");
15851      else
15852	do_vfp_nsyn_opcode ("fldmias");
15853    }
15854  else
15855    {
15856      if (is_dbmode)
15857	do_vfp_nsyn_opcode ("fstmdbs");
15858      else
15859	do_vfp_nsyn_opcode ("fstmias");
15860    }
15861}
15862
15863static void
15864do_vfp_nsyn_sqrt (void)
15865{
15866  enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15867  neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
15868
15869  if (rs == NS_FF || rs == NS_HH)
15870    {
15871      do_vfp_nsyn_opcode ("fsqrts");
15872
15873      /* ARMv8.2 fp16 instruction.  */
15874      if (rs == NS_HH)
15875	do_scalar_fp16_v82_encode ();
15876    }
15877  else
15878    do_vfp_nsyn_opcode ("fsqrtd");
15879}
15880
15881static void
15882do_vfp_nsyn_div (void)
15883{
15884  enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15885  neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15886		   N_F_ALL | N_KEY | N_VFP);
15887
15888  if (rs == NS_FFF || rs == NS_HHH)
15889    {
15890      do_vfp_nsyn_opcode ("fdivs");
15891
15892      /* ARMv8.2 fp16 instruction.  */
15893      if (rs == NS_HHH)
15894	do_scalar_fp16_v82_encode ();
15895    }
15896  else
15897    do_vfp_nsyn_opcode ("fdivd");
15898}
15899
15900static void
15901do_vfp_nsyn_nmul (void)
15902{
15903  enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15904  neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15905		   N_F_ALL | N_KEY | N_VFP);
15906
15907  if (rs == NS_FFF || rs == NS_HHH)
15908    {
15909      NEON_ENCODE (SINGLE, inst);
15910      do_vfp_sp_dyadic ();
15911
15912      /* ARMv8.2 fp16 instruction.  */
15913      if (rs == NS_HHH)
15914	do_scalar_fp16_v82_encode ();
15915    }
15916  else
15917    {
15918      NEON_ENCODE (DOUBLE, inst);
15919      do_vfp_dp_rd_rn_rm ();
15920    }
15921  do_vfp_cond_or_thumb ();
15922
15923}
15924
15925/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15926   (0, 1, 2, 3).  */
15927
15928static unsigned
15929neon_logbits (unsigned x)
15930{
15931  return ffs (x) - 4;
15932}
15933
15934#define LOW4(R) ((R) & 0xf)
15935#define HI1(R) (((R) >> 4) & 1)
15936#define LOW1(R) ((R) & 0x1)
15937#define HI4(R) (((R) >> 1) & 0xf)
15938
15939static unsigned
15940mve_get_vcmp_vpt_cond (struct neon_type_el et)
15941{
15942  switch (et.type)
15943    {
15944    default:
15945      first_error (BAD_EL_TYPE);
15946      return 0;
15947    case NT_float:
15948      switch (inst.operands[0].imm)
15949	{
15950	default:
15951	  first_error (_("invalid condition"));
15952	  return 0;
15953	case 0x0:
15954	  /* eq.  */
15955	  return 0;
15956	case 0x1:
15957	  /* ne.  */
15958	  return 1;
15959	case 0xa:
15960	  /* ge/  */
15961	  return 4;
15962	case 0xb:
15963	  /* lt.  */
15964	  return 5;
15965	case 0xc:
15966	  /* gt.  */
15967	  return 6;
15968	case 0xd:
15969	  /* le.  */
15970	  return 7;
15971	}
15972    case NT_integer:
15973      /* only accept eq and ne.  */
15974      if (inst.operands[0].imm > 1)
15975	{
15976	  first_error (_("invalid condition"));
15977	  return 0;
15978	}
15979      return inst.operands[0].imm;
15980    case NT_unsigned:
15981      if (inst.operands[0].imm == 0x2)
15982	return 2;
15983      else if (inst.operands[0].imm == 0x8)
15984	return 3;
15985      else
15986	{
15987	  first_error (_("invalid condition"));
15988	  return 0;
15989	}
15990    case NT_signed:
15991      switch (inst.operands[0].imm)
15992	{
15993	  default:
15994	    first_error (_("invalid condition"));
15995	    return 0;
15996	  case 0xa:
15997	    /* ge.  */
15998	    return 4;
15999	  case 0xb:
16000	    /* lt.  */
16001	    return 5;
16002	  case 0xc:
16003	    /* gt.  */
16004	    return 6;
16005	  case 0xd:
16006	    /* le.  */
16007	    return 7;
16008	}
16009    }
16010  /* Should be unreachable.  */
16011  abort ();
16012}
16013
16014/* For VCTP (create vector tail predicate) in MVE.  */
16015static void
16016do_mve_vctp (void)
16017{
16018  int dt = 0;
16019  unsigned size = 0x0;
16020
16021  if (inst.cond > COND_ALWAYS)
16022    inst.pred_insn_type = INSIDE_VPT_INSN;
16023  else
16024    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16025
16026  /* This is a typical MVE instruction which has no type but have size 8, 16,
16027     32 and 64.  For instructions with no type, inst.vectype.el[j].type is set
16028     to NT_untyped and size is updated in inst.vectype.el[j].size.  */
16029  if ((inst.operands[0].present) && (inst.vectype.el[0].type == NT_untyped))
16030    dt = inst.vectype.el[0].size;
16031
16032  /* Setting this does not indicate an actual NEON instruction, but only
16033     indicates that the mnemonic accepts neon-style type suffixes.  */
16034  inst.is_neon = 1;
16035
16036  switch (dt)
16037    {
16038      case 8:
16039	break;
16040      case 16:
16041	size = 0x1; break;
16042      case 32:
16043	size = 0x2; break;
16044      case 64:
16045	size = 0x3; break;
16046      default:
16047	first_error (_("Type is not allowed for this instruction"));
16048    }
16049  inst.instruction |= size << 20;
16050  inst.instruction |= inst.operands[0].reg << 16;
16051}
16052
16053static void
16054do_mve_vpt (void)
16055{
16056  /* We are dealing with a vector predicated block.  */
16057  if (inst.operands[0].present)
16058    {
16059      enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
16060      struct neon_type_el et
16061	= neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
16062			   N_EQK);
16063
16064      unsigned fcond = mve_get_vcmp_vpt_cond (et);
16065
16066      constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
16067
16068      if (et.type == NT_invtype)
16069	return;
16070
16071      if (et.type == NT_float)
16072	{
16073	  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
16074		      BAD_FPU);
16075	  constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE);
16076	  inst.instruction |= (et.size == 16) << 28;
16077	  inst.instruction |= 0x3 << 20;
16078	}
16079      else
16080	{
16081	  constraint (et.size != 8 && et.size != 16 && et.size != 32,
16082		      BAD_EL_TYPE);
16083	  inst.instruction |= 1 << 28;
16084	  inst.instruction |= neon_logbits (et.size) << 20;
16085	}
16086
16087      if (inst.operands[2].isquad)
16088	{
16089	  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16090	  inst.instruction |= LOW4 (inst.operands[2].reg);
16091	  inst.instruction |= (fcond & 0x2) >> 1;
16092	}
16093      else
16094	{
16095	  if (inst.operands[2].reg == REG_SP)
16096	    as_tsktsk (MVE_BAD_SP);
16097	  inst.instruction |= 1 << 6;
16098	  inst.instruction |= (fcond & 0x2) << 4;
16099	  inst.instruction |= inst.operands[2].reg;
16100	}
16101      inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16102      inst.instruction |= (fcond & 0x4) << 10;
16103      inst.instruction |= (fcond & 0x1) << 7;
16104
16105    }
16106    set_pred_insn_type (VPT_INSN);
16107    now_pred.cc = 0;
16108    now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
16109		    | ((inst.instruction & 0xe000) >> 13);
16110    now_pred.warn_deprecated = false;
16111    now_pred.type = VECTOR_PRED;
16112    inst.is_neon = 1;
16113}
16114
16115static void
16116do_mve_vcmp (void)
16117{
16118  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
16119  if (!inst.operands[1].isreg || !inst.operands[1].isquad)
16120    first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
16121  if (!inst.operands[2].present)
16122    first_error (_("MVE vector or ARM register expected"));
16123  constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
16124
16125  /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe.  */
16126  if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
16127      && inst.operands[1].isquad)
16128    {
16129      inst.instruction = N_MNEM_vcmp;
16130      inst.cond = 0x10;
16131    }
16132
16133  if (inst.cond > COND_ALWAYS)
16134    inst.pred_insn_type = INSIDE_VPT_INSN;
16135  else
16136    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16137
16138  enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
16139  struct neon_type_el et
16140    = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
16141		       N_EQK);
16142
16143  constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
16144	      && !inst.operands[2].iszr, BAD_PC);
16145
16146  unsigned fcond = mve_get_vcmp_vpt_cond (et);
16147
16148  inst.instruction = 0xee010f00;
16149  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16150  inst.instruction |= (fcond & 0x4) << 10;
16151  inst.instruction |= (fcond & 0x1) << 7;
16152  if (et.type == NT_float)
16153    {
16154      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
16155		  BAD_FPU);
16156      inst.instruction |= (et.size == 16) << 28;
16157      inst.instruction |= 0x3 << 20;
16158    }
16159  else
16160    {
16161      inst.instruction |= 1 << 28;
16162      inst.instruction |= neon_logbits (et.size) << 20;
16163    }
16164  if (inst.operands[2].isquad)
16165    {
16166      inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16167      inst.instruction |= (fcond & 0x2) >> 1;
16168      inst.instruction |= LOW4 (inst.operands[2].reg);
16169    }
16170  else
16171    {
16172      if (inst.operands[2].reg == REG_SP)
16173	as_tsktsk (MVE_BAD_SP);
16174      inst.instruction |= 1 << 6;
16175      inst.instruction |= (fcond & 0x2) << 4;
16176      inst.instruction |= inst.operands[2].reg;
16177    }
16178
16179  inst.is_neon = 1;
16180  return;
16181}
16182
16183static void
16184do_mve_vmaxa_vmina (void)
16185{
16186  if (inst.cond > COND_ALWAYS)
16187    inst.pred_insn_type = INSIDE_VPT_INSN;
16188  else
16189    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16190
16191  enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
16192  struct neon_type_el et
16193    = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
16194
16195  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16196  inst.instruction |= neon_logbits (et.size) << 18;
16197  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16198  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16199  inst.instruction |= LOW4 (inst.operands[1].reg);
16200  inst.is_neon = 1;
16201}
16202
16203static void
16204do_mve_vfmas (void)
16205{
16206  enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
16207  struct neon_type_el et
16208    = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
16209
16210  if (inst.cond > COND_ALWAYS)
16211    inst.pred_insn_type = INSIDE_VPT_INSN;
16212  else
16213    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16214
16215  if (inst.operands[2].reg == REG_SP)
16216    as_tsktsk (MVE_BAD_SP);
16217  else if (inst.operands[2].reg == REG_PC)
16218    as_tsktsk (MVE_BAD_PC);
16219
16220  inst.instruction |= (et.size == 16) << 28;
16221  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16222  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16223  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16224  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16225  inst.instruction |= inst.operands[2].reg;
16226  inst.is_neon = 1;
16227}
16228
16229static void
16230do_mve_viddup (void)
16231{
16232  if (inst.cond > COND_ALWAYS)
16233    inst.pred_insn_type = INSIDE_VPT_INSN;
16234  else
16235    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16236
16237  unsigned imm = inst.relocs[0].exp.X_add_number;
16238  constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
16239	      _("immediate must be either 1, 2, 4 or 8"));
16240
16241  enum neon_shape rs;
16242  struct neon_type_el et;
16243  unsigned Rm;
16244  if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
16245    {
16246      rs = neon_select_shape (NS_QRI, NS_NULL);
16247      et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
16248      Rm = 7;
16249    }
16250  else
16251    {
16252      constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
16253      if (inst.operands[2].reg == REG_SP)
16254	as_tsktsk (MVE_BAD_SP);
16255      else if (inst.operands[2].reg == REG_PC)
16256	first_error (BAD_PC);
16257
16258      rs = neon_select_shape (NS_QRRI, NS_NULL);
16259      et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
16260      Rm = inst.operands[2].reg >> 1;
16261    }
16262  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16263  inst.instruction |= neon_logbits (et.size) << 20;
16264  inst.instruction |= inst.operands[1].reg << 16;
16265  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16266  inst.instruction |= (imm > 2) << 7;
16267  inst.instruction |= Rm << 1;
16268  inst.instruction |= (imm == 2 || imm == 8);
16269  inst.is_neon = 1;
16270}
16271
16272static void
16273do_mve_vmlas (void)
16274{
16275  enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
16276  struct neon_type_el et
16277    = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16278
16279  if (inst.operands[2].reg == REG_PC)
16280    as_tsktsk (MVE_BAD_PC);
16281  else if (inst.operands[2].reg == REG_SP)
16282    as_tsktsk (MVE_BAD_SP);
16283
16284  if (inst.cond > COND_ALWAYS)
16285    inst.pred_insn_type = INSIDE_VPT_INSN;
16286  else
16287    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16288
16289  inst.instruction |= (et.type == NT_unsigned) << 28;
16290  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16291  inst.instruction |= neon_logbits (et.size) << 20;
16292  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16293  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16294  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16295  inst.instruction |= inst.operands[2].reg;
16296  inst.is_neon = 1;
16297}
16298
16299static void
16300do_mve_vshll (void)
16301{
16302  struct neon_type_el et
16303    = neon_check_type (2, NS_QQI, N_EQK, N_S8 | N_U8 | N_S16 | N_U16 | N_KEY);
16304
16305  if (inst.cond > COND_ALWAYS)
16306    inst.pred_insn_type = INSIDE_VPT_INSN;
16307  else
16308    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16309
16310  int imm = inst.operands[2].imm;
16311  constraint (imm < 1 || (unsigned)imm > et.size,
16312	      _("immediate value out of range"));
16313
16314  if ((unsigned)imm == et.size)
16315    {
16316      inst.instruction |= neon_logbits (et.size) << 18;
16317      inst.instruction |= 0x110001;
16318    }
16319  else
16320    {
16321      inst.instruction |= (et.size + imm) << 16;
16322      inst.instruction |= 0x800140;
16323    }
16324
16325  inst.instruction |= (et.type == NT_unsigned) << 28;
16326  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16327  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16328  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16329  inst.instruction |= LOW4 (inst.operands[1].reg);
16330  inst.is_neon = 1;
16331}
16332
16333static void
16334do_mve_vshlc (void)
16335{
16336  if (inst.cond > COND_ALWAYS)
16337    inst.pred_insn_type = INSIDE_VPT_INSN;
16338  else
16339    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16340
16341  if (inst.operands[1].reg == REG_PC)
16342    as_tsktsk (MVE_BAD_PC);
16343  else if (inst.operands[1].reg == REG_SP)
16344    as_tsktsk (MVE_BAD_SP);
16345
16346  int imm = inst.operands[2].imm;
16347  constraint (imm < 1 || imm > 32, _("immediate value out of range"));
16348
16349  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16350  inst.instruction |= (imm & 0x1f) << 16;
16351  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16352  inst.instruction |= inst.operands[1].reg;
16353  inst.is_neon = 1;
16354}
16355
16356static void
16357do_mve_vshrn (void)
16358{
16359  unsigned types;
16360  switch (inst.instruction)
16361    {
16362    case M_MNEM_vshrnt:
16363    case M_MNEM_vshrnb:
16364    case M_MNEM_vrshrnt:
16365    case M_MNEM_vrshrnb:
16366      types = N_I16 | N_I32;
16367      break;
16368    case M_MNEM_vqshrnt:
16369    case M_MNEM_vqshrnb:
16370    case M_MNEM_vqrshrnt:
16371    case M_MNEM_vqrshrnb:
16372      types = N_U16 | N_U32 | N_S16 | N_S32;
16373      break;
16374    case M_MNEM_vqshrunt:
16375    case M_MNEM_vqshrunb:
16376    case M_MNEM_vqrshrunt:
16377    case M_MNEM_vqrshrunb:
16378      types = N_S16 | N_S32;
16379      break;
16380    default:
16381      abort ();
16382    }
16383
16384  struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY);
16385
16386  if (inst.cond > COND_ALWAYS)
16387    inst.pred_insn_type = INSIDE_VPT_INSN;
16388  else
16389    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16390
16391  unsigned Qd = inst.operands[0].reg;
16392  unsigned Qm = inst.operands[1].reg;
16393  unsigned imm = inst.operands[2].imm;
16394  constraint (imm < 1 || ((unsigned) imm) > (et.size / 2),
16395	      et.size == 16
16396	      ? _("immediate operand expected in the range [1,8]")
16397	      : _("immediate operand expected in the range [1,16]"));
16398
16399  inst.instruction |= (et.type == NT_unsigned) << 28;
16400  inst.instruction |= HI1 (Qd) << 22;
16401  inst.instruction |= (et.size - imm) << 16;
16402  inst.instruction |= LOW4 (Qd) << 12;
16403  inst.instruction |= HI1 (Qm) << 5;
16404  inst.instruction |= LOW4 (Qm);
16405  inst.is_neon = 1;
16406}
16407
16408static void
16409do_mve_vqmovn (void)
16410{
16411  struct neon_type_el et;
16412  if (inst.instruction == M_MNEM_vqmovnt
16413     || inst.instruction == M_MNEM_vqmovnb)
16414    et = neon_check_type (2, NS_QQ, N_EQK,
16415			  N_U16 | N_U32 | N_S16 | N_S32 | N_KEY);
16416  else
16417    et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY);
16418
16419  if (inst.cond > COND_ALWAYS)
16420    inst.pred_insn_type = INSIDE_VPT_INSN;
16421  else
16422    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16423
16424  inst.instruction |= (et.type == NT_unsigned) << 28;
16425  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16426  inst.instruction |= (et.size == 32) << 18;
16427  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16428  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16429  inst.instruction |= LOW4 (inst.operands[1].reg);
16430  inst.is_neon = 1;
16431}
16432
16433static void
16434do_mve_vpsel (void)
16435{
16436  neon_select_shape (NS_QQQ, NS_NULL);
16437
16438  if (inst.cond > COND_ALWAYS)
16439    inst.pred_insn_type = INSIDE_VPT_INSN;
16440  else
16441    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16442
16443  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16444  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16445  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16446  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16447  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16448  inst.instruction |= LOW4 (inst.operands[2].reg);
16449  inst.is_neon = 1;
16450}
16451
16452static void
16453do_mve_vpnot (void)
16454{
16455  if (inst.cond > COND_ALWAYS)
16456    inst.pred_insn_type = INSIDE_VPT_INSN;
16457  else
16458    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16459}
16460
16461static void
16462do_mve_vmaxnma_vminnma (void)
16463{
16464  enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
16465  struct neon_type_el et
16466    = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
16467
16468  if (inst.cond > COND_ALWAYS)
16469    inst.pred_insn_type = INSIDE_VPT_INSN;
16470  else
16471    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16472
16473  inst.instruction |= (et.size == 16) << 28;
16474  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16475  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16476  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16477  inst.instruction |= LOW4 (inst.operands[1].reg);
16478  inst.is_neon = 1;
16479}
16480
16481static void
16482do_mve_vcmul (void)
16483{
16484  enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
16485  struct neon_type_el et
16486    = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
16487
16488  if (inst.cond > COND_ALWAYS)
16489    inst.pred_insn_type = INSIDE_VPT_INSN;
16490  else
16491    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16492
16493  unsigned rot = inst.relocs[0].exp.X_add_number;
16494  constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
16495	      _("immediate out of range"));
16496
16497  if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
16498			|| inst.operands[0].reg == inst.operands[2].reg))
16499    as_tsktsk (BAD_MVE_SRCDEST);
16500
16501  inst.instruction |= (et.size == 32) << 28;
16502  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16503  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16504  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16505  inst.instruction |= (rot > 90) << 12;
16506  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16507  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16508  inst.instruction |= LOW4 (inst.operands[2].reg);
16509  inst.instruction |= (rot == 90 || rot == 270);
16510  inst.is_neon = 1;
16511}
16512
16513/* To handle the Low Overhead Loop instructions
16514   in Armv8.1-M Mainline and MVE.  */
16515static void
16516do_t_loloop (void)
16517{
16518  unsigned long insn = inst.instruction;
16519
16520  inst.instruction = THUMB_OP32 (inst.instruction);
16521
16522  if (insn == T_MNEM_lctp)
16523    return;
16524
16525  set_pred_insn_type (MVE_OUTSIDE_PRED_INSN);
16526
16527  if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16528    {
16529      struct neon_type_el et
16530       = neon_check_type (2, NS_RR, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
16531      inst.instruction |= neon_logbits (et.size) << 20;
16532      inst.is_neon = 1;
16533    }
16534
16535  switch (insn)
16536    {
16537    case T_MNEM_letp:
16538      constraint (!inst.operands[0].present,
16539		  _("expected LR"));
16540      /* fall through.  */
16541    case T_MNEM_le:
16542      /* le <label>.  */
16543      if (!inst.operands[0].present)
16544       inst.instruction |= 1 << 21;
16545
16546      v8_1_loop_reloc (true);
16547      break;
16548
16549    case T_MNEM_wls:
16550    case T_MNEM_wlstp:
16551      v8_1_loop_reloc (false);
16552      /* fall through.  */
16553    case T_MNEM_dlstp:
16554    case T_MNEM_dls:
16555      constraint (inst.operands[1].isreg != 1, BAD_ARGS);
16556
16557      if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16558       constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16559      else if (inst.operands[1].reg == REG_PC)
16560       as_tsktsk (MVE_BAD_PC);
16561      if (inst.operands[1].reg == REG_SP)
16562       as_tsktsk (MVE_BAD_SP);
16563
16564      inst.instruction |= (inst.operands[1].reg << 16);
16565      break;
16566
16567    default:
16568      abort ();
16569    }
16570}
16571
16572
16573static void
16574do_vfp_nsyn_cmp (void)
16575{
16576  enum neon_shape rs;
16577  if (!inst.operands[0].isreg)
16578    {
16579      do_mve_vcmp ();
16580      return;
16581    }
16582  else
16583    {
16584      constraint (inst.operands[2].present, BAD_SYNTAX);
16585      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
16586		  BAD_FPU);
16587    }
16588
16589  if (inst.operands[1].isreg)
16590    {
16591      rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
16592      neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
16593
16594      if (rs == NS_FF || rs == NS_HH)
16595	{
16596	  NEON_ENCODE (SINGLE, inst);
16597	  do_vfp_sp_monadic ();
16598	}
16599      else
16600	{
16601	  NEON_ENCODE (DOUBLE, inst);
16602	  do_vfp_dp_rd_rm ();
16603	}
16604    }
16605  else
16606    {
16607      rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
16608      neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
16609
16610      switch (inst.instruction & 0x0fffffff)
16611	{
16612	case N_MNEM_vcmp:
16613	  inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
16614	  break;
16615	case N_MNEM_vcmpe:
16616	  inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
16617	  break;
16618	default:
16619	  abort ();
16620	}
16621
16622      if (rs == NS_FI || rs == NS_HI)
16623	{
16624	  NEON_ENCODE (SINGLE, inst);
16625	  do_vfp_sp_compare_z ();
16626	}
16627      else
16628	{
16629	  NEON_ENCODE (DOUBLE, inst);
16630	  do_vfp_dp_rd ();
16631	}
16632    }
16633  do_vfp_cond_or_thumb ();
16634
16635  /* ARMv8.2 fp16 instruction.  */
16636  if (rs == NS_HI || rs == NS_HH)
16637    do_scalar_fp16_v82_encode ();
16638}
16639
16640static void
16641nsyn_insert_sp (void)
16642{
16643  inst.operands[1] = inst.operands[0];
16644  memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
16645  inst.operands[0].reg = REG_SP;
16646  inst.operands[0].isreg = 1;
16647  inst.operands[0].writeback = 1;
16648  inst.operands[0].present = 1;
16649}
16650
16651/* Fix up Neon data-processing instructions, ORing in the correct bits for
16652   ARM mode or Thumb mode and moving the encoded bit 24 to bit 28.  */
16653
16654static void
16655neon_dp_fixup (struct arm_it* insn)
16656{
16657  unsigned int i = insn->instruction;
16658  insn->is_neon = 1;
16659
16660  if (thumb_mode)
16661    {
16662      /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode.  */
16663      if (i & (1 << 24))
16664	i |= 1 << 28;
16665
16666      i &= ~(1 << 24);
16667
16668      i |= 0xef000000;
16669    }
16670  else
16671    i |= 0xf2000000;
16672
16673  insn->instruction = i;
16674}
16675
16676static void
16677mve_encode_qqr (int size, int U, int fp)
16678{
16679  if (inst.operands[2].reg == REG_SP)
16680    as_tsktsk (MVE_BAD_SP);
16681  else if (inst.operands[2].reg == REG_PC)
16682    as_tsktsk (MVE_BAD_PC);
16683
16684  if (fp)
16685    {
16686      /* vadd.  */
16687      if (((unsigned)inst.instruction) == 0xd00)
16688	inst.instruction = 0xee300f40;
16689      /* vsub.  */
16690      else if (((unsigned)inst.instruction) == 0x200d00)
16691	inst.instruction = 0xee301f40;
16692      /* vmul.  */
16693      else if (((unsigned)inst.instruction) == 0x1000d10)
16694	inst.instruction = 0xee310e60;
16695
16696      /* Setting size which is 1 for F16 and 0 for F32.  */
16697      inst.instruction |= (size == 16) << 28;
16698    }
16699  else
16700    {
16701      /* vadd.  */
16702      if (((unsigned)inst.instruction) == 0x800)
16703	inst.instruction = 0xee010f40;
16704      /* vsub.  */
16705      else if (((unsigned)inst.instruction) == 0x1000800)
16706	inst.instruction = 0xee011f40;
16707      /* vhadd.  */
16708      else if (((unsigned)inst.instruction) == 0)
16709	inst.instruction = 0xee000f40;
16710      /* vhsub.  */
16711      else if (((unsigned)inst.instruction) == 0x200)
16712	inst.instruction = 0xee001f40;
16713      /* vmla.  */
16714      else if (((unsigned)inst.instruction) == 0x900)
16715	inst.instruction = 0xee010e40;
16716      /* vmul.  */
16717      else if (((unsigned)inst.instruction) == 0x910)
16718	inst.instruction = 0xee011e60;
16719      /* vqadd.  */
16720      else if (((unsigned)inst.instruction) == 0x10)
16721	inst.instruction = 0xee000f60;
16722      /* vqsub.  */
16723      else if (((unsigned)inst.instruction) == 0x210)
16724	inst.instruction = 0xee001f60;
16725      /* vqrdmlah.  */
16726      else if (((unsigned)inst.instruction) == 0x3000b10)
16727	inst.instruction = 0xee000e40;
16728      /* vqdmulh.  */
16729      else if (((unsigned)inst.instruction) == 0x0000b00)
16730	inst.instruction = 0xee010e60;
16731      /* vqrdmulh.  */
16732      else if (((unsigned)inst.instruction) == 0x1000b00)
16733	inst.instruction = 0xfe010e60;
16734
16735      /* Set U-bit.  */
16736      inst.instruction |= U << 28;
16737
16738      /* Setting bits for size.  */
16739      inst.instruction |= neon_logbits (size) << 20;
16740    }
16741  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16742  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16743  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16744  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16745  inst.instruction |= inst.operands[2].reg;
16746  inst.is_neon = 1;
16747}
16748
16749static void
16750mve_encode_rqq (unsigned bit28, unsigned size)
16751{
16752  inst.instruction |= bit28 << 28;
16753  inst.instruction |= neon_logbits (size) << 20;
16754  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16755  inst.instruction |= inst.operands[0].reg << 12;
16756  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16757  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16758  inst.instruction |= LOW4 (inst.operands[2].reg);
16759  inst.is_neon = 1;
16760}
16761
16762static void
16763mve_encode_qqq (int ubit, int size)
16764{
16765
16766  inst.instruction |= (ubit != 0) << 28;
16767  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16768  inst.instruction |= neon_logbits (size) << 20;
16769  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16770  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16771  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16772  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16773  inst.instruction |= LOW4 (inst.operands[2].reg);
16774
16775  inst.is_neon = 1;
16776}
16777
16778static void
16779mve_encode_rq (unsigned bit28, unsigned size)
16780{
16781  inst.instruction |= bit28 << 28;
16782  inst.instruction |= neon_logbits (size) << 18;
16783  inst.instruction |= inst.operands[0].reg << 12;
16784  inst.instruction |= LOW4 (inst.operands[1].reg);
16785  inst.is_neon = 1;
16786}
16787
16788static void
16789mve_encode_rrqq (unsigned U, unsigned size)
16790{
16791  constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16792
16793  inst.instruction |= U << 28;
16794  inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16795  inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16796  inst.instruction |= (size == 32) << 16;
16797  inst.instruction |= inst.operands[0].reg << 12;
16798  inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16799  inst.instruction |= inst.operands[3].reg;
16800  inst.is_neon = 1;
16801}
16802
16803/* Helper function for neon_three_same handling the operands.  */
16804static void
16805neon_three_args (int isquad)
16806{
16807  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16808  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16809  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16810  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16811  inst.instruction |= LOW4 (inst.operands[2].reg);
16812  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16813  inst.instruction |= (isquad != 0) << 6;
16814  inst.is_neon = 1;
16815}
16816
16817/* Encode insns with bit pattern:
16818
16819  |28/24|23|22 |21 20|19 16|15 12|11    8|7|6|5|4|3  0|
16820  |  U  |x |D  |size | Rn  | Rd  |x x x x|N|Q|M|x| Rm |
16821
16822  SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16823  different meaning for some instruction.  */
16824
16825static void
16826neon_three_same (int isquad, int ubit, int size)
16827{
16828  neon_three_args (isquad);
16829  inst.instruction |= (ubit != 0) << 24;
16830  if (size != -1)
16831    inst.instruction |= neon_logbits (size) << 20;
16832
16833  neon_dp_fixup (&inst);
16834}
16835
16836/* Encode instructions of the form:
16837
16838  |28/24|23|22|21 20|19 18|17 16|15 12|11      7|6|5|4|3  0|
16839  |  U  |x |D |x  x |size |x  x | Rd  |x x x x x|Q|M|x| Rm |
16840
16841  Don't write size if SIZE == -1.  */
16842
16843static void
16844neon_two_same (int qbit, int ubit, int size)
16845{
16846  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16847  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16848  inst.instruction |= LOW4 (inst.operands[1].reg);
16849  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16850  inst.instruction |= (qbit != 0) << 6;
16851  inst.instruction |= (ubit != 0) << 24;
16852
16853  if (size != -1)
16854    inst.instruction |= neon_logbits (size) << 18;
16855
16856  neon_dp_fixup (&inst);
16857}
16858
16859enum vfp_or_neon_is_neon_bits
16860{
16861NEON_CHECK_CC = 1,
16862NEON_CHECK_ARCH = 2,
16863NEON_CHECK_ARCH8 = 4
16864};
16865
16866/* Call this function if an instruction which may have belonged to the VFP or
16867 Neon instruction sets, but turned out to be a Neon instruction (due to the
16868 operand types involved, etc.). We have to check and/or fix-up a couple of
16869 things:
16870
16871   - Make sure the user hasn't attempted to make a Neon instruction
16872     conditional.
16873   - Alter the value in the condition code field if necessary.
16874   - Make sure that the arch supports Neon instructions.
16875
16876 Which of these operations take place depends on bits from enum
16877 vfp_or_neon_is_neon_bits.
16878
16879 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16880 current instruction's condition is COND_ALWAYS, the condition field is
16881 changed to inst.uncond_value.  This is necessary because instructions shared
16882 between VFP and Neon may be conditional for the VFP variants only, and the
16883 unconditional Neon version must have, e.g., 0xF in the condition field.  */
16884
16885static int
16886vfp_or_neon_is_neon (unsigned check)
16887{
16888/* Conditions are always legal in Thumb mode (IT blocks).  */
16889if (!thumb_mode && (check & NEON_CHECK_CC))
16890  {
16891    if (inst.cond != COND_ALWAYS)
16892      {
16893	first_error (_(BAD_COND));
16894	return FAIL;
16895      }
16896    if (inst.uncond_value != -1u)
16897      inst.instruction |= inst.uncond_value << 28;
16898  }
16899
16900
16901  if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
16902      || ((check & NEON_CHECK_ARCH8)
16903	  && !mark_feature_used (&fpu_neon_ext_armv8)))
16904    {
16905      first_error (_(BAD_FPU));
16906      return FAIL;
16907    }
16908
16909return SUCCESS;
16910}
16911
16912
16913/* Return TRUE if the SIMD instruction is available for the current
16914   cpu_variant.  FP is set to TRUE if this is a SIMD floating-point
16915   instruction.  CHECK contains th.  CHECK contains the set of bits to pass to
16916   vfp_or_neon_is_neon for the NEON specific checks.  */
16917
16918static bool
16919check_simd_pred_availability (int fp, unsigned check)
16920{
16921if (inst.cond > COND_ALWAYS)
16922  {
16923    if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16924      {
16925	inst.error = BAD_FPU;
16926	return false;
16927      }
16928    inst.pred_insn_type = INSIDE_VPT_INSN;
16929  }
16930else if (inst.cond < COND_ALWAYS)
16931  {
16932    if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16933      inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16934    else if (vfp_or_neon_is_neon (check) == FAIL)
16935      return false;
16936  }
16937else
16938  {
16939    if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
16940	&& vfp_or_neon_is_neon (check) == FAIL)
16941      return false;
16942
16943    if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16944      inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16945  }
16946return true;
16947}
16948
16949/* Neon instruction encoders, in approximate order of appearance.  */
16950
16951static void
16952do_neon_dyadic_i_su (void)
16953{
16954  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
16955   return;
16956
16957  enum neon_shape rs;
16958  struct neon_type_el et;
16959  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16960    rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16961  else
16962    rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16963
16964  et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
16965
16966
16967  if (rs != NS_QQR)
16968    neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16969  else
16970    mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16971}
16972
16973static void
16974do_neon_dyadic_i64_su (void)
16975{
16976  if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
16977    return;
16978  enum neon_shape rs;
16979  struct neon_type_el et;
16980  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16981    {
16982      rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16983      et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16984    }
16985  else
16986    {
16987      rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16988      et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16989    }
16990  if (rs == NS_QQR)
16991    mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16992  else
16993    neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16994}
16995
16996static void
16997neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
16998		unsigned immbits)
16999{
17000  unsigned size = et.size >> 3;
17001  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17002  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17003  inst.instruction |= LOW4 (inst.operands[1].reg);
17004  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17005  inst.instruction |= (isquad != 0) << 6;
17006  inst.instruction |= immbits << 16;
17007  inst.instruction |= (size >> 3) << 7;
17008  inst.instruction |= (size & 0x7) << 19;
17009  if (write_ubit)
17010    inst.instruction |= (uval != 0) << 24;
17011
17012  neon_dp_fixup (&inst);
17013}
17014
17015static void
17016do_neon_shl (void)
17017{
17018  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
17019   return;
17020
17021  if (!inst.operands[2].isreg)
17022    {
17023      enum neon_shape rs;
17024      struct neon_type_el et;
17025      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17026	{
17027	  rs = neon_select_shape (NS_QQI, NS_NULL);
17028	  et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_MVE);
17029	}
17030      else
17031	{
17032	  rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17033	  et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
17034	}
17035      int imm = inst.operands[2].imm;
17036
17037      constraint (imm < 0 || (unsigned)imm >= et.size,
17038		  _("immediate out of range for shift"));
17039      NEON_ENCODE (IMMED, inst);
17040      neon_imm_shift (false, 0, neon_quad (rs), et, imm);
17041    }
17042  else
17043    {
17044      enum neon_shape rs;
17045      struct neon_type_el et;
17046      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17047	{
17048	  rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17049	  et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
17050	}
17051      else
17052	{
17053	  rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17054	  et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
17055	}
17056
17057
17058      if (rs == NS_QQR)
17059	{
17060	  constraint (inst.operands[0].reg != inst.operands[1].reg,
17061		       _("invalid instruction shape"));
17062	  if (inst.operands[2].reg == REG_SP)
17063	    as_tsktsk (MVE_BAD_SP);
17064	  else if (inst.operands[2].reg == REG_PC)
17065	    as_tsktsk (MVE_BAD_PC);
17066
17067	  inst.instruction = 0xee311e60;
17068	  inst.instruction |= (et.type == NT_unsigned) << 28;
17069	  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17070	  inst.instruction |= neon_logbits (et.size) << 18;
17071	  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17072	  inst.instruction |= inst.operands[2].reg;
17073	  inst.is_neon = 1;
17074	}
17075      else
17076	{
17077	  unsigned int tmp;
17078
17079	  /* VSHL/VQSHL 3-register variants have syntax such as:
17080	       vshl.xx Dd, Dm, Dn
17081	     whereas other 3-register operations encoded by neon_three_same have
17082	     syntax like:
17083	       vadd.xx Dd, Dn, Dm
17084	     (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17085	     operands[2].reg here.  */
17086	  tmp = inst.operands[2].reg;
17087	  inst.operands[2].reg = inst.operands[1].reg;
17088	  inst.operands[1].reg = tmp;
17089	  NEON_ENCODE (INTEGER, inst);
17090	  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17091	}
17092    }
17093}
17094
17095static void
17096do_neon_qshl (void)
17097{
17098  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
17099   return;
17100
17101  if (!inst.operands[2].isreg)
17102    {
17103      enum neon_shape rs;
17104      struct neon_type_el et;
17105      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17106	{
17107	  rs = neon_select_shape (NS_QQI, NS_NULL);
17108	  et = neon_check_type (2, rs, N_EQK, N_KEY | N_SU_MVE);
17109	}
17110      else
17111	{
17112	  rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17113	  et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
17114	}
17115      int imm = inst.operands[2].imm;
17116
17117      constraint (imm < 0 || (unsigned)imm >= et.size,
17118		  _("immediate out of range for shift"));
17119      NEON_ENCODE (IMMED, inst);
17120      neon_imm_shift (true, et.type == NT_unsigned, neon_quad (rs), et, imm);
17121    }
17122  else
17123    {
17124      enum neon_shape rs;
17125      struct neon_type_el et;
17126
17127      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17128	{
17129	  rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17130	  et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
17131	}
17132      else
17133	{
17134	  rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17135	  et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
17136	}
17137
17138      if (rs == NS_QQR)
17139	{
17140	  constraint (inst.operands[0].reg != inst.operands[1].reg,
17141		       _("invalid instruction shape"));
17142	  if (inst.operands[2].reg == REG_SP)
17143	    as_tsktsk (MVE_BAD_SP);
17144	  else if (inst.operands[2].reg == REG_PC)
17145	    as_tsktsk (MVE_BAD_PC);
17146
17147	  inst.instruction = 0xee311ee0;
17148	  inst.instruction |= (et.type == NT_unsigned) << 28;
17149	  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17150	  inst.instruction |= neon_logbits (et.size) << 18;
17151	  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17152	  inst.instruction |= inst.operands[2].reg;
17153	  inst.is_neon = 1;
17154	}
17155      else
17156	{
17157	  unsigned int tmp;
17158
17159	  /* See note in do_neon_shl.  */
17160	  tmp = inst.operands[2].reg;
17161	  inst.operands[2].reg = inst.operands[1].reg;
17162	  inst.operands[1].reg = tmp;
17163	  NEON_ENCODE (INTEGER, inst);
17164	  neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17165	}
17166    }
17167}
17168
17169static void
17170do_neon_rshl (void)
17171{
17172  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
17173   return;
17174
17175  enum neon_shape rs;
17176  struct neon_type_el et;
17177  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17178    {
17179      rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17180      et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17181    }
17182  else
17183    {
17184      rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17185      et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
17186    }
17187
17188  unsigned int tmp;
17189
17190  if (rs == NS_QQR)
17191    {
17192      if (inst.operands[2].reg == REG_PC)
17193	as_tsktsk (MVE_BAD_PC);
17194      else if (inst.operands[2].reg == REG_SP)
17195	as_tsktsk (MVE_BAD_SP);
17196
17197      constraint (inst.operands[0].reg != inst.operands[1].reg,
17198		  _("invalid instruction shape"));
17199
17200      if (inst.instruction == 0x0000510)
17201	/* We are dealing with vqrshl.  */
17202	inst.instruction = 0xee331ee0;
17203      else
17204	/* We are dealing with vrshl.  */
17205	inst.instruction = 0xee331e60;
17206
17207      inst.instruction |= (et.type == NT_unsigned) << 28;
17208      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17209      inst.instruction |= neon_logbits (et.size) << 18;
17210      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17211      inst.instruction |= inst.operands[2].reg;
17212      inst.is_neon = 1;
17213    }
17214  else
17215    {
17216      tmp = inst.operands[2].reg;
17217      inst.operands[2].reg = inst.operands[1].reg;
17218      inst.operands[1].reg = tmp;
17219      neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
17220    }
17221}
17222
17223static int
17224neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
17225{
17226  /* Handle .I8 pseudo-instructions.  */
17227  if (size == 8)
17228    {
17229      /* Unfortunately, this will make everything apart from zero out-of-range.
17230	 FIXME is this the intended semantics? There doesn't seem much point in
17231	 accepting .I8 if so.  */
17232      immediate |= immediate << 8;
17233      size = 16;
17234    }
17235
17236  if (size >= 32)
17237    {
17238      if (immediate == (immediate & 0x000000ff))
17239	{
17240	  *immbits = immediate;
17241	  return 0x1;
17242	}
17243      else if (immediate == (immediate & 0x0000ff00))
17244	{
17245	  *immbits = immediate >> 8;
17246	  return 0x3;
17247	}
17248      else if (immediate == (immediate & 0x00ff0000))
17249	{
17250	  *immbits = immediate >> 16;
17251	  return 0x5;
17252	}
17253      else if (immediate == (immediate & 0xff000000))
17254	{
17255	  *immbits = immediate >> 24;
17256	  return 0x7;
17257	}
17258      if ((immediate & 0xffff) != (immediate >> 16))
17259	goto bad_immediate;
17260      immediate &= 0xffff;
17261    }
17262
17263  if (immediate == (immediate & 0x000000ff))
17264    {
17265      *immbits = immediate;
17266      return 0x9;
17267    }
17268  else if (immediate == (immediate & 0x0000ff00))
17269    {
17270      *immbits = immediate >> 8;
17271      return 0xb;
17272    }
17273
17274  bad_immediate:
17275  first_error (_("immediate value out of range"));
17276  return FAIL;
17277}
17278
17279static void
17280do_neon_logic (void)
17281{
17282  if (inst.operands[2].present && inst.operands[2].isreg)
17283    {
17284      enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17285      if (rs == NS_QQQ
17286	  && !check_simd_pred_availability (false,
17287					    NEON_CHECK_ARCH | NEON_CHECK_CC))
17288	return;
17289      else if (rs != NS_QQQ
17290	       && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17291	first_error (BAD_FPU);
17292
17293      neon_check_type (3, rs, N_IGNORE_TYPE);
17294      /* U bit and size field were set as part of the bitmask.  */
17295      NEON_ENCODE (INTEGER, inst);
17296      neon_three_same (neon_quad (rs), 0, -1);
17297    }
17298  else
17299    {
17300      const int three_ops_form = (inst.operands[2].present
17301				  && !inst.operands[2].isreg);
17302      const int immoperand = (three_ops_form ? 2 : 1);
17303      enum neon_shape rs = (three_ops_form
17304			    ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
17305			    : neon_select_shape (NS_DI, NS_QI, NS_NULL));
17306      /* Because neon_select_shape makes the second operand a copy of the first
17307	 if the second operand is not present.  */
17308      if (rs == NS_QQI
17309	  && !check_simd_pred_availability (false,
17310					    NEON_CHECK_ARCH | NEON_CHECK_CC))
17311	return;
17312      else if (rs != NS_QQI
17313	       && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17314	first_error (BAD_FPU);
17315
17316      struct neon_type_el et;
17317      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17318	et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
17319      else
17320	et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
17321			      | N_KEY, N_EQK);
17322
17323      if (et.type == NT_invtype)
17324	return;
17325      enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
17326      unsigned immbits;
17327      int cmode;
17328
17329
17330      if (three_ops_form)
17331	constraint (inst.operands[0].reg != inst.operands[1].reg,
17332		    _("first and second operands shall be the same register"));
17333
17334      NEON_ENCODE (IMMED, inst);
17335
17336      immbits = inst.operands[immoperand].imm;
17337      if (et.size == 64)
17338	{
17339	  /* .i64 is a pseudo-op, so the immediate must be a repeating
17340	     pattern.  */
17341	  if (immbits != (inst.operands[immoperand].regisimm ?
17342			  inst.operands[immoperand].reg : 0))
17343	    {
17344	      /* Set immbits to an invalid constant.  */
17345	      immbits = 0xdeadbeef;
17346	    }
17347	}
17348
17349      switch (opcode)
17350	{
17351	case N_MNEM_vbic:
17352	  cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17353	  break;
17354
17355	case N_MNEM_vorr:
17356	  cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17357	  break;
17358
17359	case N_MNEM_vand:
17360	  /* Pseudo-instruction for VBIC.  */
17361	  neon_invert_size (&immbits, 0, et.size);
17362	  cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17363	  break;
17364
17365	case N_MNEM_vorn:
17366	  /* Pseudo-instruction for VORR.  */
17367	  neon_invert_size (&immbits, 0, et.size);
17368	  cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17369	  break;
17370
17371	default:
17372	  abort ();
17373	}
17374
17375      if (cmode == FAIL)
17376	return;
17377
17378      inst.instruction |= neon_quad (rs) << 6;
17379      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17380      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17381      inst.instruction |= cmode << 8;
17382      neon_write_immbits (immbits);
17383
17384      neon_dp_fixup (&inst);
17385    }
17386}
17387
17388static void
17389do_neon_bitfield (void)
17390{
17391  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17392  neon_check_type (3, rs, N_IGNORE_TYPE);
17393  neon_three_same (neon_quad (rs), 0, -1);
17394}
17395
17396static void
17397neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
17398		  unsigned destbits)
17399{
17400  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17401  struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
17402					    types | N_KEY);
17403  if (et.type == NT_float)
17404    {
17405      NEON_ENCODE (FLOAT, inst);
17406      if (rs == NS_QQR)
17407	mve_encode_qqr (et.size, 0, 1);
17408      else
17409	neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
17410    }
17411  else
17412    {
17413      NEON_ENCODE (INTEGER, inst);
17414      if (rs == NS_QQR)
17415	mve_encode_qqr (et.size, et.type == ubit_meaning, 0);
17416      else
17417	neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
17418    }
17419}
17420
17421
17422static void
17423do_neon_dyadic_if_su_d (void)
17424{
17425  /* This version only allow D registers, but that constraint is enforced during
17426     operand parsing so we don't need to do anything extra here.  */
17427  neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
17428}
17429
17430static void
17431do_neon_dyadic_if_i_d (void)
17432{
17433  /* The "untyped" case can't happen. Do this to stop the "U" bit being
17434     affected if we specify unsigned args.  */
17435  neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17436}
17437
17438static void
17439do_mve_vstr_vldr_QI (int size, int elsize, int load)
17440{
17441  constraint (size < 32, BAD_ADDR_MODE);
17442  constraint (size != elsize, BAD_EL_TYPE);
17443  constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17444  constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
17445  constraint (load && inst.operands[0].reg == inst.operands[1].reg,
17446	      _("destination register and offset register may not be the"
17447		" same"));
17448
17449  int imm = inst.relocs[0].exp.X_add_number;
17450  int add = 1;
17451  if (imm < 0)
17452    {
17453      add = 0;
17454      imm = -imm;
17455    }
17456  constraint ((imm % (size / 8) != 0)
17457	      || imm > (0x7f << neon_logbits (size)),
17458	      (size == 32) ? _("immediate must be a multiple of 4 in the"
17459			       " range of +/-[0,508]")
17460			   : _("immediate must be a multiple of 8 in the"
17461			       " range of +/-[0,1016]"));
17462  inst.instruction |= 0x11 << 24;
17463  inst.instruction |= add << 23;
17464  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17465  inst.instruction |= inst.operands[1].writeback << 21;
17466  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17467  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17468  inst.instruction |= 1 << 12;
17469  inst.instruction |= (size == 64) << 8;
17470  inst.instruction &= 0xffffff00;
17471  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17472  inst.instruction |= imm >> neon_logbits (size);
17473}
17474
17475static void
17476do_mve_vstr_vldr_RQ (int size, int elsize, int load)
17477{
17478    unsigned os = inst.operands[1].imm >> 5;
17479    unsigned type = inst.vectype.el[0].type;
17480    constraint (os != 0 && size == 8,
17481		_("can not shift offsets when accessing less than half-word"));
17482    constraint (os && os != neon_logbits (size),
17483		_("shift immediate must be 1, 2 or 3 for half-word, word"
17484		  " or double-word accesses respectively"));
17485    if (inst.operands[1].reg == REG_PC)
17486      as_tsktsk (MVE_BAD_PC);
17487
17488    switch (size)
17489      {
17490      case 8:
17491	constraint (elsize >= 64, BAD_EL_TYPE);
17492	break;
17493      case 16:
17494	constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17495	break;
17496      case 32:
17497      case 64:
17498	constraint (elsize != size, BAD_EL_TYPE);
17499	break;
17500      default:
17501	break;
17502      }
17503    constraint (inst.operands[1].writeback || !inst.operands[1].preind,
17504		BAD_ADDR_MODE);
17505    if (load)
17506      {
17507	constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
17508		    _("destination register and offset register may not be"
17509		    " the same"));
17510	constraint (size == elsize && type == NT_signed, BAD_EL_TYPE);
17511	constraint (size != elsize && type != NT_unsigned && type != NT_signed,
17512		    BAD_EL_TYPE);
17513	inst.instruction |= ((size == elsize) || (type == NT_unsigned)) << 28;
17514      }
17515    else
17516      {
17517	constraint (type != NT_untyped, BAD_EL_TYPE);
17518      }
17519
17520    inst.instruction |= 1 << 23;
17521    inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17522    inst.instruction |= inst.operands[1].reg << 16;
17523    inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17524    inst.instruction |= neon_logbits (elsize) << 7;
17525    inst.instruction |= HI1 (inst.operands[1].imm) << 5;
17526    inst.instruction |= LOW4 (inst.operands[1].imm);
17527    inst.instruction |= !!os;
17528}
17529
17530static void
17531do_mve_vstr_vldr_RI (int size, int elsize, int load)
17532{
17533  enum neon_el_type type = inst.vectype.el[0].type;
17534
17535  constraint (size >= 64, BAD_ADDR_MODE);
17536  switch (size)
17537    {
17538    case 16:
17539      constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17540      break;
17541    case 32:
17542      constraint (elsize != size, BAD_EL_TYPE);
17543      break;
17544    default:
17545      break;
17546    }
17547  if (load)
17548    {
17549      constraint (elsize != size && type != NT_unsigned
17550		  && type != NT_signed, BAD_EL_TYPE);
17551    }
17552  else
17553    {
17554      constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
17555    }
17556
17557  int imm = inst.relocs[0].exp.X_add_number;
17558  int add = 1;
17559  if (imm < 0)
17560    {
17561      add = 0;
17562      imm = -imm;
17563    }
17564
17565  if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
17566    {
17567      switch (size)
17568	{
17569	case 8:
17570	  constraint (1, _("immediate must be in the range of +/-[0,127]"));
17571	  break;
17572	case 16:
17573	  constraint (1, _("immediate must be a multiple of 2 in the"
17574			   " range of +/-[0,254]"));
17575	  break;
17576	case 32:
17577	  constraint (1, _("immediate must be a multiple of 4 in the"
17578			   " range of +/-[0,508]"));
17579	  break;
17580	}
17581    }
17582
17583  if (size != elsize)
17584    {
17585      constraint (inst.operands[1].reg > 7, BAD_HIREG);
17586      constraint (inst.operands[0].reg > 14,
17587		  _("MVE vector register in the range [Q0..Q7] expected"));
17588      inst.instruction |= (load && type == NT_unsigned) << 28;
17589      inst.instruction |= (size == 16) << 19;
17590      inst.instruction |= neon_logbits (elsize) << 7;
17591    }
17592  else
17593    {
17594      if (inst.operands[1].reg == REG_PC)
17595	as_tsktsk (MVE_BAD_PC);
17596      else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17597	as_tsktsk (MVE_BAD_SP);
17598      inst.instruction |= 1 << 12;
17599      inst.instruction |= neon_logbits (size) << 7;
17600    }
17601  inst.instruction |= inst.operands[1].preind << 24;
17602  inst.instruction |= add << 23;
17603  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17604  inst.instruction |= inst.operands[1].writeback << 21;
17605  inst.instruction |= inst.operands[1].reg << 16;
17606  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17607  inst.instruction &= 0xffffff80;
17608  inst.instruction |= imm >> neon_logbits (size);
17609
17610}
17611
17612static void
17613do_mve_vstr_vldr (void)
17614{
17615  unsigned size;
17616  int load = 0;
17617
17618  if (inst.cond > COND_ALWAYS)
17619    inst.pred_insn_type = INSIDE_VPT_INSN;
17620  else
17621    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17622
17623  switch (inst.instruction)
17624    {
17625    default:
17626      gas_assert (0);
17627      break;
17628    case M_MNEM_vldrb:
17629      load = 1;
17630      /* fall through.  */
17631    case M_MNEM_vstrb:
17632      size = 8;
17633      break;
17634    case M_MNEM_vldrh:
17635      load = 1;
17636      /* fall through.  */
17637    case M_MNEM_vstrh:
17638      size = 16;
17639      break;
17640    case M_MNEM_vldrw:
17641      load = 1;
17642      /* fall through.  */
17643    case M_MNEM_vstrw:
17644      size = 32;
17645      break;
17646    case M_MNEM_vldrd:
17647      load = 1;
17648      /* fall through.  */
17649    case M_MNEM_vstrd:
17650      size = 64;
17651      break;
17652    }
17653  unsigned elsize = inst.vectype.el[0].size;
17654
17655  if (inst.operands[1].isquad)
17656    {
17657      /* We are dealing with [Q, imm]{!} cases.  */
17658      do_mve_vstr_vldr_QI (size, elsize, load);
17659    }
17660  else
17661    {
17662      if (inst.operands[1].immisreg == 2)
17663	{
17664	  /* We are dealing with [R, Q, {UXTW #os}] cases.  */
17665	  do_mve_vstr_vldr_RQ (size, elsize, load);
17666	}
17667      else if (!inst.operands[1].immisreg)
17668	{
17669	  /* We are dealing with [R, Imm]{!}/[R], Imm cases.  */
17670	  do_mve_vstr_vldr_RI (size, elsize, load);
17671	}
17672      else
17673	constraint (1, BAD_ADDR_MODE);
17674    }
17675
17676  inst.is_neon = 1;
17677}
17678
17679static void
17680do_mve_vst_vld (void)
17681{
17682  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17683    return;
17684
17685  constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
17686	      || inst.relocs[0].exp.X_add_number != 0
17687	      || inst.operands[1].immisreg != 0,
17688	      BAD_ADDR_MODE);
17689  constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
17690  if (inst.operands[1].reg == REG_PC)
17691    as_tsktsk (MVE_BAD_PC);
17692  else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17693    as_tsktsk (MVE_BAD_SP);
17694
17695
17696  /* These instructions are one of the "exceptions" mentioned in
17697     handle_pred_state.  They are MVE instructions that are not VPT compatible
17698     and do not accept a VPT code, thus appending such a code is a syntax
17699     error.  */
17700  if (inst.cond > COND_ALWAYS)
17701    first_error (BAD_SYNTAX);
17702  /* If we append a scalar condition code we can set this to
17703     MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error.  */
17704  else if (inst.cond < COND_ALWAYS)
17705    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17706  else
17707    inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
17708
17709  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17710  inst.instruction |= inst.operands[1].writeback << 21;
17711  inst.instruction |= inst.operands[1].reg << 16;
17712  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17713  inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
17714  inst.is_neon = 1;
17715}
17716
17717static void
17718do_mve_vaddlv (void)
17719{
17720  enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
17721  struct neon_type_el et
17722    = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
17723
17724  if (et.type == NT_invtype)
17725    first_error (BAD_EL_TYPE);
17726
17727  if (inst.cond > COND_ALWAYS)
17728    inst.pred_insn_type = INSIDE_VPT_INSN;
17729  else
17730    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17731
17732  constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17733
17734  inst.instruction |= (et.type == NT_unsigned) << 28;
17735  inst.instruction |= inst.operands[1].reg << 19;
17736  inst.instruction |= inst.operands[0].reg << 12;
17737  inst.instruction |= inst.operands[2].reg;
17738  inst.is_neon = 1;
17739}
17740
17741static void
17742do_neon_dyadic_if_su (void)
17743{
17744  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17745  struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17746					    N_SUF_32 | N_KEY);
17747
17748  constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
17749	       || inst.instruction == ((unsigned) N_MNEM_vmin))
17750	      && et.type == NT_float
17751	      && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
17752
17753  if (!check_simd_pred_availability (et.type == NT_float,
17754				     NEON_CHECK_ARCH | NEON_CHECK_CC))
17755    return;
17756
17757  neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
17758}
17759
17760static void
17761do_neon_addsub_if_i (void)
17762{
17763  if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
17764      && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
17765    return;
17766
17767  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17768  struct neon_type_el et = neon_check_type (3, rs, N_EQK,
17769					    N_EQK, N_IF_32 | N_I64 | N_KEY);
17770
17771  constraint (rs == NS_QQR && et.size == 64, BAD_FPU);
17772  /* If we are parsing Q registers and the element types match MVE, which NEON
17773     also supports, then we must check whether this is an instruction that can
17774     be used by both MVE/NEON.  This distinction can be made based on whether
17775     they are predicated or not.  */
17776  if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64)
17777    {
17778      if (!check_simd_pred_availability (et.type == NT_float,
17779					 NEON_CHECK_ARCH | NEON_CHECK_CC))
17780	return;
17781    }
17782  else
17783    {
17784      /* If they are either in a D register or are using an unsupported.  */
17785      if (rs != NS_QQR
17786	  && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
17787	return;
17788    }
17789
17790  /* The "untyped" case can't happen. Do this to stop the "U" bit being
17791     affected if we specify unsigned args.  */
17792  neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
17793}
17794
17795/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17796   result to be:
17797     V<op> A,B     (A is operand 0, B is operand 2)
17798   to mean:
17799     V<op> A,B,A
17800   not:
17801     V<op> A,B,B
17802   so handle that case specially.  */
17803
17804static void
17805neon_exchange_operands (void)
17806{
17807  if (inst.operands[1].present)
17808    {
17809      void *scratch = xmalloc (sizeof (inst.operands[0]));
17810
17811      /* Swap operands[1] and operands[2].  */
17812      memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
17813      inst.operands[1] = inst.operands[2];
17814      memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
17815      free (scratch);
17816    }
17817  else
17818    {
17819      inst.operands[1] = inst.operands[2];
17820      inst.operands[2] = inst.operands[0];
17821    }
17822}
17823
17824static void
17825neon_compare (unsigned regtypes, unsigned immtypes, int invert)
17826{
17827  if (inst.operands[2].isreg)
17828    {
17829      if (invert)
17830	neon_exchange_operands ();
17831      neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
17832    }
17833  else
17834    {
17835      enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
17836      struct neon_type_el et = neon_check_type (2, rs,
17837	N_EQK | N_SIZ, immtypes | N_KEY);
17838
17839      NEON_ENCODE (IMMED, inst);
17840      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17841      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17842      inst.instruction |= LOW4 (inst.operands[1].reg);
17843      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
17844      inst.instruction |= neon_quad (rs) << 6;
17845      inst.instruction |= (et.type == NT_float) << 10;
17846      inst.instruction |= neon_logbits (et.size) << 18;
17847
17848      neon_dp_fixup (&inst);
17849    }
17850}
17851
17852static void
17853do_neon_cmp (void)
17854{
17855  neon_compare (N_SUF_32, N_S_32 | N_F_16_32, false);
17856}
17857
17858static void
17859do_neon_cmp_inv (void)
17860{
17861  neon_compare (N_SUF_32, N_S_32 | N_F_16_32, true);
17862}
17863
17864static void
17865do_neon_ceq (void)
17866{
17867  neon_compare (N_IF_32, N_IF_32, false);
17868}
17869
17870/* For multiply instructions, we have the possibility of 16-bit or 32-bit
17871   scalars, which are encoded in 5 bits, M : Rm.
17872   For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17873   M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17874   index in M.
17875
17876   Dot Product instructions are similar to multiply instructions except elsize
17877   should always be 32.
17878
17879   This function translates SCALAR, which is GAS's internal encoding of indexed
17880   scalar register, to raw encoding.  There is also register and index range
17881   check based on ELSIZE.  */
17882
17883static unsigned
17884neon_scalar_for_mul (unsigned scalar, unsigned elsize)
17885{
17886  unsigned regno = NEON_SCALAR_REG (scalar);
17887  unsigned elno = NEON_SCALAR_INDEX (scalar);
17888
17889  switch (elsize)
17890    {
17891    case 16:
17892      if (regno > 7 || elno > 3)
17893	goto bad_scalar;
17894      return regno | (elno << 3);
17895
17896    case 32:
17897      if (regno > 15 || elno > 1)
17898	goto bad_scalar;
17899      return regno | (elno << 4);
17900
17901    default:
17902    bad_scalar:
17903      first_error (_("scalar out of range for multiply instruction"));
17904    }
17905
17906  return 0;
17907}
17908
17909/* Encode multiply / multiply-accumulate scalar instructions.  */
17910
17911static void
17912neon_mul_mac (struct neon_type_el et, int ubit)
17913{
17914  unsigned scalar;
17915
17916  /* Give a more helpful error message if we have an invalid type.  */
17917  if (et.type == NT_invtype)
17918    return;
17919
17920  scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
17921  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17922  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17923  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17924  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17925  inst.instruction |= LOW4 (scalar);
17926  inst.instruction |= HI1 (scalar) << 5;
17927  inst.instruction |= (et.type == NT_float) << 8;
17928  inst.instruction |= neon_logbits (et.size) << 20;
17929  inst.instruction |= (ubit != 0) << 24;
17930
17931  neon_dp_fixup (&inst);
17932}
17933
17934static void
17935do_neon_mac_maybe_scalar (void)
17936{
17937  if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
17938    return;
17939
17940  if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
17941    return;
17942
17943  if (inst.operands[2].isscalar)
17944    {
17945      constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17946      enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
17947      struct neon_type_el et = neon_check_type (3, rs,
17948	N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
17949      NEON_ENCODE (SCALAR, inst);
17950      neon_mul_mac (et, neon_quad (rs));
17951    }
17952  else if (!inst.operands[2].isvec)
17953    {
17954      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17955
17956      enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17957      neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17958
17959      neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0);
17960    }
17961  else
17962    {
17963      constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17964      /* The "untyped" case can't happen.  Do this to stop the "U" bit being
17965	 affected if we specify unsigned args.  */
17966      neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17967    }
17968}
17969
17970static void
17971do_bfloat_vfma (void)
17972{
17973  constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU));
17974  constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16));
17975  enum neon_shape rs;
17976  int t_bit = 0;
17977
17978  if (inst.instruction != B_MNEM_vfmab)
17979  {
17980      t_bit = 1;
17981      inst.instruction = B_MNEM_vfmat;
17982  }
17983
17984  if (inst.operands[2].isscalar)
17985    {
17986      rs = neon_select_shape (NS_QQS, NS_NULL);
17987      neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
17988
17989      inst.instruction |= (1 << 25);
17990      int idx = inst.operands[2].reg & 0xf;
17991      constraint (!(idx < 4), _("index must be in the range 0 to 3"));
17992      inst.operands[2].reg >>= 4;
17993      constraint (!(inst.operands[2].reg < 8),
17994		  _("indexed register must be less than 8"));
17995      neon_three_args (t_bit);
17996      inst.instruction |= ((idx & 1) << 3);
17997      inst.instruction |= ((idx & 2) << 4);
17998    }
17999  else
18000    {
18001      rs = neon_select_shape (NS_QQQ, NS_NULL);
18002      neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
18003      neon_three_args (t_bit);
18004    }
18005
18006}
18007
18008static void
18009do_neon_fmac (void)
18010{
18011  if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
18012      && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
18013    return;
18014
18015  if (!check_simd_pred_availability (true, NEON_CHECK_CC | NEON_CHECK_ARCH))
18016    return;
18017
18018  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18019    {
18020      enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
18021      struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
18022						N_EQK);
18023
18024      if (rs == NS_QQR)
18025	{
18026
18027	  if (inst.operands[2].reg == REG_SP)
18028	    as_tsktsk (MVE_BAD_SP);
18029	  else if (inst.operands[2].reg == REG_PC)
18030	    as_tsktsk (MVE_BAD_PC);
18031
18032	  inst.instruction = 0xee310e40;
18033	  inst.instruction |= (et.size == 16) << 28;
18034	  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18035	  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
18036	  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18037	  inst.instruction |= HI1 (inst.operands[1].reg) << 6;
18038	  inst.instruction |= inst.operands[2].reg;
18039	  inst.is_neon = 1;
18040	  return;
18041	}
18042    }
18043  else
18044    {
18045      constraint (!inst.operands[2].isvec, BAD_FPU);
18046    }
18047
18048  neon_dyadic_misc (NT_untyped, N_IF_32, 0);
18049}
18050
18051static void
18052do_mve_vfma (void)
18053{
18054  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_bf16) &&
18055      inst.cond == COND_ALWAYS)
18056    {
18057      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
18058      inst.instruction = N_MNEM_vfma;
18059      inst.pred_insn_type = INSIDE_VPT_INSN;
18060      inst.cond = 0xf;
18061      return do_neon_fmac();
18062    }
18063  else
18064    {
18065      do_bfloat_vfma();
18066    }
18067}
18068
18069static void
18070do_neon_tst (void)
18071{
18072  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18073  struct neon_type_el et = neon_check_type (3, rs,
18074    N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18075  neon_three_same (neon_quad (rs), 0, et.size);
18076}
18077
18078/* VMUL with 3 registers allows the P8 type. The scalar version supports the
18079   same types as the MAC equivalents. The polynomial type for this instruction
18080   is encoded the same as the integer type.  */
18081
18082static void
18083do_neon_mul (void)
18084{
18085  if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
18086    return;
18087
18088  if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
18089    return;
18090
18091  if (inst.operands[2].isscalar)
18092    {
18093      constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
18094      do_neon_mac_maybe_scalar ();
18095    }
18096  else
18097    {
18098      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18099	{
18100	  enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
18101	  struct neon_type_el et
18102	    = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY);
18103	  if (et.type == NT_float)
18104	    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
18105			BAD_FPU);
18106
18107	  neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0);
18108	}
18109      else
18110	{
18111	  constraint (!inst.operands[2].isvec, BAD_FPU);
18112	  neon_dyadic_misc (NT_poly,
18113			    N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
18114	}
18115    }
18116}
18117
18118static void
18119do_neon_qdmulh (void)
18120{
18121  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
18122   return;
18123
18124  if (inst.operands[2].isscalar)
18125    {
18126      constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
18127      enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
18128      struct neon_type_el et = neon_check_type (3, rs,
18129	N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18130      NEON_ENCODE (SCALAR, inst);
18131      neon_mul_mac (et, neon_quad (rs));
18132    }
18133  else
18134    {
18135      enum neon_shape rs;
18136      struct neon_type_el et;
18137      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18138	{
18139	  rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
18140	  et = neon_check_type (3, rs,
18141	    N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18142	}
18143      else
18144	{
18145	  rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18146	  et = neon_check_type (3, rs,
18147	    N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18148	}
18149
18150      NEON_ENCODE (INTEGER, inst);
18151      if (rs == NS_QQR)
18152	mve_encode_qqr (et.size, 0, 0);
18153      else
18154	/* The U bit (rounding) comes from bit mask.  */
18155	neon_three_same (neon_quad (rs), 0, et.size);
18156    }
18157}
18158
18159static void
18160do_mve_vaddv (void)
18161{
18162  enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18163  struct neon_type_el et
18164    = neon_check_type (2, rs, N_EQK,  N_SU_32 | N_KEY);
18165
18166  if (et.type == NT_invtype)
18167    first_error (BAD_EL_TYPE);
18168
18169  if (inst.cond > COND_ALWAYS)
18170    inst.pred_insn_type = INSIDE_VPT_INSN;
18171  else
18172    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18173
18174  constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
18175
18176  mve_encode_rq (et.type == NT_unsigned, et.size);
18177}
18178
18179static void
18180do_mve_vhcadd (void)
18181{
18182  enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
18183  struct neon_type_el et
18184    = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18185
18186  if (inst.cond > COND_ALWAYS)
18187    inst.pred_insn_type = INSIDE_VPT_INSN;
18188  else
18189    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18190
18191  unsigned rot = inst.relocs[0].exp.X_add_number;
18192  constraint (rot != 90 && rot != 270, _("immediate out of range"));
18193
18194  if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
18195    as_tsktsk (_("Warning: 32-bit element size and same first and third "
18196		 "operand makes instruction UNPREDICTABLE"));
18197
18198  mve_encode_qqq (0, et.size);
18199  inst.instruction |= (rot == 270) << 12;
18200  inst.is_neon = 1;
18201}
18202
18203static void
18204do_mve_vqdmull (void)
18205{
18206  enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
18207  struct neon_type_el et
18208    = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18209
18210  if (et.size == 32
18211      && (inst.operands[0].reg == inst.operands[1].reg
18212	  || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
18213    as_tsktsk (BAD_MVE_SRCDEST);
18214
18215  if (inst.cond > COND_ALWAYS)
18216    inst.pred_insn_type = INSIDE_VPT_INSN;
18217  else
18218    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18219
18220  if (rs == NS_QQQ)
18221    {
18222      mve_encode_qqq (et.size == 32, 64);
18223      inst.instruction |= 1;
18224    }
18225  else
18226    {
18227      mve_encode_qqr (64, et.size == 32, 0);
18228      inst.instruction |= 0x3 << 5;
18229    }
18230}
18231
18232static void
18233do_mve_vadc (void)
18234{
18235  enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18236  struct neon_type_el et
18237    = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
18238
18239  if (et.type == NT_invtype)
18240    first_error (BAD_EL_TYPE);
18241
18242  if (inst.cond > COND_ALWAYS)
18243    inst.pred_insn_type = INSIDE_VPT_INSN;
18244  else
18245    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18246
18247  mve_encode_qqq (0, 64);
18248}
18249
18250static void
18251do_mve_vbrsr (void)
18252{
18253  enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18254  struct neon_type_el et
18255    = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18256
18257  if (inst.cond > COND_ALWAYS)
18258    inst.pred_insn_type = INSIDE_VPT_INSN;
18259  else
18260    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18261
18262  mve_encode_qqr (et.size, 0, 0);
18263}
18264
18265static void
18266do_mve_vsbc (void)
18267{
18268  neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
18269
18270  if (inst.cond > COND_ALWAYS)
18271    inst.pred_insn_type = INSIDE_VPT_INSN;
18272  else
18273    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18274
18275  mve_encode_qqq (1, 64);
18276}
18277
18278static void
18279do_mve_vmulh (void)
18280{
18281  enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18282  struct neon_type_el et
18283    = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
18284
18285  if (inst.cond > COND_ALWAYS)
18286    inst.pred_insn_type = INSIDE_VPT_INSN;
18287  else
18288    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18289
18290  mve_encode_qqq (et.type == NT_unsigned, et.size);
18291}
18292
18293static void
18294do_mve_vqdmlah (void)
18295{
18296  enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18297  struct neon_type_el et
18298    = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
18299
18300  if (inst.cond > COND_ALWAYS)
18301    inst.pred_insn_type = INSIDE_VPT_INSN;
18302  else
18303    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18304
18305  mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
18306}
18307
18308static void
18309do_mve_vqdmladh (void)
18310{
18311  enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18312  struct neon_type_el et
18313    = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18314
18315  if (inst.cond > COND_ALWAYS)
18316    inst.pred_insn_type = INSIDE_VPT_INSN;
18317  else
18318    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18319
18320  mve_encode_qqq (0, et.size);
18321}
18322
18323
18324static void
18325do_mve_vmull (void)
18326{
18327
18328  enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
18329					  NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
18330  if (inst.cond == COND_ALWAYS
18331      && ((unsigned)inst.instruction) == M_MNEM_vmullt)
18332    {
18333
18334      if (rs == NS_QQQ)
18335	{
18336	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18337	    goto neon_vmul;
18338	}
18339      else
18340	goto neon_vmul;
18341    }
18342
18343  constraint (rs != NS_QQQ, BAD_FPU);
18344  struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
18345					    N_SU_32 | N_P8 | N_P16 | N_KEY);
18346
18347  /* We are dealing with MVE's vmullt.  */
18348  if (et.size == 32
18349      && (inst.operands[0].reg == inst.operands[1].reg
18350	  || inst.operands[0].reg == inst.operands[2].reg))
18351    as_tsktsk (BAD_MVE_SRCDEST);
18352
18353  if (inst.cond > COND_ALWAYS)
18354    inst.pred_insn_type = INSIDE_VPT_INSN;
18355  else
18356    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18357
18358  if (et.type == NT_poly)
18359    mve_encode_qqq (neon_logbits (et.size), 64);
18360  else
18361    mve_encode_qqq (et.type == NT_unsigned, et.size);
18362
18363  return;
18364
18365 neon_vmul:
18366  inst.instruction = N_MNEM_vmul;
18367  inst.cond = 0xb;
18368  if (thumb_mode)
18369    inst.pred_insn_type = INSIDE_IT_INSN;
18370  do_neon_mul ();
18371}
18372
18373static void
18374do_mve_vabav (void)
18375{
18376  enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18377
18378  if (rs == NS_NULL)
18379    return;
18380
18381  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18382    return;
18383
18384  struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
18385					    | N_S16 | N_S32 | N_U8 | N_U16
18386					    | N_U32);
18387
18388  if (inst.cond > COND_ALWAYS)
18389    inst.pred_insn_type = INSIDE_VPT_INSN;
18390  else
18391    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18392
18393  mve_encode_rqq (et.type == NT_unsigned, et.size);
18394}
18395
18396static void
18397do_mve_vmladav (void)
18398{
18399  enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18400  struct neon_type_el et = neon_check_type (3, rs,
18401					    N_EQK, N_EQK, N_SU_MVE | N_KEY);
18402
18403  if (et.type == NT_unsigned
18404      && (inst.instruction == M_MNEM_vmladavx
18405	  || inst.instruction == M_MNEM_vmladavax
18406	  || inst.instruction == M_MNEM_vmlsdav
18407	  || inst.instruction == M_MNEM_vmlsdava
18408	  || inst.instruction == M_MNEM_vmlsdavx
18409	  || inst.instruction == M_MNEM_vmlsdavax))
18410    first_error (BAD_SIMD_TYPE);
18411
18412  constraint (inst.operands[2].reg > 14,
18413	      _("MVE vector register in the range [Q0..Q7] expected"));
18414
18415  if (inst.cond > COND_ALWAYS)
18416    inst.pred_insn_type = INSIDE_VPT_INSN;
18417  else
18418    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18419
18420  if (inst.instruction == M_MNEM_vmlsdav
18421      || inst.instruction == M_MNEM_vmlsdava
18422      || inst.instruction == M_MNEM_vmlsdavx
18423      || inst.instruction == M_MNEM_vmlsdavax)
18424    inst.instruction |= (et.size == 8) << 28;
18425  else
18426    inst.instruction |= (et.size == 8) << 8;
18427
18428  mve_encode_rqq (et.type == NT_unsigned, 64);
18429  inst.instruction |= (et.size == 32) << 16;
18430}
18431
18432static void
18433do_mve_vmlaldav (void)
18434{
18435  enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
18436  struct neon_type_el et
18437    = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
18438		       N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
18439
18440  if (et.type == NT_unsigned
18441      && (inst.instruction == M_MNEM_vmlsldav
18442	  || inst.instruction == M_MNEM_vmlsldava
18443	  || inst.instruction == M_MNEM_vmlsldavx
18444	  || inst.instruction == M_MNEM_vmlsldavax))
18445    first_error (BAD_SIMD_TYPE);
18446
18447  if (inst.cond > COND_ALWAYS)
18448    inst.pred_insn_type = INSIDE_VPT_INSN;
18449  else
18450    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18451
18452  mve_encode_rrqq (et.type == NT_unsigned, et.size);
18453}
18454
18455static void
18456do_mve_vrmlaldavh (void)
18457{
18458  struct neon_type_el et;
18459  if (inst.instruction == M_MNEM_vrmlsldavh
18460     || inst.instruction == M_MNEM_vrmlsldavha
18461     || inst.instruction == M_MNEM_vrmlsldavhx
18462     || inst.instruction == M_MNEM_vrmlsldavhax)
18463    {
18464      et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18465      if (inst.operands[1].reg == REG_SP)
18466	as_tsktsk (MVE_BAD_SP);
18467    }
18468  else
18469    {
18470      if (inst.instruction == M_MNEM_vrmlaldavhx
18471	  || inst.instruction == M_MNEM_vrmlaldavhax)
18472	et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18473      else
18474	et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
18475			      N_U32 | N_S32 | N_KEY);
18476      /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18477	 with vmax/min instructions, making the use of SP in assembly really
18478	 nonsensical, so instead of issuing a warning like we do for other uses
18479	 of SP for the odd register operand we error out.  */
18480      constraint (inst.operands[1].reg == REG_SP, BAD_SP);
18481    }
18482
18483  /* Make sure we still check the second operand is an odd one and that PC is
18484     disallowed.  This because we are parsing for any GPR operand, to be able
18485     to distinguish between giving a warning or an error for SP as described
18486     above.  */
18487  constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
18488  constraint (inst.operands[1].reg == REG_PC, BAD_PC);
18489
18490  if (inst.cond > COND_ALWAYS)
18491    inst.pred_insn_type = INSIDE_VPT_INSN;
18492  else
18493    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18494
18495  mve_encode_rrqq (et.type == NT_unsigned, 0);
18496}
18497
18498
18499static void
18500do_mve_vmaxnmv (void)
18501{
18502  enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18503  struct neon_type_el et
18504    = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
18505
18506  if (inst.cond > COND_ALWAYS)
18507    inst.pred_insn_type = INSIDE_VPT_INSN;
18508  else
18509    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18510
18511  if (inst.operands[0].reg == REG_SP)
18512    as_tsktsk (MVE_BAD_SP);
18513  else if (inst.operands[0].reg == REG_PC)
18514    as_tsktsk (MVE_BAD_PC);
18515
18516  mve_encode_rq (et.size == 16, 64);
18517}
18518
18519static void
18520do_mve_vmaxv (void)
18521{
18522  enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18523  struct neon_type_el et;
18524
18525  if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
18526    et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
18527  else
18528    et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18529
18530  if (inst.cond > COND_ALWAYS)
18531    inst.pred_insn_type = INSIDE_VPT_INSN;
18532  else
18533    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18534
18535  if (inst.operands[0].reg == REG_SP)
18536    as_tsktsk (MVE_BAD_SP);
18537  else if (inst.operands[0].reg == REG_PC)
18538    as_tsktsk (MVE_BAD_PC);
18539
18540  mve_encode_rq (et.type == NT_unsigned, et.size);
18541}
18542
18543
18544static void
18545do_neon_qrdmlah (void)
18546{
18547  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
18548   return;
18549  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18550    {
18551      /* Check we're on the correct architecture.  */
18552      if (!mark_feature_used (&fpu_neon_ext_armv8))
18553	inst.error
18554	  = _("instruction form not available on this architecture.");
18555      else if (!mark_feature_used (&fpu_neon_ext_v8_1))
18556	{
18557	  as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18558	  record_feature_use (&fpu_neon_ext_v8_1);
18559	}
18560	if (inst.operands[2].isscalar)
18561	  {
18562	    enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
18563	    struct neon_type_el et = neon_check_type (3, rs,
18564	      N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18565	    NEON_ENCODE (SCALAR, inst);
18566	    neon_mul_mac (et, neon_quad (rs));
18567	  }
18568	else
18569	  {
18570	    enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18571	    struct neon_type_el et = neon_check_type (3, rs,
18572	      N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18573	    NEON_ENCODE (INTEGER, inst);
18574	    /* The U bit (rounding) comes from bit mask.  */
18575	    neon_three_same (neon_quad (rs), 0, et.size);
18576	  }
18577    }
18578  else
18579    {
18580      enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18581      struct neon_type_el et
18582	= neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
18583
18584      NEON_ENCODE (INTEGER, inst);
18585      mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
18586    }
18587}
18588
18589static void
18590do_neon_fcmp_absolute (void)
18591{
18592  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18593  struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18594					    N_F_16_32 | N_KEY);
18595  /* Size field comes from bit mask.  */
18596  neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
18597}
18598
18599static void
18600do_neon_fcmp_absolute_inv (void)
18601{
18602  neon_exchange_operands ();
18603  do_neon_fcmp_absolute ();
18604}
18605
18606static void
18607do_neon_step (void)
18608{
18609  enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18610  struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18611					    N_F_16_32 | N_KEY);
18612  neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
18613}
18614
18615static void
18616do_neon_abs_neg (void)
18617{
18618  enum neon_shape rs;
18619  struct neon_type_el et;
18620
18621  if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
18622    return;
18623
18624  rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
18625  et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
18626
18627  if (!check_simd_pred_availability (et.type == NT_float,
18628				     NEON_CHECK_ARCH | NEON_CHECK_CC))
18629    return;
18630
18631  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18632  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18633  inst.instruction |= LOW4 (inst.operands[1].reg);
18634  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18635  inst.instruction |= neon_quad (rs) << 6;
18636  inst.instruction |= (et.type == NT_float) << 10;
18637  inst.instruction |= neon_logbits (et.size) << 18;
18638
18639  neon_dp_fixup (&inst);
18640}
18641
18642static void
18643do_neon_sli (void)
18644{
18645  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
18646    return;
18647
18648  enum neon_shape rs;
18649  struct neon_type_el et;
18650  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18651    {
18652      rs = neon_select_shape (NS_QQI, NS_NULL);
18653      et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18654    }
18655  else
18656    {
18657      rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18658      et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18659    }
18660
18661
18662  int imm = inst.operands[2].imm;
18663  constraint (imm < 0 || (unsigned)imm >= et.size,
18664	      _("immediate out of range for insert"));
18665  neon_imm_shift (false, 0, neon_quad (rs), et, imm);
18666}
18667
18668static void
18669do_neon_sri (void)
18670{
18671  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
18672    return;
18673
18674  enum neon_shape rs;
18675  struct neon_type_el et;
18676  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18677    {
18678      rs = neon_select_shape (NS_QQI, NS_NULL);
18679      et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18680    }
18681  else
18682    {
18683      rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18684      et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18685    }
18686
18687  int imm = inst.operands[2].imm;
18688  constraint (imm < 1 || (unsigned)imm > et.size,
18689	      _("immediate out of range for insert"));
18690  neon_imm_shift (false, 0, neon_quad (rs), et, et.size - imm);
18691}
18692
18693static void
18694do_neon_qshlu_imm (void)
18695{
18696  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
18697    return;
18698
18699  enum neon_shape rs;
18700  struct neon_type_el et;
18701  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18702    {
18703      rs = neon_select_shape (NS_QQI, NS_NULL);
18704      et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18705    }
18706  else
18707    {
18708      rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18709      et = neon_check_type (2, rs, N_EQK | N_UNS,
18710			    N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
18711    }
18712
18713  int imm = inst.operands[2].imm;
18714  constraint (imm < 0 || (unsigned)imm >= et.size,
18715	      _("immediate out of range for shift"));
18716  /* Only encodes the 'U present' variant of the instruction.
18717     In this case, signed types have OP (bit 8) set to 0.
18718     Unsigned types have OP set to 1.  */
18719  inst.instruction |= (et.type == NT_unsigned) << 8;
18720  /* The rest of the bits are the same as other immediate shifts.  */
18721  neon_imm_shift (false, 0, neon_quad (rs), et, imm);
18722}
18723
18724static void
18725do_neon_qmovn (void)
18726{
18727  struct neon_type_el et = neon_check_type (2, NS_DQ,
18728    N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18729  /* Saturating move where operands can be signed or unsigned, and the
18730     destination has the same signedness.  */
18731  NEON_ENCODE (INTEGER, inst);
18732  if (et.type == NT_unsigned)
18733    inst.instruction |= 0xc0;
18734  else
18735    inst.instruction |= 0x80;
18736  neon_two_same (0, 1, et.size / 2);
18737}
18738
18739static void
18740do_neon_qmovun (void)
18741{
18742  struct neon_type_el et = neon_check_type (2, NS_DQ,
18743    N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18744  /* Saturating move with unsigned results. Operands must be signed.  */
18745  NEON_ENCODE (INTEGER, inst);
18746  neon_two_same (0, 1, et.size / 2);
18747}
18748
18749static void
18750do_neon_rshift_sat_narrow (void)
18751{
18752  /* FIXME: Types for narrowing. If operands are signed, results can be signed
18753     or unsigned. If operands are unsigned, results must also be unsigned.  */
18754  struct neon_type_el et = neon_check_type (2, NS_DQI,
18755    N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18756  int imm = inst.operands[2].imm;
18757  /* This gets the bounds check, size encoding and immediate bits calculation
18758     right.  */
18759  et.size /= 2;
18760
18761  /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18762     VQMOVN.I<size> <Dd>, <Qm>.  */
18763  if (imm == 0)
18764    {
18765      inst.operands[2].present = 0;
18766      inst.instruction = N_MNEM_vqmovn;
18767      do_neon_qmovn ();
18768      return;
18769    }
18770
18771  constraint (imm < 1 || (unsigned)imm > et.size,
18772	      _("immediate out of range"));
18773  neon_imm_shift (true, et.type == NT_unsigned, 0, et, et.size - imm);
18774}
18775
18776static void
18777do_neon_rshift_sat_narrow_u (void)
18778{
18779  /* FIXME: Types for narrowing. If operands are signed, results can be signed
18780     or unsigned. If operands are unsigned, results must also be unsigned.  */
18781  struct neon_type_el et = neon_check_type (2, NS_DQI,
18782    N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18783  int imm = inst.operands[2].imm;
18784  /* This gets the bounds check, size encoding and immediate bits calculation
18785     right.  */
18786  et.size /= 2;
18787
18788  /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18789     VQMOVUN.I<size> <Dd>, <Qm>.  */
18790  if (imm == 0)
18791    {
18792      inst.operands[2].present = 0;
18793      inst.instruction = N_MNEM_vqmovun;
18794      do_neon_qmovun ();
18795      return;
18796    }
18797
18798  constraint (imm < 1 || (unsigned)imm > et.size,
18799	      _("immediate out of range"));
18800  /* FIXME: The manual is kind of unclear about what value U should have in
18801     VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18802     must be 1.  */
18803  neon_imm_shift (true, 1, 0, et, et.size - imm);
18804}
18805
18806static void
18807do_neon_movn (void)
18808{
18809  struct neon_type_el et = neon_check_type (2, NS_DQ,
18810    N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18811  NEON_ENCODE (INTEGER, inst);
18812  neon_two_same (0, 1, et.size / 2);
18813}
18814
18815static void
18816do_neon_rshift_narrow (void)
18817{
18818  struct neon_type_el et = neon_check_type (2, NS_DQI,
18819    N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18820  int imm = inst.operands[2].imm;
18821  /* This gets the bounds check, size encoding and immediate bits calculation
18822     right.  */
18823  et.size /= 2;
18824
18825  /* If immediate is zero then we are a pseudo-instruction for
18826     VMOVN.I<size> <Dd>, <Qm>  */
18827  if (imm == 0)
18828    {
18829      inst.operands[2].present = 0;
18830      inst.instruction = N_MNEM_vmovn;
18831      do_neon_movn ();
18832      return;
18833    }
18834
18835  constraint (imm < 1 || (unsigned)imm > et.size,
18836	      _("immediate out of range for narrowing operation"));
18837  neon_imm_shift (false, 0, 0, et, et.size - imm);
18838}
18839
18840static void
18841do_neon_shll (void)
18842{
18843  /* FIXME: Type checking when lengthening.  */
18844  struct neon_type_el et = neon_check_type (2, NS_QDI,
18845    N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
18846  unsigned imm = inst.operands[2].imm;
18847
18848  if (imm == et.size)
18849    {
18850      /* Maximum shift variant.  */
18851      NEON_ENCODE (INTEGER, inst);
18852      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18853      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18854      inst.instruction |= LOW4 (inst.operands[1].reg);
18855      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18856      inst.instruction |= neon_logbits (et.size) << 18;
18857
18858      neon_dp_fixup (&inst);
18859    }
18860  else
18861    {
18862      /* A more-specific type check for non-max versions.  */
18863      et = neon_check_type (2, NS_QDI,
18864	N_EQK | N_DBL, N_SU_32 | N_KEY);
18865      NEON_ENCODE (IMMED, inst);
18866      neon_imm_shift (true, et.type == NT_unsigned, 0, et, imm);
18867    }
18868}
18869
18870/* Check the various types for the VCVT instruction, and return which version
18871   the current instruction is.  */
18872
18873#define CVT_FLAVOUR_VAR							      \
18874  CVT_VAR (s32_f32, N_S32, N_F32, whole_reg,   "ftosls", "ftosis", "ftosizs") \
18875  CVT_VAR (u32_f32, N_U32, N_F32, whole_reg,   "ftouls", "ftouis", "ftouizs") \
18876  CVT_VAR (f32_s32, N_F32, N_S32, whole_reg,   "fsltos", "fsitos", NULL)      \
18877  CVT_VAR (f32_u32, N_F32, N_U32, whole_reg,   "fultos", "fuitos", NULL)      \
18878  /* Half-precision conversions.  */					      \
18879  CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL)	      \
18880  CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL)	      \
18881  CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL)	      \
18882  CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL)	      \
18883  CVT_VAR (f32_f16, N_F32, N_F16, whole_reg,   NULL,     NULL,     NULL)      \
18884  CVT_VAR (f16_f32, N_F16, N_F32, whole_reg,   NULL,     NULL,     NULL)      \
18885  /* New VCVT instructions introduced by ARMv8.2 fp16 extension.	      \
18886     Compared with single/double precision variants, only the co-processor    \
18887     field is different, so the encoding flow is reused here.  */	      \
18888  CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL)    \
18889  CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL)    \
18890  CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18891  CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18892  CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg,   NULL, NULL, NULL)	      \
18893  /* VFP instructions.  */						      \
18894  CVT_VAR (f32_f64, N_F32, N_F64, N_VFP,       NULL,     "fcvtsd", NULL)      \
18895  CVT_VAR (f64_f32, N_F64, N_F32, N_VFP,       NULL,     "fcvtds", NULL)      \
18896  CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18897  CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18898  CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL)      \
18899  CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL)      \
18900  /* VFP instructions with bitshift.  */				      \
18901  CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL,     NULL)      \
18902  CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL,     NULL)      \
18903  CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL,     NULL)      \
18904  CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL,     NULL)      \
18905  CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL,     NULL)      \
18906  CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL,     NULL)      \
18907  CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL,     NULL)      \
18908  CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL,     NULL)
18909
18910#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18911  neon_cvt_flavour_##C,
18912
18913/* The different types of conversions we can do.  */
18914enum neon_cvt_flavour
18915{
18916  CVT_FLAVOUR_VAR
18917  neon_cvt_flavour_invalid,
18918  neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
18919};
18920
18921#undef CVT_VAR
18922
18923static enum neon_cvt_flavour
18924get_neon_cvt_flavour (enum neon_shape rs)
18925{
18926#define CVT_VAR(C,X,Y,R,BSN,CN,ZN)			\
18927  et = neon_check_type (2, rs, (R) | (X), (R) | (Y));	\
18928  if (et.type != NT_invtype)				\
18929    {							\
18930      inst.error = NULL;				\
18931      return (neon_cvt_flavour_##C);			\
18932    }
18933
18934  struct neon_type_el et;
18935  unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
18936			|| rs == NS_FF) ? N_VFP : 0;
18937  /* The instruction versions which take an immediate take one register
18938     argument, which is extended to the width of the full register. Thus the
18939     "source" and "destination" registers must have the same width.  Hack that
18940     here by making the size equal to the key (wider, in this case) operand.  */
18941  unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
18942
18943  CVT_FLAVOUR_VAR;
18944
18945  return neon_cvt_flavour_invalid;
18946#undef CVT_VAR
18947}
18948
18949enum neon_cvt_mode
18950{
18951  neon_cvt_mode_a,
18952  neon_cvt_mode_n,
18953  neon_cvt_mode_p,
18954  neon_cvt_mode_m,
18955  neon_cvt_mode_z,
18956  neon_cvt_mode_x,
18957  neon_cvt_mode_r
18958};
18959
18960/* Neon-syntax VFP conversions.  */
18961
18962static void
18963do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
18964{
18965  const char *opname = 0;
18966
18967  if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
18968      || rs == NS_FHI || rs == NS_HFI)
18969    {
18970      /* Conversions with immediate bitshift.  */
18971      const char *enc[] =
18972	{
18973#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18974	  CVT_FLAVOUR_VAR
18975	  NULL
18976#undef CVT_VAR
18977	};
18978
18979      if (flavour < (int) ARRAY_SIZE (enc))
18980	{
18981	  opname = enc[flavour];
18982	  constraint (inst.operands[0].reg != inst.operands[1].reg,
18983		      _("operands 0 and 1 must be the same register"));
18984	  inst.operands[1] = inst.operands[2];
18985	  memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
18986	}
18987    }
18988  else
18989    {
18990      /* Conversions without bitshift.  */
18991      const char *enc[] =
18992	{
18993#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18994	  CVT_FLAVOUR_VAR
18995	  NULL
18996#undef CVT_VAR
18997	};
18998
18999      if (flavour < (int) ARRAY_SIZE (enc))
19000	opname = enc[flavour];
19001    }
19002
19003  if (opname)
19004    do_vfp_nsyn_opcode (opname);
19005
19006  /* ARMv8.2 fp16 VCVT instruction.  */
19007  if (flavour == neon_cvt_flavour_s32_f16
19008      || flavour == neon_cvt_flavour_u32_f16
19009      || flavour == neon_cvt_flavour_f16_u32
19010      || flavour == neon_cvt_flavour_f16_s32)
19011    do_scalar_fp16_v82_encode ();
19012}
19013
19014static void
19015do_vfp_nsyn_cvtz (void)
19016{
19017  enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
19018  enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
19019  const char *enc[] =
19020    {
19021#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
19022      CVT_FLAVOUR_VAR
19023      NULL
19024#undef CVT_VAR
19025    };
19026
19027  if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
19028    do_vfp_nsyn_opcode (enc[flavour]);
19029}
19030
19031static void
19032do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
19033		      enum neon_cvt_mode mode)
19034{
19035  int sz, op;
19036  int rm;
19037
19038  /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
19039     D register operands.  */
19040  if (flavour == neon_cvt_flavour_s32_f64
19041      || flavour == neon_cvt_flavour_u32_f64)
19042    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19043		_(BAD_FPU));
19044
19045  if (flavour == neon_cvt_flavour_s32_f16
19046      || flavour == neon_cvt_flavour_u32_f16)
19047    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
19048		_(BAD_FP16));
19049
19050  set_pred_insn_type (OUTSIDE_PRED_INSN);
19051
19052  switch (flavour)
19053    {
19054    case neon_cvt_flavour_s32_f64:
19055      sz = 1;
19056      op = 1;
19057      break;
19058    case neon_cvt_flavour_s32_f32:
19059      sz = 0;
19060      op = 1;
19061      break;
19062    case neon_cvt_flavour_s32_f16:
19063      sz = 0;
19064      op = 1;
19065      break;
19066    case neon_cvt_flavour_u32_f64:
19067      sz = 1;
19068      op = 0;
19069      break;
19070    case neon_cvt_flavour_u32_f32:
19071      sz = 0;
19072      op = 0;
19073      break;
19074    case neon_cvt_flavour_u32_f16:
19075      sz = 0;
19076      op = 0;
19077      break;
19078    default:
19079      first_error (_("invalid instruction shape"));
19080      return;
19081    }
19082
19083  switch (mode)
19084    {
19085    case neon_cvt_mode_a: rm = 0; break;
19086    case neon_cvt_mode_n: rm = 1; break;
19087    case neon_cvt_mode_p: rm = 2; break;
19088    case neon_cvt_mode_m: rm = 3; break;
19089    default: first_error (_("invalid rounding mode")); return;
19090    }
19091
19092  NEON_ENCODE (FPV8, inst);
19093  encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
19094  encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
19095  inst.instruction |= sz << 8;
19096
19097  /* ARMv8.2 fp16 VCVT instruction.  */
19098  if (flavour == neon_cvt_flavour_s32_f16
19099      ||flavour == neon_cvt_flavour_u32_f16)
19100    do_scalar_fp16_v82_encode ();
19101  inst.instruction |= op << 7;
19102  inst.instruction |= rm << 16;
19103  inst.instruction |= 0xf0000000;
19104  inst.is_neon = true;
19105}
19106
19107static void
19108do_neon_cvt_1 (enum neon_cvt_mode mode)
19109{
19110  enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
19111					  NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
19112					  NS_FH, NS_HF, NS_FHI, NS_HFI,
19113					  NS_NULL);
19114  enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
19115
19116  if (flavour == neon_cvt_flavour_invalid)
19117    return;
19118
19119  /* PR11109: Handle round-to-zero for VCVT conversions.  */
19120  if (mode == neon_cvt_mode_z
19121      && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
19122      && (flavour == neon_cvt_flavour_s16_f16
19123	  || flavour == neon_cvt_flavour_u16_f16
19124	  || flavour == neon_cvt_flavour_s32_f32
19125	  || flavour == neon_cvt_flavour_u32_f32
19126	  || flavour == neon_cvt_flavour_s32_f64
19127	  || flavour == neon_cvt_flavour_u32_f64)
19128      && (rs == NS_FD || rs == NS_FF))
19129    {
19130      do_vfp_nsyn_cvtz ();
19131      return;
19132    }
19133
19134  /* ARMv8.2 fp16 VCVT conversions.  */
19135  if (mode == neon_cvt_mode_z
19136      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
19137      && (flavour == neon_cvt_flavour_s32_f16
19138	  || flavour == neon_cvt_flavour_u32_f16)
19139      && (rs == NS_FH))
19140    {
19141      do_vfp_nsyn_cvtz ();
19142      do_scalar_fp16_v82_encode ();
19143      return;
19144    }
19145
19146  if ((rs == NS_FD || rs == NS_QQI) && mode == neon_cvt_mode_n
19147      && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19148    {
19149      /* We are dealing with vcvt with the 'ne' condition.  */
19150      inst.cond = 0x1;
19151      inst.instruction = N_MNEM_vcvt;
19152      do_neon_cvt_1 (neon_cvt_mode_z);
19153      return;
19154    }
19155
19156  /* VFP rather than Neon conversions.  */
19157  if (flavour >= neon_cvt_flavour_first_fp)
19158    {
19159      if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
19160	do_vfp_nsyn_cvt (rs, flavour);
19161      else
19162	do_vfp_nsyn_cvt_fpv8 (flavour, mode);
19163
19164      return;
19165    }
19166
19167  switch (rs)
19168    {
19169    case NS_QQI:
19170      if (mode == neon_cvt_mode_z
19171	  && (flavour == neon_cvt_flavour_f16_s16
19172	      || flavour == neon_cvt_flavour_f16_u16
19173	      || flavour == neon_cvt_flavour_s16_f16
19174	      || flavour == neon_cvt_flavour_u16_f16
19175	      || flavour == neon_cvt_flavour_f32_u32
19176	      || flavour == neon_cvt_flavour_f32_s32
19177	      || flavour == neon_cvt_flavour_s32_f32
19178	      || flavour == neon_cvt_flavour_u32_f32))
19179	{
19180	  if (!check_simd_pred_availability (true,
19181					     NEON_CHECK_CC | NEON_CHECK_ARCH))
19182	    return;
19183	}
19184      /* fall through.  */
19185    case NS_DDI:
19186      {
19187	unsigned immbits;
19188	unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19189			     0x0000100, 0x1000100, 0x0, 0x1000000};
19190
19191	if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19192	    && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19193	    return;
19194
19195	if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19196	  {
19197	    constraint (inst.operands[2].present && inst.operands[2].imm == 0,
19198			_("immediate value out of range"));
19199	    switch (flavour)
19200	      {
19201		case neon_cvt_flavour_f16_s16:
19202		case neon_cvt_flavour_f16_u16:
19203		case neon_cvt_flavour_s16_f16:
19204		case neon_cvt_flavour_u16_f16:
19205		  constraint (inst.operands[2].imm > 16,
19206			      _("immediate value out of range"));
19207		  break;
19208		case neon_cvt_flavour_f32_u32:
19209		case neon_cvt_flavour_f32_s32:
19210		case neon_cvt_flavour_s32_f32:
19211		case neon_cvt_flavour_u32_f32:
19212		  constraint (inst.operands[2].imm > 32,
19213			      _("immediate value out of range"));
19214		  break;
19215		default:
19216		  inst.error = BAD_FPU;
19217		  return;
19218	      }
19219	  }
19220
19221	/* Fixed-point conversion with #0 immediate is encoded as an
19222	   integer conversion.  */
19223	if (inst.operands[2].present && inst.operands[2].imm == 0)
19224	  goto int_encode;
19225	NEON_ENCODE (IMMED, inst);
19226	if (flavour != neon_cvt_flavour_invalid)
19227	  inst.instruction |= enctab[flavour];
19228	inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19229	inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19230	inst.instruction |= LOW4 (inst.operands[1].reg);
19231	inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19232	inst.instruction |= neon_quad (rs) << 6;
19233	inst.instruction |= 1 << 21;
19234	if (flavour < neon_cvt_flavour_s16_f16)
19235	  {
19236	    inst.instruction |= 1 << 21;
19237	    immbits = 32 - inst.operands[2].imm;
19238	    inst.instruction |= immbits << 16;
19239	  }
19240	else
19241	  {
19242	    inst.instruction |= 3 << 20;
19243	    immbits = 16 - inst.operands[2].imm;
19244	    inst.instruction |= immbits << 16;
19245	    inst.instruction &= ~(1 << 9);
19246	  }
19247
19248	neon_dp_fixup (&inst);
19249      }
19250      break;
19251
19252    case NS_QQ:
19253      if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
19254	   || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
19255	  && (flavour == neon_cvt_flavour_s16_f16
19256	      || flavour == neon_cvt_flavour_u16_f16
19257	      || flavour == neon_cvt_flavour_s32_f32
19258	      || flavour == neon_cvt_flavour_u32_f32))
19259	{
19260	  if (!check_simd_pred_availability (true,
19261					     NEON_CHECK_CC | NEON_CHECK_ARCH8))
19262	    return;
19263	}
19264      else if (mode == neon_cvt_mode_z
19265	       && (flavour == neon_cvt_flavour_f16_s16
19266		   || flavour == neon_cvt_flavour_f16_u16
19267		   || flavour == neon_cvt_flavour_s16_f16
19268		   || flavour == neon_cvt_flavour_u16_f16
19269		   || flavour == neon_cvt_flavour_f32_u32
19270		   || flavour == neon_cvt_flavour_f32_s32
19271		   || flavour == neon_cvt_flavour_s32_f32
19272		   || flavour == neon_cvt_flavour_u32_f32))
19273	{
19274	  if (!check_simd_pred_availability (true,
19275					     NEON_CHECK_CC | NEON_CHECK_ARCH))
19276	    return;
19277	}
19278      /* fall through.  */
19279    case NS_DD:
19280      if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
19281	{
19282
19283	  NEON_ENCODE (FLOAT, inst);
19284	  if (!check_simd_pred_availability (true,
19285					     NEON_CHECK_CC | NEON_CHECK_ARCH8))
19286	    return;
19287
19288	  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19289	  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19290	  inst.instruction |= LOW4 (inst.operands[1].reg);
19291	  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19292	  inst.instruction |= neon_quad (rs) << 6;
19293	  inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
19294			       || flavour == neon_cvt_flavour_u32_f32) << 7;
19295	  inst.instruction |= mode << 8;
19296	  if (flavour == neon_cvt_flavour_u16_f16
19297	      || flavour == neon_cvt_flavour_s16_f16)
19298	    /* Mask off the original size bits and reencode them.  */
19299	    inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
19300
19301	  if (thumb_mode)
19302	    inst.instruction |= 0xfc000000;
19303	  else
19304	    inst.instruction |= 0xf0000000;
19305	}
19306      else
19307	{
19308    int_encode:
19309	  {
19310	    unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
19311				  0x100, 0x180, 0x0, 0x080};
19312
19313	    NEON_ENCODE (INTEGER, inst);
19314
19315	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19316	    {
19317	      if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19318		return;
19319	    }
19320
19321	    if (flavour != neon_cvt_flavour_invalid)
19322	      inst.instruction |= enctab[flavour];
19323
19324	    inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19325	    inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19326	    inst.instruction |= LOW4 (inst.operands[1].reg);
19327	    inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19328	    inst.instruction |= neon_quad (rs) << 6;
19329	    if (flavour >= neon_cvt_flavour_s16_f16
19330		&& flavour <= neon_cvt_flavour_f16_u16)
19331	      /* Half precision.  */
19332	      inst.instruction |= 1 << 18;
19333	    else
19334	      inst.instruction |= 2 << 18;
19335
19336	    neon_dp_fixup (&inst);
19337	  }
19338	}
19339      break;
19340
19341    /* Half-precision conversions for Advanced SIMD -- neon.  */
19342    case NS_QD:
19343    case NS_DQ:
19344      if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19345	return;
19346
19347      if ((rs == NS_DQ)
19348	  && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
19349	  {
19350	    as_bad (_("operand size must match register width"));
19351	    break;
19352	  }
19353
19354      if ((rs == NS_QD)
19355	  && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
19356	  {
19357	    as_bad (_("operand size must match register width"));
19358	    break;
19359	  }
19360
19361      if (rs == NS_DQ)
19362	{
19363	  if (flavour == neon_cvt_flavour_bf16_f32)
19364	    {
19365	      if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8) == FAIL)
19366		return;
19367	      constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16));
19368	      /* VCVT.bf16.f32.  */
19369	      inst.instruction = 0x11b60640;
19370	    }
19371	  else
19372	    /* VCVT.f16.f32.  */
19373	    inst.instruction = 0x3b60600;
19374	}
19375      else
19376	/* VCVT.f32.f16.  */
19377	inst.instruction = 0x3b60700;
19378
19379      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19380      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19381      inst.instruction |= LOW4 (inst.operands[1].reg);
19382      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19383      neon_dp_fixup (&inst);
19384      break;
19385
19386    default:
19387      /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32).  */
19388      if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
19389	do_vfp_nsyn_cvt (rs, flavour);
19390      else
19391	do_vfp_nsyn_cvt_fpv8 (flavour, mode);
19392    }
19393}
19394
19395static void
19396do_neon_cvtr (void)
19397{
19398  do_neon_cvt_1 (neon_cvt_mode_x);
19399}
19400
19401static void
19402do_neon_cvt (void)
19403{
19404  do_neon_cvt_1 (neon_cvt_mode_z);
19405}
19406
19407static void
19408do_neon_cvta (void)
19409{
19410  do_neon_cvt_1 (neon_cvt_mode_a);
19411}
19412
19413static void
19414do_neon_cvtn (void)
19415{
19416  do_neon_cvt_1 (neon_cvt_mode_n);
19417}
19418
19419static void
19420do_neon_cvtp (void)
19421{
19422  do_neon_cvt_1 (neon_cvt_mode_p);
19423}
19424
19425static void
19426do_neon_cvtm (void)
19427{
19428  do_neon_cvt_1 (neon_cvt_mode_m);
19429}
19430
19431static void
19432do_neon_cvttb_2 (bool t, bool to, bool is_double)
19433{
19434  if (is_double)
19435    mark_feature_used (&fpu_vfp_ext_armv8);
19436
19437  encode_arm_vfp_reg (inst.operands[0].reg,
19438		      (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
19439  encode_arm_vfp_reg (inst.operands[1].reg,
19440		      (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
19441  inst.instruction |= to ? 0x10000 : 0;
19442  inst.instruction |= t ? 0x80 : 0;
19443  inst.instruction |= is_double ? 0x100 : 0;
19444  do_vfp_cond_or_thumb ();
19445}
19446
19447static void
19448do_neon_cvttb_1 (bool t)
19449{
19450  enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
19451					  NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
19452
19453  if (rs == NS_NULL)
19454    return;
19455  else if (rs == NS_QQ || rs == NS_QQI)
19456    {
19457      int single_to_half = 0;
19458      if (!check_simd_pred_availability (true, NEON_CHECK_ARCH))
19459	return;
19460
19461      enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
19462
19463      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19464	  && (flavour ==  neon_cvt_flavour_u16_f16
19465	      || flavour ==  neon_cvt_flavour_s16_f16
19466	      || flavour ==  neon_cvt_flavour_f16_s16
19467	      || flavour ==  neon_cvt_flavour_f16_u16
19468	      || flavour ==  neon_cvt_flavour_u32_f32
19469	      || flavour ==  neon_cvt_flavour_s32_f32
19470	      || flavour ==  neon_cvt_flavour_f32_s32
19471	      || flavour ==  neon_cvt_flavour_f32_u32))
19472	{
19473	  inst.cond = 0xf;
19474	  inst.instruction = N_MNEM_vcvt;
19475	  set_pred_insn_type (INSIDE_VPT_INSN);
19476	  do_neon_cvt_1 (neon_cvt_mode_z);
19477	  return;
19478	}
19479      else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
19480	single_to_half = 1;
19481      else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
19482	{
19483	  first_error (BAD_FPU);
19484	  return;
19485	}
19486
19487      inst.instruction = 0xee3f0e01;
19488      inst.instruction |= single_to_half << 28;
19489      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19490      inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
19491      inst.instruction |= t << 12;
19492      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19493      inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
19494      inst.is_neon = 1;
19495    }
19496  else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
19497    {
19498      inst.error = NULL;
19499      do_neon_cvttb_2 (t, /*to=*/true, /*is_double=*/false);
19500    }
19501  else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
19502    {
19503      inst.error = NULL;
19504      do_neon_cvttb_2 (t, /*to=*/false, /*is_double=*/false);
19505    }
19506  else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
19507    {
19508      /* The VCVTB and VCVTT instructions with D-register operands
19509         don't work for SP only targets.  */
19510      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19511		  _(BAD_FPU));
19512
19513      inst.error = NULL;
19514      do_neon_cvttb_2 (t, /*to=*/true, /*is_double=*/true);
19515    }
19516  else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
19517    {
19518      /* The VCVTB and VCVTT instructions with D-register operands
19519         don't work for SP only targets.  */
19520      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19521		  _(BAD_FPU));
19522
19523      inst.error = NULL;
19524      do_neon_cvttb_2 (t, /*to=*/false, /*is_double=*/true);
19525    }
19526  else if (neon_check_type (2, rs, N_BF16 | N_VFP, N_F32).type != NT_invtype)
19527    {
19528      constraint (!mark_feature_used (&arm_ext_bf16), _(BAD_BF16));
19529      inst.error = NULL;
19530      inst.instruction |= (1 << 8);
19531      inst.instruction &= ~(1 << 9);
19532      do_neon_cvttb_2 (t, /*to=*/true, /*is_double=*/false);
19533    }
19534  else
19535    return;
19536}
19537
19538static void
19539do_neon_cvtb (void)
19540{
19541  do_neon_cvttb_1 (false);
19542}
19543
19544
19545static void
19546do_neon_cvtt (void)
19547{
19548  do_neon_cvttb_1 (true);
19549}
19550
19551static void
19552neon_move_immediate (void)
19553{
19554  enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
19555  struct neon_type_el et = neon_check_type (2, rs,
19556    N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
19557  unsigned immlo, immhi = 0, immbits;
19558  int op, cmode, float_p;
19559
19560  constraint (et.type == NT_invtype,
19561	      _("operand size must be specified for immediate VMOV"));
19562
19563  /* We start out as an MVN instruction if OP = 1, MOV otherwise.  */
19564  op = (inst.instruction & (1 << 5)) != 0;
19565
19566  immlo = inst.operands[1].imm;
19567  if (inst.operands[1].regisimm)
19568    immhi = inst.operands[1].reg;
19569
19570  constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
19571	      _("immediate has bits set outside the operand size"));
19572
19573  float_p = inst.operands[1].immisfloat;
19574
19575  if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
19576					et.size, et.type)) == FAIL)
19577    {
19578      /* Invert relevant bits only.  */
19579      neon_invert_size (&immlo, &immhi, et.size);
19580      /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19581	 with one or the other; those cases are caught by
19582	 neon_cmode_for_move_imm.  */
19583      op = !op;
19584      if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
19585					    &op, et.size, et.type)) == FAIL)
19586	{
19587	  first_error (_("immediate out of range"));
19588	  return;
19589	}
19590    }
19591
19592  inst.instruction &= ~(1 << 5);
19593  inst.instruction |= op << 5;
19594
19595  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19596  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19597  inst.instruction |= neon_quad (rs) << 6;
19598  inst.instruction |= cmode << 8;
19599
19600  neon_write_immbits (immbits);
19601}
19602
19603static void
19604do_neon_mvn (void)
19605{
19606  if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
19607    return;
19608
19609  if (inst.operands[1].isreg)
19610    {
19611      enum neon_shape rs;
19612      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19613	rs = neon_select_shape (NS_QQ, NS_NULL);
19614      else
19615	rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19616
19617      if (rs == NS_NULL)
19618	return;
19619
19620      NEON_ENCODE (INTEGER, inst);
19621      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19622      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19623      inst.instruction |= LOW4 (inst.operands[1].reg);
19624      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19625      inst.instruction |= neon_quad (rs) << 6;
19626    }
19627  else
19628    {
19629      NEON_ENCODE (IMMED, inst);
19630      neon_move_immediate ();
19631    }
19632
19633  neon_dp_fixup (&inst);
19634
19635  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19636    {
19637      constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
19638    }
19639}
19640
19641/* Encode instructions of form:
19642
19643  |28/24|23|22|21 20|19 16|15 12|11    8|7|6|5|4|3  0|
19644  |  U  |x |D |size | Rn  | Rd  |x x x x|N|x|M|x| Rm |  */
19645
19646static void
19647neon_mixed_length (struct neon_type_el et, unsigned size)
19648{
19649  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19650  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19651  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19652  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19653  inst.instruction |= LOW4 (inst.operands[2].reg);
19654  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19655  inst.instruction |= (et.type == NT_unsigned) << 24;
19656  inst.instruction |= neon_logbits (size) << 20;
19657
19658  neon_dp_fixup (&inst);
19659}
19660
19661static void
19662do_neon_dyadic_long (void)
19663{
19664  enum neon_shape rs = neon_select_shape (NS_QDD, NS_HHH, NS_FFF, NS_DDD, NS_NULL);
19665  if (rs == NS_QDD)
19666    {
19667      if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
19668	return;
19669
19670      NEON_ENCODE (INTEGER, inst);
19671      /* FIXME: Type checking for lengthening op.  */
19672      struct neon_type_el et = neon_check_type (3, NS_QDD,
19673	N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
19674      neon_mixed_length (et, et.size);
19675    }
19676  else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19677	   && (inst.cond == 0xf || inst.cond == 0x10))
19678    {
19679      /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19680	 in an IT block with le/lt conditions.  */
19681
19682      if (inst.cond == 0xf)
19683	inst.cond = 0xb;
19684      else if (inst.cond == 0x10)
19685	inst.cond = 0xd;
19686
19687      inst.pred_insn_type = INSIDE_IT_INSN;
19688
19689      if (inst.instruction == N_MNEM_vaddl)
19690	{
19691	  inst.instruction = N_MNEM_vadd;
19692	  do_neon_addsub_if_i ();
19693	}
19694      else if (inst.instruction == N_MNEM_vsubl)
19695	{
19696	  inst.instruction = N_MNEM_vsub;
19697	  do_neon_addsub_if_i ();
19698	}
19699      else if (inst.instruction == N_MNEM_vabdl)
19700	{
19701	  inst.instruction = N_MNEM_vabd;
19702	  do_neon_dyadic_if_su ();
19703	}
19704    }
19705  else
19706    first_error (BAD_FPU);
19707}
19708
19709static void
19710do_neon_abal (void)
19711{
19712  struct neon_type_el et = neon_check_type (3, NS_QDD,
19713    N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
19714  neon_mixed_length (et, et.size);
19715}
19716
19717static void
19718neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
19719{
19720  if (inst.operands[2].isscalar)
19721    {
19722      struct neon_type_el et = neon_check_type (3, NS_QDS,
19723	N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
19724      NEON_ENCODE (SCALAR, inst);
19725      neon_mul_mac (et, et.type == NT_unsigned);
19726    }
19727  else
19728    {
19729      struct neon_type_el et = neon_check_type (3, NS_QDD,
19730	N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
19731      NEON_ENCODE (INTEGER, inst);
19732      neon_mixed_length (et, et.size);
19733    }
19734}
19735
19736static void
19737do_neon_mac_maybe_scalar_long (void)
19738{
19739  neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
19740}
19741
19742/* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19743   internal SCALAR.  QUAD_P is 1 if it's for Q format, otherwise it's 0.  */
19744
19745static unsigned
19746neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
19747{
19748  unsigned regno = NEON_SCALAR_REG (scalar);
19749  unsigned elno = NEON_SCALAR_INDEX (scalar);
19750
19751  if (quad_p)
19752    {
19753      if (regno > 7 || elno > 3)
19754	goto bad_scalar;
19755
19756      return ((regno & 0x7)
19757	      | ((elno & 0x1) << 3)
19758	      | (((elno >> 1) & 0x1) << 5));
19759    }
19760  else
19761    {
19762      if (regno > 15 || elno > 1)
19763	goto bad_scalar;
19764
19765      return (((regno & 0x1) << 5)
19766	      | ((regno >> 1) & 0x7)
19767	      | ((elno & 0x1) << 3));
19768    }
19769
19770 bad_scalar:
19771  first_error (_("scalar out of range for multiply instruction"));
19772  return 0;
19773}
19774
19775static void
19776do_neon_fmac_maybe_scalar_long (int subtype)
19777{
19778  enum neon_shape rs;
19779  int high8;
19780  /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding.  'size"
19781     field (bits[21:20]) has different meaning.  For scalar index variant, it's
19782     used to differentiate add and subtract, otherwise it's with fixed value
19783     0x2.  */
19784  int size = -1;
19785
19786  /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19787     be a scalar index register.  */
19788  if (inst.operands[2].isscalar)
19789    {
19790      high8 = 0xfe000000;
19791      if (subtype)
19792	size = 16;
19793      rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
19794    }
19795  else
19796    {
19797      high8 = 0xfc000000;
19798      size = 32;
19799      if (subtype)
19800	inst.instruction |= (0x1 << 23);
19801      rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
19802    }
19803
19804
19805  if (inst.cond != COND_ALWAYS)
19806    as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19807	       "behaviour is UNPREDICTABLE"));
19808
19809  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
19810	      _(BAD_FP16));
19811
19812  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
19813	      _(BAD_FPU));
19814
19815  /* "opcode" from template has included "ubit", so simply pass 0 here.  Also,
19816     the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19817     so we simply pass -1 as size.  */
19818  unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
19819  neon_three_same (quad_p, 0, size);
19820
19821  /* Undo neon_dp_fixup.  Redo the high eight bits.  */
19822  inst.instruction &= 0x00ffffff;
19823  inst.instruction |= high8;
19824
19825  /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19826     whether the instruction is in Q form and whether Vm is a scalar indexed
19827     operand.  */
19828  if (inst.operands[2].isscalar)
19829    {
19830      unsigned rm
19831	= neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
19832      inst.instruction &= 0xffffffd0;
19833      inst.instruction |= rm;
19834
19835      if (!quad_p)
19836	{
19837	  /* Redo Rn as well.  */
19838	  inst.instruction &= 0xfff0ff7f;
19839	  inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19840	  inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19841	}
19842    }
19843  else if (!quad_p)
19844    {
19845      /* Redo Rn and Rm.  */
19846      inst.instruction &= 0xfff0ff50;
19847      inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19848      inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19849      inst.instruction |= HI4 (inst.operands[2].reg);
19850      inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
19851    }
19852}
19853
19854static void
19855do_neon_vfmal (void)
19856{
19857  return do_neon_fmac_maybe_scalar_long (0);
19858}
19859
19860static void
19861do_neon_vfmsl (void)
19862{
19863  return do_neon_fmac_maybe_scalar_long (1);
19864}
19865
19866static void
19867do_neon_dyadic_wide (void)
19868{
19869  struct neon_type_el et = neon_check_type (3, NS_QQD,
19870    N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
19871  neon_mixed_length (et, et.size);
19872}
19873
19874static void
19875do_neon_dyadic_narrow (void)
19876{
19877  struct neon_type_el et = neon_check_type (3, NS_QDD,
19878    N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
19879  /* Operand sign is unimportant, and the U bit is part of the opcode,
19880     so force the operand type to integer.  */
19881  et.type = NT_integer;
19882  neon_mixed_length (et, et.size / 2);
19883}
19884
19885static void
19886do_neon_mul_sat_scalar_long (void)
19887{
19888  neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
19889}
19890
19891static void
19892do_neon_vmull (void)
19893{
19894  if (inst.operands[2].isscalar)
19895    do_neon_mac_maybe_scalar_long ();
19896  else
19897    {
19898      struct neon_type_el et = neon_check_type (3, NS_QDD,
19899	N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
19900
19901      if (et.type == NT_poly)
19902	NEON_ENCODE (POLY, inst);
19903      else
19904	NEON_ENCODE (INTEGER, inst);
19905
19906      /* For polynomial encoding the U bit must be zero, and the size must
19907	 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19908	 obviously, as 0b10).  */
19909      if (et.size == 64)
19910	{
19911	  /* Check we're on the correct architecture.  */
19912	  if (!mark_feature_used (&fpu_crypto_ext_armv8))
19913	    inst.error =
19914	      _("Instruction form not available on this architecture.");
19915
19916	  et.size = 32;
19917	}
19918
19919      neon_mixed_length (et, et.size);
19920    }
19921}
19922
19923static void
19924do_neon_ext (void)
19925{
19926  enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
19927  struct neon_type_el et = neon_check_type (3, rs,
19928    N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
19929  unsigned imm = (inst.operands[3].imm * et.size) / 8;
19930
19931  constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
19932	      _("shift out of range"));
19933  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19934  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19935  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19936  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19937  inst.instruction |= LOW4 (inst.operands[2].reg);
19938  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19939  inst.instruction |= neon_quad (rs) << 6;
19940  inst.instruction |= imm << 8;
19941
19942  neon_dp_fixup (&inst);
19943}
19944
19945static void
19946do_neon_rev (void)
19947{
19948  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
19949   return;
19950
19951  enum neon_shape rs;
19952  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19953    rs = neon_select_shape (NS_QQ, NS_NULL);
19954  else
19955    rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19956
19957  struct neon_type_el et = neon_check_type (2, rs,
19958    N_EQK, N_8 | N_16 | N_32 | N_KEY);
19959
19960  unsigned op = (inst.instruction >> 7) & 3;
19961  /* N (width of reversed regions) is encoded as part of the bitmask. We
19962     extract it here to check the elements to be reversed are smaller.
19963     Otherwise we'd get a reserved instruction.  */
19964  unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
19965
19966  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64
19967      && inst.operands[0].reg == inst.operands[1].reg)
19968    as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19969		 " operands makes instruction UNPREDICTABLE"));
19970
19971  gas_assert (elsize != 0);
19972  constraint (et.size >= elsize,
19973	      _("elements must be smaller than reversal region"));
19974  neon_two_same (neon_quad (rs), 1, et.size);
19975}
19976
19977static void
19978do_neon_dup (void)
19979{
19980  if (inst.operands[1].isscalar)
19981    {
19982      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19983		  BAD_FPU);
19984      enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
19985      struct neon_type_el et = neon_check_type (2, rs,
19986	N_EQK, N_8 | N_16 | N_32 | N_KEY);
19987      unsigned sizebits = et.size >> 3;
19988      unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
19989      int logsize = neon_logbits (et.size);
19990      unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
19991
19992      if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
19993	return;
19994
19995      NEON_ENCODE (SCALAR, inst);
19996      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19997      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19998      inst.instruction |= LOW4 (dm);
19999      inst.instruction |= HI1 (dm) << 5;
20000      inst.instruction |= neon_quad (rs) << 6;
20001      inst.instruction |= x << 17;
20002      inst.instruction |= sizebits << 16;
20003
20004      neon_dp_fixup (&inst);
20005    }
20006  else
20007    {
20008      enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
20009      struct neon_type_el et = neon_check_type (2, rs,
20010	N_8 | N_16 | N_32 | N_KEY, N_EQK);
20011      if (rs == NS_QR)
20012	{
20013	  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH))
20014	    return;
20015	}
20016      else
20017	constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
20018		    BAD_FPU);
20019
20020      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20021	{
20022	  if (inst.operands[1].reg == REG_SP)
20023	    as_tsktsk (MVE_BAD_SP);
20024	  else if (inst.operands[1].reg == REG_PC)
20025	    as_tsktsk (MVE_BAD_PC);
20026	}
20027
20028      /* Duplicate ARM register to lanes of vector.  */
20029      NEON_ENCODE (ARMREG, inst);
20030      switch (et.size)
20031	{
20032	case 8:  inst.instruction |= 0x400000; break;
20033	case 16: inst.instruction |= 0x000020; break;
20034	case 32: inst.instruction |= 0x000000; break;
20035	default: break;
20036	}
20037      inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20038      inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
20039      inst.instruction |= HI1 (inst.operands[0].reg) << 7;
20040      inst.instruction |= neon_quad (rs) << 21;
20041      /* The encoding for this instruction is identical for the ARM and Thumb
20042	 variants, except for the condition field.  */
20043      do_vfp_cond_or_thumb ();
20044    }
20045}
20046
20047static void
20048do_mve_mov (int toQ)
20049{
20050  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20051    return;
20052  if (inst.cond > COND_ALWAYS)
20053    inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
20054
20055  unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
20056  if (toQ)
20057    {
20058      Q0 = 0;
20059      Q1 = 1;
20060      Rt = 2;
20061      Rt2 = 3;
20062    }
20063
20064  constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
20065	      _("Index one must be [2,3] and index two must be two less than"
20066		" index one."));
20067  constraint (!toQ && inst.operands[Rt].reg == inst.operands[Rt2].reg,
20068	      _("Destination registers may not be the same"));
20069  constraint (inst.operands[Rt].reg == REG_SP
20070	      || inst.operands[Rt2].reg == REG_SP,
20071	      BAD_SP);
20072  constraint (inst.operands[Rt].reg == REG_PC
20073	      || inst.operands[Rt2].reg == REG_PC,
20074	      BAD_PC);
20075
20076  inst.instruction = 0xec000f00;
20077  inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
20078  inst.instruction |= !!toQ << 20;
20079  inst.instruction |= inst.operands[Rt2].reg << 16;
20080  inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
20081  inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
20082  inst.instruction |= inst.operands[Rt].reg;
20083}
20084
20085static void
20086do_mve_movn (void)
20087{
20088  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20089    return;
20090
20091  if (inst.cond > COND_ALWAYS)
20092    inst.pred_insn_type = INSIDE_VPT_INSN;
20093  else
20094    inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
20095
20096  struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32
20097					    | N_KEY);
20098
20099  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20100  inst.instruction |= (neon_logbits (et.size) - 1) << 18;
20101  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20102  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20103  inst.instruction |= LOW4 (inst.operands[1].reg);
20104  inst.is_neon = 1;
20105
20106}
20107
20108/* VMOV has particularly many variations. It can be one of:
20109     0. VMOV<c><q> <Qd>, <Qm>
20110     1. VMOV<c><q> <Dd>, <Dm>
20111   (Register operations, which are VORR with Rm = Rn.)
20112     2. VMOV<c><q>.<dt> <Qd>, #<imm>
20113     3. VMOV<c><q>.<dt> <Dd>, #<imm>
20114   (Immediate loads.)
20115     4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20116   (ARM register to scalar.)
20117     5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20118   (Two ARM registers to vector.)
20119     6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20120   (Scalar to ARM register.)
20121     7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20122   (Vector to two ARM registers.)
20123     8. VMOV.F32 <Sd>, <Sm>
20124     9. VMOV.F64 <Dd>, <Dm>
20125   (VFP register moves.)
20126    10. VMOV.F32 <Sd>, #imm
20127    11. VMOV.F64 <Dd>, #imm
20128   (VFP float immediate load.)
20129    12. VMOV <Rd>, <Sm>
20130   (VFP single to ARM reg.)
20131    13. VMOV <Sd>, <Rm>
20132   (ARM reg to VFP single.)
20133    14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20134   (Two ARM regs to two VFP singles.)
20135    15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20136   (Two VFP singles to two ARM regs.)
20137   16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20138   17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20139   18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20140   19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20141
20142   These cases can be disambiguated using neon_select_shape, except cases 1/9
20143   and 3/11 which depend on the operand type too.
20144
20145   All the encoded bits are hardcoded by this function.
20146
20147   Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20148   Cases 5, 7 may be used with VFPv2 and above.
20149
20150   FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20151   can specify a type where it doesn't make sense to, and is ignored).  */
20152
20153static void
20154do_neon_mov (void)
20155{
20156  enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR,
20157					  NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI,
20158					  NS_DI, NS_SR, NS_RS, NS_FF, NS_FI,
20159					  NS_RF, NS_FR, NS_HR, NS_RH, NS_HI,
20160					  NS_NULL);
20161  struct neon_type_el et;
20162  const char *ldconst = 0;
20163
20164  switch (rs)
20165    {
20166    case NS_DD:  /* case 1/9.  */
20167      et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
20168      /* It is not an error here if no type is given.  */
20169      inst.error = NULL;
20170
20171      /* In MVE we interpret the following instructions as same, so ignoring
20172	 the following type (float) and size (64) checks.
20173	 a: VMOV<c><q> <Dd>, <Dm>
20174	 b: VMOV<c><q>.F64 <Dd>, <Dm>.  */
20175      if ((et.type == NT_float && et.size == 64)
20176	  || (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
20177	{
20178	  do_vfp_nsyn_opcode ("fcpyd");
20179	  break;
20180	}
20181      /* fall through.  */
20182
20183    case NS_QQ:  /* case 0/1.  */
20184      {
20185	if (!check_simd_pred_availability (false,
20186					   NEON_CHECK_CC | NEON_CHECK_ARCH))
20187	  return;
20188	/* The architecture manual I have doesn't explicitly state which
20189	   value the U bit should have for register->register moves, but
20190	   the equivalent VORR instruction has U = 0, so do that.  */
20191	inst.instruction = 0x0200110;
20192	inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20193	inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20194	inst.instruction |= LOW4 (inst.operands[1].reg);
20195	inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20196	inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20197	inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20198	inst.instruction |= neon_quad (rs) << 6;
20199
20200	neon_dp_fixup (&inst);
20201      }
20202      break;
20203
20204    case NS_DI:  /* case 3/11.  */
20205      et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
20206      inst.error = NULL;
20207      if (et.type == NT_float && et.size == 64)
20208	{
20209	  /* case 11 (fconstd).  */
20210	  ldconst = "fconstd";
20211	  goto encode_fconstd;
20212	}
20213      /* fall through.  */
20214
20215    case NS_QI:  /* case 2/3.  */
20216      if (!check_simd_pred_availability (false,
20217					 NEON_CHECK_CC | NEON_CHECK_ARCH))
20218	return;
20219      inst.instruction = 0x0800010;
20220      neon_move_immediate ();
20221      neon_dp_fixup (&inst);
20222      break;
20223
20224    case NS_SR:  /* case 4.  */
20225      {
20226	unsigned bcdebits = 0;
20227	int logsize;
20228	unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
20229	unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
20230
20231	/* .<size> is optional here, defaulting to .32. */
20232	if (inst.vectype.elems == 0
20233	    && inst.operands[0].vectype.type == NT_invtype
20234	    && inst.operands[1].vectype.type == NT_invtype)
20235	  {
20236	    inst.vectype.el[0].type = NT_untyped;
20237	    inst.vectype.el[0].size = 32;
20238	    inst.vectype.elems = 1;
20239	  }
20240
20241	et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
20242	logsize = neon_logbits (et.size);
20243
20244	if (et.size != 32)
20245	  {
20246	    if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20247		&& vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL)
20248	      return;
20249	  }
20250	else
20251	  {
20252	    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
20253			&& !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20254			_(BAD_FPU));
20255	  }
20256
20257	if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20258	  {
20259	    if (inst.operands[1].reg == REG_SP)
20260	      as_tsktsk (MVE_BAD_SP);
20261	    else if (inst.operands[1].reg == REG_PC)
20262	      as_tsktsk (MVE_BAD_PC);
20263	  }
20264	unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
20265
20266	constraint (et.type == NT_invtype, _("bad type for scalar"));
20267	constraint (x >= size / et.size, _("scalar index out of range"));
20268
20269
20270	switch (et.size)
20271	  {
20272	  case 8:  bcdebits = 0x8; break;
20273	  case 16: bcdebits = 0x1; break;
20274	  case 32: bcdebits = 0x0; break;
20275	  default: ;
20276	  }
20277
20278	bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
20279
20280	inst.instruction = 0xe000b10;
20281	do_vfp_cond_or_thumb ();
20282	inst.instruction |= LOW4 (dn) << 16;
20283	inst.instruction |= HI1 (dn) << 7;
20284	inst.instruction |= inst.operands[1].reg << 12;
20285	inst.instruction |= (bcdebits & 3) << 5;
20286	inst.instruction |= ((bcdebits >> 2) & 3) << 21;
20287	inst.instruction |= (x >> (3-logsize)) << 16;
20288      }
20289      break;
20290
20291    case NS_DRR:  /* case 5 (fmdrr).  */
20292      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20293		  && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20294		  _(BAD_FPU));
20295
20296      inst.instruction = 0xc400b10;
20297      do_vfp_cond_or_thumb ();
20298      inst.instruction |= LOW4 (inst.operands[0].reg);
20299      inst.instruction |= HI1 (inst.operands[0].reg) << 5;
20300      inst.instruction |= inst.operands[1].reg << 12;
20301      inst.instruction |= inst.operands[2].reg << 16;
20302      break;
20303
20304    case NS_RS:  /* case 6.  */
20305      {
20306	unsigned logsize;
20307	unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
20308	unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
20309	unsigned abcdebits = 0;
20310
20311	/* .<dt> is optional here, defaulting to .32. */
20312	if (inst.vectype.elems == 0
20313	    && inst.operands[0].vectype.type == NT_invtype
20314	    && inst.operands[1].vectype.type == NT_invtype)
20315	  {
20316	    inst.vectype.el[0].type = NT_untyped;
20317	    inst.vectype.el[0].size = 32;
20318	    inst.vectype.elems = 1;
20319	  }
20320
20321	et = neon_check_type (2, NS_NULL,
20322			      N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
20323	logsize = neon_logbits (et.size);
20324
20325	if (et.size != 32)
20326	  {
20327	    if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20328		&& vfp_or_neon_is_neon (NEON_CHECK_CC
20329					| NEON_CHECK_ARCH) == FAIL)
20330	      return;
20331	  }
20332	else
20333	  {
20334	    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
20335			&& !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20336			_(BAD_FPU));
20337	  }
20338
20339	if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20340	  {
20341	    if (inst.operands[0].reg == REG_SP)
20342	      as_tsktsk (MVE_BAD_SP);
20343	    else if (inst.operands[0].reg == REG_PC)
20344	      as_tsktsk (MVE_BAD_PC);
20345	  }
20346
20347	unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
20348
20349	constraint (et.type == NT_invtype, _("bad type for scalar"));
20350	constraint (x >= size / et.size, _("scalar index out of range"));
20351
20352	switch (et.size)
20353	  {
20354	  case 8:  abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
20355	  case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
20356	  case 32: abcdebits = 0x00; break;
20357	  default: ;
20358	  }
20359
20360	abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
20361	inst.instruction = 0xe100b10;
20362	do_vfp_cond_or_thumb ();
20363	inst.instruction |= LOW4 (dn) << 16;
20364	inst.instruction |= HI1 (dn) << 7;
20365	inst.instruction |= inst.operands[0].reg << 12;
20366	inst.instruction |= (abcdebits & 3) << 5;
20367	inst.instruction |= (abcdebits >> 2) << 21;
20368	inst.instruction |= (x >> (3-logsize)) << 16;
20369      }
20370      break;
20371
20372    case NS_RRD:  /* case 7 (fmrrd).  */
20373      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20374		  && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20375		  _(BAD_FPU));
20376
20377      inst.instruction = 0xc500b10;
20378      do_vfp_cond_or_thumb ();
20379      inst.instruction |= inst.operands[0].reg << 12;
20380      inst.instruction |= inst.operands[1].reg << 16;
20381      inst.instruction |= LOW4 (inst.operands[2].reg);
20382      inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20383      break;
20384
20385    case NS_FF:  /* case 8 (fcpys).  */
20386      do_vfp_nsyn_opcode ("fcpys");
20387      break;
20388
20389    case NS_HI:
20390    case NS_FI:  /* case 10 (fconsts).  */
20391      ldconst = "fconsts";
20392    encode_fconstd:
20393      if (!inst.operands[1].immisfloat)
20394	{
20395	  unsigned new_imm;
20396	  /* Immediate has to fit in 8 bits so float is enough.  */
20397	  float imm = (float) inst.operands[1].imm;
20398	  memcpy (&new_imm, &imm, sizeof (float));
20399	  /* But the assembly may have been written to provide an integer
20400	     bit pattern that equates to a float, so check that the
20401	     conversion has worked.  */
20402	  if (is_quarter_float (new_imm))
20403	    {
20404	      if (is_quarter_float (inst.operands[1].imm))
20405		as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20406
20407	      inst.operands[1].imm = new_imm;
20408	      inst.operands[1].immisfloat = 1;
20409	    }
20410	}
20411
20412      if (is_quarter_float (inst.operands[1].imm))
20413	{
20414	  inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
20415	  do_vfp_nsyn_opcode (ldconst);
20416
20417	  /* ARMv8.2 fp16 vmov.f16 instruction.  */
20418	  if (rs == NS_HI)
20419	    do_scalar_fp16_v82_encode ();
20420	}
20421      else
20422	first_error (_("immediate out of range"));
20423      break;
20424
20425    case NS_RH:
20426    case NS_RF:  /* case 12 (fmrs).  */
20427      do_vfp_nsyn_opcode ("fmrs");
20428      /* ARMv8.2 fp16 vmov.f16 instruction.  */
20429      if (rs == NS_RH)
20430	do_scalar_fp16_v82_encode ();
20431      break;
20432
20433    case NS_HR:
20434    case NS_FR:  /* case 13 (fmsr).  */
20435      do_vfp_nsyn_opcode ("fmsr");
20436      /* ARMv8.2 fp16 vmov.f16 instruction.  */
20437      if (rs == NS_HR)
20438	do_scalar_fp16_v82_encode ();
20439      break;
20440
20441    case NS_RRSS:
20442      do_mve_mov (0);
20443      break;
20444    case NS_SSRR:
20445      do_mve_mov (1);
20446      break;
20447
20448    /* The encoders for the fmrrs and fmsrr instructions expect three operands
20449       (one of which is a list), but we have parsed four.  Do some fiddling to
20450       make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20451       expect.  */
20452    case NS_RRFF:  /* case 14 (fmrrs).  */
20453      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20454		  && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20455		  _(BAD_FPU));
20456      constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
20457		  _("VFP registers must be adjacent"));
20458      inst.operands[2].imm = 2;
20459      memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20460      do_vfp_nsyn_opcode ("fmrrs");
20461      break;
20462
20463    case NS_FFRR:  /* case 15 (fmsrr).  */
20464      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20465		  && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20466		  _(BAD_FPU));
20467      constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
20468		  _("VFP registers must be adjacent"));
20469      inst.operands[1] = inst.operands[2];
20470      inst.operands[2] = inst.operands[3];
20471      inst.operands[0].imm = 2;
20472      memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20473      do_vfp_nsyn_opcode ("fmsrr");
20474      break;
20475
20476    case NS_NULL:
20477      /* neon_select_shape has determined that the instruction
20478	 shape is wrong and has already set the error message.  */
20479      break;
20480
20481    default:
20482      abort ();
20483    }
20484}
20485
20486static void
20487do_mve_movl (void)
20488{
20489  if (!(inst.operands[0].present && inst.operands[0].isquad
20490      && inst.operands[1].present && inst.operands[1].isquad
20491      && !inst.operands[2].present))
20492    {
20493      inst.instruction = 0;
20494      inst.cond = 0xb;
20495      if (thumb_mode)
20496	set_pred_insn_type (INSIDE_IT_INSN);
20497      do_neon_mov ();
20498      return;
20499    }
20500
20501  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20502    return;
20503
20504  if (inst.cond != COND_ALWAYS)
20505    inst.pred_insn_type = INSIDE_VPT_INSN;
20506
20507  struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8
20508					    | N_S16 | N_U16 | N_KEY);
20509
20510  inst.instruction |= (et.type == NT_unsigned) << 28;
20511  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20512  inst.instruction |= (neon_logbits (et.size) + 1) << 19;
20513  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20514  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20515  inst.instruction |= LOW4 (inst.operands[1].reg);
20516  inst.is_neon = 1;
20517}
20518
20519static void
20520do_neon_rshift_round_imm (void)
20521{
20522  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
20523   return;
20524
20525  enum neon_shape rs;
20526  struct neon_type_el et;
20527
20528  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20529    {
20530      rs = neon_select_shape (NS_QQI, NS_NULL);
20531      et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
20532    }
20533  else
20534    {
20535      rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
20536      et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
20537    }
20538  int imm = inst.operands[2].imm;
20539
20540  /* imm == 0 case is encoded as VMOV for V{R}SHR.  */
20541  if (imm == 0)
20542    {
20543      inst.operands[2].present = 0;
20544      do_neon_mov ();
20545      return;
20546    }
20547
20548  constraint (imm < 1 || (unsigned)imm > et.size,
20549	      _("immediate out of range for shift"));
20550  neon_imm_shift (true, et.type == NT_unsigned, neon_quad (rs), et,
20551		  et.size - imm);
20552}
20553
20554static void
20555do_neon_movhf (void)
20556{
20557  enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
20558  constraint (rs != NS_HH, _("invalid suffix"));
20559
20560  if (inst.cond != COND_ALWAYS)
20561    {
20562      if (thumb_mode)
20563	{
20564	  as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20565		     " the behaviour is UNPREDICTABLE"));
20566	}
20567      else
20568	{
20569	  inst.error = BAD_COND;
20570	  return;
20571	}
20572    }
20573
20574  do_vfp_sp_monadic ();
20575
20576  inst.is_neon = 1;
20577  inst.instruction |= 0xf0000000;
20578}
20579
20580static void
20581do_neon_movl (void)
20582{
20583  struct neon_type_el et = neon_check_type (2, NS_QD,
20584    N_EQK | N_DBL, N_SU_32 | N_KEY);
20585  unsigned sizebits = et.size >> 3;
20586  inst.instruction |= sizebits << 19;
20587  neon_two_same (0, et.type == NT_unsigned, -1);
20588}
20589
20590static void
20591do_neon_trn (void)
20592{
20593  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20594  struct neon_type_el et = neon_check_type (2, rs,
20595    N_EQK, N_8 | N_16 | N_32 | N_KEY);
20596  NEON_ENCODE (INTEGER, inst);
20597  neon_two_same (neon_quad (rs), 1, et.size);
20598}
20599
20600static void
20601do_neon_zip_uzp (void)
20602{
20603  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20604  struct neon_type_el et = neon_check_type (2, rs,
20605    N_EQK, N_8 | N_16 | N_32 | N_KEY);
20606  if (rs == NS_DD && et.size == 32)
20607    {
20608      /* Special case: encode as VTRN.32 <Dd>, <Dm>.  */
20609      inst.instruction = N_MNEM_vtrn;
20610      do_neon_trn ();
20611      return;
20612    }
20613  neon_two_same (neon_quad (rs), 1, et.size);
20614}
20615
20616static void
20617do_neon_sat_abs_neg (void)
20618{
20619  if (!check_simd_pred_availability (false, NEON_CHECK_CC | NEON_CHECK_ARCH))
20620    return;
20621
20622  enum neon_shape rs;
20623  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20624    rs = neon_select_shape (NS_QQ, NS_NULL);
20625  else
20626    rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20627  struct neon_type_el et = neon_check_type (2, rs,
20628    N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
20629  neon_two_same (neon_quad (rs), 1, et.size);
20630}
20631
20632static void
20633do_neon_pair_long (void)
20634{
20635  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20636  struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
20637  /* Unsigned is encoded in OP field (bit 7) for these instruction.  */
20638  inst.instruction |= (et.type == NT_unsigned) << 7;
20639  neon_two_same (neon_quad (rs), 1, et.size);
20640}
20641
20642static void
20643do_neon_recip_est (void)
20644{
20645  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20646  struct neon_type_el et = neon_check_type (2, rs,
20647    N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
20648  inst.instruction |= (et.type == NT_float) << 8;
20649  neon_two_same (neon_quad (rs), 1, et.size);
20650}
20651
20652static void
20653do_neon_cls (void)
20654{
20655  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
20656    return;
20657
20658  enum neon_shape rs;
20659  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20660   rs = neon_select_shape (NS_QQ, NS_NULL);
20661  else
20662   rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20663
20664  struct neon_type_el et = neon_check_type (2, rs,
20665    N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
20666  neon_two_same (neon_quad (rs), 1, et.size);
20667}
20668
20669static void
20670do_neon_clz (void)
20671{
20672  if (!check_simd_pred_availability (false, NEON_CHECK_ARCH | NEON_CHECK_CC))
20673    return;
20674
20675  enum neon_shape rs;
20676  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20677   rs = neon_select_shape (NS_QQ, NS_NULL);
20678  else
20679   rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20680
20681  struct neon_type_el et = neon_check_type (2, rs,
20682    N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
20683  neon_two_same (neon_quad (rs), 1, et.size);
20684}
20685
20686static void
20687do_neon_cnt (void)
20688{
20689  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20690  struct neon_type_el et = neon_check_type (2, rs,
20691    N_EQK | N_INT, N_8 | N_KEY);
20692  neon_two_same (neon_quad (rs), 1, et.size);
20693}
20694
20695static void
20696do_neon_swp (void)
20697{
20698  enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20699  if (rs == NS_NULL)
20700    return;
20701  neon_two_same (neon_quad (rs), 1, -1);
20702}
20703
20704static void
20705do_neon_tbl_tbx (void)
20706{
20707  unsigned listlenbits;
20708  neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
20709
20710  if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
20711    {
20712      first_error (_("bad list length for table lookup"));
20713      return;
20714    }
20715
20716  listlenbits = inst.operands[1].imm - 1;
20717  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20718  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20719  inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20720  inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20721  inst.instruction |= LOW4 (inst.operands[2].reg);
20722  inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20723  inst.instruction |= listlenbits << 8;
20724
20725  neon_dp_fixup (&inst);
20726}
20727
20728static void
20729do_neon_ldm_stm (void)
20730{
20731  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
20732	      && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20733	      _(BAD_FPU));
20734  /* P, U and L bits are part of bitmask.  */
20735  int is_dbmode = (inst.instruction & (1 << 24)) != 0;
20736  unsigned offsetbits = inst.operands[1].imm * 2;
20737
20738  if (inst.operands[1].issingle)
20739    {
20740      do_vfp_nsyn_ldm_stm (is_dbmode);
20741      return;
20742    }
20743
20744  constraint (is_dbmode && !inst.operands[0].writeback,
20745	      _("writeback (!) must be used for VLDMDB and VSTMDB"));
20746
20747  constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20748	      _("register list must contain at least 1 and at most 16 "
20749		"registers"));
20750
20751  inst.instruction |= inst.operands[0].reg << 16;
20752  inst.instruction |= inst.operands[0].writeback << 21;
20753  inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20754  inst.instruction |= HI1 (inst.operands[1].reg) << 22;
20755
20756  inst.instruction |= offsetbits;
20757
20758  do_vfp_cond_or_thumb ();
20759}
20760
20761static void
20762do_vfp_nsyn_push_pop_check (void)
20763{
20764  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd), _(BAD_FPU));
20765
20766  if (inst.operands[1].issingle)
20767    {
20768      constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 32,
20769		  _("register list must contain at least 1 and at most 32 registers"));
20770    }
20771  else
20772    {
20773      constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
20774		  _("register list must contain at least 1 and at most 16 registers"));
20775    }
20776}
20777
20778static void
20779do_vfp_nsyn_pop (void)
20780{
20781  nsyn_insert_sp ();
20782
20783  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20784    return do_vfp_nsyn_opcode ("vldm");
20785
20786  do_vfp_nsyn_push_pop_check ();
20787
20788  if (inst.operands[1].issingle)
20789    do_vfp_nsyn_opcode ("fldmias");
20790  else
20791    do_vfp_nsyn_opcode ("fldmiad");
20792}
20793
20794static void
20795do_vfp_nsyn_push (void)
20796{
20797  nsyn_insert_sp ();
20798
20799  if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20800    return do_vfp_nsyn_opcode ("vstmdb");
20801
20802  do_vfp_nsyn_push_pop_check ();
20803
20804  if (inst.operands[1].issingle)
20805    do_vfp_nsyn_opcode ("fstmdbs");
20806  else
20807    do_vfp_nsyn_opcode ("fstmdbd");
20808}
20809
20810static void
20811do_neon_ldr_str (void)
20812{
20813  int is_ldr = (inst.instruction & (1 << 20)) != 0;
20814
20815  /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20816     And is UNPREDICTABLE in thumb mode.  */
20817  if (!is_ldr
20818      && inst.operands[1].reg == REG_PC
20819      && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
20820    {
20821      if (thumb_mode)
20822	inst.error = _("Use of PC here is UNPREDICTABLE");
20823      else if (warn_on_deprecated)
20824	as_tsktsk (_("Use of PC here is deprecated"));
20825    }
20826
20827  if (inst.operands[0].issingle)
20828    {
20829      if (is_ldr)
20830	do_vfp_nsyn_opcode ("flds");
20831      else
20832	do_vfp_nsyn_opcode ("fsts");
20833
20834      /* ARMv8.2 vldr.16/vstr.16 instruction.  */
20835      if (inst.vectype.el[0].size == 16)
20836	do_scalar_fp16_v82_encode ();
20837    }
20838  else
20839    {
20840      if (is_ldr)
20841	do_vfp_nsyn_opcode ("fldd");
20842      else
20843	do_vfp_nsyn_opcode ("fstd");
20844    }
20845}
20846
20847static void
20848do_t_vldr_vstr_sysreg (void)
20849{
20850  int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
20851  bool is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
20852
20853  /* Use of PC is UNPREDICTABLE.  */
20854  if (inst.operands[1].reg == REG_PC)
20855    inst.error = _("Use of PC here is UNPREDICTABLE");
20856
20857  if (inst.operands[1].immisreg)
20858    inst.error = _("instruction does not accept register index");
20859
20860  if (!inst.operands[1].isreg)
20861    inst.error = _("instruction does not accept PC-relative addressing");
20862
20863  if (abs (inst.operands[1].imm) >= (1 << 7))
20864    inst.error = _("immediate value out of range");
20865
20866  inst.instruction = 0xec000f80;
20867  if (is_vldr)
20868    inst.instruction |= 1 << sysreg_vldr_bitno;
20869  encode_arm_cp_address (1, true, false, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
20870  inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
20871  inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
20872}
20873
20874static void
20875do_vldr_vstr (void)
20876{
20877  bool sysreg_op = !inst.operands[0].isreg;
20878
20879  /* VLDR/VSTR (System Register).  */
20880  if (sysreg_op)
20881    {
20882      if (!mark_feature_used (&arm_ext_v8_1m_main))
20883	as_bad (_("Instruction not permitted on this architecture"));
20884
20885      do_t_vldr_vstr_sysreg ();
20886    }
20887  /* VLDR/VSTR.  */
20888  else
20889    {
20890      if (!mark_feature_used (&fpu_vfp_ext_v1xd)
20891	  && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20892	as_bad (_("Instruction not permitted on this architecture"));
20893      do_neon_ldr_str ();
20894    }
20895}
20896
20897/* "interleave" version also handles non-interleaving register VLD1/VST1
20898   instructions.  */
20899
20900static void
20901do_neon_ld_st_interleave (void)
20902{
20903  struct neon_type_el et = neon_check_type (1, NS_NULL,
20904					    N_8 | N_16 | N_32 | N_64);
20905  unsigned alignbits = 0;
20906  unsigned idx;
20907  /* The bits in this table go:
20908     0: register stride of one (0) or two (1)
20909     1,2: register list length, minus one (1, 2, 3, 4).
20910     3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20911     We use -1 for invalid entries.  */
20912  const int typetable[] =
20913    {
20914      0x7,  -1, 0xa,  -1, 0x6,  -1, 0x2,  -1, /* VLD1 / VST1.  */
20915       -1,  -1, 0x8, 0x9,  -1,  -1, 0x3,  -1, /* VLD2 / VST2.  */
20916       -1,  -1,  -1,  -1, 0x4, 0x5,  -1,  -1, /* VLD3 / VST3.  */
20917       -1,  -1,  -1,  -1,  -1,  -1, 0x0, 0x1  /* VLD4 / VST4.  */
20918    };
20919  int typebits;
20920
20921  if (et.type == NT_invtype)
20922    return;
20923
20924  if (inst.operands[1].immisalign)
20925    switch (inst.operands[1].imm >> 8)
20926      {
20927      case 64: alignbits = 1; break;
20928      case 128:
20929	if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
20930	    && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20931	  goto bad_alignment;
20932	alignbits = 2;
20933	break;
20934      case 256:
20935	if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20936	  goto bad_alignment;
20937	alignbits = 3;
20938	break;
20939      default:
20940      bad_alignment:
20941	first_error (_("bad alignment"));
20942	return;
20943      }
20944
20945  inst.instruction |= alignbits << 4;
20946  inst.instruction |= neon_logbits (et.size) << 6;
20947
20948  /* Bits [4:6] of the immediate in a list specifier encode register stride
20949     (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20950     VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20951     up the right value for "type" in a table based on this value and the given
20952     list style, then stick it back.  */
20953  idx = ((inst.operands[0].imm >> 4) & 7)
20954	| (((inst.instruction >> 8) & 3) << 3);
20955
20956  typebits = typetable[idx];
20957
20958  constraint (typebits == -1, _("bad list type for instruction"));
20959  constraint (((inst.instruction >> 8) & 3) && et.size == 64,
20960	      BAD_EL_TYPE);
20961
20962  inst.instruction &= ~0xf00;
20963  inst.instruction |= typebits << 8;
20964}
20965
20966/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20967   *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20968   otherwise. The variable arguments are a list of pairs of legal (size, align)
20969   values, terminated with -1.  */
20970
20971static int
20972neon_alignment_bit (int size, int align, int *do_alignment, ...)
20973{
20974  va_list ap;
20975  int result = FAIL, thissize, thisalign;
20976
20977  if (!inst.operands[1].immisalign)
20978    {
20979      *do_alignment = 0;
20980      return SUCCESS;
20981    }
20982
20983  va_start (ap, do_alignment);
20984
20985  do
20986    {
20987      thissize = va_arg (ap, int);
20988      if (thissize == -1)
20989	break;
20990      thisalign = va_arg (ap, int);
20991
20992      if (size == thissize && align == thisalign)
20993	result = SUCCESS;
20994    }
20995  while (result != SUCCESS);
20996
20997  va_end (ap);
20998
20999  if (result == SUCCESS)
21000    *do_alignment = 1;
21001  else
21002    first_error (_("unsupported alignment for instruction"));
21003
21004  return result;
21005}
21006
21007static void
21008do_neon_ld_st_lane (void)
21009{
21010  struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
21011  int align_good, do_alignment = 0;
21012  int logsize = neon_logbits (et.size);
21013  int align = inst.operands[1].imm >> 8;
21014  int n = (inst.instruction >> 8) & 3;
21015  int max_el = 64 / et.size;
21016
21017  if (et.type == NT_invtype)
21018    return;
21019
21020  constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
21021	      _("bad list length"));
21022  constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
21023	      _("scalar index out of range"));
21024  constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
21025	      && et.size == 8,
21026	      _("stride of 2 unavailable when element size is 8"));
21027
21028  switch (n)
21029    {
21030    case 0:  /* VLD1 / VST1.  */
21031      align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
21032				       32, 32, -1);
21033      if (align_good == FAIL)
21034	return;
21035      if (do_alignment)
21036	{
21037	  unsigned alignbits = 0;
21038	  switch (et.size)
21039	    {
21040	    case 16: alignbits = 0x1; break;
21041	    case 32: alignbits = 0x3; break;
21042	    default: ;
21043	    }
21044	  inst.instruction |= alignbits << 4;
21045	}
21046      break;
21047
21048    case 1:  /* VLD2 / VST2.  */
21049      align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
21050		      16, 32, 32, 64, -1);
21051      if (align_good == FAIL)
21052	return;
21053      if (do_alignment)
21054	inst.instruction |= 1 << 4;
21055      break;
21056
21057    case 2:  /* VLD3 / VST3.  */
21058      constraint (inst.operands[1].immisalign,
21059		  _("can't use alignment with this instruction"));
21060      break;
21061
21062    case 3:  /* VLD4 / VST4.  */
21063      align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
21064				       16, 64, 32, 64, 32, 128, -1);
21065      if (align_good == FAIL)
21066	return;
21067      if (do_alignment)
21068	{
21069	  unsigned alignbits = 0;
21070	  switch (et.size)
21071	    {
21072	    case 8:  alignbits = 0x1; break;
21073	    case 16: alignbits = 0x1; break;
21074	    case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
21075	    default: ;
21076	    }
21077	  inst.instruction |= alignbits << 4;
21078	}
21079      break;
21080
21081    default: ;
21082    }
21083
21084  /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32.  */
21085  if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21086    inst.instruction |= 1 << (4 + logsize);
21087
21088  inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
21089  inst.instruction |= logsize << 10;
21090}
21091
21092/* Encode single n-element structure to all lanes VLD<n> instructions.  */
21093
21094static void
21095do_neon_ld_dup (void)
21096{
21097  struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
21098  int align_good, do_alignment = 0;
21099
21100  if (et.type == NT_invtype)
21101    return;
21102
21103  switch ((inst.instruction >> 8) & 3)
21104    {
21105    case 0:  /* VLD1.  */
21106      gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
21107      align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
21108				       &do_alignment, 16, 16, 32, 32, -1);
21109      if (align_good == FAIL)
21110	return;
21111      switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
21112	{
21113	case 1: break;
21114	case 2: inst.instruction |= 1 << 5; break;
21115	default: first_error (_("bad list length")); return;
21116	}
21117      inst.instruction |= neon_logbits (et.size) << 6;
21118      break;
21119
21120    case 1:  /* VLD2.  */
21121      align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
21122				       &do_alignment, 8, 16, 16, 32, 32, 64,
21123				       -1);
21124      if (align_good == FAIL)
21125	return;
21126      constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
21127		  _("bad list length"));
21128      if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21129	inst.instruction |= 1 << 5;
21130      inst.instruction |= neon_logbits (et.size) << 6;
21131      break;
21132
21133    case 2:  /* VLD3.  */
21134      constraint (inst.operands[1].immisalign,
21135		  _("can't use alignment with this instruction"));
21136      constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
21137		  _("bad list length"));
21138      if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21139	inst.instruction |= 1 << 5;
21140      inst.instruction |= neon_logbits (et.size) << 6;
21141      break;
21142
21143    case 3:  /* VLD4.  */
21144      {
21145	int align = inst.operands[1].imm >> 8;
21146	align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
21147					 16, 64, 32, 64, 32, 128, -1);
21148	if (align_good == FAIL)
21149	  return;
21150	constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
21151		    _("bad list length"));
21152	if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
21153	  inst.instruction |= 1 << 5;
21154	if (et.size == 32 && align == 128)
21155	  inst.instruction |= 0x3 << 6;
21156	else
21157	  inst.instruction |= neon_logbits (et.size) << 6;
21158      }
21159      break;
21160
21161    default: ;
21162    }
21163
21164  inst.instruction |= do_alignment << 4;
21165}
21166
21167/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21168   apart from bits [11:4].  */
21169
21170static void
21171do_neon_ldx_stx (void)
21172{
21173  if (inst.operands[1].isreg)
21174    constraint (inst.operands[1].reg == REG_PC, BAD_PC);
21175
21176  switch (NEON_LANE (inst.operands[0].imm))
21177    {
21178    case NEON_INTERLEAVE_LANES:
21179      NEON_ENCODE (INTERLV, inst);
21180      do_neon_ld_st_interleave ();
21181      break;
21182
21183    case NEON_ALL_LANES:
21184      NEON_ENCODE (DUP, inst);
21185      if (inst.instruction == N_INV)
21186	{
21187	  first_error ("only loads support such operands");
21188	  break;
21189	}
21190      do_neon_ld_dup ();
21191      break;
21192
21193    default:
21194      NEON_ENCODE (LANE, inst);
21195      do_neon_ld_st_lane ();
21196    }
21197
21198  /* L bit comes from bit mask.  */
21199  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21200  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21201  inst.instruction |= inst.operands[1].reg << 16;
21202
21203  if (inst.operands[1].postind)
21204    {
21205      int postreg = inst.operands[1].imm & 0xf;
21206      constraint (!inst.operands[1].immisreg,
21207		  _("post-index must be a register"));
21208      constraint (postreg == 0xd || postreg == 0xf,
21209		  _("bad register for post-index"));
21210      inst.instruction |= postreg;
21211    }
21212  else
21213    {
21214      constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
21215      constraint (inst.relocs[0].exp.X_op != O_constant
21216		  || inst.relocs[0].exp.X_add_number != 0,
21217		  BAD_ADDR_MODE);
21218
21219      if (inst.operands[1].writeback)
21220	{
21221	  inst.instruction |= 0xd;
21222	}
21223      else
21224	inst.instruction |= 0xf;
21225    }
21226
21227  if (thumb_mode)
21228    inst.instruction |= 0xf9000000;
21229  else
21230    inst.instruction |= 0xf4000000;
21231}
21232
21233/* FP v8.  */
21234static void
21235do_vfp_nsyn_fpv8 (enum neon_shape rs)
21236{
21237  /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21238     D register operands.  */
21239  if (neon_shape_class[rs] == SC_DOUBLE)
21240    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21241		_(BAD_FPU));
21242
21243  NEON_ENCODE (FPV8, inst);
21244
21245  if (rs == NS_FFF || rs == NS_HHH)
21246    {
21247      do_vfp_sp_dyadic ();
21248
21249      /* ARMv8.2 fp16 instruction.  */
21250      if (rs == NS_HHH)
21251	do_scalar_fp16_v82_encode ();
21252    }
21253  else
21254    do_vfp_dp_rd_rn_rm ();
21255
21256  if (rs == NS_DDD)
21257    inst.instruction |= 0x100;
21258
21259  inst.instruction |= 0xf0000000;
21260}
21261
21262static void
21263do_vsel (void)
21264{
21265  set_pred_insn_type (OUTSIDE_PRED_INSN);
21266
21267  if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
21268    first_error (_("invalid instruction shape"));
21269}
21270
21271static void
21272do_vmaxnm (void)
21273{
21274  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21275    set_pred_insn_type (OUTSIDE_PRED_INSN);
21276
21277  if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
21278    return;
21279
21280  if (!check_simd_pred_availability (true, NEON_CHECK_CC | NEON_CHECK_ARCH8))
21281    return;
21282
21283  neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
21284}
21285
21286static void
21287do_vrint_1 (enum neon_cvt_mode mode)
21288{
21289  enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
21290  struct neon_type_el et;
21291
21292  if (rs == NS_NULL)
21293    return;
21294
21295  /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21296     D register operands.  */
21297  if (neon_shape_class[rs] == SC_DOUBLE)
21298    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21299		_(BAD_FPU));
21300
21301  et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
21302			| N_VFP);
21303  if (et.type != NT_invtype)
21304    {
21305      /* VFP encodings.  */
21306      if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
21307	  || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
21308	set_pred_insn_type (OUTSIDE_PRED_INSN);
21309
21310      NEON_ENCODE (FPV8, inst);
21311      if (rs == NS_FF || rs == NS_HH)
21312	do_vfp_sp_monadic ();
21313      else
21314	do_vfp_dp_rd_rm ();
21315
21316      switch (mode)
21317	{
21318	case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
21319	case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
21320	case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
21321	case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
21322	case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
21323	case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
21324	case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
21325	default: abort ();
21326	}
21327
21328      inst.instruction |= (rs == NS_DD) << 8;
21329      do_vfp_cond_or_thumb ();
21330
21331      /* ARMv8.2 fp16 vrint instruction.  */
21332      if (rs == NS_HH)
21333      do_scalar_fp16_v82_encode ();
21334    }
21335  else
21336    {
21337      /* Neon encodings (or something broken...).  */
21338      inst.error = NULL;
21339      et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
21340
21341      if (et.type == NT_invtype)
21342	return;
21343
21344      if (!check_simd_pred_availability (true,
21345					 NEON_CHECK_CC | NEON_CHECK_ARCH8))
21346	return;
21347
21348      NEON_ENCODE (FLOAT, inst);
21349
21350      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21351      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21352      inst.instruction |= LOW4 (inst.operands[1].reg);
21353      inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21354      inst.instruction |= neon_quad (rs) << 6;
21355      /* Mask off the original size bits and reencode them.  */
21356      inst.instruction = ((inst.instruction & 0xfff3ffff)
21357			  | neon_logbits (et.size) << 18);
21358
21359      switch (mode)
21360	{
21361	case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
21362	case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
21363	case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
21364	case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
21365	case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
21366	case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
21367	case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
21368	default: abort ();
21369	}
21370
21371      if (thumb_mode)
21372	inst.instruction |= 0xfc000000;
21373      else
21374	inst.instruction |= 0xf0000000;
21375    }
21376}
21377
21378static void
21379do_vrintx (void)
21380{
21381  do_vrint_1 (neon_cvt_mode_x);
21382}
21383
21384static void
21385do_vrintz (void)
21386{
21387  do_vrint_1 (neon_cvt_mode_z);
21388}
21389
21390static void
21391do_vrintr (void)
21392{
21393  do_vrint_1 (neon_cvt_mode_r);
21394}
21395
21396static void
21397do_vrinta (void)
21398{
21399  do_vrint_1 (neon_cvt_mode_a);
21400}
21401
21402static void
21403do_vrintn (void)
21404{
21405  do_vrint_1 (neon_cvt_mode_n);
21406}
21407
21408static void
21409do_vrintp (void)
21410{
21411  do_vrint_1 (neon_cvt_mode_p);
21412}
21413
21414static void
21415do_vrintm (void)
21416{
21417  do_vrint_1 (neon_cvt_mode_m);
21418}
21419
21420static unsigned
21421neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
21422{
21423  unsigned regno = NEON_SCALAR_REG (opnd);
21424  unsigned elno = NEON_SCALAR_INDEX (opnd);
21425
21426  if (elsize == 16 && elno < 2 && regno < 16)
21427    return regno | (elno << 4);
21428  else if (elsize == 32 && elno == 0)
21429    return regno;
21430
21431  first_error (_("scalar out of range"));
21432  return 0;
21433}
21434
21435static void
21436do_vcmla (void)
21437{
21438  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
21439	      && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21440		  || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
21441  constraint (inst.relocs[0].exp.X_op != O_constant,
21442	      _("expression too complex"));
21443  unsigned rot = inst.relocs[0].exp.X_add_number;
21444  constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
21445	      _("immediate out of range"));
21446  rot /= 90;
21447
21448  if (!check_simd_pred_availability (true,
21449				     NEON_CHECK_ARCH8 | NEON_CHECK_CC))
21450    return;
21451
21452  if (inst.operands[2].isscalar)
21453    {
21454      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21455	first_error (_("invalid instruction shape"));
21456      enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
21457      unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21458				       N_KEY | N_F16 | N_F32).size;
21459      unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
21460      inst.is_neon = 1;
21461      inst.instruction = 0xfe000800;
21462      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21463      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21464      inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21465      inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21466      inst.instruction |= LOW4 (m);
21467      inst.instruction |= HI1 (m) << 5;
21468      inst.instruction |= neon_quad (rs) << 6;
21469      inst.instruction |= rot << 20;
21470      inst.instruction |= (size == 32) << 23;
21471    }
21472  else
21473    {
21474      enum neon_shape rs;
21475      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21476	rs = neon_select_shape (NS_QQQI, NS_NULL);
21477      else
21478	rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21479
21480      unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21481				       N_KEY | N_F16 | N_F32).size;
21482      if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
21483	  && (inst.operands[0].reg == inst.operands[1].reg
21484	      || inst.operands[0].reg == inst.operands[2].reg))
21485	as_tsktsk (BAD_MVE_SRCDEST);
21486
21487      neon_three_same (neon_quad (rs), 0, -1);
21488      inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup.  */
21489      inst.instruction |= 0xfc200800;
21490      inst.instruction |= rot << 23;
21491      inst.instruction |= (size == 32) << 20;
21492    }
21493}
21494
21495static void
21496do_vcadd (void)
21497{
21498  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
21499	      && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21500		  || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
21501  constraint (inst.relocs[0].exp.X_op != O_constant,
21502	      _("expression too complex"));
21503
21504  unsigned rot = inst.relocs[0].exp.X_add_number;
21505  constraint (rot != 90 && rot != 270, _("immediate out of range"));
21506  enum neon_shape rs;
21507  struct neon_type_el et;
21508  if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21509    {
21510      rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21511      et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
21512    }
21513  else
21514    {
21515      rs = neon_select_shape (NS_QQQI, NS_NULL);
21516      et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
21517			    | N_I16 | N_I32);
21518      if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
21519	as_tsktsk (_("Warning: 32-bit element size and same first and third "
21520		     "operand makes instruction UNPREDICTABLE"));
21521    }
21522
21523  if (et.type == NT_invtype)
21524    return;
21525
21526  if (!check_simd_pred_availability (et.type == NT_float,
21527				     NEON_CHECK_ARCH8 | NEON_CHECK_CC))
21528    return;
21529
21530  if (et.type == NT_float)
21531    {
21532      neon_three_same (neon_quad (rs), 0, -1);
21533      inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup.  */
21534      inst.instruction |= 0xfc800800;
21535      inst.instruction |= (rot == 270) << 24;
21536      inst.instruction |= (et.size == 32) << 20;
21537    }
21538  else
21539    {
21540      constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
21541      inst.instruction = 0xfe000f00;
21542      inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21543      inst.instruction |= neon_logbits (et.size) << 20;
21544      inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21545      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21546      inst.instruction |= (rot == 270) << 12;
21547      inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21548      inst.instruction |= HI1 (inst.operands[2].reg) << 5;
21549      inst.instruction |= LOW4 (inst.operands[2].reg);
21550      inst.is_neon = 1;
21551    }
21552}
21553
21554/* Dot Product instructions encoding support.  */
21555
21556static void
21557do_neon_dotproduct (int unsigned_p)
21558{
21559  enum neon_shape rs;
21560  unsigned scalar_oprd2 = 0;
21561  int high8;
21562
21563  if (inst.cond != COND_ALWAYS)
21564    as_warn (_("Dot Product instructions cannot be conditional,  the behaviour "
21565	       "is UNPREDICTABLE"));
21566
21567  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
21568	      _(BAD_FPU));
21569
21570  /* Dot Product instructions are in three-same D/Q register format or the third
21571     operand can be a scalar index register.  */
21572  if (inst.operands[2].isscalar)
21573    {
21574      scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
21575      high8 = 0xfe000000;
21576      rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21577    }
21578  else
21579    {
21580      high8 = 0xfc000000;
21581      rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
21582    }
21583
21584  if (unsigned_p)
21585    neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
21586  else
21587    neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
21588
21589  /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21590     Product instruction, so we pass 0 as the "ubit" parameter.  And the
21591     "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter.  */
21592  neon_three_same (neon_quad (rs), 0, 32);
21593
21594  /* Undo neon_dp_fixup.  Dot Product instructions are using a slightly
21595     different NEON three-same encoding.  */
21596  inst.instruction &= 0x00ffffff;
21597  inst.instruction |= high8;
21598  /* Encode 'U' bit which indicates signedness.  */
21599  inst.instruction |= (unsigned_p ? 1 : 0) << 4;
21600  /* Re-encode operand2 if it's indexed scalar operand.  What has been encoded
21601     from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21602     the instruction encoding.  */
21603  if (inst.operands[2].isscalar)
21604    {
21605      inst.instruction &= 0xffffffd0;
21606      inst.instruction |= LOW4 (scalar_oprd2);
21607      inst.instruction |= HI1 (scalar_oprd2) << 5;
21608    }
21609}
21610
21611/* Dot Product instructions for signed integer.  */
21612
21613static void
21614do_neon_dotproduct_s (void)
21615{
21616  return do_neon_dotproduct (0);
21617}
21618
21619/* Dot Product instructions for unsigned integer.  */
21620
21621static void
21622do_neon_dotproduct_u (void)
21623{
21624  return do_neon_dotproduct (1);
21625}
21626
21627static void
21628do_vusdot (void)
21629{
21630  enum neon_shape rs;
21631  set_pred_insn_type (OUTSIDE_PRED_INSN);
21632  if (inst.operands[2].isscalar)
21633    {
21634      rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21635      neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_KEY);
21636
21637      inst.instruction |= (1 << 25);
21638      int idx = inst.operands[2].reg & 0xf;
21639      constraint ((idx != 1 && idx != 0), _("index must be 0 or 1"));
21640      inst.operands[2].reg >>= 4;
21641      constraint (!(inst.operands[2].reg < 16),
21642		  _("indexed register must be less than 16"));
21643      neon_three_args (rs == NS_QQS);
21644      inst.instruction |= (idx << 5);
21645    }
21646  else
21647    {
21648      inst.instruction |= (1 << 21);
21649      rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
21650      neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_KEY);
21651      neon_three_args (rs == NS_QQQ);
21652    }
21653}
21654
21655static void
21656do_vsudot (void)
21657{
21658  enum neon_shape rs;
21659  set_pred_insn_type (OUTSIDE_PRED_INSN);
21660  if (inst.operands[2].isscalar)
21661    {
21662      rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21663      neon_check_type (3, rs, N_EQK, N_EQK, N_U8 | N_KEY);
21664
21665      inst.instruction |= (1 << 25);
21666      int idx = inst.operands[2].reg & 0xf;
21667      constraint ((idx != 1 && idx != 0), _("index must be 0 or 1"));
21668      inst.operands[2].reg >>= 4;
21669      constraint (!(inst.operands[2].reg < 16),
21670		  _("indexed register must be less than 16"));
21671      neon_three_args (rs == NS_QQS);
21672      inst.instruction |= (idx << 5);
21673    }
21674}
21675
21676static void
21677do_vsmmla (void)
21678{
21679  enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
21680  neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_KEY);
21681
21682  set_pred_insn_type (OUTSIDE_PRED_INSN);
21683
21684  neon_three_args (1);
21685
21686}
21687
21688static void
21689do_vummla (void)
21690{
21691  enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
21692  neon_check_type (3, rs, N_EQK, N_EQK, N_U8 | N_KEY);
21693
21694  set_pred_insn_type (OUTSIDE_PRED_INSN);
21695
21696  neon_three_args (1);
21697
21698}
21699
21700static void
21701check_cde_operand (size_t idx, int is_dual)
21702{
21703  unsigned Rx = inst.operands[idx].reg;
21704  bool isvec = inst.operands[idx].isvec;
21705  if (is_dual == 0 && thumb_mode)
21706    constraint (
21707		!((Rx <= 14 && Rx != 13) || (Rx == REG_PC && isvec)),
21708		_("Register must be r0-r14 except r13, or APSR_nzcv."));
21709  else
21710    constraint ( !((Rx <= 10 && Rx % 2 == 0 )),
21711      _("Register must be an even register between r0-r10."));
21712}
21713
21714static bool
21715cde_coproc_enabled (unsigned coproc)
21716{
21717  switch (coproc)
21718  {
21719    case 0: return mark_feature_used (&arm_ext_cde0);
21720    case 1: return mark_feature_used (&arm_ext_cde1);
21721    case 2: return mark_feature_used (&arm_ext_cde2);
21722    case 3: return mark_feature_used (&arm_ext_cde3);
21723    case 4: return mark_feature_used (&arm_ext_cde4);
21724    case 5: return mark_feature_used (&arm_ext_cde5);
21725    case 6: return mark_feature_used (&arm_ext_cde6);
21726    case 7: return mark_feature_used (&arm_ext_cde7);
21727    default: return false;
21728  }
21729}
21730
21731#define cde_coproc_pos 8
21732static void
21733cde_handle_coproc (void)
21734{
21735  unsigned coproc = inst.operands[0].reg;
21736  constraint (coproc > 7, _("CDE Coprocessor must be in range 0-7"));
21737  constraint (!(cde_coproc_enabled (coproc)), BAD_CDE_COPROC);
21738  inst.instruction |= coproc << cde_coproc_pos;
21739}
21740#undef cde_coproc_pos
21741
21742static void
21743cxn_handle_predication (bool is_accum)
21744{
21745  if (is_accum && conditional_insn ())
21746    set_pred_insn_type (INSIDE_IT_INSN);
21747  else if (conditional_insn ())
21748  /* conditional_insn essentially checks for a suffix, not whether the
21749     instruction is inside an IT block or not.
21750     The non-accumulator versions should not have suffixes.  */
21751    inst.error = BAD_SYNTAX;
21752  else
21753    set_pred_insn_type (OUTSIDE_PRED_INSN);
21754}
21755
21756static void
21757do_custom_instruction_1 (int is_dual, bool is_accum)
21758{
21759
21760  constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
21761
21762  unsigned imm, Rd;
21763
21764  Rd = inst.operands[1].reg;
21765  check_cde_operand (1, is_dual);
21766
21767  if (is_dual == 1)
21768    {
21769      constraint (inst.operands[2].reg != Rd + 1,
21770		  _("cx1d requires consecutive destination registers."));
21771      imm = inst.operands[3].imm;
21772    }
21773  else if (is_dual == 0)
21774    imm = inst.operands[2].imm;
21775  else
21776    abort ();
21777
21778  inst.instruction |= Rd << 12;
21779  inst.instruction |= (imm & 0x1F80) << 9;
21780  inst.instruction |= (imm & 0x0040) << 1;
21781  inst.instruction |= (imm & 0x003f);
21782
21783  cde_handle_coproc ();
21784  cxn_handle_predication (is_accum);
21785}
21786
21787static void
21788do_custom_instruction_2 (int is_dual, bool is_accum)
21789{
21790
21791  constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
21792
21793  unsigned imm, Rd, Rn;
21794
21795  Rd = inst.operands[1].reg;
21796
21797  if (is_dual == 1)
21798    {
21799      constraint (inst.operands[2].reg != Rd + 1,
21800		  _("cx2d requires consecutive destination registers."));
21801      imm = inst.operands[4].imm;
21802      Rn = inst.operands[3].reg;
21803    }
21804  else if (is_dual == 0)
21805  {
21806    imm = inst.operands[3].imm;
21807    Rn = inst.operands[2].reg;
21808  }
21809  else
21810    abort ();
21811
21812  check_cde_operand (2 + is_dual, /* is_dual = */0);
21813  check_cde_operand (1, is_dual);
21814
21815  inst.instruction |= Rd << 12;
21816  inst.instruction |= Rn << 16;
21817
21818  inst.instruction |= (imm & 0x0380) << 13;
21819  inst.instruction |= (imm & 0x0040) << 1;
21820  inst.instruction |= (imm & 0x003f);
21821
21822  cde_handle_coproc ();
21823  cxn_handle_predication (is_accum);
21824}
21825
21826static void
21827do_custom_instruction_3 (int is_dual, bool is_accum)
21828{
21829
21830  constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
21831
21832  unsigned imm, Rd, Rn, Rm;
21833
21834  Rd = inst.operands[1].reg;
21835
21836  if (is_dual == 1)
21837    {
21838      constraint (inst.operands[2].reg != Rd + 1,
21839		  _("cx3d requires consecutive destination registers."));
21840      imm = inst.operands[5].imm;
21841      Rn = inst.operands[3].reg;
21842      Rm = inst.operands[4].reg;
21843    }
21844  else if (is_dual == 0)
21845  {
21846    imm = inst.operands[4].imm;
21847    Rn = inst.operands[2].reg;
21848    Rm = inst.operands[3].reg;
21849  }
21850  else
21851    abort ();
21852
21853  check_cde_operand (1, is_dual);
21854  check_cde_operand (2 + is_dual, /* is_dual = */0);
21855  check_cde_operand (3 + is_dual, /* is_dual = */0);
21856
21857  inst.instruction |= Rd;
21858  inst.instruction |= Rn << 16;
21859  inst.instruction |= Rm << 12;
21860
21861  inst.instruction |= (imm & 0x0038) << 17;
21862  inst.instruction |= (imm & 0x0004) << 5;
21863  inst.instruction |= (imm & 0x0003) << 4;
21864
21865  cde_handle_coproc ();
21866  cxn_handle_predication (is_accum);
21867}
21868
21869static void
21870do_cx1 (void)
21871{
21872  return do_custom_instruction_1 (0, 0);
21873}
21874
21875static void
21876do_cx1a (void)
21877{
21878  return do_custom_instruction_1 (0, 1);
21879}
21880
21881static void
21882do_cx1d (void)
21883{
21884  return do_custom_instruction_1 (1, 0);
21885}
21886
21887static void
21888do_cx1da (void)
21889{
21890  return do_custom_instruction_1 (1, 1);
21891}
21892
21893static void
21894do_cx2 (void)
21895{
21896  return do_custom_instruction_2 (0, 0);
21897}
21898
21899static void
21900do_cx2a (void)
21901{
21902  return do_custom_instruction_2 (0, 1);
21903}
21904
21905static void
21906do_cx2d (void)
21907{
21908  return do_custom_instruction_2 (1, 0);
21909}
21910
21911static void
21912do_cx2da (void)
21913{
21914  return do_custom_instruction_2 (1, 1);
21915}
21916
21917static void
21918do_cx3 (void)
21919{
21920  return do_custom_instruction_3 (0, 0);
21921}
21922
21923static void
21924do_cx3a (void)
21925{
21926  return do_custom_instruction_3 (0, 1);
21927}
21928
21929static void
21930do_cx3d (void)
21931{
21932  return do_custom_instruction_3 (1, 0);
21933}
21934
21935static void
21936do_cx3da (void)
21937{
21938  return do_custom_instruction_3 (1, 1);
21939}
21940
21941static void
21942vcx_assign_vec_d (unsigned regnum)
21943{
21944  inst.instruction |= HI4 (regnum) << 12;
21945  inst.instruction |= LOW1 (regnum) << 22;
21946}
21947
21948static void
21949vcx_assign_vec_m (unsigned regnum)
21950{
21951  inst.instruction |= HI4 (regnum);
21952  inst.instruction |= LOW1 (regnum) << 5;
21953}
21954
21955static void
21956vcx_assign_vec_n (unsigned regnum)
21957{
21958  inst.instruction |= HI4 (regnum) << 16;
21959  inst.instruction |= LOW1 (regnum) << 7;
21960}
21961
21962enum vcx_reg_type {
21963    q_reg,
21964    d_reg,
21965    s_reg
21966};
21967
21968static enum vcx_reg_type
21969vcx_get_reg_type (enum neon_shape ns)
21970{
21971  gas_assert (ns == NS_PQI
21972	      || ns == NS_PDI
21973	      || ns == NS_PFI
21974	      || ns == NS_PQQI
21975	      || ns == NS_PDDI
21976	      || ns == NS_PFFI
21977	      || ns == NS_PQQQI
21978	      || ns == NS_PDDDI
21979	      || ns == NS_PFFFI);
21980  if (ns == NS_PQI || ns == NS_PQQI || ns == NS_PQQQI)
21981    return q_reg;
21982  if (ns == NS_PDI || ns == NS_PDDI || ns == NS_PDDDI)
21983    return d_reg;
21984  return s_reg;
21985}
21986
21987#define vcx_size_pos 24
21988#define vcx_vec_pos 6
21989static unsigned
21990vcx_handle_shape (enum vcx_reg_type reg_type)
21991{
21992  unsigned mult = 2;
21993  if (reg_type == q_reg)
21994    inst.instruction |= 1 << vcx_vec_pos;
21995  else if (reg_type == d_reg)
21996    inst.instruction |= 1 << vcx_size_pos;
21997  else
21998    mult = 1;
21999  /* NOTE:
22000     The documentation says that the Q registers are encoded as 2*N in the D:Vd
22001     bits (or equivalent for N and M registers).
22002     Similarly the D registers are encoded as N in D:Vd bits.
22003     While the S registers are encoded as N in the Vd:D bits.
22004
22005     Taking into account the maximum values of these registers we can see a
22006     nicer pattern for calculation:
22007       Q -> 7, D -> 15, S -> 31
22008
22009     If we say that everything is encoded in the Vd:D bits, then we can say
22010     that Q is encoded as 4*N, and D is encoded as 2*N.
22011     This way the bits will end up the same, and calculation is simpler.
22012     (calculation is now:
22013	1. Multiply by a number determined by the register letter.
22014	2. Encode resulting number in Vd:D bits.)
22015
22016      This is made a little more complicated by automatic handling of 'Q'
22017      registers elsewhere, which means the register number is already 2*N where
22018      N is the number the user wrote after the register letter.
22019     */
22020  return mult;
22021}
22022#undef vcx_vec_pos
22023#undef vcx_size_pos
22024
22025static void
22026vcx_ensure_register_in_range (unsigned R, enum vcx_reg_type reg_type)
22027{
22028  if (reg_type == q_reg)
22029    {
22030      gas_assert (R % 2 == 0);
22031      constraint (R >= 16, _("'q' register must be in range 0-7"));
22032    }
22033  else if (reg_type == d_reg)
22034    constraint (R >= 16, _("'d' register must be in range 0-15"));
22035  else
22036    constraint (R >= 32, _("'s' register must be in range 0-31"));
22037}
22038
22039static void (*vcx_assign_vec[3]) (unsigned) = {
22040    vcx_assign_vec_d,
22041    vcx_assign_vec_m,
22042    vcx_assign_vec_n
22043};
22044
22045static void
22046vcx_handle_register_arguments (unsigned num_registers,
22047			       enum vcx_reg_type reg_type)
22048{
22049  unsigned R, i;
22050  unsigned reg_mult = vcx_handle_shape (reg_type);
22051  for (i = 0; i < num_registers; i++)
22052    {
22053      R = inst.operands[i+1].reg;
22054      vcx_ensure_register_in_range (R, reg_type);
22055      if (num_registers == 3 && i > 0)
22056	{
22057	  if (i == 2)
22058	    vcx_assign_vec[1] (R * reg_mult);
22059	  else
22060	    vcx_assign_vec[2] (R * reg_mult);
22061	  continue;
22062	}
22063      vcx_assign_vec[i](R * reg_mult);
22064    }
22065}
22066
22067static void
22068vcx_handle_insn_block (enum vcx_reg_type reg_type)
22069{
22070  if (reg_type == q_reg)
22071    if (inst.cond > COND_ALWAYS)
22072      inst.pred_insn_type = INSIDE_VPT_INSN;
22073    else
22074      inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
22075  else if (inst.cond == COND_ALWAYS)
22076    inst.pred_insn_type = OUTSIDE_PRED_INSN;
22077  else
22078    inst.error = BAD_NOT_IT;
22079}
22080
22081static void
22082vcx_handle_common_checks (unsigned num_args, enum neon_shape rs)
22083{
22084  constraint (!mark_feature_used (&arm_ext_cde), _(BAD_CDE));
22085  cde_handle_coproc ();
22086  enum vcx_reg_type reg_type = vcx_get_reg_type (rs);
22087  vcx_handle_register_arguments (num_args, reg_type);
22088  vcx_handle_insn_block (reg_type);
22089  if (reg_type == q_reg)
22090    constraint (!mark_feature_used (&mve_ext),
22091		_("vcx instructions with Q registers require MVE"));
22092  else
22093    constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp, cpu_variant)
22094		  && mark_feature_used (&armv8m_fp))
22095		&& !mark_feature_used (&mve_ext),
22096		_("vcx instructions with S or D registers require either MVE"
22097		  " or Armv8-M floating point extension."));
22098}
22099
22100static void
22101do_vcx1 (void)
22102{
22103  enum neon_shape rs = neon_select_shape (NS_PQI, NS_PDI, NS_PFI, NS_NULL);
22104  vcx_handle_common_checks (1, rs);
22105
22106  unsigned imm = inst.operands[2].imm;
22107  inst.instruction |= (imm & 0x03f);
22108  inst.instruction |= (imm & 0x040) << 1;
22109  inst.instruction |= (imm & 0x780) << 9;
22110  if (rs != NS_PQI)
22111    constraint (imm >= 2048,
22112		_("vcx1 with S or D registers takes immediate within 0-2047"));
22113  inst.instruction |= (imm & 0x800) << 13;
22114}
22115
22116static void
22117do_vcx2 (void)
22118{
22119  enum neon_shape rs = neon_select_shape (NS_PQQI, NS_PDDI, NS_PFFI, NS_NULL);
22120  vcx_handle_common_checks (2, rs);
22121
22122  unsigned imm = inst.operands[3].imm;
22123  inst.instruction |= (imm & 0x01) << 4;
22124  inst.instruction |= (imm & 0x02) << 6;
22125  inst.instruction |= (imm & 0x3c) << 14;
22126  if (rs != NS_PQQI)
22127    constraint (imm >= 64,
22128		_("vcx2 with S or D registers takes immediate within 0-63"));
22129  inst.instruction |= (imm & 0x40) << 18;
22130}
22131
22132static void
22133do_vcx3 (void)
22134{
22135  enum neon_shape rs = neon_select_shape (NS_PQQQI, NS_PDDDI, NS_PFFFI, NS_NULL);
22136  vcx_handle_common_checks (3, rs);
22137
22138  unsigned imm = inst.operands[4].imm;
22139  inst.instruction |= (imm & 0x1) << 4;
22140  inst.instruction |= (imm & 0x6) << 19;
22141  if (rs != NS_PQQQI)
22142    constraint (imm >= 8,
22143		_("vcx2 with S or D registers takes immediate within 0-7"));
22144  inst.instruction |= (imm & 0x8) << 21;
22145}
22146
22147/* Crypto v1 instructions.  */
22148static void
22149do_crypto_2op_1 (unsigned elttype, int op)
22150{
22151  set_pred_insn_type (OUTSIDE_PRED_INSN);
22152
22153  if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
22154      == NT_invtype)
22155    return;
22156
22157  inst.error = NULL;
22158
22159  NEON_ENCODE (INTEGER, inst);
22160  inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
22161  inst.instruction |= HI1 (inst.operands[0].reg) << 22;
22162  inst.instruction |= LOW4 (inst.operands[1].reg);
22163  inst.instruction |= HI1 (inst.operands[1].reg) << 5;
22164  if (op != -1)
22165    inst.instruction |= op << 6;
22166
22167  if (thumb_mode)
22168    inst.instruction |= 0xfc000000;
22169  else
22170    inst.instruction |= 0xf0000000;
22171}
22172
22173static void
22174do_crypto_3op_1 (int u, int op)
22175{
22176  set_pred_insn_type (OUTSIDE_PRED_INSN);
22177
22178  if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
22179		       N_32 | N_UNT | N_KEY).type == NT_invtype)
22180    return;
22181
22182  inst.error = NULL;
22183
22184  NEON_ENCODE (INTEGER, inst);
22185  neon_three_same (1, u, 8 << op);
22186}
22187
22188static void
22189do_aese (void)
22190{
22191  do_crypto_2op_1 (N_8, 0);
22192}
22193
22194static void
22195do_aesd (void)
22196{
22197  do_crypto_2op_1 (N_8, 1);
22198}
22199
22200static void
22201do_aesmc (void)
22202{
22203  do_crypto_2op_1 (N_8, 2);
22204}
22205
22206static void
22207do_aesimc (void)
22208{
22209  do_crypto_2op_1 (N_8, 3);
22210}
22211
22212static void
22213do_sha1c (void)
22214{
22215  do_crypto_3op_1 (0, 0);
22216}
22217
22218static void
22219do_sha1p (void)
22220{
22221  do_crypto_3op_1 (0, 1);
22222}
22223
22224static void
22225do_sha1m (void)
22226{
22227  do_crypto_3op_1 (0, 2);
22228}
22229
22230static void
22231do_sha1su0 (void)
22232{
22233  do_crypto_3op_1 (0, 3);
22234}
22235
22236static void
22237do_sha256h (void)
22238{
22239  do_crypto_3op_1 (1, 0);
22240}
22241
22242static void
22243do_sha256h2 (void)
22244{
22245  do_crypto_3op_1 (1, 1);
22246}
22247
22248static void
22249do_sha256su1 (void)
22250{
22251  do_crypto_3op_1 (1, 2);
22252}
22253
22254static void
22255do_sha1h (void)
22256{
22257  do_crypto_2op_1 (N_32, -1);
22258}
22259
22260static void
22261do_sha1su1 (void)
22262{
22263  do_crypto_2op_1 (N_32, 0);
22264}
22265
22266static void
22267do_sha256su0 (void)
22268{
22269  do_crypto_2op_1 (N_32, 1);
22270}
22271
22272static void
22273do_crc32_1 (unsigned int poly, unsigned int sz)
22274{
22275  unsigned int Rd = inst.operands[0].reg;
22276  unsigned int Rn = inst.operands[1].reg;
22277  unsigned int Rm = inst.operands[2].reg;
22278
22279  set_pred_insn_type (OUTSIDE_PRED_INSN);
22280  inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
22281  inst.instruction |= LOW4 (Rn) << 16;
22282  inst.instruction |= LOW4 (Rm);
22283  inst.instruction |= sz << (thumb_mode ? 4 : 21);
22284  inst.instruction |= poly << (thumb_mode ? 20 : 9);
22285
22286  if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
22287    as_warn (UNPRED_REG ("r15"));
22288}
22289
22290static void
22291do_crc32b (void)
22292{
22293  do_crc32_1 (0, 0);
22294}
22295
22296static void
22297do_crc32h (void)
22298{
22299  do_crc32_1 (0, 1);
22300}
22301
22302static void
22303do_crc32w (void)
22304{
22305  do_crc32_1 (0, 2);
22306}
22307
22308static void
22309do_crc32cb (void)
22310{
22311  do_crc32_1 (1, 0);
22312}
22313
22314static void
22315do_crc32ch (void)
22316{
22317  do_crc32_1 (1, 1);
22318}
22319
22320static void
22321do_crc32cw (void)
22322{
22323  do_crc32_1 (1, 2);
22324}
22325
22326static void
22327do_vjcvt (void)
22328{
22329  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
22330	      _(BAD_FPU));
22331  neon_check_type (2, NS_FD, N_S32, N_F64);
22332  do_vfp_sp_dp_cvt ();
22333  do_vfp_cond_or_thumb ();
22334}
22335
22336static void
22337do_vdot (void)
22338{
22339  enum neon_shape rs;
22340  constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU));
22341  set_pred_insn_type (OUTSIDE_PRED_INSN);
22342  if (inst.operands[2].isscalar)
22343    {
22344      rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
22345      neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
22346
22347      inst.instruction |= (1 << 25);
22348      int idx = inst.operands[2].reg & 0xf;
22349      constraint ((idx != 1 && idx != 0), _("index must be 0 or 1"));
22350      inst.operands[2].reg >>= 4;
22351      constraint (!(inst.operands[2].reg < 16),
22352		  _("indexed register must be less than 16"));
22353      neon_three_args (rs == NS_QQS);
22354      inst.instruction |= (idx << 5);
22355    }
22356  else
22357    {
22358      rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
22359      neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
22360      neon_three_args (rs == NS_QQQ);
22361    }
22362}
22363
22364static void
22365do_vmmla (void)
22366{
22367  enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
22368  neon_check_type (3, rs, N_EQK, N_EQK, N_BF16 | N_KEY);
22369
22370  constraint (!mark_feature_used (&fpu_neon_ext_armv8), _(BAD_FPU));
22371  set_pred_insn_type (OUTSIDE_PRED_INSN);
22372
22373  neon_three_args (1);
22374}
22375
22376static void
22377do_t_pacbti (void)
22378{
22379  inst.instruction = THUMB_OP32 (inst.instruction);
22380}
22381
22382static void
22383do_t_pacbti_nonop (void)
22384{
22385  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, pacbti_ext),
22386	      _(BAD_PACBTI));
22387
22388  inst.instruction = THUMB_OP32 (inst.instruction);
22389  inst.instruction |= inst.operands[0].reg << 12;
22390  inst.instruction |= inst.operands[1].reg << 16;
22391  inst.instruction |= inst.operands[2].reg;
22392}
22393
22394static void
22395do_t_pacbti_pacg (void)
22396{
22397  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, pacbti_ext),
22398	      _(BAD_PACBTI));
22399
22400  inst.instruction = THUMB_OP32 (inst.instruction);
22401  inst.instruction |= inst.operands[0].reg << 8;
22402  inst.instruction |= inst.operands[1].reg << 16;
22403  inst.instruction |= inst.operands[2].reg;
22404}
22405
22406
22407/* Overall per-instruction processing.	*/
22408
22409/* We need to be able to fix up arbitrary expressions in some statements.
22410   This is so that we can handle symbols that are an arbitrary distance from
22411   the pc.  The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22412   which returns part of an address in a form which will be valid for
22413   a data instruction.	We do this by pushing the expression into a symbol
22414   in the expr_section, and creating a fix for that.  */
22415
22416static void
22417fix_new_arm (fragS *	   frag,
22418	     int	   where,
22419	     short int	   size,
22420	     expressionS * exp,
22421	     int	   pc_rel,
22422	     int	   reloc)
22423{
22424  fixS *	   new_fix;
22425
22426  switch (exp->X_op)
22427    {
22428    case O_constant:
22429      if (pc_rel)
22430	{
22431	  /* Create an absolute valued symbol, so we have something to
22432	     refer to in the object file.  Unfortunately for us, gas's
22433	     generic expression parsing will already have folded out
22434	     any use of .set foo/.type foo %function that may have
22435	     been used to set type information of the target location,
22436	     that's being specified symbolically.  We have to presume
22437	     the user knows what they are doing.  */
22438	  char name[16 + 8];
22439	  symbolS *symbol;
22440
22441	  sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
22442
22443	  symbol = symbol_find_or_make (name);
22444	  S_SET_SEGMENT (symbol, absolute_section);
22445	  symbol_set_frag (symbol, &zero_address_frag);
22446	  S_SET_VALUE (symbol, exp->X_add_number);
22447	  exp->X_op = O_symbol;
22448	  exp->X_add_symbol = symbol;
22449	  exp->X_add_number = 0;
22450	}
22451      /* FALLTHROUGH */
22452    case O_symbol:
22453    case O_add:
22454    case O_subtract:
22455      new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
22456			     (enum bfd_reloc_code_real) reloc);
22457      break;
22458
22459    default:
22460      new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
22461				  pc_rel, (enum bfd_reloc_code_real) reloc);
22462      break;
22463    }
22464
22465  /* Mark whether the fix is to a THUMB instruction, or an ARM
22466     instruction.  */
22467  new_fix->tc_fix_data = thumb_mode;
22468}
22469
22470/* Create a frg for an instruction requiring relaxation.  */
22471static void
22472output_relax_insn (void)
22473{
22474  char * to;
22475  symbolS *sym;
22476  int offset;
22477
22478  /* The size of the instruction is unknown, so tie the debug info to the
22479     start of the instruction.  */
22480  dwarf2_emit_insn (0);
22481
22482  switch (inst.relocs[0].exp.X_op)
22483    {
22484    case O_symbol:
22485      sym = inst.relocs[0].exp.X_add_symbol;
22486      offset = inst.relocs[0].exp.X_add_number;
22487      break;
22488    case O_constant:
22489      sym = NULL;
22490      offset = inst.relocs[0].exp.X_add_number;
22491      break;
22492    default:
22493      sym = make_expr_symbol (&inst.relocs[0].exp);
22494      offset = 0;
22495      break;
22496  }
22497  to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
22498		 inst.relax, sym, offset, NULL/*offset, opcode*/);
22499  md_number_to_chars (to, inst.instruction, THUMB_SIZE);
22500}
22501
22502/* Write a 32-bit thumb instruction to buf.  */
22503static void
22504put_thumb32_insn (char * buf, unsigned long insn)
22505{
22506  md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
22507  md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
22508}
22509
22510static void
22511output_inst (const char * str)
22512{
22513  char * to = NULL;
22514
22515  if (inst.error)
22516    {
22517      as_bad ("%s -- `%s'", inst.error, str);
22518      return;
22519    }
22520  if (inst.relax)
22521    {
22522      output_relax_insn ();
22523      return;
22524    }
22525  if (inst.size == 0)
22526    return;
22527
22528  to = frag_more (inst.size);
22529  /* PR 9814: Record the thumb mode into the current frag so that we know
22530     what type of NOP padding to use, if necessary.  We override any previous
22531     setting so that if the mode has changed then the NOPS that we use will
22532     match the encoding of the last instruction in the frag.  */
22533  frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
22534
22535  if (thumb_mode && (inst.size > THUMB_SIZE))
22536    {
22537      gas_assert (inst.size == (2 * THUMB_SIZE));
22538      put_thumb32_insn (to, inst.instruction);
22539    }
22540  else if (inst.size > INSN_SIZE)
22541    {
22542      gas_assert (inst.size == (2 * INSN_SIZE));
22543      md_number_to_chars (to, inst.instruction, INSN_SIZE);
22544      md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
22545    }
22546  else
22547    md_number_to_chars (to, inst.instruction, inst.size);
22548
22549  int r;
22550  for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
22551    {
22552      if (inst.relocs[r].type != BFD_RELOC_UNUSED)
22553	fix_new_arm (frag_now, to - frag_now->fr_literal,
22554		     inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
22555		     inst.relocs[r].type);
22556    }
22557
22558  dwarf2_emit_insn (inst.size);
22559}
22560
22561static char *
22562output_it_inst (int cond, int mask, char * to)
22563{
22564  unsigned long instruction = 0xbf00;
22565
22566  mask &= 0xf;
22567  instruction |= mask;
22568  instruction |= cond << 4;
22569
22570  if (to == NULL)
22571    {
22572      to = frag_more (2);
22573#ifdef OBJ_ELF
22574      dwarf2_emit_insn (2);
22575#endif
22576    }
22577
22578  md_number_to_chars (to, instruction, 2);
22579
22580  return to;
22581}
22582
22583/* Tag values used in struct asm_opcode's tag field.  */
22584enum opcode_tag
22585{
22586  OT_unconditional,	/* Instruction cannot be conditionalized.
22587			   The ARM condition field is still 0xE.  */
22588  OT_unconditionalF,	/* Instruction cannot be conditionalized
22589			   and carries 0xF in its ARM condition field.  */
22590  OT_csuffix,		/* Instruction takes a conditional suffix.  */
22591  OT_csuffixF,		/* Some forms of the instruction take a scalar
22592			   conditional suffix, others place 0xF where the
22593			   condition field would be, others take a vector
22594			   conditional suffix.  */
22595  OT_cinfix3,		/* Instruction takes a conditional infix,
22596			   beginning at character index 3.  (In
22597			   unified mode, it becomes a suffix.)  */
22598  OT_cinfix3_deprecated, /* The same as OT_cinfix3.  This is used for
22599			    tsts, cmps, cmns, and teqs. */
22600  OT_cinfix3_legacy,	/* Legacy instruction takes a conditional infix at
22601			   character index 3, even in unified mode.  Used for
22602			   legacy instructions where suffix and infix forms
22603			   may be ambiguous.  */
22604  OT_csuf_or_in3,	/* Instruction takes either a conditional
22605			   suffix or an infix at character index 3.  */
22606  OT_odd_infix_unc,	/* This is the unconditional variant of an
22607			   instruction that takes a conditional infix
22608			   at an unusual position.  In unified mode,
22609			   this variant will accept a suffix.  */
22610  OT_odd_infix_0	/* Values greater than or equal to OT_odd_infix_0
22611			   are the conditional variants of instructions that
22612			   take conditional infixes in unusual positions.
22613			   The infix appears at character index
22614			   (tag - OT_odd_infix_0).  These are not accepted
22615			   in unified mode.  */
22616};
22617
22618/* Subroutine of md_assemble, responsible for looking up the primary
22619   opcode from the mnemonic the user wrote.  STR points to the
22620   beginning of the mnemonic.
22621
22622   This is not simply a hash table lookup, because of conditional
22623   variants.  Most instructions have conditional variants, which are
22624   expressed with a _conditional affix_ to the mnemonic.  If we were
22625   to encode each conditional variant as a literal string in the opcode
22626   table, it would have approximately 20,000 entries.
22627
22628   Most mnemonics take this affix as a suffix, and in unified syntax,
22629   'most' is upgraded to 'all'.  However, in the divided syntax, some
22630   instructions take the affix as an infix, notably the s-variants of
22631   the arithmetic instructions.  Of those instructions, all but six
22632   have the infix appear after the third character of the mnemonic.
22633
22634   Accordingly, the algorithm for looking up primary opcodes given
22635   an identifier is:
22636
22637   1. Look up the identifier in the opcode table.
22638      If we find a match, go to step U.
22639
22640   2. Look up the last two characters of the identifier in the
22641      conditions table.  If we find a match, look up the first N-2
22642      characters of the identifier in the opcode table.  If we
22643      find a match, go to step CE.
22644
22645   3. Look up the fourth and fifth characters of the identifier in
22646      the conditions table.  If we find a match, extract those
22647      characters from the identifier, and look up the remaining
22648      characters in the opcode table.  If we find a match, go
22649      to step CM.
22650
22651   4. Fail.
22652
22653   U. Examine the tag field of the opcode structure, in case this is
22654      one of the six instructions with its conditional infix in an
22655      unusual place.  If it is, the tag tells us where to find the
22656      infix; look it up in the conditions table and set inst.cond
22657      accordingly.  Otherwise, this is an unconditional instruction.
22658      Again set inst.cond accordingly.  Return the opcode structure.
22659
22660  CE. Examine the tag field to make sure this is an instruction that
22661      should receive a conditional suffix.  If it is not, fail.
22662      Otherwise, set inst.cond from the suffix we already looked up,
22663      and return the opcode structure.
22664
22665  CM. Examine the tag field to make sure this is an instruction that
22666      should receive a conditional infix after the third character.
22667      If it is not, fail.  Otherwise, undo the edits to the current
22668      line of input and proceed as for case CE.  */
22669
22670static const struct asm_opcode *
22671opcode_lookup (char **str)
22672{
22673  char *end, *base;
22674  char *affix;
22675  const struct asm_opcode *opcode;
22676  const struct asm_cond *cond;
22677  char save[2];
22678
22679  /* Scan up to the end of the mnemonic, which must end in white space,
22680     '.' (in unified mode, or for Neon/VFP instructions), or end of string.  */
22681  for (base = end = *str; *end != '\0'; end++)
22682    if (*end == ' ' || *end == '.')
22683      break;
22684
22685  if (end == base)
22686    return NULL;
22687
22688  /* Handle a possible width suffix and/or Neon type suffix.  */
22689  if (end[0] == '.')
22690    {
22691      int offset = 2;
22692
22693      /* The .w and .n suffixes are only valid if the unified syntax is in
22694	 use.  */
22695      if (unified_syntax && end[1] == 'w')
22696	inst.size_req = 4;
22697      else if (unified_syntax && end[1] == 'n')
22698	inst.size_req = 2;
22699      else
22700	offset = 0;
22701
22702      inst.vectype.elems = 0;
22703
22704      *str = end + offset;
22705
22706      if (end[offset] == '.')
22707	{
22708	  /* See if we have a Neon type suffix (possible in either unified or
22709	     non-unified ARM syntax mode).  */
22710	  if (parse_neon_type (&inst.vectype, str) == FAIL)
22711	    return NULL;
22712	}
22713      else if (end[offset] != '\0' && end[offset] != ' ')
22714	return NULL;
22715    }
22716  else
22717    *str = end;
22718
22719  /* Look for unaffixed or special-case affixed mnemonic.  */
22720  opcode = (const struct asm_opcode *) str_hash_find_n (arm_ops_hsh, base,
22721							end - base);
22722  cond = NULL;
22723  if (opcode)
22724    {
22725      /* step U */
22726      if (opcode->tag < OT_odd_infix_0)
22727	{
22728	  inst.cond = COND_ALWAYS;
22729	  return opcode;
22730	}
22731
22732      if (warn_on_deprecated && unified_syntax)
22733	as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22734      affix = base + (opcode->tag - OT_odd_infix_0);
22735      cond = (const struct asm_cond *) str_hash_find_n (arm_cond_hsh, affix, 2);
22736      gas_assert (cond);
22737
22738      inst.cond = cond->value;
22739      return opcode;
22740    }
22741 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
22742   {
22743    /* Cannot have a conditional suffix on a mnemonic of less than a character.
22744     */
22745    if (end - base < 2)
22746      return NULL;
22747     affix = end - 1;
22748     cond = (const struct asm_cond *) str_hash_find_n (arm_vcond_hsh, affix, 1);
22749     opcode = (const struct asm_opcode *) str_hash_find_n (arm_ops_hsh, base,
22750							   affix - base);
22751     /* If this opcode can not be vector predicated then don't accept it with a
22752	vector predication code.  */
22753     if (opcode && !opcode->mayBeVecPred)
22754       opcode = NULL;
22755   }
22756  if (!opcode || !cond)
22757    {
22758      /* Cannot have a conditional suffix on a mnemonic of less than two
22759	 characters.  */
22760      if (end - base < 3)
22761	return NULL;
22762
22763      /* Look for suffixed mnemonic.  */
22764      affix = end - 2;
22765      cond = (const struct asm_cond *) str_hash_find_n (arm_cond_hsh, affix, 2);
22766      opcode = (const struct asm_opcode *) str_hash_find_n (arm_ops_hsh, base,
22767							    affix - base);
22768    }
22769
22770  if (opcode && cond)
22771    {
22772      /* step CE */
22773      switch (opcode->tag)
22774	{
22775	case OT_cinfix3_legacy:
22776	  /* Ignore conditional suffixes matched on infix only mnemonics.  */
22777	  break;
22778
22779	case OT_cinfix3:
22780	case OT_cinfix3_deprecated:
22781	case OT_odd_infix_unc:
22782	  if (!unified_syntax)
22783	    return NULL;
22784	  /* Fall through.  */
22785
22786	case OT_csuffix:
22787	case OT_csuffixF:
22788	case OT_csuf_or_in3:
22789	  inst.cond = cond->value;
22790	  return opcode;
22791
22792	case OT_unconditional:
22793	case OT_unconditionalF:
22794	  if (thumb_mode)
22795	    inst.cond = cond->value;
22796	  else
22797	    {
22798	      /* Delayed diagnostic.  */
22799	      inst.error = BAD_COND;
22800	      inst.cond = COND_ALWAYS;
22801	    }
22802	  return opcode;
22803
22804	default:
22805	  return NULL;
22806	}
22807    }
22808
22809  /* Cannot have a usual-position infix on a mnemonic of less than
22810     six characters (five would be a suffix).  */
22811  if (end - base < 6)
22812    return NULL;
22813
22814  /* Look for infixed mnemonic in the usual position.  */
22815  affix = base + 3;
22816  cond = (const struct asm_cond *) str_hash_find_n (arm_cond_hsh, affix, 2);
22817  if (!cond)
22818    return NULL;
22819
22820  memcpy (save, affix, 2);
22821  memmove (affix, affix + 2, (end - affix) - 2);
22822  opcode = (const struct asm_opcode *) str_hash_find_n (arm_ops_hsh, base,
22823							(end - base) - 2);
22824  memmove (affix + 2, affix, (end - affix) - 2);
22825  memcpy (affix, save, 2);
22826
22827  if (opcode
22828      && (opcode->tag == OT_cinfix3
22829	  || opcode->tag == OT_cinfix3_deprecated
22830	  || opcode->tag == OT_csuf_or_in3
22831	  || opcode->tag == OT_cinfix3_legacy))
22832    {
22833      /* Step CM.  */
22834      if (warn_on_deprecated && unified_syntax
22835	  && (opcode->tag == OT_cinfix3
22836	      || opcode->tag == OT_cinfix3_deprecated))
22837	as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22838
22839      inst.cond = cond->value;
22840      return opcode;
22841    }
22842
22843  return NULL;
22844}
22845
22846/* This function generates an initial IT instruction, leaving its block
22847   virtually open for the new instructions. Eventually,
22848   the mask will be updated by now_pred_add_mask () each time
22849   a new instruction needs to be included in the IT block.
22850   Finally, the block is closed with close_automatic_it_block ().
22851   The block closure can be requested either from md_assemble (),
22852   a tencode (), or due to a label hook.  */
22853
22854static void
22855new_automatic_it_block (int cond)
22856{
22857  now_pred.state = AUTOMATIC_PRED_BLOCK;
22858  now_pred.mask = 0x18;
22859  now_pred.cc = cond;
22860  now_pred.block_length = 1;
22861  mapping_state (MAP_THUMB);
22862  now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
22863  now_pred.warn_deprecated = false;
22864  now_pred.insn_cond = true;
22865}
22866
22867/* Close an automatic IT block.
22868   See comments in new_automatic_it_block ().  */
22869
22870static void
22871close_automatic_it_block (void)
22872{
22873  now_pred.mask = 0x10;
22874  now_pred.block_length = 0;
22875}
22876
22877/* Update the mask of the current automatically-generated IT
22878   instruction. See comments in new_automatic_it_block ().  */
22879
22880static void
22881now_pred_add_mask (int cond)
22882{
22883#define CLEAR_BIT(value, nbit)  ((value) & ~(1 << (nbit)))
22884#define SET_BIT_VALUE(value, bitvalue, nbit)  (CLEAR_BIT (value, nbit) \
22885					      | ((bitvalue) << (nbit)))
22886  const int resulting_bit = (cond & 1);
22887
22888  now_pred.mask &= 0xf;
22889  now_pred.mask = SET_BIT_VALUE (now_pred.mask,
22890				   resulting_bit,
22891				  (5 - now_pred.block_length));
22892  now_pred.mask = SET_BIT_VALUE (now_pred.mask,
22893				   1,
22894				   ((5 - now_pred.block_length) - 1));
22895  output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn);
22896
22897#undef CLEAR_BIT
22898#undef SET_BIT_VALUE
22899}
22900
22901/* The IT blocks handling machinery is accessed through the these functions:
22902     it_fsm_pre_encode ()               from md_assemble ()
22903     set_pred_insn_type ()		optional, from the tencode functions
22904     set_pred_insn_type_last ()		ditto
22905     in_pred_block ()			ditto
22906     it_fsm_post_encode ()              from md_assemble ()
22907     force_automatic_it_block_close ()  from label handling functions
22908
22909   Rationale:
22910     1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22911	initializing the IT insn type with a generic initial value depending
22912	on the inst.condition.
22913     2) During the tencode function, two things may happen:
22914	a) The tencode function overrides the IT insn type by
22915	   calling either set_pred_insn_type (type) or
22916	   set_pred_insn_type_last ().
22917	b) The tencode function queries the IT block state by
22918	   calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22919
22920	Both set_pred_insn_type and in_pred_block run the internal FSM state
22921	handling function (handle_pred_state), because: a) setting the IT insn
22922	type may incur in an invalid state (exiting the function),
22923	and b) querying the state requires the FSM to be updated.
22924	Specifically we want to avoid creating an IT block for conditional
22925	branches, so it_fsm_pre_encode is actually a guess and we can't
22926	determine whether an IT block is required until the tencode () routine
22927	has decided what type of instruction this actually it.
22928	Because of this, if set_pred_insn_type and in_pred_block have to be
22929	used, set_pred_insn_type has to be called first.
22930
22931	set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22932	that determines the insn IT type depending on the inst.cond code.
22933	When a tencode () routine encodes an instruction that can be
22934	either outside an IT block, or, in the case of being inside, has to be
22935	the last one, set_pred_insn_type_last () will determine the proper
22936	IT instruction type based on the inst.cond code. Otherwise,
22937	set_pred_insn_type can be called for overriding that logic or
22938	for covering other cases.
22939
22940	Calling handle_pred_state () may not transition the IT block state to
22941	OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22942	still queried. Instead, if the FSM determines that the state should
22943	be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22944	after the tencode () function: that's what it_fsm_post_encode () does.
22945
22946	Since in_pred_block () calls the state handling function to get an
22947	updated state, an error may occur (due to invalid insns combination).
22948	In that case, inst.error is set.
22949	Therefore, inst.error has to be checked after the execution of
22950	the tencode () routine.
22951
22952     3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22953	any pending state change (if any) that didn't take place in
22954	handle_pred_state () as explained above.  */
22955
22956static void
22957it_fsm_pre_encode (void)
22958{
22959  if (inst.cond != COND_ALWAYS)
22960    inst.pred_insn_type =  INSIDE_IT_INSN;
22961  else
22962    inst.pred_insn_type = OUTSIDE_PRED_INSN;
22963
22964  now_pred.state_handled = 0;
22965}
22966
22967/* IT state FSM handling function.  */
22968/* MVE instructions and non-MVE instructions are handled differently because of
22969   the introduction of VPT blocks.
22970   Specifications say that any non-MVE instruction inside a VPT block is
22971   UNPREDICTABLE, with the exception of the BKPT instruction.  Whereas most MVE
22972   instructions are deemed to be UNPREDICTABLE if inside an IT block.  For the
22973   few exceptions we have MVE_UNPREDICABLE_INSN.
22974   The error messages provided depending on the different combinations possible
22975   are described in the cases below:
22976   For 'most' MVE instructions:
22977   1) In an IT block, with an IT code: syntax error
22978   2) In an IT block, with a VPT code: error: must be in a VPT block
22979   3) In an IT block, with no code: warning: UNPREDICTABLE
22980   4) In a VPT block, with an IT code: syntax error
22981   5) In a VPT block, with a VPT code: OK!
22982   6) In a VPT block, with no code: error: missing code
22983   7) Outside a pred block, with an IT code: error: syntax error
22984   8) Outside a pred block, with a VPT code: error: should be in a VPT block
22985   9) Outside a pred block, with no code: OK!
22986   For non-MVE instructions:
22987   10) In an IT block, with an IT code: OK!
22988   11) In an IT block, with a VPT code: syntax error
22989   12) In an IT block, with no code: error: missing code
22990   13) In a VPT block, with an IT code: error: should be in an IT block
22991   14) In a VPT block, with a VPT code: syntax error
22992   15) In a VPT block, with no code: UNPREDICTABLE
22993   16) Outside a pred block, with an IT code: error: should be in an IT block
22994   17) Outside a pred block, with a VPT code: syntax error
22995   18) Outside a pred block, with no code: OK!
22996 */
22997
22998
22999static int
23000handle_pred_state (void)
23001{
23002  now_pred.state_handled = 1;
23003  now_pred.insn_cond = false;
23004
23005  switch (now_pred.state)
23006    {
23007    case OUTSIDE_PRED_BLOCK:
23008      switch (inst.pred_insn_type)
23009	{
23010	case MVE_UNPREDICABLE_INSN:
23011	case MVE_OUTSIDE_PRED_INSN:
23012	  if (inst.cond < COND_ALWAYS)
23013	    {
23014	      /* Case 7: Outside a pred block, with an IT code: error: syntax
23015		 error.  */
23016	      inst.error = BAD_SYNTAX;
23017	      return FAIL;
23018	    }
23019	  /* Case 9:  Outside a pred block, with no code: OK!  */
23020	  break;
23021	case OUTSIDE_PRED_INSN:
23022	  if (inst.cond > COND_ALWAYS)
23023	    {
23024	      /* Case 17:  Outside a pred block, with a VPT code: syntax error.
23025	       */
23026	      inst.error = BAD_SYNTAX;
23027	      return FAIL;
23028	    }
23029	  /* Case 18: Outside a pred block, with no code: OK!  */
23030	  break;
23031
23032	case INSIDE_VPT_INSN:
23033	  /* Case 8: Outside a pred block, with a VPT code: error: should be in
23034	     a VPT block.  */
23035	  inst.error = BAD_OUT_VPT;
23036	  return FAIL;
23037
23038	case INSIDE_IT_INSN:
23039	case INSIDE_IT_LAST_INSN:
23040	  if (inst.cond < COND_ALWAYS)
23041	    {
23042	      /* Case 16: Outside a pred block, with an IT code: error: should
23043		 be in an IT block.  */
23044	      if (thumb_mode == 0)
23045		{
23046		  if (unified_syntax
23047		      && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
23048		    as_tsktsk (_("Warning: conditional outside an IT block"\
23049				 " for Thumb."));
23050		}
23051	      else
23052		{
23053		  if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
23054		      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
23055		    {
23056		      /* Automatically generate the IT instruction.  */
23057		      new_automatic_it_block (inst.cond);
23058		      if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
23059			close_automatic_it_block ();
23060		    }
23061		  else
23062		    {
23063		      inst.error = BAD_OUT_IT;
23064		      return FAIL;
23065		    }
23066		}
23067	      break;
23068	    }
23069	  else if (inst.cond > COND_ALWAYS)
23070	    {
23071	      /* Case 17: Outside a pred block, with a VPT code: syntax error.
23072	       */
23073	      inst.error = BAD_SYNTAX;
23074	      return FAIL;
23075	    }
23076	  else
23077	    gas_assert (0);
23078	case IF_INSIDE_IT_LAST_INSN:
23079	case NEUTRAL_IT_INSN:
23080	  break;
23081
23082	case VPT_INSN:
23083	  if (inst.cond != COND_ALWAYS)
23084	    first_error (BAD_SYNTAX);
23085	  now_pred.state = MANUAL_PRED_BLOCK;
23086	  now_pred.block_length = 0;
23087	  now_pred.type = VECTOR_PRED;
23088	  now_pred.cc = 0;
23089	  break;
23090	case IT_INSN:
23091	  now_pred.state = MANUAL_PRED_BLOCK;
23092	  now_pred.block_length = 0;
23093	  now_pred.type = SCALAR_PRED;
23094	  break;
23095	}
23096      break;
23097
23098    case AUTOMATIC_PRED_BLOCK:
23099      /* Three things may happen now:
23100	 a) We should increment current it block size;
23101	 b) We should close current it block (closing insn or 4 insns);
23102	 c) We should close current it block and start a new one (due
23103	 to incompatible conditions or
23104	 4 insns-length block reached).  */
23105
23106      switch (inst.pred_insn_type)
23107	{
23108	case INSIDE_VPT_INSN:
23109	case VPT_INSN:
23110	case MVE_UNPREDICABLE_INSN:
23111	case MVE_OUTSIDE_PRED_INSN:
23112	  gas_assert (0);
23113	case OUTSIDE_PRED_INSN:
23114	  /* The closure of the block shall happen immediately,
23115	     so any in_pred_block () call reports the block as closed.  */
23116	  force_automatic_it_block_close ();
23117	  break;
23118
23119	case INSIDE_IT_INSN:
23120	case INSIDE_IT_LAST_INSN:
23121	case IF_INSIDE_IT_LAST_INSN:
23122	  now_pred.block_length++;
23123
23124	  if (now_pred.block_length > 4
23125	      || !now_pred_compatible (inst.cond))
23126	    {
23127	      force_automatic_it_block_close ();
23128	      if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
23129		new_automatic_it_block (inst.cond);
23130	    }
23131	  else
23132	    {
23133	      now_pred.insn_cond = true;
23134	      now_pred_add_mask (inst.cond);
23135	    }
23136
23137	  if (now_pred.state == AUTOMATIC_PRED_BLOCK
23138	      && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
23139		  || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
23140	    close_automatic_it_block ();
23141	  break;
23142
23143	  /* Fallthrough.  */
23144	case NEUTRAL_IT_INSN:
23145	  now_pred.block_length++;
23146	  now_pred.insn_cond = true;
23147
23148	  if (now_pred.block_length > 4)
23149	    force_automatic_it_block_close ();
23150	  else
23151	    now_pred_add_mask (now_pred.cc & 1);
23152	  break;
23153
23154	case IT_INSN:
23155	  close_automatic_it_block ();
23156	  now_pred.state = MANUAL_PRED_BLOCK;
23157	  break;
23158	}
23159      break;
23160
23161    case MANUAL_PRED_BLOCK:
23162      {
23163	unsigned int cond;
23164	int is_last;
23165	if (now_pred.type == SCALAR_PRED)
23166	  {
23167	    /* Check conditional suffixes.  */
23168	    cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1;
23169	    now_pred.mask <<= 1;
23170	    now_pred.mask &= 0x1f;
23171	    is_last = (now_pred.mask == 0x10);
23172	  }
23173	else
23174	  {
23175	    now_pred.cc ^= (now_pred.mask >> 4);
23176	    cond = now_pred.cc + 0xf;
23177	    now_pred.mask <<= 1;
23178	    now_pred.mask &= 0x1f;
23179	    is_last = now_pred.mask == 0x10;
23180	  }
23181	now_pred.insn_cond = true;
23182
23183	switch (inst.pred_insn_type)
23184	  {
23185	  case OUTSIDE_PRED_INSN:
23186	    if (now_pred.type == SCALAR_PRED)
23187	      {
23188		if (inst.cond == COND_ALWAYS)
23189		  {
23190		    /* Case 12: In an IT block, with no code: error: missing
23191		       code.  */
23192		    inst.error = BAD_NOT_IT;
23193		    return FAIL;
23194		  }
23195		else if (inst.cond > COND_ALWAYS)
23196		  {
23197		    /* Case 11: In an IT block, with a VPT code: syntax error.
23198		     */
23199		    inst.error = BAD_SYNTAX;
23200		    return FAIL;
23201		  }
23202		else if (thumb_mode)
23203		  {
23204		    /* This is for some special cases where a non-MVE
23205		       instruction is not allowed in an IT block, such as cbz,
23206		       but are put into one with a condition code.
23207		       You could argue this should be a syntax error, but we
23208		       gave the 'not allowed in IT block' diagnostic in the
23209		       past so we will keep doing so.  */
23210		    inst.error = BAD_NOT_IT;
23211		    return FAIL;
23212		  }
23213		break;
23214	      }
23215	    else
23216	      {
23217		/* Case 15: In a VPT block, with no code: UNPREDICTABLE.  */
23218		as_tsktsk (MVE_NOT_VPT);
23219		return SUCCESS;
23220	      }
23221	  case MVE_OUTSIDE_PRED_INSN:
23222	    if (now_pred.type == SCALAR_PRED)
23223	      {
23224		if (inst.cond == COND_ALWAYS)
23225		  {
23226		    /* Case 3: In an IT block, with no code: warning:
23227		       UNPREDICTABLE.  */
23228		    as_tsktsk (MVE_NOT_IT);
23229		    return SUCCESS;
23230		  }
23231		else if (inst.cond < COND_ALWAYS)
23232		  {
23233		    /* Case 1: In an IT block, with an IT code: syntax error.
23234		     */
23235		    inst.error = BAD_SYNTAX;
23236		    return FAIL;
23237		  }
23238		else
23239		  gas_assert (0);
23240	      }
23241	    else
23242	      {
23243		if (inst.cond < COND_ALWAYS)
23244		  {
23245		    /* Case 4: In a VPT block, with an IT code: syntax error.
23246		     */
23247		    inst.error = BAD_SYNTAX;
23248		    return FAIL;
23249		  }
23250		else if (inst.cond == COND_ALWAYS)
23251		  {
23252		    /* Case 6: In a VPT block, with no code: error: missing
23253		       code.  */
23254		    inst.error = BAD_NOT_VPT;
23255		    return FAIL;
23256		  }
23257		else
23258		  {
23259		    gas_assert (0);
23260		  }
23261	      }
23262	  case MVE_UNPREDICABLE_INSN:
23263	    as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
23264	    return SUCCESS;
23265	  case INSIDE_IT_INSN:
23266	    if (inst.cond > COND_ALWAYS)
23267	      {
23268		/* Case 11: In an IT block, with a VPT code: syntax error.  */
23269		/* Case 14: In a VPT block, with a VPT code: syntax error.  */
23270		inst.error = BAD_SYNTAX;
23271		return FAIL;
23272	      }
23273	    else if (now_pred.type == SCALAR_PRED)
23274	      {
23275		/* Case 10: In an IT block, with an IT code: OK!  */
23276		if (cond != inst.cond)
23277		  {
23278		    inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
23279		      BAD_VPT_COND;
23280		    return FAIL;
23281		  }
23282	      }
23283	    else
23284	      {
23285		/* Case 13: In a VPT block, with an IT code: error: should be
23286		   in an IT block.  */
23287		inst.error = BAD_OUT_IT;
23288		return FAIL;
23289	      }
23290	    break;
23291
23292	  case INSIDE_VPT_INSN:
23293	    if (now_pred.type == SCALAR_PRED)
23294	      {
23295		/* Case 2: In an IT block, with a VPT code: error: must be in a
23296		   VPT block.  */
23297		inst.error = BAD_OUT_VPT;
23298		return FAIL;
23299	      }
23300	    /* Case 5:  In a VPT block, with a VPT code: OK!  */
23301	    else if (cond != inst.cond)
23302	      {
23303		inst.error = BAD_VPT_COND;
23304		return FAIL;
23305	      }
23306	    break;
23307	  case INSIDE_IT_LAST_INSN:
23308	  case IF_INSIDE_IT_LAST_INSN:
23309	    if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
23310	      {
23311		/* Case 4: In a VPT block, with an IT code: syntax error.  */
23312		/* Case 11: In an IT block, with a VPT code: syntax error.  */
23313		inst.error = BAD_SYNTAX;
23314		return FAIL;
23315	      }
23316	    else if (cond != inst.cond)
23317	      {
23318		inst.error = BAD_IT_COND;
23319		return FAIL;
23320	      }
23321	    if (!is_last)
23322	      {
23323		inst.error = BAD_BRANCH;
23324		return FAIL;
23325	      }
23326	    break;
23327
23328	  case NEUTRAL_IT_INSN:
23329	    /* The BKPT instruction is unconditional even in a IT or VPT
23330	       block.  */
23331	    break;
23332
23333	  case IT_INSN:
23334	    if (now_pred.type == SCALAR_PRED)
23335	      {
23336		inst.error = BAD_IT_IT;
23337		return FAIL;
23338	      }
23339	    /* fall through.  */
23340	  case VPT_INSN:
23341	    if (inst.cond == COND_ALWAYS)
23342	      {
23343		/* Executing a VPT/VPST instruction inside an IT block or a
23344		   VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23345		 */
23346		if (now_pred.type == SCALAR_PRED)
23347		  as_tsktsk (MVE_NOT_IT);
23348		else
23349		  as_tsktsk (MVE_NOT_VPT);
23350		return SUCCESS;
23351	      }
23352	    else
23353	      {
23354		/* VPT/VPST do not accept condition codes.  */
23355		inst.error = BAD_SYNTAX;
23356		return FAIL;
23357	      }
23358	  }
23359	}
23360      break;
23361    }
23362
23363  return SUCCESS;
23364}
23365
23366struct depr_insn_mask
23367{
23368  unsigned long pattern;
23369  unsigned long mask;
23370  const char* description;
23371};
23372
23373/* List of 16-bit instruction patterns deprecated in an IT block in
23374   ARMv8.  */
23375static const struct depr_insn_mask depr_it_insns[] = {
23376  { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23377  { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23378  { 0xa000, 0xb800, N_("ADR") },
23379  { 0x4800, 0xf800, N_("Literal loads") },
23380  { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23381  { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23382  /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23383     field in asm_opcode. 'tvalue' is used at the stage this check happen.  */
23384  { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23385  { 0, 0, NULL }
23386};
23387
23388static void
23389it_fsm_post_encode (void)
23390{
23391  int is_last;
23392
23393  if (!now_pred.state_handled)
23394    handle_pred_state ();
23395
23396  if (now_pred.insn_cond
23397      && warn_on_restrict_it
23398      && !now_pred.warn_deprecated
23399      && warn_on_deprecated
23400      && (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
23401          || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8r))
23402      && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
23403    {
23404      if (inst.instruction >= 0x10000)
23405	{
23406	  as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23407		     "performance deprecated in ARMv8-A and ARMv8-R"));
23408	  now_pred.warn_deprecated = true;
23409	}
23410      else
23411	{
23412	  const struct depr_insn_mask *p = depr_it_insns;
23413
23414	  while (p->mask != 0)
23415	    {
23416	      if ((inst.instruction & p->mask) == p->pattern)
23417		{
23418		  as_tsktsk (_("IT blocks containing 16-bit Thumb "
23419			       "instructions of the following class are "
23420			       "performance deprecated in ARMv8-A and "
23421			       "ARMv8-R: %s"), p->description);
23422		  now_pred.warn_deprecated = true;
23423		  break;
23424		}
23425
23426	      ++p;
23427	    }
23428	}
23429
23430      if (now_pred.block_length > 1)
23431	{
23432	  as_tsktsk (_("IT blocks containing more than one conditional "
23433		     "instruction are performance deprecated in ARMv8-A and "
23434		     "ARMv8-R"));
23435	  now_pred.warn_deprecated = true;
23436	}
23437    }
23438
23439    is_last = (now_pred.mask == 0x10);
23440    if (is_last)
23441      {
23442	now_pred.state = OUTSIDE_PRED_BLOCK;
23443	now_pred.mask = 0;
23444      }
23445}
23446
23447static void
23448force_automatic_it_block_close (void)
23449{
23450  if (now_pred.state == AUTOMATIC_PRED_BLOCK)
23451    {
23452      close_automatic_it_block ();
23453      now_pred.state = OUTSIDE_PRED_BLOCK;
23454      now_pred.mask = 0;
23455    }
23456}
23457
23458static int
23459in_pred_block (void)
23460{
23461  if (!now_pred.state_handled)
23462    handle_pred_state ();
23463
23464  return now_pred.state != OUTSIDE_PRED_BLOCK;
23465}
23466
23467/* Whether OPCODE only has T32 encoding.  Since this function is only used by
23468   t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23469   here, hence the "known" in the function name.  */
23470
23471static bool
23472known_t32_only_insn (const struct asm_opcode *opcode)
23473{
23474  /* Original Thumb-1 wide instruction.  */
23475  if (opcode->tencode == do_t_blx
23476      || opcode->tencode == do_t_branch23
23477      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
23478      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
23479    return true;
23480
23481  /* Wide-only instruction added to ARMv8-M Baseline.  */
23482  if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
23483      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
23484      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
23485      || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
23486    return true;
23487
23488  return false;
23489}
23490
23491/* Whether wide instruction variant can be used if available for a valid OPCODE
23492   in ARCH.  */
23493
23494static bool
23495t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
23496{
23497  if (known_t32_only_insn (opcode))
23498    return true;
23499
23500  /* Instruction with narrow and wide encoding added to ARMv8-M.  Availability
23501     of variant T3 of B.W is checked in do_t_branch.  */
23502  if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
23503      && opcode->tencode == do_t_branch)
23504    return true;
23505
23506  /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit.  */
23507  if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
23508      && opcode->tencode == do_t_mov_cmp
23509      /* Make sure CMP instruction is not affected.  */
23510      && opcode->aencode == do_mov)
23511    return true;
23512
23513  /* Wide instruction variants of all instructions with narrow *and* wide
23514     variants become available with ARMv6t2.  Other opcodes are either
23515     narrow-only or wide-only and are thus available if OPCODE is valid.  */
23516  if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
23517    return true;
23518
23519  /* OPCODE with narrow only instruction variant or wide variant not
23520     available.  */
23521  return false;
23522}
23523
23524void
23525md_assemble (char *str)
23526{
23527  char *p = str;
23528  const struct asm_opcode * opcode;
23529
23530  /* Align the previous label if needed.  */
23531  if (last_label_seen != NULL)
23532    {
23533      symbol_set_frag (last_label_seen, frag_now);
23534      S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
23535      S_SET_SEGMENT (last_label_seen, now_seg);
23536    }
23537
23538  memset (&inst, '\0', sizeof (inst));
23539  int r;
23540  for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
23541    inst.relocs[r].type = BFD_RELOC_UNUSED;
23542
23543  opcode = opcode_lookup (&p);
23544  if (!opcode)
23545    {
23546      /* It wasn't an instruction, but it might be a register alias of
23547	 the form alias .req reg, or a Neon .dn/.qn directive.  */
23548      if (! create_register_alias (str, p)
23549	  && ! create_neon_reg_alias (str, p))
23550	as_bad (_("bad instruction `%s'"), str);
23551
23552      return;
23553    }
23554
23555  if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
23556    as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23557
23558  /* The value which unconditional instructions should have in place of the
23559     condition field.  */
23560  inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1u;
23561
23562  if (thumb_mode)
23563    {
23564      arm_feature_set variant;
23565
23566      variant = cpu_variant;
23567      /* Only allow coprocessor instructions on Thumb-2 capable devices.  */
23568      if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
23569	ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
23570      /* Check that this instruction is supported for this CPU.  */
23571      if (!opcode->tvariant
23572	  || (thumb_mode == 1
23573	      && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
23574	{
23575	  if (opcode->tencode == do_t_swi)
23576	    as_bad (_("SVC is not permitted on this architecture"));
23577	  else
23578	    as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
23579	  return;
23580	}
23581      if (inst.cond != COND_ALWAYS && !unified_syntax
23582	  && opcode->tencode != do_t_branch)
23583	{
23584	  as_bad (_("Thumb does not support conditional execution"));
23585	  return;
23586	}
23587
23588      /* Two things are addressed here:
23589	 1) Implicit require narrow instructions on Thumb-1.
23590	    This avoids relaxation accidentally introducing Thumb-2
23591	    instructions.
23592	 2) Reject wide instructions in non Thumb-2 cores.
23593
23594	 Only instructions with narrow and wide variants need to be handled
23595	 but selecting all non wide-only instructions is easier.  */
23596      if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
23597	  && !t32_insn_ok (variant, opcode))
23598	{
23599	  if (inst.size_req == 0)
23600	    inst.size_req = 2;
23601	  else if (inst.size_req == 4)
23602	    {
23603	      if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
23604		as_bad (_("selected processor does not support 32bit wide "
23605			  "variant of instruction `%s'"), str);
23606	      else
23607		as_bad (_("selected processor does not support `%s' in "
23608			  "Thumb-2 mode"), str);
23609	      return;
23610	    }
23611	}
23612
23613      inst.instruction = opcode->tvalue;
23614
23615      if (!parse_operands (p, opcode->operands, /*thumb=*/true))
23616	{
23617	  /* Prepare the pred_insn_type for those encodings that don't set
23618	     it.  */
23619	  it_fsm_pre_encode ();
23620
23621	  opcode->tencode ();
23622
23623	  it_fsm_post_encode ();
23624	}
23625
23626      if (!(inst.error || inst.relax))
23627	{
23628	  gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
23629	  inst.size = (inst.instruction > 0xffff ? 4 : 2);
23630	  if (inst.size_req && inst.size_req != inst.size)
23631	    {
23632	      as_bad (_("cannot honor width suffix -- `%s'"), str);
23633	      return;
23634	    }
23635	}
23636
23637      /* Something has gone badly wrong if we try to relax a fixed size
23638	 instruction.  */
23639      gas_assert (inst.size_req == 0 || !inst.relax);
23640
23641      ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
23642			      *opcode->tvariant);
23643      /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23644	 set those bits when Thumb-2 32-bit instructions are seen.  The impact
23645	 of relaxable instructions will be considered later after we finish all
23646	 relaxation.  */
23647      if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
23648	variant = arm_arch_none;
23649      else
23650	variant = cpu_variant;
23651      if (inst.size == 4 && !t32_insn_ok (variant, opcode))
23652	ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
23653				arm_ext_v6t2);
23654
23655      check_neon_suffixes;
23656
23657      if (!inst.error)
23658	{
23659	  mapping_state (MAP_THUMB);
23660	}
23661    }
23662  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23663    {
23664      bool is_bx;
23665
23666      /* bx is allowed on v5 cores, and sometimes on v4 cores.  */
23667      is_bx = (opcode->aencode == do_bx);
23668
23669      /* Check that this instruction is supported for this CPU.  */
23670      if (!(is_bx && fix_v4bx)
23671	  && !(opcode->avariant &&
23672	       ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
23673	{
23674	  as_bad (_("selected processor does not support `%s' in ARM mode"), str);
23675	  return;
23676	}
23677      if (inst.size_req)
23678	{
23679	  as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
23680	  return;
23681	}
23682
23683      inst.instruction = opcode->avalue;
23684      if (opcode->tag == OT_unconditionalF)
23685	inst.instruction |= 0xFU << 28;
23686      else
23687	inst.instruction |= inst.cond << 28;
23688      inst.size = INSN_SIZE;
23689      if (!parse_operands (p, opcode->operands, /*thumb=*/false))
23690	{
23691	  it_fsm_pre_encode ();
23692	  opcode->aencode ();
23693	  it_fsm_post_encode ();
23694	}
23695      /* Arm mode bx is marked as both v4T and v5 because it's still required
23696	 on a hypothetical non-thumb v5 core.  */
23697      if (is_bx)
23698	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
23699      else
23700	ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
23701				*opcode->avariant);
23702
23703      check_neon_suffixes;
23704
23705      if (!inst.error)
23706	{
23707	  mapping_state (MAP_ARM);
23708	}
23709    }
23710  else
23711    {
23712      as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23713		"-- `%s'"), str);
23714      return;
23715    }
23716  output_inst (str);
23717}
23718
23719static void
23720check_pred_blocks_finished (void)
23721{
23722#ifdef OBJ_ELF
23723  asection *sect;
23724
23725  for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
23726    {
23727      segment_info_type *seginfo = seg_info (sect);
23728
23729      if (seginfo && seginfo->tc_segment_info_data.current_pred.state
23730	  == MANUAL_PRED_BLOCK)
23731	{
23732	  if (now_pred.type == SCALAR_PRED)
23733	    as_warn (_("section '%s' finished with an open IT block."),
23734		     sect->name);
23735	  else
23736	    as_warn (_("section '%s' finished with an open VPT/VPST block."),
23737		   sect->name);
23738	}
23739    }
23740#else
23741  if (now_pred.state == MANUAL_PRED_BLOCK)
23742    {
23743      if (now_pred.type == SCALAR_PRED)
23744       as_warn (_("file finished with an open IT block."));
23745      else
23746	as_warn (_("file finished with an open VPT/VPST block."));
23747    }
23748#endif
23749}
23750
23751/* Various frobbings of labels and their addresses.  */
23752
23753void
23754arm_start_line_hook (void)
23755{
23756  last_label_seen = NULL;
23757}
23758
23759void
23760arm_frob_label (symbolS * sym)
23761{
23762  last_label_seen = sym;
23763
23764  ARM_SET_THUMB (sym, thumb_mode);
23765
23766#if defined OBJ_COFF || defined OBJ_ELF
23767  ARM_SET_INTERWORK (sym, support_interwork);
23768#endif
23769
23770  force_automatic_it_block_close ();
23771
23772  /* Note - do not allow local symbols (.Lxxx) to be labelled
23773     as Thumb functions.  This is because these labels, whilst
23774     they exist inside Thumb code, are not the entry points for
23775     possible ARM->Thumb calls.	 Also, these labels can be used
23776     as part of a computed goto or switch statement.  eg gcc
23777     can generate code that looks like this:
23778
23779		ldr  r2, [pc, .Laaa]
23780		lsl  r3, r3, #2
23781		ldr  r2, [r3, r2]
23782		mov  pc, r2
23783
23784       .Lbbb:  .word .Lxxx
23785       .Lccc:  .word .Lyyy
23786       ..etc...
23787       .Laaa:	.word Lbbb
23788
23789     The first instruction loads the address of the jump table.
23790     The second instruction converts a table index into a byte offset.
23791     The third instruction gets the jump address out of the table.
23792     The fourth instruction performs the jump.
23793
23794     If the address stored at .Laaa is that of a symbol which has the
23795     Thumb_Func bit set, then the linker will arrange for this address
23796     to have the bottom bit set, which in turn would mean that the
23797     address computation performed by the third instruction would end
23798     up with the bottom bit set.  Since the ARM is capable of unaligned
23799     word loads, the instruction would then load the incorrect address
23800     out of the jump table, and chaos would ensue.  */
23801  if (label_is_thumb_function_name
23802      && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
23803      && (bfd_section_flags (now_seg) & SEC_CODE) != 0)
23804    {
23805      /* When the address of a Thumb function is taken the bottom
23806	 bit of that address should be set.  This will allow
23807	 interworking between Arm and Thumb functions to work
23808	 correctly.  */
23809
23810      THUMB_SET_FUNC (sym, 1);
23811
23812      label_is_thumb_function_name = false;
23813    }
23814
23815  dwarf2_emit_label (sym);
23816}
23817
23818bool
23819arm_data_in_code (void)
23820{
23821  if (thumb_mode && startswith (input_line_pointer + 1, "data:"))
23822    {
23823      *input_line_pointer = '/';
23824      input_line_pointer += 5;
23825      *input_line_pointer = 0;
23826      return true;
23827    }
23828
23829  return false;
23830}
23831
23832char *
23833arm_canonicalize_symbol_name (char * name)
23834{
23835  int len;
23836
23837  if (thumb_mode && (len = strlen (name)) > 5
23838      && streq (name + len - 5, "/data"))
23839    *(name + len - 5) = 0;
23840
23841  return name;
23842}
23843
23844/* Table of all register names defined by default.  The user can
23845   define additional names with .req.  Note that all register names
23846   should appear in both upper and lowercase variants.	Some registers
23847   also have mixed-case names.	*/
23848
23849#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, true, 0 }
23850#define REGNUM(p,n,t) REGDEF(p##n, n, t)
23851#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23852#define REGSET(p,t) \
23853  REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23854  REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23855  REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23856  REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23857#define REGSETH(p,t) \
23858  REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23859  REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23860  REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23861  REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23862#define REGSET2(p,t) \
23863  REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23864  REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23865  REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23866  REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23867#define SPLRBANK(base,bank,t) \
23868  REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23869  REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23870  REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23871  REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23872  REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23873  REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23874
23875static const struct reg_entry reg_names[] =
23876{
23877  /* ARM integer registers.  */
23878  REGSET(r, RN), REGSET(R, RN),
23879
23880  /* ATPCS synonyms.  */
23881  REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
23882  REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
23883  REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
23884
23885  REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
23886  REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
23887  REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
23888
23889  /* Well-known aliases.  */
23890  REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
23891  REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
23892
23893  REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
23894  REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
23895
23896  /* Defining the new Zero register from ARMv8.1-M.  */
23897  REGDEF(zr,15,ZR),
23898  REGDEF(ZR,15,ZR),
23899
23900  /* Coprocessor numbers.  */
23901  REGSET(p, CP), REGSET(P, CP),
23902
23903  /* Coprocessor register numbers.  The "cr" variants are for backward
23904     compatibility.  */
23905  REGSET(c,  CN), REGSET(C, CN),
23906  REGSET(cr, CN), REGSET(CR, CN),
23907
23908  /* ARM banked registers.  */
23909  REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
23910  REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
23911  REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
23912  REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
23913  REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
23914  REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
23915  REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
23916
23917  REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
23918  REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
23919  REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
23920  REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
23921  REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
23922  REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
23923  REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
23924  REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
23925
23926  SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
23927  SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
23928  SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
23929  SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
23930  SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
23931  REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
23932  REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
23933  REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
23934  REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
23935
23936  /* FPA registers.  */
23937  REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
23938  REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
23939
23940  REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
23941  REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
23942
23943  /* VFP SP registers.	*/
23944  REGSET(s,VFS),  REGSET(S,VFS),
23945  REGSETH(s,VFS), REGSETH(S,VFS),
23946
23947  /* VFP DP Registers.	*/
23948  REGSET(d,VFD),  REGSET(D,VFD),
23949  /* Extra Neon DP registers.  */
23950  REGSETH(d,VFD), REGSETH(D,VFD),
23951
23952  /* Neon QP registers.  */
23953  REGSET2(q,NQ),  REGSET2(Q,NQ),
23954
23955  /* VFP control registers.  */
23956  REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
23957  REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
23958  REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
23959  REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
23960  REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
23961  REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
23962  REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
23963  REGDEF(fpscr_nzcvqc,2,VFC), REGDEF(FPSCR_nzcvqc,2,VFC),
23964  REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC),
23965  REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC),
23966  REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC),
23967  REGDEF(fpcxtns,14,VFC), REGDEF(FPCXTNS,14,VFC),
23968  REGDEF(fpcxts,15,VFC), REGDEF(FPCXTS,15,VFC),
23969
23970  /* Maverick DSP coprocessor registers.  */
23971  REGSET(mvf,MVF),  REGSET(mvd,MVD),  REGSET(mvfx,MVFX),  REGSET(mvdx,MVDX),
23972  REGSET(MVF,MVF),  REGSET(MVD,MVD),  REGSET(MVFX,MVFX),  REGSET(MVDX,MVDX),
23973
23974  REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
23975  REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
23976  REGDEF(dspsc,0,DSPSC),
23977
23978  REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
23979  REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
23980  REGDEF(DSPSC,0,DSPSC),
23981
23982  /* iWMMXt data registers - p0, c0-15.	 */
23983  REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
23984
23985  /* iWMMXt control registers - p1, c0-3.  */
23986  REGDEF(wcid,	0,MMXWC),  REGDEF(wCID,	 0,MMXWC),  REGDEF(WCID,  0,MMXWC),
23987  REGDEF(wcon,	1,MMXWC),  REGDEF(wCon,	 1,MMXWC),  REGDEF(WCON,  1,MMXWC),
23988  REGDEF(wcssf, 2,MMXWC),  REGDEF(wCSSF, 2,MMXWC),  REGDEF(WCSSF, 2,MMXWC),
23989  REGDEF(wcasf, 3,MMXWC),  REGDEF(wCASF, 3,MMXWC),  REGDEF(WCASF, 3,MMXWC),
23990
23991  /* iWMMXt scalar (constant/offset) registers - p1, c8-11.  */
23992  REGDEF(wcgr0, 8,MMXWCG),  REGDEF(wCGR0, 8,MMXWCG),  REGDEF(WCGR0, 8,MMXWCG),
23993  REGDEF(wcgr1, 9,MMXWCG),  REGDEF(wCGR1, 9,MMXWCG),  REGDEF(WCGR1, 9,MMXWCG),
23994  REGDEF(wcgr2,10,MMXWCG),  REGDEF(wCGR2,10,MMXWCG),  REGDEF(WCGR2,10,MMXWCG),
23995  REGDEF(wcgr3,11,MMXWCG),  REGDEF(wCGR3,11,MMXWCG),  REGDEF(WCGR3,11,MMXWCG),
23996
23997  /* XScale accumulator registers.  */
23998  REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
23999
24000  /* DWARF ABI defines RA_AUTH_CODE to 143. It also reserves 134-142 for future
24001     expansion.  RA_AUTH_CODE here is given the value 143 % 134 to make it easy
24002     for tc_arm_regname_to_dw2regnum to translate to DWARF reg number using
24003     134 + reg_number should the range 134 to 142 be used for more pseudo regs
24004     in the future.  This also helps fit RA_AUTH_CODE into a bitmask.  */
24005  REGDEF(ra_auth_code,12,PSEUDO),
24006};
24007#undef REGDEF
24008#undef REGNUM
24009#undef REGSET
24010
24011/* Table of all PSR suffixes.  Bare "CPSR" and "SPSR" are handled
24012   within psr_required_here.  */
24013static const struct asm_psr psrs[] =
24014{
24015  /* Backward compatibility notation.  Note that "all" is no longer
24016     truly all possible PSR bits.  */
24017  {"all",  PSR_c | PSR_f},
24018  {"flg",  PSR_f},
24019  {"ctl",  PSR_c},
24020
24021  /* Individual flags.	*/
24022  {"f",	   PSR_f},
24023  {"c",	   PSR_c},
24024  {"x",	   PSR_x},
24025  {"s",	   PSR_s},
24026
24027  /* Combinations of flags.  */
24028  {"fs",   PSR_f | PSR_s},
24029  {"fx",   PSR_f | PSR_x},
24030  {"fc",   PSR_f | PSR_c},
24031  {"sf",   PSR_s | PSR_f},
24032  {"sx",   PSR_s | PSR_x},
24033  {"sc",   PSR_s | PSR_c},
24034  {"xf",   PSR_x | PSR_f},
24035  {"xs",   PSR_x | PSR_s},
24036  {"xc",   PSR_x | PSR_c},
24037  {"cf",   PSR_c | PSR_f},
24038  {"cs",   PSR_c | PSR_s},
24039  {"cx",   PSR_c | PSR_x},
24040  {"fsx",  PSR_f | PSR_s | PSR_x},
24041  {"fsc",  PSR_f | PSR_s | PSR_c},
24042  {"fxs",  PSR_f | PSR_x | PSR_s},
24043  {"fxc",  PSR_f | PSR_x | PSR_c},
24044  {"fcs",  PSR_f | PSR_c | PSR_s},
24045  {"fcx",  PSR_f | PSR_c | PSR_x},
24046  {"sfx",  PSR_s | PSR_f | PSR_x},
24047  {"sfc",  PSR_s | PSR_f | PSR_c},
24048  {"sxf",  PSR_s | PSR_x | PSR_f},
24049  {"sxc",  PSR_s | PSR_x | PSR_c},
24050  {"scf",  PSR_s | PSR_c | PSR_f},
24051  {"scx",  PSR_s | PSR_c | PSR_x},
24052  {"xfs",  PSR_x | PSR_f | PSR_s},
24053  {"xfc",  PSR_x | PSR_f | PSR_c},
24054  {"xsf",  PSR_x | PSR_s | PSR_f},
24055  {"xsc",  PSR_x | PSR_s | PSR_c},
24056  {"xcf",  PSR_x | PSR_c | PSR_f},
24057  {"xcs",  PSR_x | PSR_c | PSR_s},
24058  {"cfs",  PSR_c | PSR_f | PSR_s},
24059  {"cfx",  PSR_c | PSR_f | PSR_x},
24060  {"csf",  PSR_c | PSR_s | PSR_f},
24061  {"csx",  PSR_c | PSR_s | PSR_x},
24062  {"cxf",  PSR_c | PSR_x | PSR_f},
24063  {"cxs",  PSR_c | PSR_x | PSR_s},
24064  {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
24065  {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
24066  {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
24067  {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
24068  {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
24069  {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
24070  {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
24071  {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
24072  {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
24073  {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
24074  {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
24075  {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
24076  {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
24077  {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
24078  {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
24079  {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
24080  {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
24081  {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
24082  {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
24083  {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
24084  {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
24085  {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
24086  {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
24087  {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
24088};
24089
24090/* Table of V7M psr names.  */
24091static const struct asm_psr v7m_psrs[] =
24092{
24093  {"apsr",	   0x0 }, {"APSR",	   0x0 },
24094  {"iapsr",	   0x1 }, {"IAPSR",	   0x1 },
24095  {"eapsr",	   0x2 }, {"EAPSR",	   0x2 },
24096  {"psr",	   0x3 }, {"PSR",	   0x3 },
24097  {"xpsr",	   0x3 }, {"XPSR",	   0x3 }, {"xPSR",	  3 },
24098  {"ipsr",	   0x5 }, {"IPSR",	   0x5 },
24099  {"epsr",	   0x6 }, {"EPSR",	   0x6 },
24100  {"iepsr",	   0x7 }, {"IEPSR",	   0x7 },
24101  {"msp",	   0x8 }, {"MSP",	   0x8 },
24102  {"psp",	   0x9 }, {"PSP",	   0x9 },
24103  {"msplim",	   0xa }, {"MSPLIM",	   0xa },
24104  {"psplim",	   0xb }, {"PSPLIM",	   0xb },
24105  {"primask",	   0x10}, {"PRIMASK",	   0x10},
24106  {"basepri",	   0x11}, {"BASEPRI",	   0x11},
24107  {"basepri_max",  0x12}, {"BASEPRI_MAX",  0x12},
24108  {"faultmask",	   0x13}, {"FAULTMASK",	   0x13},
24109  {"control",	   0x14}, {"CONTROL",	   0x14},
24110  {"msp_ns",	   0x88}, {"MSP_NS",	   0x88},
24111  {"psp_ns",	   0x89}, {"PSP_NS",	   0x89},
24112  {"msplim_ns",	   0x8a}, {"MSPLIM_NS",	   0x8a},
24113  {"psplim_ns",	   0x8b}, {"PSPLIM_NS",	   0x8b},
24114  {"primask_ns",   0x90}, {"PRIMASK_NS",   0x90},
24115  {"basepri_ns",   0x91}, {"BASEPRI_NS",   0x91},
24116  {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24117  {"control_ns",   0x94}, {"CONTROL_NS",   0x94},
24118  {"sp_ns",	   0x98}, {"SP_NS",	   0x98 }
24119};
24120
24121/* Table of all shift-in-operand names.	 */
24122static const struct asm_shift_name shift_names [] =
24123{
24124  { "asl", SHIFT_LSL },	 { "ASL", SHIFT_LSL },
24125  { "lsl", SHIFT_LSL },	 { "LSL", SHIFT_LSL },
24126  { "lsr", SHIFT_LSR },	 { "LSR", SHIFT_LSR },
24127  { "asr", SHIFT_ASR },	 { "ASR", SHIFT_ASR },
24128  { "ror", SHIFT_ROR },	 { "ROR", SHIFT_ROR },
24129  { "rrx", SHIFT_RRX },	 { "RRX", SHIFT_RRX },
24130  { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
24131};
24132
24133/* Table of all explicit relocation names.  */
24134#ifdef OBJ_ELF
24135static struct reloc_entry reloc_names[] =
24136{
24137  { "got",     BFD_RELOC_ARM_GOT32   },	 { "GOT",     BFD_RELOC_ARM_GOT32   },
24138  { "gotoff",  BFD_RELOC_ARM_GOTOFF  },	 { "GOTOFF",  BFD_RELOC_ARM_GOTOFF  },
24139  { "plt",     BFD_RELOC_ARM_PLT32   },	 { "PLT",     BFD_RELOC_ARM_PLT32   },
24140  { "target1", BFD_RELOC_ARM_TARGET1 },	 { "TARGET1", BFD_RELOC_ARM_TARGET1 },
24141  { "target2", BFD_RELOC_ARM_TARGET2 },	 { "TARGET2", BFD_RELOC_ARM_TARGET2 },
24142  { "sbrel",   BFD_RELOC_ARM_SBREL32 },	 { "SBREL",   BFD_RELOC_ARM_SBREL32 },
24143  { "tlsgd",   BFD_RELOC_ARM_TLS_GD32},  { "TLSGD",   BFD_RELOC_ARM_TLS_GD32},
24144  { "tlsldm",  BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM",  BFD_RELOC_ARM_TLS_LDM32},
24145  { "tlsldo",  BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO",  BFD_RELOC_ARM_TLS_LDO32},
24146  { "gottpoff",BFD_RELOC_ARM_TLS_IE32},  { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
24147  { "tpoff",   BFD_RELOC_ARM_TLS_LE32},  { "TPOFF",   BFD_RELOC_ARM_TLS_LE32},
24148  { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
24149  { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
24150	{ "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
24151  { "tlscall", BFD_RELOC_ARM_TLS_CALL},
24152	{ "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
24153  { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
24154	{ "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
24155  { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
24156	{ "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
24157  { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
24158	{ "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
24159  { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
24160	{ "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
24161   { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC },      { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
24162   { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC },    { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
24163   { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC },   { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
24164};
24165#endif
24166
24167/* Table of all conditional affixes.  */
24168static const struct asm_cond conds[] =
24169{
24170  {"eq", 0x0},
24171  {"ne", 0x1},
24172  {"cs", 0x2}, {"hs", 0x2},
24173  {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24174  {"mi", 0x4},
24175  {"pl", 0x5},
24176  {"vs", 0x6},
24177  {"vc", 0x7},
24178  {"hi", 0x8},
24179  {"ls", 0x9},
24180  {"ge", 0xa},
24181  {"lt", 0xb},
24182  {"gt", 0xc},
24183  {"le", 0xd},
24184  {"al", 0xe}
24185};
24186static const struct asm_cond vconds[] =
24187{
24188    {"t", 0xf},
24189    {"e", 0x10}
24190};
24191
24192#define UL_BARRIER(L,U,CODE,FEAT) \
24193  { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24194  { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24195
24196static struct asm_barrier_opt barrier_opt_names[] =
24197{
24198  UL_BARRIER ("sy",	"SY",	 0xf, ARM_EXT_BARRIER),
24199  UL_BARRIER ("st",	"ST",	 0xe, ARM_EXT_BARRIER),
24200  UL_BARRIER ("ld",	"LD",	 0xd, ARM_EXT_V8),
24201  UL_BARRIER ("ish",	"ISH",	 0xb, ARM_EXT_BARRIER),
24202  UL_BARRIER ("sh",	"SH",	 0xb, ARM_EXT_BARRIER),
24203  UL_BARRIER ("ishst",	"ISHST", 0xa, ARM_EXT_BARRIER),
24204  UL_BARRIER ("shst",	"SHST",	 0xa, ARM_EXT_BARRIER),
24205  UL_BARRIER ("ishld",	"ISHLD", 0x9, ARM_EXT_V8),
24206  UL_BARRIER ("un",	"UN",	 0x7, ARM_EXT_BARRIER),
24207  UL_BARRIER ("nsh",	"NSH",	 0x7, ARM_EXT_BARRIER),
24208  UL_BARRIER ("unst",	"UNST",	 0x6, ARM_EXT_BARRIER),
24209  UL_BARRIER ("nshst",	"NSHST", 0x6, ARM_EXT_BARRIER),
24210  UL_BARRIER ("nshld",	"NSHLD", 0x5, ARM_EXT_V8),
24211  UL_BARRIER ("osh",	"OSH",	 0x3, ARM_EXT_BARRIER),
24212  UL_BARRIER ("oshst",	"OSHST", 0x2, ARM_EXT_BARRIER),
24213  UL_BARRIER ("oshld",	"OSHLD", 0x1, ARM_EXT_V8)
24214};
24215
24216#undef UL_BARRIER
24217
24218/* Table of ARM-format instructions.	*/
24219
24220/* Macros for gluing together operand strings.  N.B. In all cases
24221   other than OPS0, the trailing OP_stop comes from default
24222   zero-initialization of the unspecified elements of the array.  */
24223#define OPS0()		  { OP_stop, }
24224#define OPS1(a)		  { OP_##a, }
24225#define OPS2(a,b)	  { OP_##a,OP_##b, }
24226#define OPS3(a,b,c)	  { OP_##a,OP_##b,OP_##c, }
24227#define OPS4(a,b,c,d)	  { OP_##a,OP_##b,OP_##c,OP_##d, }
24228#define OPS5(a,b,c,d,e)	  { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24229#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24230
24231/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24232   This is useful when mixing operands for ARM and THUMB, i.e. using the
24233   MIX_ARM_THUMB_OPERANDS macro.
24234   In order to use these macros, prefix the number of operands with _
24235   e.g. _3.  */
24236#define OPS_1(a)	   { a, }
24237#define OPS_2(a,b)	   { a,b, }
24238#define OPS_3(a,b,c)	   { a,b,c, }
24239#define OPS_4(a,b,c,d)	   { a,b,c,d, }
24240#define OPS_5(a,b,c,d,e)   { a,b,c,d,e, }
24241#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24242
24243/* These macros abstract out the exact format of the mnemonic table and
24244   save some repeated characters.  */
24245
24246/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix.  */
24247#define TxCE(mnem, op, top, nops, ops, ae, te) \
24248  { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24249    THUMB_VARIANT, do_##ae, do_##te, 0 }
24250
24251/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24252   a T_MNEM_xyz enumerator.  */
24253#define TCE(mnem, aop, top, nops, ops, ae, te) \
24254      TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24255#define tCE(mnem, aop, top, nops, ops, ae, te) \
24256      TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24257
24258/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24259   infix after the third character.  */
24260#define TxC3(mnem, op, top, nops, ops, ae, te) \
24261  { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24262    THUMB_VARIANT, do_##ae, do_##te, 0 }
24263#define TxC3w(mnem, op, top, nops, ops, ae, te) \
24264  { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24265    THUMB_VARIANT, do_##ae, do_##te, 0 }
24266#define TC3(mnem, aop, top, nops, ops, ae, te) \
24267      TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24268#define TC3w(mnem, aop, top, nops, ops, ae, te) \
24269      TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24270#define tC3(mnem, aop, top, nops, ops, ae, te) \
24271      TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24272#define tC3w(mnem, aop, top, nops, ops, ae, te) \
24273      TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24274
24275/* Mnemonic that cannot be conditionalized.  The ARM condition-code
24276   field is still 0xE.  Many of the Thumb variants can be executed
24277   conditionally, so this is checked separately.  */
24278#define TUE(mnem, op, top, nops, ops, ae, te)				\
24279  { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24280    THUMB_VARIANT, do_##ae, do_##te, 0 }
24281
24282/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24283   Used by mnemonics that have very minimal differences in the encoding for
24284   ARM and Thumb variants and can be handled in a common function.  */
24285#define TUEc(mnem, op, top, nops, ops, en) \
24286  { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24287    THUMB_VARIANT, do_##en, do_##en, 0 }
24288
24289/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24290   condition code field.  */
24291#define TUF(mnem, op, top, nops, ops, ae, te)				\
24292  { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24293    THUMB_VARIANT, do_##ae, do_##te, 0 }
24294
24295/* ARM-only variants of all the above.  */
24296#define CE(mnem,  op, nops, ops, ae)	\
24297  { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24298
24299#define C3(mnem, op, nops, ops, ae)	\
24300  { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24301
24302/* Thumb-only variants of TCE and TUE.  */
24303#define ToC(mnem, top, nops, ops, te) \
24304  { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24305    do_##te, 0 }
24306
24307#define ToU(mnem, top, nops, ops, te) \
24308  { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24309    NULL, do_##te, 0 }
24310
24311/* T_MNEM_xyz enumerator variants of ToC.  */
24312#define toC(mnem, top, nops, ops, te) \
24313  { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24314    do_##te, 0 }
24315
24316/* T_MNEM_xyz enumerator variants of ToU.  */
24317#define toU(mnem, top, nops, ops, te) \
24318  { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24319    NULL, do_##te, 0 }
24320
24321/* Legacy mnemonics that always have conditional infix after the third
24322   character.  */
24323#define CL(mnem, op, nops, ops, ae)	\
24324  { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24325    0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24326
24327/* Coprocessor instructions.  Isomorphic between Arm and Thumb-2.  */
24328#define cCE(mnem,  op, nops, ops, ae)	\
24329  { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24330
24331/* mov instructions that are shared between coprocessor and MVE.  */
24332#define mcCE(mnem,  op, nops, ops, ae)	\
24333  { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24334
24335/* Legacy coprocessor instructions where conditional infix and conditional
24336   suffix are ambiguous.  For consistency this includes all FPA instructions,
24337   not just the potentially ambiguous ones.  */
24338#define cCL(mnem, op, nops, ops, ae)	\
24339  { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24340    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24341
24342/* Coprocessor, takes either a suffix or a position-3 infix
24343   (for an FPA corner case). */
24344#define C3E(mnem, op, nops, ops, ae) \
24345  { mnem, OPS##nops ops, OT_csuf_or_in3, \
24346    0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24347
24348#define xCM_(m1, m2, m3, op, nops, ops, ae)	\
24349  { m1 #m2 m3, OPS##nops ops, \
24350    sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24351    0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24352
24353#define CM(m1, m2, op, nops, ops, ae)	\
24354  xCM_ (m1,   , m2, op, nops, ops, ae),	\
24355  xCM_ (m1, eq, m2, op, nops, ops, ae),	\
24356  xCM_ (m1, ne, m2, op, nops, ops, ae),	\
24357  xCM_ (m1, cs, m2, op, nops, ops, ae),	\
24358  xCM_ (m1, hs, m2, op, nops, ops, ae),	\
24359  xCM_ (m1, cc, m2, op, nops, ops, ae),	\
24360  xCM_ (m1, ul, m2, op, nops, ops, ae),	\
24361  xCM_ (m1, lo, m2, op, nops, ops, ae),	\
24362  xCM_ (m1, mi, m2, op, nops, ops, ae),	\
24363  xCM_ (m1, pl, m2, op, nops, ops, ae),	\
24364  xCM_ (m1, vs, m2, op, nops, ops, ae),	\
24365  xCM_ (m1, vc, m2, op, nops, ops, ae),	\
24366  xCM_ (m1, hi, m2, op, nops, ops, ae),	\
24367  xCM_ (m1, ls, m2, op, nops, ops, ae),	\
24368  xCM_ (m1, ge, m2, op, nops, ops, ae),	\
24369  xCM_ (m1, lt, m2, op, nops, ops, ae),	\
24370  xCM_ (m1, gt, m2, op, nops, ops, ae),	\
24371  xCM_ (m1, le, m2, op, nops, ops, ae),	\
24372  xCM_ (m1, al, m2, op, nops, ops, ae)
24373
24374#define UE(mnem, op, nops, ops, ae)	\
24375  { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24376
24377#define UF(mnem, op, nops, ops, ae)	\
24378  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24379
24380/* Neon data-processing. ARM versions are unconditional with cond=0xf.
24381   The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24382   use the same encoding function for each.  */
24383#define NUF(mnem, op, nops, ops, enc)					\
24384  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op,		\
24385    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24386
24387/* Neon data processing, version which indirects through neon_enc_tab for
24388   the various overloaded versions of opcodes.  */
24389#define nUF(mnem, op, nops, ops, enc)					\
24390  { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op,	\
24391    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24392
24393/* Neon insn with conditional suffix for the ARM version, non-overloaded
24394   version.  */
24395#define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p)				\
24396  { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT,		\
24397    THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24398
24399#define NCE(mnem, op, nops, ops, enc)					\
24400   NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24401
24402#define NCEF(mnem, op, nops, ops, enc)					\
24403    NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24404
24405/* Neon insn with conditional suffix for the ARM version, overloaded types.  */
24406#define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p)				\
24407  { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op,		\
24408    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24409
24410#define nCE(mnem, op, nops, ops, enc)					\
24411   nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24412
24413#define nCEF(mnem, op, nops, ops, enc)					\
24414    nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24415
24416/*   */
24417#define mCEF(mnem, op, nops, ops, enc)				\
24418  { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op,	\
24419    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24420
24421
24422/* nCEF but for MVE predicated instructions.  */
24423#define mnCEF(mnem, op, nops, ops, enc)					\
24424    nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24425
24426/* nCE but for MVE predicated instructions.  */
24427#define mnCE(mnem, op, nops, ops, enc)					\
24428   nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24429
24430/* NUF but for potentially MVE predicated instructions.  */
24431#define MNUF(mnem, op, nops, ops, enc)					\
24432  { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op,		\
24433    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24434
24435/* nUF but for potentially MVE predicated instructions.  */
24436#define mnUF(mnem, op, nops, ops, enc)					\
24437  { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op,	\
24438    ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24439
24440/* ToC but for potentially MVE predicated instructions.  */
24441#define mToC(mnem, top, nops, ops, te) \
24442  { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24443    do_##te, 1 }
24444
24445/* NCE but for MVE predicated instructions.  */
24446#define MNCE(mnem, op, nops, ops, enc)					\
24447   NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24448
24449/* NCEF but for MVE predicated instructions.  */
24450#define MNCEF(mnem, op, nops, ops, enc)					\
24451    NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24452#define do_0 0
24453
24454static const struct asm_opcode insns[] =
24455{
24456#define ARM_VARIANT    & arm_ext_v1 /* Core ARM Instructions.  */
24457#define THUMB_VARIANT  & arm_ext_v4t
24458 tCE("and",	0000000, _and,     3, (RR, oRR, SH), arit, t_arit3c),
24459 tC3("ands",	0100000, _ands,	   3, (RR, oRR, SH), arit, t_arit3c),
24460 tCE("eor",	0200000, _eor,	   3, (RR, oRR, SH), arit, t_arit3c),
24461 tC3("eors",	0300000, _eors,	   3, (RR, oRR, SH), arit, t_arit3c),
24462 tCE("sub",	0400000, _sub,	   3, (RR, oRR, SH), arit, t_add_sub),
24463 tC3("subs",	0500000, _subs,	   3, (RR, oRR, SH), arit, t_add_sub),
24464 tCE("add",	0800000, _add,	   3, (RR, oRR, SHG), arit, t_add_sub),
24465 tC3("adds",	0900000, _adds,	   3, (RR, oRR, SHG), arit, t_add_sub),
24466 tCE("adc",	0a00000, _adc,	   3, (RR, oRR, SH), arit, t_arit3c),
24467 tC3("adcs",	0b00000, _adcs,	   3, (RR, oRR, SH), arit, t_arit3c),
24468 tCE("sbc",	0c00000, _sbc,	   3, (RR, oRR, SH), arit, t_arit3),
24469 tC3("sbcs",	0d00000, _sbcs,	   3, (RR, oRR, SH), arit, t_arit3),
24470 tCE("orr",	1800000, _orr,	   3, (RR, oRR, SH), arit, t_arit3c),
24471 tC3("orrs",	1900000, _orrs,	   3, (RR, oRR, SH), arit, t_arit3c),
24472 tCE("bic",	1c00000, _bic,	   3, (RR, oRR, SH), arit, t_arit3),
24473 tC3("bics",	1d00000, _bics,	   3, (RR, oRR, SH), arit, t_arit3),
24474
24475 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24476    for setting PSR flag bits.  They are obsolete in V6 and do not
24477    have Thumb equivalents. */
24478 tCE("tst",	1100000, _tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
24479 tC3w("tsts",	1100000, _tst,	   2, (RR, SH),      cmp,  t_mvn_tst),
24480  CL("tstp",	110f000,     	   2, (RR, SH),      cmp),
24481 tCE("cmp",	1500000, _cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
24482 tC3w("cmps",	1500000, _cmp,	   2, (RR, SH),      cmp,  t_mov_cmp),
24483  CL("cmpp",	150f000,     	   2, (RR, SH),      cmp),
24484 tCE("cmn",	1700000, _cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
24485 tC3w("cmns",	1700000, _cmn,	   2, (RR, SH),      cmp,  t_mvn_tst),
24486  CL("cmnp",	170f000,     	   2, (RR, SH),      cmp),
24487
24488 tCE("mov",	1a00000, _mov,	   2, (RR, SH),      mov,  t_mov_cmp),
24489 tC3("movs",	1b00000, _movs,	   2, (RR, SHG),     mov,  t_mov_cmp),
24490 tCE("mvn",	1e00000, _mvn,	   2, (RR, SH),      mov,  t_mvn_tst),
24491 tC3("mvns",	1f00000, _mvns,	   2, (RR, SH),      mov,  t_mvn_tst),
24492
24493 tCE("ldr",	4100000, _ldr,	   2, (RR, ADDRGLDR),ldst, t_ldst),
24494 tC3("ldrb",	4500000, _ldrb,	   2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
24495 tCE("str",	4000000, _str,	   _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
24496								OP_RRnpc),
24497					OP_ADDRGLDR),ldst, t_ldst),
24498 tC3("strb",	4400000, _strb,	   2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
24499
24500 tCE("stm",	8800000, _stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
24501 tC3("stmia",	8800000, _stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
24502 tC3("stmea",	8800000, _stmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
24503 tCE("ldm",	8900000, _ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
24504 tC3("ldmia",	8900000, _ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
24505 tC3("ldmfd",	8900000, _ldmia,    2, (RRw, REGLST), ldmstm, t_ldmstm),
24506
24507 tCE("b",	a000000, _b,	   1, (EXPr),	     branch, t_branch),
24508 TCE("bl",	b000000, f000f800, 1, (EXPr),	     bl, t_branch23),
24509
24510  /* Pseudo ops.  */
24511 tCE("adr",	28f0000, _adr,	   2, (RR, EXP),     adr,  t_adr),
24512  C3(adrl,	28f0000,           2, (RR, EXP),     adrl),
24513 tCE("nop",	1a00000, _nop,	   1, (oI255c),	     nop,  t_nop),
24514 tCE("udf",	7f000f0, _udf,     1, (oIffffb),     bkpt, t_udf),
24515
24516  /* Thumb-compatibility pseudo ops.  */
24517 tCE("lsl",	1a00000, _lsl,	   3, (RR, oRR, SH), shift, t_shift),
24518 tC3("lsls",	1b00000, _lsls,	   3, (RR, oRR, SH), shift, t_shift),
24519 tCE("lsr",	1a00020, _lsr,	   3, (RR, oRR, SH), shift, t_shift),
24520 tC3("lsrs",	1b00020, _lsrs,	   3, (RR, oRR, SH), shift, t_shift),
24521 tCE("asr",	1a00040, _asr,	   3, (RR, oRR, SH), shift, t_shift),
24522 tC3("asrs",      1b00040, _asrs,     3, (RR, oRR, SH), shift, t_shift),
24523 tCE("ror",	1a00060, _ror,	   3, (RR, oRR, SH), shift, t_shift),
24524 tC3("rors",	1b00060, _rors,	   3, (RR, oRR, SH), shift, t_shift),
24525 tCE("neg",	2600000, _neg,	   2, (RR, RR),      rd_rn, t_neg),
24526 tC3("negs",	2700000, _negs,	   2, (RR, RR),      rd_rn, t_neg),
24527 tCE("push",	92d0000, _push,     1, (REGLST),	     push_pop, t_push_pop),
24528 tCE("pop",	8bd0000, _pop,	   1, (REGLST),	     push_pop, t_push_pop),
24529
24530 /* These may simplify to neg.  */
24531 TCE("rsb",	0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
24532 TC3("rsbs",	0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
24533
24534#undef THUMB_VARIANT
24535#define THUMB_VARIANT  & arm_ext_os
24536
24537 TCE("swi",	f000000, df00,     1, (EXPi),        swi, t_swi),
24538 TCE("svc",	f000000, df00,     1, (EXPi),        swi, t_swi),
24539
24540#undef  THUMB_VARIANT
24541#define THUMB_VARIANT  & arm_ext_v6
24542
24543 TCE("cpy",       1a00000, 4600,     2, (RR, RR),      rd_rm, t_cpy),
24544
24545 /* V1 instructions with no Thumb analogue prior to V6T2.  */
24546#undef  THUMB_VARIANT
24547#define THUMB_VARIANT  & arm_ext_v6t2
24548
24549 TCE("teq",	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
24550 TC3w("teqs",	1300000, ea900f00, 2, (RR, SH),      cmp,  t_mvn_tst),
24551  CL("teqp",	130f000,           2, (RR, SH),      cmp),
24552
24553 TC3("ldrt",	4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
24554 TC3("ldrbt",	4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
24555 TC3("strt",	4200000, f8400e00, 2, (RR_npcsp, ADDR),   ldstt, t_ldstt),
24556 TC3("strbt",	4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
24557
24558 TC3("stmdb",	9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24559 TC3("stmfd",     9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24560
24561 TC3("ldmdb",	9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24562 TC3("ldmea",	9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
24563
24564 /* V1 instructions with no Thumb analogue at all.  */
24565  CE("rsc",	0e00000,	   3, (RR, oRR, SH), arit),
24566  C3(rscs,	0f00000,	   3, (RR, oRR, SH), arit),
24567
24568  C3(stmib,	9800000,	   2, (RRw, REGLST), ldmstm),
24569  C3(stmfa,	9800000,	   2, (RRw, REGLST), ldmstm),
24570  C3(stmda,	8000000,	   2, (RRw, REGLST), ldmstm),
24571  C3(stmed,	8000000,	   2, (RRw, REGLST), ldmstm),
24572  C3(ldmib,	9900000,	   2, (RRw, REGLST), ldmstm),
24573  C3(ldmed,	9900000,	   2, (RRw, REGLST), ldmstm),
24574  C3(ldmda,	8100000,	   2, (RRw, REGLST), ldmstm),
24575  C3(ldmfa,	8100000,	   2, (RRw, REGLST), ldmstm),
24576
24577#undef  ARM_VARIANT
24578#define ARM_VARIANT    & arm_ext_v2	/* ARM 2 - multiplies.	*/
24579#undef  THUMB_VARIANT
24580#define THUMB_VARIANT  & arm_ext_v4t
24581
24582 tCE("mul",	0000090, _mul,	   3, (RRnpc, RRnpc, oRR), mul, t_mul),
24583 tC3("muls",	0100090, _muls,	   3, (RRnpc, RRnpc, oRR), mul, t_mul),
24584
24585#undef  THUMB_VARIANT
24586#define THUMB_VARIANT  & arm_ext_v6t2
24587
24588 TCE("mla",	0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
24589  C3(mlas,	0300090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
24590
24591  /* Generic coprocessor instructions.	*/
24592 TCE("cdp",	e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
24593 TCE("ldc",	c100000, ec100000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
24594 TC3("ldcl",	c500000, ec500000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
24595 TCE("stc",	c000000, ec000000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
24596 TC3("stcl",	c400000, ec400000, 3, (RCP, RCN, ADDRGLDC),	        lstc,   lstc),
24597 TCE("mcr",	e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
24598 TCE("mrc",	e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b),   co_reg, co_reg),
24599
24600#undef  ARM_VARIANT
24601#define ARM_VARIANT  & arm_ext_v2s /* ARM 3 - swp instructions.  */
24602
24603  CE("swp",	1000090,           3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
24604  C3(swpb,	1400090,           3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
24605
24606#undef  ARM_VARIANT
24607#define ARM_VARIANT    & arm_ext_v3	/* ARM 6 Status register instructions.	*/
24608#undef  THUMB_VARIANT
24609#define THUMB_VARIANT  & arm_ext_msr
24610
24611 TCE("mrs",	1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
24612 TCE("msr",	120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
24613
24614#undef  ARM_VARIANT
24615#define ARM_VARIANT    & arm_ext_v3m	 /* ARM 7M long multiplies.  */
24616#undef  THUMB_VARIANT
24617#define THUMB_VARIANT  & arm_ext_v6t2
24618
24619 TCE("smull",	0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24620  CM("smull","s",	0d00090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24621 TCE("umull",	0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24622  CM("umull","s",	0900090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24623 TCE("smlal",	0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24624  CM("smlal","s",	0f00090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24625 TCE("umlal",	0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
24626  CM("umlal","s",	0b00090,           4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
24627
24628#undef  ARM_VARIANT
24629#define ARM_VARIANT    & arm_ext_v4	/* ARM Architecture 4.	*/
24630#undef  THUMB_VARIANT
24631#define THUMB_VARIANT  & arm_ext_v4t
24632
24633 tC3("ldrh",	01000b0, _ldrh,     2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24634 tC3("strh",	00000b0, _strh,     2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24635 tC3("ldrsh",	01000f0, _ldrsh,    2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24636 tC3("ldrsb",	01000d0, _ldrsb,    2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24637 tC3("ldsh",	01000f0, _ldrsh,    2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24638 tC3("ldsb",	01000d0, _ldrsb,    2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
24639
24640#undef  ARM_VARIANT
24641#define ARM_VARIANT  & arm_ext_v4t_5
24642
24643  /* ARM Architecture 4T.  */
24644  /* Note: bx (and blx) are required on V5, even if the processor does
24645     not support Thumb.	 */
24646 TCE("bx",	12fff10, 4700, 1, (RR),	bx, t_bx),
24647
24648#undef  ARM_VARIANT
24649#define ARM_VARIANT    & arm_ext_v5 /*  ARM Architecture 5T.	 */
24650#undef  THUMB_VARIANT
24651#define THUMB_VARIANT  & arm_ext_v5t
24652
24653  /* Note: blx has 2 variants; the .value coded here is for
24654     BLX(2).  Only this variant has conditional execution.  */
24655 TCE("blx",	12fff30, 4780, 1, (RR_EXr),			    blx,  t_blx),
24656 TUE("bkpt",	1200070, be00, 1, (oIffffb),			    bkpt, t_bkpt),
24657
24658#undef  THUMB_VARIANT
24659#define THUMB_VARIANT  & arm_ext_v6t2
24660
24661 TCE("clz",	16f0f10, fab0f080, 2, (RRnpc, RRnpc),		        rd_rm,  t_clz),
24662 TUF("ldc2",	c100000, fc100000, 3, (RCP, RCN, ADDRGLDC),	        lstc,	lstc),
24663 TUF("ldc2l",	c500000, fc500000, 3, (RCP, RCN, ADDRGLDC),		        lstc,	lstc),
24664 TUF("stc2",	c000000, fc000000, 3, (RCP, RCN, ADDRGLDC),	        lstc,	lstc),
24665 TUF("stc2l",	c400000, fc400000, 3, (RCP, RCN, ADDRGLDC),		        lstc,	lstc),
24666 TUF("cdp2",	e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp,    cdp),
24667 TUF("mcr2",	e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
24668 TUF("mrc2",	e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b),   co_reg, co_reg),
24669
24670#undef  ARM_VARIANT
24671#define ARM_VARIANT    & arm_ext_v5exp /*  ARM Architecture 5TExP.  */
24672#undef  THUMB_VARIANT
24673#define THUMB_VARIANT  & arm_ext_v5exp
24674
24675 TCE("smlabb",	1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
24676 TCE("smlatb",	10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
24677 TCE("smlabt",	10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
24678 TCE("smlatt",	10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
24679
24680 TCE("smlawb",	1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
24681 TCE("smlawt",	12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smla, t_mla),
24682
24683 TCE("smlalbb",	1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
24684 TCE("smlaltb",	14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
24685 TCE("smlalbt",	14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
24686 TCE("smlaltt",	14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),   smlal, t_mlal),
24687
24688 TCE("smulbb",	1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
24689 TCE("smultb",	16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
24690 TCE("smulbt",	16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
24691 TCE("smultt",	16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
24692
24693 TCE("smulwb",	12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
24694 TCE("smulwt",	12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc),	    smul, t_simd),
24695
24696 TCE("qadd",	1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, t_simd2),
24697 TCE("qdadd",	1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, t_simd2),
24698 TCE("qsub",	1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, t_simd2),
24699 TCE("qdsub",	1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc),	    rd_rm_rn, t_simd2),
24700
24701#undef  ARM_VARIANT
24702#define ARM_VARIANT    & arm_ext_v5e /*  ARM Architecture 5TE.  */
24703#undef  THUMB_VARIANT
24704#define THUMB_VARIANT  & arm_ext_v6t2
24705
24706 TUF("pld",	450f000, f810f000, 1, (ADDR),		     pld,  t_pld),
24707 TC3("ldrd",	00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
24708     ldrd, t_ldstd),
24709 TC3("strd",	00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
24710				       ADDRGLDRS), ldrd, t_ldstd),
24711
24712 TCE("mcrr",	c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24713 TCE("mrrc",	c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24714
24715#undef  ARM_VARIANT
24716#define ARM_VARIANT  & arm_ext_v5j /*  ARM Architecture 5TEJ.  */
24717
24718 TCE("bxj",	12fff20, f3c08f00, 1, (RR),			  bxj, t_bxj),
24719
24720#undef  ARM_VARIANT
24721#define ARM_VARIANT    & arm_ext_v6 /*  ARM V6.  */
24722#undef  THUMB_VARIANT
24723#define THUMB_VARIANT  & arm_ext_v6
24724
24725 TUF("cpsie",     1080000, b660,     2, (CPSF, oI31b),              cpsi,   t_cpsi),
24726 TUF("cpsid",     10c0000, b670,     2, (CPSF, oI31b),              cpsi,   t_cpsi),
24727 tCE("rev",       6bf0f30, _rev,      2, (RRnpc, RRnpc),             rd_rm,  t_rev),
24728 tCE("rev16",     6bf0fb0, _rev16,    2, (RRnpc, RRnpc),             rd_rm,  t_rev),
24729 tCE("revsh",     6ff0fb0, _revsh,    2, (RRnpc, RRnpc),             rd_rm,  t_rev),
24730 tCE("sxth",      6bf0070, _sxth,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
24731 tCE("uxth",      6ff0070, _uxth,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
24732 tCE("sxtb",      6af0070, _sxtb,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
24733 tCE("uxtb",      6ef0070, _uxtb,     3, (RRnpc, RRnpc, oROR),       sxth,   t_sxth),
24734 TUF("setend",    1010000, b650,     1, (ENDI),                     setend, t_setend),
24735
24736#undef  THUMB_VARIANT
24737#define THUMB_VARIANT  & arm_ext_v6t2_v8m
24738
24739 TCE("ldrex",	1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR),	  ldrex, t_ldrex),
24740 TCE("strex",	1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
24741				      strex,  t_strex),
24742#undef  THUMB_VARIANT
24743#define THUMB_VARIANT  & arm_ext_v6t2
24744
24745 TUF("mcrr2",	c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24746 TUF("mrrc2",	c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
24747
24748 TCE("ssat",	6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat,   t_ssat),
24749 TCE("usat",	6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat,   t_usat),
24750
24751/*  ARM V6 not included in V7M.  */
24752#undef  THUMB_VARIANT
24753#define THUMB_VARIANT  & arm_ext_v6_notm
24754 TUF("rfeia",	8900a00, e990c000, 1, (RRw),			   rfe, rfe),
24755 TUF("rfe",	8900a00, e990c000, 1, (RRw),			   rfe, rfe),
24756  UF(rfeib,	9900a00,           1, (RRw),			   rfe),
24757  UF(rfeda,	8100a00,           1, (RRw),			   rfe),
24758 TUF("rfedb",	9100a00, e810c000, 1, (RRw),			   rfe, rfe),
24759 TUF("rfefd",	8900a00, e990c000, 1, (RRw),			   rfe, rfe),
24760  UF(rfefa,	8100a00,           1, (RRw),			   rfe),
24761 TUF("rfeea",	9100a00, e810c000, 1, (RRw),			   rfe, rfe),
24762  UF(rfeed,	9900a00,           1, (RRw),			   rfe),
24763 TUF("srsia",	8c00500, e980c000, 2, (oRRw, I31w),		   srs,  srs),
24764 TUF("srs",	8c00500, e980c000, 2, (oRRw, I31w),		   srs,  srs),
24765 TUF("srsea",	8c00500, e980c000, 2, (oRRw, I31w),		   srs,  srs),
24766  UF(srsib,	9c00500,           2, (oRRw, I31w),		   srs),
24767  UF(srsfa,	9c00500,           2, (oRRw, I31w),		   srs),
24768  UF(srsda,	8400500,	   2, (oRRw, I31w),		   srs),
24769  UF(srsed,	8400500,	   2, (oRRw, I31w),		   srs),
24770 TUF("srsdb",	9400500, e800c000, 2, (oRRw, I31w),		   srs,  srs),
24771 TUF("srsfd",	9400500, e800c000, 2, (oRRw, I31w),		   srs,  srs),
24772 TUF("cps",	1020000, f3af8100, 1, (I31b),			  imm0, t_cps),
24773
24774/*  ARM V6 not included in V7M (eg. integer SIMD).  */
24775#undef  THUMB_VARIANT
24776#define THUMB_VARIANT  & arm_ext_v6_dsp
24777 TCE("pkhbt",	6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll),   pkhbt, t_pkhbt),
24778 TCE("pkhtb",	6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar),   pkhtb, t_pkhtb),
24779 TCE("qadd16",	6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24780 TCE("qadd8",	6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24781 TCE("qasx",	6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24782 /* Old name for QASX.  */
24783 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24784 TCE("qsax",	6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24785 /* Old name for QSAX.  */
24786 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24787 TCE("qsub16",	6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24788 TCE("qsub8",	6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24789 TCE("sadd16",	6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24790 TCE("sadd8",	6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24791 TCE("sasx",	6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24792 /* Old name for SASX.  */
24793 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24794 TCE("shadd16",	6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24795 TCE("shadd8",	6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24796 TCE("shasx",   6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24797 /* Old name for SHASX.  */
24798 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24799 TCE("shsax",     6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24800 /* Old name for SHSAX.  */
24801 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24802 TCE("shsub16",	6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24803 TCE("shsub8",	6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24804 TCE("ssax",	6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24805 /* Old name for SSAX.  */
24806 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24807 TCE("ssub16",	6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24808 TCE("ssub8",	6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24809 TCE("uadd16",	6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24810 TCE("uadd8",	6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24811 TCE("uasx",	6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24812 /* Old name for UASX.  */
24813 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24814 TCE("uhadd16",	6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24815 TCE("uhadd8",	6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24816 TCE("uhasx",   6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24817 /* Old name for UHASX.  */
24818 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24819 TCE("uhsax",     6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24820 /* Old name for UHSAX.  */
24821 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24822 TCE("uhsub16",	6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24823 TCE("uhsub8",	6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24824 TCE("uqadd16",	6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24825 TCE("uqadd8",	6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24826 TCE("uqasx",   6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24827 /* Old name for UQASX.  */
24828 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24829 TCE("uqsax",     6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24830 /* Old name for UQSAX.  */
24831 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24832 TCE("uqsub16",	6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24833 TCE("uqsub8",	6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24834 TCE("usub16",	6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24835 TCE("usax",	6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24836 /* Old name for USAX.  */
24837 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24838 TCE("usub8",	6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24839 TCE("sxtah",	6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24840 TCE("sxtab16",	6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24841 TCE("sxtab",	6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24842 TCE("sxtb16",	68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR),	   sxth,  t_sxth),
24843 TCE("uxtah",	6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24844 TCE("uxtab16",	6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24845 TCE("uxtab",	6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
24846 TCE("uxtb16",	6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR),	   sxth,  t_sxth),
24847 TCE("sel",	6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc),	   rd_rn_rm, t_simd),
24848 TCE("smlad",	7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24849 TCE("smladx",	7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24850 TCE("smlald",	7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24851 TCE("smlaldx",	7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24852 TCE("smlsd",	7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24853 TCE("smlsdx",	7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24854 TCE("smlsld",	7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24855 TCE("smlsldx",	7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
24856 TCE("smmla",	7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24857 TCE("smmlar",	7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24858 TCE("smmls",	75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24859 TCE("smmlsr",	75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
24860 TCE("smmul",	750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
24861 TCE("smmulr",	750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
24862 TCE("smuad",	700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
24863 TCE("smuadx",	700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
24864 TCE("smusd",	700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
24865 TCE("smusdx",	700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc),	   smul, t_simd),
24866 TCE("ssat16",	6a00f30, f3200000, 3, (RRnpc, I16, RRnpc),	   ssat16, t_ssat16),
24867 TCE("umaal",	0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,  t_mlal),
24868 TCE("usad8",	780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc),	   smul,   t_simd),
24869 TCE("usada8",	7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla,   t_mla),
24870 TCE("usat16",	6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc),	   usat16, t_usat16),
24871
24872#undef  ARM_VARIANT
24873#define ARM_VARIANT   & arm_ext_v6k_v6t2
24874#undef  THUMB_VARIANT
24875#define THUMB_VARIANT & arm_ext_v6k_v6t2
24876
24877 tCE("yield",	320f001, _yield,    0, (), noargs, t_hint),
24878 tCE("wfe",	320f002, _wfe,      0, (), noargs, t_hint),
24879 tCE("wfi",	320f003, _wfi,      0, (), noargs, t_hint),
24880 tCE("sev",	320f004, _sev,      0, (), noargs, t_hint),
24881
24882#undef  THUMB_VARIANT
24883#define THUMB_VARIANT  & arm_ext_v6_notm
24884 TCE("ldrexd",	1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
24885				      ldrexd, t_ldrexd),
24886 TCE("strexd",	1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
24887				       RRnpcb), strexd, t_strexd),
24888
24889#undef  THUMB_VARIANT
24890#define THUMB_VARIANT  & arm_ext_v6t2_v8m
24891 TCE("ldrexb",	1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
24892     rd_rn,  rd_rn),
24893 TCE("ldrexh",	1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
24894     rd_rn,  rd_rn),
24895 TCE("strexb",	1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
24896     strex, t_strexbh),
24897 TCE("strexh",	1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
24898     strex, t_strexbh),
24899 TUF("clrex",	57ff01f, f3bf8f2f, 0, (),			      noargs, noargs),
24900
24901#undef  ARM_VARIANT
24902#define ARM_VARIANT    & arm_ext_sec
24903#undef  THUMB_VARIANT
24904#define THUMB_VARIANT  & arm_ext_sec
24905
24906 TCE("smc",	1600070, f7f08000, 1, (EXPi), smc, t_smc),
24907
24908#undef	ARM_VARIANT
24909#define	ARM_VARIANT    & arm_ext_virt
24910#undef	THUMB_VARIANT
24911#define	THUMB_VARIANT    & arm_ext_virt
24912
24913 TCE("hvc",	1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
24914 TCE("eret",	160006e, f3de8f00, 0, (), noargs, noargs),
24915
24916#undef	ARM_VARIANT
24917#define	ARM_VARIANT    & arm_ext_pan
24918#undef	THUMB_VARIANT
24919#define	THUMB_VARIANT  & arm_ext_pan
24920
24921 TUF("setpan",	1100000, b610, 1, (I7), setpan, t_setpan),
24922
24923#undef  ARM_VARIANT
24924#define ARM_VARIANT    & arm_ext_v6t2
24925#undef  THUMB_VARIANT
24926#define THUMB_VARIANT  & arm_ext_v6t2
24927
24928 TCE("bfc",	7c0001f, f36f0000, 3, (RRnpc, I31, I32),	   bfc, t_bfc),
24929 TCE("bfi",	7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
24930 TCE("sbfx",	7a00050, f3400000, 4, (RR, RR, I31, I32),	   bfx, t_bfx),
24931 TCE("ubfx",	7e00050, f3c00000, 4, (RR, RR, I31, I32),	   bfx, t_bfx),
24932
24933 TCE("mls",	0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
24934 TCE("rbit",	6ff0f30, fa90f0a0, 2, (RR, RR),			    rd_rm, t_rbit),
24935
24936 TC3("ldrht",	03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24937 TC3("ldrsht",	03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24938 TC3("ldrsbt",	03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24939 TC3("strht",	02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
24940
24941#undef  ARM_VARIANT
24942#define ARM_VARIANT    & arm_ext_v3
24943#undef  THUMB_VARIANT
24944#define THUMB_VARIANT  & arm_ext_v6t2
24945
24946 TUE("csdb",	320f014, f3af8014, 0, (), noargs, t_csdb),
24947 TUF("ssbb",	57ff040, f3bf8f40, 0, (), noargs, t_csdb),
24948 TUF("pssbb",	57ff044, f3bf8f44, 0, (), noargs, t_csdb),
24949
24950#undef  ARM_VARIANT
24951#define ARM_VARIANT    & arm_ext_v6t2
24952#undef  THUMB_VARIANT
24953#define THUMB_VARIANT  & arm_ext_v6t2_v8m
24954 TCE("movw",	3000000, f2400000, 2, (RRnpc, HALF),		    mov16, t_mov16),
24955 TCE("movt",	3400000, f2c00000, 2, (RRnpc, HALF),		    mov16, t_mov16),
24956
24957 /* Thumb-only instructions.  */
24958#undef  ARM_VARIANT
24959#define ARM_VARIANT NULL
24960  TUE("cbnz",     0,           b900,     2, (RR, EXP), 0, t_cbz),
24961  TUE("cbz",      0,           b100,     2, (RR, EXP), 0, t_cbz),
24962
24963 /* ARM does not really have an IT instruction, so always allow it.
24964    The opcode is copied from Thumb in order to allow warnings in
24965    -mimplicit-it=[never | arm] modes.  */
24966#undef  ARM_VARIANT
24967#define ARM_VARIANT  & arm_ext_v1
24968#undef  THUMB_VARIANT
24969#define THUMB_VARIANT  & arm_ext_v6t2
24970
24971 TUE("it",        bf08,        bf08,     1, (COND),   it,    t_it),
24972 TUE("itt",       bf0c,        bf0c,     1, (COND),   it,    t_it),
24973 TUE("ite",       bf04,        bf04,     1, (COND),   it,    t_it),
24974 TUE("ittt",      bf0e,        bf0e,     1, (COND),   it,    t_it),
24975 TUE("itet",      bf06,        bf06,     1, (COND),   it,    t_it),
24976 TUE("itte",      bf0a,        bf0a,     1, (COND),   it,    t_it),
24977 TUE("itee",      bf02,        bf02,     1, (COND),   it,    t_it),
24978 TUE("itttt",     bf0f,        bf0f,     1, (COND),   it,    t_it),
24979 TUE("itett",     bf07,        bf07,     1, (COND),   it,    t_it),
24980 TUE("ittet",     bf0b,        bf0b,     1, (COND),   it,    t_it),
24981 TUE("iteet",     bf03,        bf03,     1, (COND),   it,    t_it),
24982 TUE("ittte",     bf0d,        bf0d,     1, (COND),   it,    t_it),
24983 TUE("itete",     bf05,        bf05,     1, (COND),   it,    t_it),
24984 TUE("ittee",     bf09,        bf09,     1, (COND),   it,    t_it),
24985 TUE("iteee",     bf01,        bf01,     1, (COND),   it,    t_it),
24986 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent.  */
24987 TC3("rrx",       01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
24988 TC3("rrxs",      01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
24989
24990 /* Thumb2 only instructions.  */
24991#undef  ARM_VARIANT
24992#define ARM_VARIANT  NULL
24993
24994 TCE("addw",	0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24995 TCE("subw",	0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24996 TCE("orn",       0, ea600000, 3, (RR, oRR, SH),  0, t_orn),
24997 TCE("orns",      0, ea700000, 3, (RR, oRR, SH),  0, t_orn),
24998 TCE("tbb",       0, e8d0f000, 1, (TB), 0, t_tb),
24999 TCE("tbh",       0, e8d0f010, 1, (TB), 0, t_tb),
25000
25001 /* Hardware division instructions.  */
25002#undef  ARM_VARIANT
25003#define ARM_VARIANT    & arm_ext_adiv
25004#undef  THUMB_VARIANT
25005#define THUMB_VARIANT  & arm_ext_div
25006
25007 TCE("sdiv",	710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
25008 TCE("udiv",	730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
25009
25010 /* ARM V6M/V7 instructions.  */
25011#undef  ARM_VARIANT
25012#define ARM_VARIANT    & arm_ext_barrier
25013#undef  THUMB_VARIANT
25014#define THUMB_VARIANT  & arm_ext_barrier
25015
25016 TUF("dmb",	57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
25017 TUF("dsb",	57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
25018 TUF("isb",	57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
25019
25020 /* ARM V7 instructions.  */
25021#undef  ARM_VARIANT
25022#define ARM_VARIANT    & arm_ext_v7
25023#undef  THUMB_VARIANT
25024#define THUMB_VARIANT  & arm_ext_v7
25025
25026 TUF("pli",	450f000, f910f000, 1, (ADDR),	  pli,	    t_pld),
25027 TCE("dbg",	320f0f0, f3af80f0, 1, (I15),	  dbg,	    t_dbg),
25028
25029#undef  ARM_VARIANT
25030#define ARM_VARIANT    & arm_ext_mp
25031#undef  THUMB_VARIANT
25032#define THUMB_VARIANT  & arm_ext_mp
25033
25034 TUF("pldw",	410f000, f830f000, 1, (ADDR),	pld,	t_pld),
25035
25036 /* AArchv8 instructions.  */
25037#undef  ARM_VARIANT
25038#define ARM_VARIANT   & arm_ext_v8
25039
25040/* Instructions shared between armv8-a and armv8-m.  */
25041#undef  THUMB_VARIANT
25042#define THUMB_VARIANT & arm_ext_atomics
25043
25044 TCE("lda",	1900c9f, e8d00faf, 2, (RRnpc, RRnpcb),	rd_rn,	rd_rn),
25045 TCE("ldab",	1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb),	rd_rn,  rd_rn),
25046 TCE("ldah",	1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb),	rd_rn,  rd_rn),
25047 TCE("stl",	180fc90, e8c00faf, 2, (RRnpc, RRnpcb),	rm_rn,  rd_rn),
25048 TCE("stlb",	1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb),	rm_rn,  rd_rn),
25049 TCE("stlh",	1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb),	rm_rn,  rd_rn),
25050 TCE("ldaex",	1900e9f, e8d00fef, 2, (RRnpc, RRnpcb),	rd_rn,	rd_rn),
25051 TCE("ldaexb",	1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb),	rd_rn,  rd_rn),
25052 TCE("ldaexh",	1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb),	rd_rn,  rd_rn),
25053 TCE("stlex",	1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
25054							stlex,  t_stlex),
25055 TCE("stlexb",	1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
25056							stlex, t_stlex),
25057 TCE("stlexh",	1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
25058							stlex, t_stlex),
25059#undef  THUMB_VARIANT
25060#define THUMB_VARIANT & arm_ext_v8
25061
25062 tCE("sevl",	320f005, _sevl,    0, (),		noargs,	t_hint),
25063 TCE("ldaexd",	1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
25064							ldrexd, t_ldrexd),
25065 TCE("stlexd",	1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
25066							strexd, t_strexd),
25067#undef THUMB_VARIANT
25068#define THUMB_VARIANT & arm_ext_v8r
25069#undef ARM_VARIANT
25070#define ARM_VARIANT & arm_ext_v8r
25071
25072/* ARMv8-R instructions.  */
25073 TUF("dfb",	57ff04c, f3bf8f4c, 0, (), noargs, noargs),
25074
25075/* Defined in V8 but is in undefined encoding space for earlier
25076   architectures.  However earlier architectures are required to treat
25077   this instuction as a semihosting trap as well.  Hence while not explicitly
25078   defined as such, it is in fact correct to define the instruction for all
25079   architectures.  */
25080#undef  THUMB_VARIANT
25081#define THUMB_VARIANT  & arm_ext_v1
25082#undef  ARM_VARIANT
25083#define ARM_VARIANT  & arm_ext_v1
25084 TUE("hlt",	1000070, ba80,     1, (oIffffb),	bkpt,	t_hlt),
25085
25086 /* ARMv8 T32 only.  */
25087#undef  ARM_VARIANT
25088#define ARM_VARIANT  NULL
25089 TUF("dcps1",	0,	 f78f8001, 0, (),	noargs, noargs),
25090 TUF("dcps2",	0,	 f78f8002, 0, (),	noargs, noargs),
25091 TUF("dcps3",	0,	 f78f8003, 0, (),	noargs, noargs),
25092
25093  /* FP for ARMv8.  */
25094#undef  ARM_VARIANT
25095#define ARM_VARIANT   & fpu_vfp_ext_armv8xd
25096#undef  THUMB_VARIANT
25097#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
25098
25099  nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD),		vsel),
25100  nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD),		vsel),
25101  nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD),		vsel),
25102  nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD),		vsel),
25103  nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ),		vrintr),
25104  mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ),		vrintz),
25105  mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ),		vrintx),
25106  mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ),		vrinta),
25107  mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ),		vrintn),
25108  mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ),		vrintp),
25109  mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ),		vrintm),
25110
25111  /* Crypto v1 extensions.  */
25112#undef  ARM_VARIANT
25113#define ARM_VARIANT & fpu_crypto_ext_armv8
25114#undef  THUMB_VARIANT
25115#define THUMB_VARIANT & fpu_crypto_ext_armv8
25116
25117  nUF(aese, _aes, 2, (RNQ, RNQ), aese),
25118  nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
25119  nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
25120  nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
25121  nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
25122  nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
25123  nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
25124  nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
25125  nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
25126  nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
25127  nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
25128  nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
25129  nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
25130  nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
25131
25132#undef  ARM_VARIANT
25133#define ARM_VARIANT   & arm_ext_crc
25134#undef  THUMB_VARIANT
25135#define THUMB_VARIANT & arm_ext_crc
25136  TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
25137  TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
25138  TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
25139  TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
25140  TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
25141  TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
25142
25143 /* ARMv8.2 RAS extension.  */
25144#undef  ARM_VARIANT
25145#define ARM_VARIANT   & arm_ext_ras
25146#undef  THUMB_VARIANT
25147#define THUMB_VARIANT & arm_ext_ras
25148 TUE ("esb", 320f010, f3af8010, 0, (), noargs,  noargs),
25149
25150#undef  ARM_VARIANT
25151#define ARM_VARIANT   & arm_ext_v8_3
25152#undef  THUMB_VARIANT
25153#define THUMB_VARIANT & arm_ext_v8_3
25154 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
25155
25156#undef  ARM_VARIANT
25157#define ARM_VARIANT   & fpu_neon_ext_dotprod
25158#undef  THUMB_VARIANT
25159#define THUMB_VARIANT & fpu_neon_ext_dotprod
25160 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
25161 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
25162
25163#undef  ARM_VARIANT
25164#define ARM_VARIANT  & fpu_fpa_ext_v1  /* Core FPA instruction set (V1).  */
25165#undef  THUMB_VARIANT
25166#define THUMB_VARIANT NULL
25167
25168 cCE("wfs",	e200110, 1, (RR),	     rd),
25169 cCE("rfs",	e300110, 1, (RR),	     rd),
25170 cCE("wfc",	e400110, 1, (RR),	     rd),
25171 cCE("rfc",	e500110, 1, (RR),	     rd),
25172
25173 cCL("ldfs",	c100100, 2, (RF, ADDRGLDC),  rd_cpaddr),
25174 cCL("ldfd",	c108100, 2, (RF, ADDRGLDC),  rd_cpaddr),
25175 cCL("ldfe",	c500100, 2, (RF, ADDRGLDC),  rd_cpaddr),
25176 cCL("ldfp",	c508100, 2, (RF, ADDRGLDC),  rd_cpaddr),
25177
25178 cCL("stfs",	c000100, 2, (RF, ADDRGLDC),  rd_cpaddr),
25179 cCL("stfd",	c008100, 2, (RF, ADDRGLDC),  rd_cpaddr),
25180 cCL("stfe",	c400100, 2, (RF, ADDRGLDC),  rd_cpaddr),
25181 cCL("stfp",	c408100, 2, (RF, ADDRGLDC),  rd_cpaddr),
25182
25183 cCL("mvfs",	e008100, 2, (RF, RF_IF),     rd_rm),
25184 cCL("mvfsp",	e008120, 2, (RF, RF_IF),     rd_rm),
25185 cCL("mvfsm",	e008140, 2, (RF, RF_IF),     rd_rm),
25186 cCL("mvfsz",	e008160, 2, (RF, RF_IF),     rd_rm),
25187 cCL("mvfd",	e008180, 2, (RF, RF_IF),     rd_rm),
25188 cCL("mvfdp",	e0081a0, 2, (RF, RF_IF),     rd_rm),
25189 cCL("mvfdm",	e0081c0, 2, (RF, RF_IF),     rd_rm),
25190 cCL("mvfdz",	e0081e0, 2, (RF, RF_IF),     rd_rm),
25191 cCL("mvfe",	e088100, 2, (RF, RF_IF),     rd_rm),
25192 cCL("mvfep",	e088120, 2, (RF, RF_IF),     rd_rm),
25193 cCL("mvfem",	e088140, 2, (RF, RF_IF),     rd_rm),
25194 cCL("mvfez",	e088160, 2, (RF, RF_IF),     rd_rm),
25195
25196 cCL("mnfs",	e108100, 2, (RF, RF_IF),     rd_rm),
25197 cCL("mnfsp",	e108120, 2, (RF, RF_IF),     rd_rm),
25198 cCL("mnfsm",	e108140, 2, (RF, RF_IF),     rd_rm),
25199 cCL("mnfsz",	e108160, 2, (RF, RF_IF),     rd_rm),
25200 cCL("mnfd",	e108180, 2, (RF, RF_IF),     rd_rm),
25201 cCL("mnfdp",	e1081a0, 2, (RF, RF_IF),     rd_rm),
25202 cCL("mnfdm",	e1081c0, 2, (RF, RF_IF),     rd_rm),
25203 cCL("mnfdz",	e1081e0, 2, (RF, RF_IF),     rd_rm),
25204 cCL("mnfe",	e188100, 2, (RF, RF_IF),     rd_rm),
25205 cCL("mnfep",	e188120, 2, (RF, RF_IF),     rd_rm),
25206 cCL("mnfem",	e188140, 2, (RF, RF_IF),     rd_rm),
25207 cCL("mnfez",	e188160, 2, (RF, RF_IF),     rd_rm),
25208
25209 cCL("abss",	e208100, 2, (RF, RF_IF),     rd_rm),
25210 cCL("abssp",	e208120, 2, (RF, RF_IF),     rd_rm),
25211 cCL("abssm",	e208140, 2, (RF, RF_IF),     rd_rm),
25212 cCL("abssz",	e208160, 2, (RF, RF_IF),     rd_rm),
25213 cCL("absd",	e208180, 2, (RF, RF_IF),     rd_rm),
25214 cCL("absdp",	e2081a0, 2, (RF, RF_IF),     rd_rm),
25215 cCL("absdm",	e2081c0, 2, (RF, RF_IF),     rd_rm),
25216 cCL("absdz",	e2081e0, 2, (RF, RF_IF),     rd_rm),
25217 cCL("abse",	e288100, 2, (RF, RF_IF),     rd_rm),
25218 cCL("absep",	e288120, 2, (RF, RF_IF),     rd_rm),
25219 cCL("absem",	e288140, 2, (RF, RF_IF),     rd_rm),
25220 cCL("absez",	e288160, 2, (RF, RF_IF),     rd_rm),
25221
25222 cCL("rnds",	e308100, 2, (RF, RF_IF),     rd_rm),
25223 cCL("rndsp",	e308120, 2, (RF, RF_IF),     rd_rm),
25224 cCL("rndsm",	e308140, 2, (RF, RF_IF),     rd_rm),
25225 cCL("rndsz",	e308160, 2, (RF, RF_IF),     rd_rm),
25226 cCL("rndd",	e308180, 2, (RF, RF_IF),     rd_rm),
25227 cCL("rnddp",	e3081a0, 2, (RF, RF_IF),     rd_rm),
25228 cCL("rnddm",	e3081c0, 2, (RF, RF_IF),     rd_rm),
25229 cCL("rnddz",	e3081e0, 2, (RF, RF_IF),     rd_rm),
25230 cCL("rnde",	e388100, 2, (RF, RF_IF),     rd_rm),
25231 cCL("rndep",	e388120, 2, (RF, RF_IF),     rd_rm),
25232 cCL("rndem",	e388140, 2, (RF, RF_IF),     rd_rm),
25233 cCL("rndez",	e388160, 2, (RF, RF_IF),     rd_rm),
25234
25235 cCL("sqts",	e408100, 2, (RF, RF_IF),     rd_rm),
25236 cCL("sqtsp",	e408120, 2, (RF, RF_IF),     rd_rm),
25237 cCL("sqtsm",	e408140, 2, (RF, RF_IF),     rd_rm),
25238 cCL("sqtsz",	e408160, 2, (RF, RF_IF),     rd_rm),
25239 cCL("sqtd",	e408180, 2, (RF, RF_IF),     rd_rm),
25240 cCL("sqtdp",	e4081a0, 2, (RF, RF_IF),     rd_rm),
25241 cCL("sqtdm",	e4081c0, 2, (RF, RF_IF),     rd_rm),
25242 cCL("sqtdz",	e4081e0, 2, (RF, RF_IF),     rd_rm),
25243 cCL("sqte",	e488100, 2, (RF, RF_IF),     rd_rm),
25244 cCL("sqtep",	e488120, 2, (RF, RF_IF),     rd_rm),
25245 cCL("sqtem",	e488140, 2, (RF, RF_IF),     rd_rm),
25246 cCL("sqtez",	e488160, 2, (RF, RF_IF),     rd_rm),
25247
25248 cCL("logs",	e508100, 2, (RF, RF_IF),     rd_rm),
25249 cCL("logsp",	e508120, 2, (RF, RF_IF),     rd_rm),
25250 cCL("logsm",	e508140, 2, (RF, RF_IF),     rd_rm),
25251 cCL("logsz",	e508160, 2, (RF, RF_IF),     rd_rm),
25252 cCL("logd",	e508180, 2, (RF, RF_IF),     rd_rm),
25253 cCL("logdp",	e5081a0, 2, (RF, RF_IF),     rd_rm),
25254 cCL("logdm",	e5081c0, 2, (RF, RF_IF),     rd_rm),
25255 cCL("logdz",	e5081e0, 2, (RF, RF_IF),     rd_rm),
25256 cCL("loge",	e588100, 2, (RF, RF_IF),     rd_rm),
25257 cCL("logep",	e588120, 2, (RF, RF_IF),     rd_rm),
25258 cCL("logem",	e588140, 2, (RF, RF_IF),     rd_rm),
25259 cCL("logez",	e588160, 2, (RF, RF_IF),     rd_rm),
25260
25261 cCL("lgns",	e608100, 2, (RF, RF_IF),     rd_rm),
25262 cCL("lgnsp",	e608120, 2, (RF, RF_IF),     rd_rm),
25263 cCL("lgnsm",	e608140, 2, (RF, RF_IF),     rd_rm),
25264 cCL("lgnsz",	e608160, 2, (RF, RF_IF),     rd_rm),
25265 cCL("lgnd",	e608180, 2, (RF, RF_IF),     rd_rm),
25266 cCL("lgndp",	e6081a0, 2, (RF, RF_IF),     rd_rm),
25267 cCL("lgndm",	e6081c0, 2, (RF, RF_IF),     rd_rm),
25268 cCL("lgndz",	e6081e0, 2, (RF, RF_IF),     rd_rm),
25269 cCL("lgne",	e688100, 2, (RF, RF_IF),     rd_rm),
25270 cCL("lgnep",	e688120, 2, (RF, RF_IF),     rd_rm),
25271 cCL("lgnem",	e688140, 2, (RF, RF_IF),     rd_rm),
25272 cCL("lgnez",	e688160, 2, (RF, RF_IF),     rd_rm),
25273
25274 cCL("exps",	e708100, 2, (RF, RF_IF),     rd_rm),
25275 cCL("expsp",	e708120, 2, (RF, RF_IF),     rd_rm),
25276 cCL("expsm",	e708140, 2, (RF, RF_IF),     rd_rm),
25277 cCL("expsz",	e708160, 2, (RF, RF_IF),     rd_rm),
25278 cCL("expd",	e708180, 2, (RF, RF_IF),     rd_rm),
25279 cCL("expdp",	e7081a0, 2, (RF, RF_IF),     rd_rm),
25280 cCL("expdm",	e7081c0, 2, (RF, RF_IF),     rd_rm),
25281 cCL("expdz",	e7081e0, 2, (RF, RF_IF),     rd_rm),
25282 cCL("expe",	e788100, 2, (RF, RF_IF),     rd_rm),
25283 cCL("expep",	e788120, 2, (RF, RF_IF),     rd_rm),
25284 cCL("expem",	e788140, 2, (RF, RF_IF),     rd_rm),
25285 cCL("expdz",	e788160, 2, (RF, RF_IF),     rd_rm),
25286
25287 cCL("sins",	e808100, 2, (RF, RF_IF),     rd_rm),
25288 cCL("sinsp",	e808120, 2, (RF, RF_IF),     rd_rm),
25289 cCL("sinsm",	e808140, 2, (RF, RF_IF),     rd_rm),
25290 cCL("sinsz",	e808160, 2, (RF, RF_IF),     rd_rm),
25291 cCL("sind",	e808180, 2, (RF, RF_IF),     rd_rm),
25292 cCL("sindp",	e8081a0, 2, (RF, RF_IF),     rd_rm),
25293 cCL("sindm",	e8081c0, 2, (RF, RF_IF),     rd_rm),
25294 cCL("sindz",	e8081e0, 2, (RF, RF_IF),     rd_rm),
25295 cCL("sine",	e888100, 2, (RF, RF_IF),     rd_rm),
25296 cCL("sinep",	e888120, 2, (RF, RF_IF),     rd_rm),
25297 cCL("sinem",	e888140, 2, (RF, RF_IF),     rd_rm),
25298 cCL("sinez",	e888160, 2, (RF, RF_IF),     rd_rm),
25299
25300 cCL("coss",	e908100, 2, (RF, RF_IF),     rd_rm),
25301 cCL("cossp",	e908120, 2, (RF, RF_IF),     rd_rm),
25302 cCL("cossm",	e908140, 2, (RF, RF_IF),     rd_rm),
25303 cCL("cossz",	e908160, 2, (RF, RF_IF),     rd_rm),
25304 cCL("cosd",	e908180, 2, (RF, RF_IF),     rd_rm),
25305 cCL("cosdp",	e9081a0, 2, (RF, RF_IF),     rd_rm),
25306 cCL("cosdm",	e9081c0, 2, (RF, RF_IF),     rd_rm),
25307 cCL("cosdz",	e9081e0, 2, (RF, RF_IF),     rd_rm),
25308 cCL("cose",	e988100, 2, (RF, RF_IF),     rd_rm),
25309 cCL("cosep",	e988120, 2, (RF, RF_IF),     rd_rm),
25310 cCL("cosem",	e988140, 2, (RF, RF_IF),     rd_rm),
25311 cCL("cosez",	e988160, 2, (RF, RF_IF),     rd_rm),
25312
25313 cCL("tans",	ea08100, 2, (RF, RF_IF),     rd_rm),
25314 cCL("tansp",	ea08120, 2, (RF, RF_IF),     rd_rm),
25315 cCL("tansm",	ea08140, 2, (RF, RF_IF),     rd_rm),
25316 cCL("tansz",	ea08160, 2, (RF, RF_IF),     rd_rm),
25317 cCL("tand",	ea08180, 2, (RF, RF_IF),     rd_rm),
25318 cCL("tandp",	ea081a0, 2, (RF, RF_IF),     rd_rm),
25319 cCL("tandm",	ea081c0, 2, (RF, RF_IF),     rd_rm),
25320 cCL("tandz",	ea081e0, 2, (RF, RF_IF),     rd_rm),
25321 cCL("tane",	ea88100, 2, (RF, RF_IF),     rd_rm),
25322 cCL("tanep",	ea88120, 2, (RF, RF_IF),     rd_rm),
25323 cCL("tanem",	ea88140, 2, (RF, RF_IF),     rd_rm),
25324 cCL("tanez",	ea88160, 2, (RF, RF_IF),     rd_rm),
25325
25326 cCL("asns",	eb08100, 2, (RF, RF_IF),     rd_rm),
25327 cCL("asnsp",	eb08120, 2, (RF, RF_IF),     rd_rm),
25328 cCL("asnsm",	eb08140, 2, (RF, RF_IF),     rd_rm),
25329 cCL("asnsz",	eb08160, 2, (RF, RF_IF),     rd_rm),
25330 cCL("asnd",	eb08180, 2, (RF, RF_IF),     rd_rm),
25331 cCL("asndp",	eb081a0, 2, (RF, RF_IF),     rd_rm),
25332 cCL("asndm",	eb081c0, 2, (RF, RF_IF),     rd_rm),
25333 cCL("asndz",	eb081e0, 2, (RF, RF_IF),     rd_rm),
25334 cCL("asne",	eb88100, 2, (RF, RF_IF),     rd_rm),
25335 cCL("asnep",	eb88120, 2, (RF, RF_IF),     rd_rm),
25336 cCL("asnem",	eb88140, 2, (RF, RF_IF),     rd_rm),
25337 cCL("asnez",	eb88160, 2, (RF, RF_IF),     rd_rm),
25338
25339 cCL("acss",	ec08100, 2, (RF, RF_IF),     rd_rm),
25340 cCL("acssp",	ec08120, 2, (RF, RF_IF),     rd_rm),
25341 cCL("acssm",	ec08140, 2, (RF, RF_IF),     rd_rm),
25342 cCL("acssz",	ec08160, 2, (RF, RF_IF),     rd_rm),
25343 cCL("acsd",	ec08180, 2, (RF, RF_IF),     rd_rm),
25344 cCL("acsdp",	ec081a0, 2, (RF, RF_IF),     rd_rm),
25345 cCL("acsdm",	ec081c0, 2, (RF, RF_IF),     rd_rm),
25346 cCL("acsdz",	ec081e0, 2, (RF, RF_IF),     rd_rm),
25347 cCL("acse",	ec88100, 2, (RF, RF_IF),     rd_rm),
25348 cCL("acsep",	ec88120, 2, (RF, RF_IF),     rd_rm),
25349 cCL("acsem",	ec88140, 2, (RF, RF_IF),     rd_rm),
25350 cCL("acsez",	ec88160, 2, (RF, RF_IF),     rd_rm),
25351
25352 cCL("atns",	ed08100, 2, (RF, RF_IF),     rd_rm),
25353 cCL("atnsp",	ed08120, 2, (RF, RF_IF),     rd_rm),
25354 cCL("atnsm",	ed08140, 2, (RF, RF_IF),     rd_rm),
25355 cCL("atnsz",	ed08160, 2, (RF, RF_IF),     rd_rm),
25356 cCL("atnd",	ed08180, 2, (RF, RF_IF),     rd_rm),
25357 cCL("atndp",	ed081a0, 2, (RF, RF_IF),     rd_rm),
25358 cCL("atndm",	ed081c0, 2, (RF, RF_IF),     rd_rm),
25359 cCL("atndz",	ed081e0, 2, (RF, RF_IF),     rd_rm),
25360 cCL("atne",	ed88100, 2, (RF, RF_IF),     rd_rm),
25361 cCL("atnep",	ed88120, 2, (RF, RF_IF),     rd_rm),
25362 cCL("atnem",	ed88140, 2, (RF, RF_IF),     rd_rm),
25363 cCL("atnez",	ed88160, 2, (RF, RF_IF),     rd_rm),
25364
25365 cCL("urds",	ee08100, 2, (RF, RF_IF),     rd_rm),
25366 cCL("urdsp",	ee08120, 2, (RF, RF_IF),     rd_rm),
25367 cCL("urdsm",	ee08140, 2, (RF, RF_IF),     rd_rm),
25368 cCL("urdsz",	ee08160, 2, (RF, RF_IF),     rd_rm),
25369 cCL("urdd",	ee08180, 2, (RF, RF_IF),     rd_rm),
25370 cCL("urddp",	ee081a0, 2, (RF, RF_IF),     rd_rm),
25371 cCL("urddm",	ee081c0, 2, (RF, RF_IF),     rd_rm),
25372 cCL("urddz",	ee081e0, 2, (RF, RF_IF),     rd_rm),
25373 cCL("urde",	ee88100, 2, (RF, RF_IF),     rd_rm),
25374 cCL("urdep",	ee88120, 2, (RF, RF_IF),     rd_rm),
25375 cCL("urdem",	ee88140, 2, (RF, RF_IF),     rd_rm),
25376 cCL("urdez",	ee88160, 2, (RF, RF_IF),     rd_rm),
25377
25378 cCL("nrms",	ef08100, 2, (RF, RF_IF),     rd_rm),
25379 cCL("nrmsp",	ef08120, 2, (RF, RF_IF),     rd_rm),
25380 cCL("nrmsm",	ef08140, 2, (RF, RF_IF),     rd_rm),
25381 cCL("nrmsz",	ef08160, 2, (RF, RF_IF),     rd_rm),
25382 cCL("nrmd",	ef08180, 2, (RF, RF_IF),     rd_rm),
25383 cCL("nrmdp",	ef081a0, 2, (RF, RF_IF),     rd_rm),
25384 cCL("nrmdm",	ef081c0, 2, (RF, RF_IF),     rd_rm),
25385 cCL("nrmdz",	ef081e0, 2, (RF, RF_IF),     rd_rm),
25386 cCL("nrme",	ef88100, 2, (RF, RF_IF),     rd_rm),
25387 cCL("nrmep",	ef88120, 2, (RF, RF_IF),     rd_rm),
25388 cCL("nrmem",	ef88140, 2, (RF, RF_IF),     rd_rm),
25389 cCL("nrmez",	ef88160, 2, (RF, RF_IF),     rd_rm),
25390
25391 cCL("adfs",	e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
25392 cCL("adfsp",	e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
25393 cCL("adfsm",	e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
25394 cCL("adfsz",	e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
25395 cCL("adfd",	e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
25396 cCL("adfdp",	e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25397 cCL("adfdm",	e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25398 cCL("adfdz",	e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25399 cCL("adfe",	e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
25400 cCL("adfep",	e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
25401 cCL("adfem",	e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
25402 cCL("adfez",	e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
25403
25404 cCL("sufs",	e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
25405 cCL("sufsp",	e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
25406 cCL("sufsm",	e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
25407 cCL("sufsz",	e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
25408 cCL("sufd",	e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
25409 cCL("sufdp",	e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25410 cCL("sufdm",	e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25411 cCL("sufdz",	e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25412 cCL("sufe",	e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
25413 cCL("sufep",	e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
25414 cCL("sufem",	e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
25415 cCL("sufez",	e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
25416
25417 cCL("rsfs",	e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
25418 cCL("rsfsp",	e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
25419 cCL("rsfsm",	e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
25420 cCL("rsfsz",	e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
25421 cCL("rsfd",	e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
25422 cCL("rsfdp",	e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25423 cCL("rsfdm",	e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25424 cCL("rsfdz",	e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25425 cCL("rsfe",	e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
25426 cCL("rsfep",	e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
25427 cCL("rsfem",	e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
25428 cCL("rsfez",	e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
25429
25430 cCL("mufs",	e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
25431 cCL("mufsp",	e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
25432 cCL("mufsm",	e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
25433 cCL("mufsz",	e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
25434 cCL("mufd",	e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
25435 cCL("mufdp",	e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25436 cCL("mufdm",	e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25437 cCL("mufdz",	e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25438 cCL("mufe",	e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
25439 cCL("mufep",	e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
25440 cCL("mufem",	e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
25441 cCL("mufez",	e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
25442
25443 cCL("dvfs",	e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
25444 cCL("dvfsp",	e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
25445 cCL("dvfsm",	e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
25446 cCL("dvfsz",	e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
25447 cCL("dvfd",	e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
25448 cCL("dvfdp",	e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25449 cCL("dvfdm",	e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25450 cCL("dvfdz",	e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25451 cCL("dvfe",	e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
25452 cCL("dvfep",	e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
25453 cCL("dvfem",	e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
25454 cCL("dvfez",	e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
25455
25456 cCL("rdfs",	e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
25457 cCL("rdfsp",	e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
25458 cCL("rdfsm",	e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
25459 cCL("rdfsz",	e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
25460 cCL("rdfd",	e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
25461 cCL("rdfdp",	e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25462 cCL("rdfdm",	e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25463 cCL("rdfdz",	e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25464 cCL("rdfe",	e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
25465 cCL("rdfep",	e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
25466 cCL("rdfem",	e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
25467 cCL("rdfez",	e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
25468
25469 cCL("pows",	e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
25470 cCL("powsp",	e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
25471 cCL("powsm",	e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
25472 cCL("powsz",	e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
25473 cCL("powd",	e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
25474 cCL("powdp",	e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25475 cCL("powdm",	e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25476 cCL("powdz",	e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25477 cCL("powe",	e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
25478 cCL("powep",	e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
25479 cCL("powem",	e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
25480 cCL("powez",	e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
25481
25482 cCL("rpws",	e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
25483 cCL("rpwsp",	e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
25484 cCL("rpwsm",	e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
25485 cCL("rpwsz",	e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
25486 cCL("rpwd",	e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
25487 cCL("rpwdp",	e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25488 cCL("rpwdm",	e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25489 cCL("rpwdz",	e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25490 cCL("rpwe",	e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
25491 cCL("rpwep",	e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
25492 cCL("rpwem",	e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
25493 cCL("rpwez",	e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
25494
25495 cCL("rmfs",	e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
25496 cCL("rmfsp",	e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
25497 cCL("rmfsm",	e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
25498 cCL("rmfsz",	e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
25499 cCL("rmfd",	e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
25500 cCL("rmfdp",	e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25501 cCL("rmfdm",	e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25502 cCL("rmfdz",	e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25503 cCL("rmfe",	e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
25504 cCL("rmfep",	e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
25505 cCL("rmfem",	e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
25506 cCL("rmfez",	e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
25507
25508 cCL("fmls",	e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
25509 cCL("fmlsp",	e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
25510 cCL("fmlsm",	e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
25511 cCL("fmlsz",	e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
25512 cCL("fmld",	e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
25513 cCL("fmldp",	e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25514 cCL("fmldm",	e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25515 cCL("fmldz",	e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25516 cCL("fmle",	e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
25517 cCL("fmlep",	e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
25518 cCL("fmlem",	e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
25519 cCL("fmlez",	e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
25520
25521 cCL("fdvs",	ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
25522 cCL("fdvsp",	ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
25523 cCL("fdvsm",	ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
25524 cCL("fdvsz",	ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
25525 cCL("fdvd",	ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
25526 cCL("fdvdp",	ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25527 cCL("fdvdm",	ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25528 cCL("fdvdz",	ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25529 cCL("fdve",	ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
25530 cCL("fdvep",	ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
25531 cCL("fdvem",	ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
25532 cCL("fdvez",	ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
25533
25534 cCL("frds",	eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
25535 cCL("frdsp",	eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
25536 cCL("frdsm",	eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
25537 cCL("frdsz",	eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
25538 cCL("frdd",	eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
25539 cCL("frddp",	eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25540 cCL("frddm",	eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25541 cCL("frddz",	eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25542 cCL("frde",	eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
25543 cCL("frdep",	eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
25544 cCL("frdem",	eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
25545 cCL("frdez",	eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
25546
25547 cCL("pols",	ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
25548 cCL("polsp",	ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
25549 cCL("polsm",	ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
25550 cCL("polsz",	ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
25551 cCL("pold",	ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
25552 cCL("poldp",	ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
25553 cCL("poldm",	ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
25554 cCL("poldz",	ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
25555 cCL("pole",	ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
25556 cCL("polep",	ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
25557 cCL("polem",	ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
25558 cCL("polez",	ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
25559
25560 cCE("cmf",	e90f110, 2, (RF, RF_IF),     fpa_cmp),
25561 C3E("cmfe",	ed0f110, 2, (RF, RF_IF),     fpa_cmp),
25562 cCE("cnf",	eb0f110, 2, (RF, RF_IF),     fpa_cmp),
25563 C3E("cnfe",	ef0f110, 2, (RF, RF_IF),     fpa_cmp),
25564
25565 cCL("flts",	e000110, 2, (RF, RR),	     rn_rd),
25566 cCL("fltsp",	e000130, 2, (RF, RR),	     rn_rd),
25567 cCL("fltsm",	e000150, 2, (RF, RR),	     rn_rd),
25568 cCL("fltsz",	e000170, 2, (RF, RR),	     rn_rd),
25569 cCL("fltd",	e000190, 2, (RF, RR),	     rn_rd),
25570 cCL("fltdp",	e0001b0, 2, (RF, RR),	     rn_rd),
25571 cCL("fltdm",	e0001d0, 2, (RF, RR),	     rn_rd),
25572 cCL("fltdz",	e0001f0, 2, (RF, RR),	     rn_rd),
25573 cCL("flte",	e080110, 2, (RF, RR),	     rn_rd),
25574 cCL("fltep",	e080130, 2, (RF, RR),	     rn_rd),
25575 cCL("fltem",	e080150, 2, (RF, RR),	     rn_rd),
25576 cCL("fltez",	e080170, 2, (RF, RR),	     rn_rd),
25577
25578  /* The implementation of the FIX instruction is broken on some
25579     assemblers, in that it accepts a precision specifier as well as a
25580     rounding specifier, despite the fact that this is meaningless.
25581     To be more compatible, we accept it as well, though of course it
25582     does not set any bits.  */
25583 cCE("fix",	e100110, 2, (RR, RF),	     rd_rm),
25584 cCL("fixp",	e100130, 2, (RR, RF),	     rd_rm),
25585 cCL("fixm",	e100150, 2, (RR, RF),	     rd_rm),
25586 cCL("fixz",	e100170, 2, (RR, RF),	     rd_rm),
25587 cCL("fixsp",	e100130, 2, (RR, RF),	     rd_rm),
25588 cCL("fixsm",	e100150, 2, (RR, RF),	     rd_rm),
25589 cCL("fixsz",	e100170, 2, (RR, RF),	     rd_rm),
25590 cCL("fixdp",	e100130, 2, (RR, RF),	     rd_rm),
25591 cCL("fixdm",	e100150, 2, (RR, RF),	     rd_rm),
25592 cCL("fixdz",	e100170, 2, (RR, RF),	     rd_rm),
25593 cCL("fixep",	e100130, 2, (RR, RF),	     rd_rm),
25594 cCL("fixem",	e100150, 2, (RR, RF),	     rd_rm),
25595 cCL("fixez",	e100170, 2, (RR, RF),	     rd_rm),
25596
25597  /* Instructions that were new with the real FPA, call them V2.  */
25598#undef  ARM_VARIANT
25599#define ARM_VARIANT  & fpu_fpa_ext_v2
25600
25601 cCE("lfm",	c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25602 cCL("lfmfd",	c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25603 cCL("lfmea",	d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25604 cCE("sfm",	c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25605 cCL("sfmfd",	d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25606 cCL("sfmea",	c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
25607
25608#undef  ARM_VARIANT
25609#define ARM_VARIANT  & fpu_vfp_ext_v1xd  /* VFP V1xD (single precision).  */
25610#undef THUMB_VARIANT
25611#define THUMB_VARIANT  & arm_ext_v6t2
25612 mcCE(vmrs,	ef00a10, 2, (APSR_RR, RVC),   vmrs),
25613 mcCE(vmsr,	ee00a10, 2, (RVC, RR),        vmsr),
25614 mcCE(fldd,	d100b00, 2, (RVD, ADDRGLDC),  vfp_dp_ldst),
25615 mcCE(fstd,	d000b00, 2, (RVD, ADDRGLDC),  vfp_dp_ldst),
25616 mcCE(flds,	d100a00, 2, (RVS, ADDRGLDC),  vfp_sp_ldst),
25617 mcCE(fsts,	d000a00, 2, (RVS, ADDRGLDC),  vfp_sp_ldst),
25618
25619  /* Memory operations.	 */
25620 mcCE(fldmias,	c900a00, 2, (RRnpctw, VRSLST),    vfp_sp_ldstmia),
25621 mcCE(fldmdbs,	d300a00, 2, (RRnpctw, VRSLST),    vfp_sp_ldstmdb),
25622 mcCE(fstmias,	c800a00, 2, (RRnpctw, VRSLST),    vfp_sp_ldstmia),
25623 mcCE(fstmdbs,	d200a00, 2, (RRnpctw, VRSLST),    vfp_sp_ldstmdb),
25624#undef THUMB_VARIANT
25625
25626  /* Moves and type conversions.  */
25627 cCE("fmstat",	ef1fa10, 0, (),		      noargs),
25628 cCE("fsitos",	eb80ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
25629 cCE("fuitos",	eb80a40, 2, (RVS, RVS),	      vfp_sp_monadic),
25630 cCE("ftosis",	ebd0a40, 2, (RVS, RVS),	      vfp_sp_monadic),
25631 cCE("ftosizs",	ebd0ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
25632 cCE("ftouis",	ebc0a40, 2, (RVS, RVS),	      vfp_sp_monadic),
25633 cCE("ftouizs",	ebc0ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
25634 cCE("fmrx",	ef00a10, 2, (RR, RVC),	      rd_rn),
25635 cCE("fmxr",	ee00a10, 2, (RVC, RR),	      rn_rd),
25636
25637  /* Memory operations.	 */
25638 cCE("fldmfds",	c900a00, 2, (RRnpctw, VRSLST),    vfp_sp_ldstmia),
25639 cCE("fldmeas",	d300a00, 2, (RRnpctw, VRSLST),    vfp_sp_ldstmdb),
25640 cCE("fldmiax",	c900b00, 2, (RRnpctw, VRDLST),    vfp_xp_ldstmia),
25641 cCE("fldmfdx",	c900b00, 2, (RRnpctw, VRDLST),    vfp_xp_ldstmia),
25642 cCE("fldmdbx",	d300b00, 2, (RRnpctw, VRDLST),    vfp_xp_ldstmdb),
25643 cCE("fldmeax",	d300b00, 2, (RRnpctw, VRDLST),    vfp_xp_ldstmdb),
25644 cCE("fstmeas",	c800a00, 2, (RRnpctw, VRSLST),    vfp_sp_ldstmia),
25645 cCE("fstmfds",	d200a00, 2, (RRnpctw, VRSLST),    vfp_sp_ldstmdb),
25646 cCE("fstmiax",	c800b00, 2, (RRnpctw, VRDLST),    vfp_xp_ldstmia),
25647 cCE("fstmeax",	c800b00, 2, (RRnpctw, VRDLST),    vfp_xp_ldstmia),
25648 cCE("fstmdbx",	d200b00, 2, (RRnpctw, VRDLST),    vfp_xp_ldstmdb),
25649 cCE("fstmfdx",	d200b00, 2, (RRnpctw, VRDLST),    vfp_xp_ldstmdb),
25650
25651  /* Monadic operations.  */
25652 cCE("fabss",	eb00ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
25653 cCE("fnegs",	eb10a40, 2, (RVS, RVS),	      vfp_sp_monadic),
25654 cCE("fsqrts",	eb10ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
25655
25656  /* Dyadic operations.	 */
25657 cCE("fadds",	e300a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
25658 cCE("fsubs",	e300a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
25659 cCE("fmuls",	e200a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
25660 cCE("fdivs",	e800a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
25661 cCE("fmacs",	e000a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
25662 cCE("fmscs",	e100a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
25663 cCE("fnmuls",	e200a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
25664 cCE("fnmacs",	e000a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
25665 cCE("fnmscs",	e100a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
25666
25667  /* Comparisons.  */
25668 cCE("fcmps",	eb40a40, 2, (RVS, RVS),	      vfp_sp_monadic),
25669 cCE("fcmpzs",	eb50a40, 1, (RVS),	      vfp_sp_compare_z),
25670 cCE("fcmpes",	eb40ac0, 2, (RVS, RVS),	      vfp_sp_monadic),
25671 cCE("fcmpezs",	eb50ac0, 1, (RVS),	      vfp_sp_compare_z),
25672
25673 /* Double precision load/store are still present on single precision
25674    implementations.  */
25675 cCE("fldmiad",	c900b00, 2, (RRnpctw, VRDLST),    vfp_dp_ldstmia),
25676 cCE("fldmfdd",	c900b00, 2, (RRnpctw, VRDLST),    vfp_dp_ldstmia),
25677 cCE("fldmdbd",	d300b00, 2, (RRnpctw, VRDLST),    vfp_dp_ldstmdb),
25678 cCE("fldmead",	d300b00, 2, (RRnpctw, VRDLST),    vfp_dp_ldstmdb),
25679 cCE("fstmiad",	c800b00, 2, (RRnpctw, VRDLST),    vfp_dp_ldstmia),
25680 cCE("fstmead",	c800b00, 2, (RRnpctw, VRDLST),    vfp_dp_ldstmia),
25681 cCE("fstmdbd",	d200b00, 2, (RRnpctw, VRDLST),    vfp_dp_ldstmdb),
25682 cCE("fstmfdd",	d200b00, 2, (RRnpctw, VRDLST),    vfp_dp_ldstmdb),
25683
25684#undef  ARM_VARIANT
25685#define ARM_VARIANT  & fpu_vfp_ext_v1 /* VFP V1 (Double precision).  */
25686
25687  /* Moves and type conversions.  */
25688 cCE("fcvtds",	eb70ac0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
25689 cCE("fcvtsd",	eb70bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
25690 cCE("fmdhr",	e200b10, 2, (RVD, RR),	      vfp_dp_rn_rd),
25691 cCE("fmdlr",	e000b10, 2, (RVD, RR),	      vfp_dp_rn_rd),
25692 cCE("fmrdh",	e300b10, 2, (RR, RVD),	      vfp_dp_rd_rn),
25693 cCE("fmrdl",	e100b10, 2, (RR, RVD),	      vfp_dp_rd_rn),
25694 cCE("fsitod",	eb80bc0, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
25695 cCE("fuitod",	eb80b40, 2, (RVD, RVS),	      vfp_dp_sp_cvt),
25696 cCE("ftosid",	ebd0b40, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
25697 cCE("ftosizd",	ebd0bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
25698 cCE("ftouid",	ebc0b40, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
25699 cCE("ftouizd",	ebc0bc0, 2, (RVS, RVD),	      vfp_sp_dp_cvt),
25700
25701  /* Monadic operations.  */
25702 cCE("fabsd",	eb00bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
25703 cCE("fnegd",	eb10b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
25704 cCE("fsqrtd",	eb10bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
25705
25706  /* Dyadic operations.	 */
25707 cCE("faddd",	e300b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
25708 cCE("fsubd",	e300b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
25709 cCE("fmuld",	e200b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
25710 cCE("fdivd",	e800b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
25711 cCE("fmacd",	e000b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
25712 cCE("fmscd",	e100b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
25713 cCE("fnmuld",	e200b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
25714 cCE("fnmacd",	e000b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
25715 cCE("fnmscd",	e100b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
25716
25717  /* Comparisons.  */
25718 cCE("fcmpd",	eb40b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
25719 cCE("fcmpzd",	eb50b40, 1, (RVD),	      vfp_dp_rd),
25720 cCE("fcmped",	eb40bc0, 2, (RVD, RVD),	      vfp_dp_rd_rm),
25721 cCE("fcmpezd",	eb50bc0, 1, (RVD),	      vfp_dp_rd),
25722
25723/* Instructions which may belong to either the Neon or VFP instruction sets.
25724   Individual encoder functions perform additional architecture checks.  */
25725#undef  ARM_VARIANT
25726#define ARM_VARIANT    & fpu_vfp_ext_v1xd
25727#undef  THUMB_VARIANT
25728#define THUMB_VARIANT  & arm_ext_v6t2
25729
25730 NCE(vldm,      c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25731 NCE(vldmia,    c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25732 NCE(vldmdb,    d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25733 NCE(vstm,      c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25734 NCE(vstmia,    c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25735 NCE(vstmdb,    d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
25736
25737 NCE(vpop,      0,       1, (VRSDLST),          vfp_nsyn_pop),
25738 NCE(vpush,     0,       1, (VRSDLST),          vfp_nsyn_push),
25739
25740#undef  THUMB_VARIANT
25741#define THUMB_VARIANT  & fpu_vfp_ext_v1xd
25742
25743  /* These mnemonics are unique to VFP.  */
25744 NCE(vsqrt,     0,       2, (RVSD, RVSD),       vfp_nsyn_sqrt),
25745 NCE(vdiv,      0,       3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
25746 nCE(vnmul,     _vnmul,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25747 nCE(vnmla,     _vnmla,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25748 nCE(vnmls,     _vnmls,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25749 NCE(vcvtz,     0,       2, (RVSD, RVSD),       vfp_nsyn_cvtz),
25750
25751  /* Mnemonics shared by Neon and VFP.  */
25752 nCEF(vmls,     _vmls,    3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
25753
25754 mnCEF(vcvt,     _vcvt,   3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
25755 nCEF(vcvtr,    _vcvt,   2, (RNSDQ, RNSDQ), neon_cvtr),
25756 MNCEF(vcvtb,	eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
25757 MNCEF(vcvtt,	eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
25758
25759
25760  /* NOTE: All VMOV encoding is special-cased!  */
25761 NCE(vmovq,     0,       1, (VMOV), neon_mov),
25762
25763#undef  THUMB_VARIANT
25764/* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25765   by different feature bits.  Since we are setting the Thumb guard, we can
25766   require Thumb-1 which makes it a nop guard and set the right feature bit in
25767   do_vldr_vstr ().  */
25768#define THUMB_VARIANT  & arm_ext_v4t
25769 NCE(vldr,      d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
25770 NCE(vstr,      d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
25771
25772#undef  ARM_VARIANT
25773#define ARM_VARIANT    & arm_ext_fp16
25774#undef  THUMB_VARIANT
25775#define THUMB_VARIANT  & arm_ext_fp16
25776 /* New instructions added from v8.2, allowing the extraction and insertion of
25777    the upper 16 bits of a 32-bit vector register.  */
25778 NCE (vmovx,     eb00a40,       2, (RVS, RVS), neon_movhf),
25779 NCE (vins,      eb00ac0,       2, (RVS, RVS), neon_movhf),
25780
25781 /* New backported fma/fms instructions optional in v8.2.  */
25782 NUF (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
25783 NUF (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
25784
25785#undef  THUMB_VARIANT
25786#define THUMB_VARIANT  & fpu_neon_ext_v1
25787#undef  ARM_VARIANT
25788#define ARM_VARIANT    & fpu_neon_ext_v1
25789
25790  /* Data processing with three registers of the same length.  */
25791  /* integer ops, valid types S8 S16 S32 U8 U16 U32.  */
25792 NUF(vaba,      0000710, 3, (RNDQ, RNDQ,  RNDQ), neon_dyadic_i_su),
25793 NUF(vabaq,     0000710, 3, (RNQ,  RNQ,   RNQ),  neon_dyadic_i_su),
25794 NUF(vhaddq,    0000000, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
25795 NUF(vrhaddq,   0000100, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
25796 NUF(vhsubq,    0000200, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i_su),
25797  /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64.  */
25798 NUF(vqaddq,    0000010, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i64_su),
25799 NUF(vqsubq,    0000210, 3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_i64_su),
25800 NUF(vrshlq,    0000500, 3, (RNQ,  oRNQ,  RNQ),  neon_rshl),
25801 NUF(vqrshlq,   0000510, 3, (RNQ,  oRNQ,  RNQ),  neon_rshl),
25802  /* If not immediate, fall back to neon_dyadic_i64_su.
25803     shl should accept I8 I16 I32 I64,
25804     qshl should accept S8 S16 S32 S64 U8 U16 U32 U64.  */
25805 nUF(vshlq,     _vshl,    3, (RNQ,  oRNQ,  RNDQ_I63b), neon_shl),
25806 nUF(vqshlq,    _vqshl,   3, (RNQ,  oRNQ,  RNDQ_I63b), neon_qshl),
25807  /* Logic ops, types optional & ignored.  */
25808 nUF(vandq,     _vand,    3, (RNQ,  oRNQ,  RNDQ_Ibig), neon_logic),
25809 nUF(vbicq,     _vbic,    3, (RNQ,  oRNQ,  RNDQ_Ibig), neon_logic),
25810 nUF(vorrq,     _vorr,    3, (RNQ,  oRNQ,  RNDQ_Ibig), neon_logic),
25811 nUF(vornq,     _vorn,    3, (RNQ,  oRNQ,  RNDQ_Ibig), neon_logic),
25812 nUF(veorq,     _veor,    3, (RNQ,  oRNQ,  RNQ),       neon_logic),
25813  /* Bitfield ops, untyped.  */
25814 NUF(vbsl,      1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
25815 NUF(vbslq,     1100110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
25816 NUF(vbit,      1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
25817 NUF(vbitq,     1200110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
25818 NUF(vbif,      1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
25819 NUF(vbifq,     1300110, 3, (RNQ,  RNQ,  RNQ),  neon_bitfield),
25820  /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32.  */
25821 nUF(vabdq,     _vabd,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
25822 nUF(vmaxq,     _vmax,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
25823 nUF(vminq,     _vmin,    3, (RNQ,  oRNQ,  RNQ),  neon_dyadic_if_su),
25824  /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25825     back to neon_dyadic_if_su.  */
25826 nUF(vcge,      _vcge,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
25827 nUF(vcgeq,     _vcge,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp),
25828 nUF(vcgt,      _vcgt,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
25829 nUF(vcgtq,     _vcgt,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp),
25830 nUF(vclt,      _vclt,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
25831 nUF(vcltq,     _vclt,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp_inv),
25832 nUF(vcle,      _vcle,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
25833 nUF(vcleq,     _vcle,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_cmp_inv),
25834  /* Comparison. Type I8 I16 I32 F32.  */
25835 nUF(vceq,      _vceq,    3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
25836 nUF(vceqq,     _vceq,    3, (RNQ,  oRNQ,  RNDQ_I0), neon_ceq),
25837  /* As above, D registers only.  */
25838 nUF(vpmax,     _vpmax,   3, (RND, oRND, RND), neon_dyadic_if_su_d),
25839 nUF(vpmin,     _vpmin,   3, (RND, oRND, RND), neon_dyadic_if_su_d),
25840  /* Int and float variants, signedness unimportant.  */
25841 nUF(vmlaq,     _vmla,    3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mac_maybe_scalar),
25842 nUF(vmlsq,     _vmls,    3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mac_maybe_scalar),
25843 nUF(vpadd,     _vpadd,   3, (RND,  oRND,  RND),       neon_dyadic_if_i_d),
25844  /* Add/sub take types I8 I16 I32 I64 F32.  */
25845 nUF(vaddq,     _vadd,    3, (RNQ,  oRNQ,  RNQ),  neon_addsub_if_i),
25846 nUF(vsubq,     _vsub,    3, (RNQ,  oRNQ,  RNQ),  neon_addsub_if_i),
25847  /* vtst takes sizes 8, 16, 32.  */
25848 NUF(vtst,      0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
25849 NUF(vtstq,     0000810, 3, (RNQ,  oRNQ,  RNQ),  neon_tst),
25850  /* VMUL takes I8 I16 I32 F32 P8.  */
25851 nUF(vmulq,     _vmul,     3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_mul),
25852  /* VQD{R}MULH takes S16 S32.  */
25853 nUF(vqdmulhq,  _vqdmulh,  3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qdmulh),
25854 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qdmulh),
25855 NUF(vacge,     0000e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
25856 NUF(vacgeq,    0000e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute),
25857 NUF(vacgt,     0200e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
25858 NUF(vacgtq,    0200e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute),
25859 NUF(vaclt,     0200e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
25860 NUF(vacltq,    0200e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute_inv),
25861 NUF(vacle,     0000e10,  3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
25862 NUF(vacleq,    0000e10,  3, (RNQ,  oRNQ,  RNQ),  neon_fcmp_absolute_inv),
25863 NUF(vrecps,    0000f10,  3, (RNDQ, oRNDQ, RNDQ), neon_step),
25864 NUF(vrecpsq,   0000f10,  3, (RNQ,  oRNQ,  RNQ),  neon_step),
25865 NUF(vrsqrts,   0200f10,  3, (RNDQ, oRNDQ, RNDQ), neon_step),
25866 NUF(vrsqrtsq,  0200f10,  3, (RNQ,  oRNQ,  RNQ),  neon_step),
25867 /* ARM v8.1 extension.  */
25868 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qrdmlah),
25869 nUF (vqrdmlsh,  _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
25870 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ,  oRNQ,  RNDQ_RNSC), neon_qrdmlah),
25871
25872  /* Two address, int/float. Types S8 S16 S32 F32.  */
25873 NUF(vabsq,     1b10300, 2, (RNQ,  RNQ),      neon_abs_neg),
25874 NUF(vnegq,     1b10380, 2, (RNQ,  RNQ),      neon_abs_neg),
25875
25876  /* Data processing with two registers and a shift amount.  */
25877  /* Right shifts, and variants with rounding.
25878     Types accepted S8 S16 S32 S64 U8 U16 U32 U64.  */
25879 NUF(vshrq,     0800010, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
25880 NUF(vrshrq,    0800210, 3, (RNQ,  oRNQ,  I64z), neon_rshift_round_imm),
25881 NUF(vsra,      0800110, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
25882 NUF(vsraq,     0800110, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
25883 NUF(vrsra,     0800310, 3, (RNDQ, oRNDQ, I64),  neon_rshift_round_imm),
25884 NUF(vrsraq,    0800310, 3, (RNQ,  oRNQ,  I64),  neon_rshift_round_imm),
25885  /* Shift and insert. Sizes accepted 8 16 32 64.  */
25886 NUF(vsliq,     1800510, 3, (RNQ,  oRNQ,  I63), neon_sli),
25887 NUF(vsriq,     1800410, 3, (RNQ,  oRNQ,  I64), neon_sri),
25888  /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64.  */
25889 NUF(vqshluq,   1800610, 3, (RNQ,  oRNQ,  I63), neon_qshlu_imm),
25890  /* Right shift immediate, saturating & narrowing, with rounding variants.
25891     Types accepted S16 S32 S64 U16 U32 U64.  */
25892 NUF(vqshrn,    0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
25893 NUF(vqrshrn,   0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
25894  /* As above, unsigned. Types accepted S16 S32 S64.  */
25895 NUF(vqshrun,   0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
25896 NUF(vqrshrun,  0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
25897  /* Right shift narrowing. Types accepted I16 I32 I64.  */
25898 NUF(vshrn,     0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
25899 NUF(vrshrn,    0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
25900  /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant.  */
25901 nUF(vshll,     _vshll,   3, (RNQ, RND, I32),  neon_shll),
25902  /* CVT with optional immediate for fixed-point variant.  */
25903 nUF(vcvtq,     _vcvt,    3, (RNQ, RNQ, oI32b), neon_cvt),
25904
25905 nUF(vmvnq,     _vmvn,    2, (RNQ,  RNDQ_Ibig), neon_mvn),
25906
25907  /* Data processing, three registers of different lengths.  */
25908  /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32.  */
25909 NUF(vabal,     0800500, 3, (RNQ, RND, RND),  neon_abal),
25910  /* If not scalar, fall back to neon_dyadic_long.
25911     Vector types as above, scalar types S16 S32 U16 U32.  */
25912 nUF(vmlal,     _vmlal,   3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
25913 nUF(vmlsl,     _vmlsl,   3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
25914  /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32.  */
25915 NUF(vaddw,     0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
25916 NUF(vsubw,     0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
25917  /* Dyadic, narrowing insns. Types I16 I32 I64.  */
25918 NUF(vaddhn,    0800400, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
25919 NUF(vraddhn,   1800400, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
25920 NUF(vsubhn,    0800600, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
25921 NUF(vrsubhn,   1800600, 3, (RND, RNQ, RNQ),  neon_dyadic_narrow),
25922  /* Saturating doubling multiplies. Types S16 S32.  */
25923 nUF(vqdmlal,   _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
25924 nUF(vqdmlsl,   _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
25925 nUF(vqdmull,   _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
25926  /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25927     S16 S32 U16 U32.  */
25928 nUF(vmull,     _vmull,   3, (RNQ, RND, RND_RNSC), neon_vmull),
25929
25930  /* Extract. Size 8.  */
25931 NUF(vext,      0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
25932 NUF(vextq,     0b00000, 4, (RNQ,  oRNQ,  RNQ,  I15), neon_ext),
25933
25934  /* Two registers, miscellaneous.  */
25935  /* Reverse. Sizes 8 16 32 (must be < size in opcode).  */
25936 NUF(vrev64q,   1b00000, 2, (RNQ,  RNQ),      neon_rev),
25937 NUF(vrev32q,   1b00080, 2, (RNQ,  RNQ),      neon_rev),
25938 NUF(vrev16q,   1b00100, 2, (RNQ,  RNQ),      neon_rev),
25939  /* Vector replicate. Sizes 8 16 32.  */
25940 nCE(vdupq,     _vdup,    2, (RNQ,  RR_RNSC),  neon_dup),
25941  /* VMOVL. Types S8 S16 S32 U8 U16 U32.  */
25942 NUF(vmovl,     0800a10, 2, (RNQ, RND),       neon_movl),
25943  /* VMOVN. Types I16 I32 I64.  */
25944 nUF(vmovn,     _vmovn,   2, (RND, RNQ),       neon_movn),
25945  /* VQMOVN. Types S16 S32 S64 U16 U32 U64.  */
25946 nUF(vqmovn,    _vqmovn,  2, (RND, RNQ),       neon_qmovn),
25947  /* VQMOVUN. Types S16 S32 S64.  */
25948 nUF(vqmovun,   _vqmovun, 2, (RND, RNQ),       neon_qmovun),
25949  /* VZIP / VUZP. Sizes 8 16 32.  */
25950 NUF(vzip,      1b20180, 2, (RNDQ, RNDQ),     neon_zip_uzp),
25951 NUF(vzipq,     1b20180, 2, (RNQ,  RNQ),      neon_zip_uzp),
25952 NUF(vuzp,      1b20100, 2, (RNDQ, RNDQ),     neon_zip_uzp),
25953 NUF(vuzpq,     1b20100, 2, (RNQ,  RNQ),      neon_zip_uzp),
25954  /* VQABS / VQNEG. Types S8 S16 S32.  */
25955 NUF(vqabsq,    1b00700, 2, (RNQ,  RNQ),      neon_sat_abs_neg),
25956 NUF(vqnegq,    1b00780, 2, (RNQ,  RNQ),      neon_sat_abs_neg),
25957  /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32.  */
25958 NUF(vpadal,    1b00600, 2, (RNDQ, RNDQ),     neon_pair_long),
25959 NUF(vpadalq,   1b00600, 2, (RNQ,  RNQ),      neon_pair_long),
25960 NUF(vpaddl,    1b00200, 2, (RNDQ, RNDQ),     neon_pair_long),
25961 NUF(vpaddlq,   1b00200, 2, (RNQ,  RNQ),      neon_pair_long),
25962  /* Reciprocal estimates.  Types U32 F16 F32.  */
25963 NUF(vrecpe,    1b30400, 2, (RNDQ, RNDQ),     neon_recip_est),
25964 NUF(vrecpeq,   1b30400, 2, (RNQ,  RNQ),      neon_recip_est),
25965 NUF(vrsqrte,   1b30480, 2, (RNDQ, RNDQ),     neon_recip_est),
25966 NUF(vrsqrteq,  1b30480, 2, (RNQ,  RNQ),      neon_recip_est),
25967  /* VCLS. Types S8 S16 S32.  */
25968 NUF(vclsq,     1b00400, 2, (RNQ,  RNQ),      neon_cls),
25969  /* VCLZ. Types I8 I16 I32.  */
25970 NUF(vclzq,     1b00480, 2, (RNQ,  RNQ),      neon_clz),
25971  /* VCNT. Size 8.  */
25972 NUF(vcnt,      1b00500, 2, (RNDQ, RNDQ),     neon_cnt),
25973 NUF(vcntq,     1b00500, 2, (RNQ,  RNQ),      neon_cnt),
25974  /* Two address, untyped.  */
25975 NUF(vswp,      1b20000, 2, (RNDQ, RNDQ),     neon_swp),
25976 NUF(vswpq,     1b20000, 2, (RNQ,  RNQ),      neon_swp),
25977  /* VTRN. Sizes 8 16 32.  */
25978 nUF(vtrn,      _vtrn,    2, (RNDQ, RNDQ),     neon_trn),
25979 nUF(vtrnq,     _vtrn,    2, (RNQ,  RNQ),      neon_trn),
25980
25981  /* Table lookup. Size 8.  */
25982 NUF(vtbl,      1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
25983 NUF(vtbx,      1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
25984
25985#undef  THUMB_VARIANT
25986#define THUMB_VARIANT  & fpu_vfp_v3_or_neon_ext
25987#undef  ARM_VARIANT
25988#define ARM_VARIANT    & fpu_vfp_v3_or_neon_ext
25989
25990  /* Neon element/structure load/store.  */
25991 nUF(vld1,      _vld1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
25992 nUF(vst1,      _vst1,    2, (NSTRLST, ADDR),  neon_ldx_stx),
25993 nUF(vld2,      _vld2,    2, (NSTRLST, ADDR),  neon_ldx_stx),
25994 nUF(vst2,      _vst2,    2, (NSTRLST, ADDR),  neon_ldx_stx),
25995 nUF(vld3,      _vld3,    2, (NSTRLST, ADDR),  neon_ldx_stx),
25996 nUF(vst3,      _vst3,    2, (NSTRLST, ADDR),  neon_ldx_stx),
25997 nUF(vld4,      _vld4,    2, (NSTRLST, ADDR),  neon_ldx_stx),
25998 nUF(vst4,      _vst4,    2, (NSTRLST, ADDR),  neon_ldx_stx),
25999
26000#undef  THUMB_VARIANT
26001#define THUMB_VARIANT & fpu_vfp_ext_v3xd
26002#undef  ARM_VARIANT
26003#define ARM_VARIANT   & fpu_vfp_ext_v3xd
26004 cCE("fconsts",   eb00a00, 2, (RVS, I255),      vfp_sp_const),
26005 cCE("fshtos",    eba0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
26006 cCE("fsltos",    eba0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
26007 cCE("fuhtos",    ebb0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
26008 cCE("fultos",    ebb0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
26009 cCE("ftoshs",    ebe0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
26010 cCE("ftosls",    ebe0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
26011 cCE("ftouhs",    ebf0a40, 2, (RVS, I16z),      vfp_sp_conv_16),
26012 cCE("ftouls",    ebf0ac0, 2, (RVS, I32),       vfp_sp_conv_32),
26013
26014#undef  THUMB_VARIANT
26015#define THUMB_VARIANT  & fpu_vfp_ext_v3
26016#undef  ARM_VARIANT
26017#define ARM_VARIANT    & fpu_vfp_ext_v3
26018
26019 cCE("fconstd",   eb00b00, 2, (RVD, I255),      vfp_dp_const),
26020 cCE("fshtod",    eba0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
26021 cCE("fsltod",    eba0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
26022 cCE("fuhtod",    ebb0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
26023 cCE("fultod",    ebb0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
26024 cCE("ftoshd",    ebe0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
26025 cCE("ftosld",    ebe0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
26026 cCE("ftouhd",    ebf0b40, 2, (RVD, I16z),      vfp_dp_conv_16),
26027 cCE("ftould",    ebf0bc0, 2, (RVD, I32),       vfp_dp_conv_32),
26028
26029#undef  ARM_VARIANT
26030#define ARM_VARIANT    & fpu_vfp_ext_fma
26031#undef  THUMB_VARIANT
26032#define THUMB_VARIANT  & fpu_vfp_ext_fma
26033 /* Mnemonics shared by Neon, VFP, MVE and BF16.  These are included in the
26034    VFP FMA variant; NEON and VFP FMA always includes the NEON
26035    FMA instructions.  */
26036 mnCEF(vfma,     _vfma,    3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
26037 TUF ("vfmat",    c300850,    fc300850,  3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), mve_vfma, mve_vfma),
26038 mnCEF(vfms,     _vfms,    3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ),  neon_fmac),
26039
26040 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
26041    the v form should always be used.  */
26042 cCE("ffmas",	ea00a00, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
26043 cCE("ffnmas",	ea00a40, 3, (RVS, RVS, RVS),  vfp_sp_dyadic),
26044 cCE("ffmad",	ea00b00, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
26045 cCE("ffnmad",	ea00b40, 3, (RVD, RVD, RVD),  vfp_dp_rd_rn_rm),
26046 nCE(vfnma,     _vfnma,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
26047 nCE(vfnms,     _vfnms,   3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
26048
26049#undef THUMB_VARIANT
26050#undef  ARM_VARIANT
26051#define ARM_VARIANT  & arm_cext_xscale /* Intel XScale extensions.  */
26052
26053 cCE("mia",	e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
26054 cCE("miaph",	e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
26055 cCE("miabb",	e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
26056 cCE("miabt",	e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
26057 cCE("miatb",	e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
26058 cCE("miatt",	e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
26059 cCE("mar",	c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
26060 cCE("mra",	c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
26061
26062#undef  ARM_VARIANT
26063#define ARM_VARIANT  & arm_cext_iwmmxt /* Intel Wireless MMX technology.  */
26064
26065 cCE("tandcb",	e13f130, 1, (RR),		    iwmmxt_tandorc),
26066 cCE("tandch",	e53f130, 1, (RR),		    iwmmxt_tandorc),
26067 cCE("tandcw",	e93f130, 1, (RR),		    iwmmxt_tandorc),
26068 cCE("tbcstb",	e400010, 2, (RIWR, RR),		    rn_rd),
26069 cCE("tbcsth",	e400050, 2, (RIWR, RR),		    rn_rd),
26070 cCE("tbcstw",	e400090, 2, (RIWR, RR),		    rn_rd),
26071 cCE("textrcb",	e130170, 2, (RR, I7),		    iwmmxt_textrc),
26072 cCE("textrch",	e530170, 2, (RR, I7),		    iwmmxt_textrc),
26073 cCE("textrcw",	e930170, 2, (RR, I7),		    iwmmxt_textrc),
26074 cCE("textrmub",e100070, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
26075 cCE("textrmuh",e500070, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
26076 cCE("textrmuw",e900070, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
26077 cCE("textrmsb",e100078, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
26078 cCE("textrmsh",e500078, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
26079 cCE("textrmsw",e900078, 3, (RR, RIWR, I7),	    iwmmxt_textrm),
26080 cCE("tinsrb",	e600010, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
26081 cCE("tinsrh",	e600050, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
26082 cCE("tinsrw",	e600090, 3, (RIWR, RR, I7),	    iwmmxt_tinsr),
26083 cCE("tmcr",	e000110, 2, (RIWC_RIWG, RR),	    rn_rd),
26084 cCE("tmcrr",	c400000, 3, (RIWR, RR, RR),	    rm_rd_rn),
26085 cCE("tmia",	e200010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
26086 cCE("tmiaph",	e280010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
26087 cCE("tmiabb",	e2c0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
26088 cCE("tmiabt",	e2d0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
26089 cCE("tmiatb",	e2e0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
26090 cCE("tmiatt",	e2f0010, 3, (RIWR, RR, RR),	    iwmmxt_tmia),
26091 cCE("tmovmskb",e100030, 2, (RR, RIWR),		    rd_rn),
26092 cCE("tmovmskh",e500030, 2, (RR, RIWR),		    rd_rn),
26093 cCE("tmovmskw",e900030, 2, (RR, RIWR),		    rd_rn),
26094 cCE("tmrc",	e100110, 2, (RR, RIWC_RIWG),	    rd_rn),
26095 cCE("tmrrc",	c500000, 3, (RR, RR, RIWR),	    rd_rn_rm),
26096 cCE("torcb",	e13f150, 1, (RR),		    iwmmxt_tandorc),
26097 cCE("torch",	e53f150, 1, (RR),		    iwmmxt_tandorc),
26098 cCE("torcw",	e93f150, 1, (RR),		    iwmmxt_tandorc),
26099 cCE("waccb",	e0001c0, 2, (RIWR, RIWR),	    rd_rn),
26100 cCE("wacch",	e4001c0, 2, (RIWR, RIWR),	    rd_rn),
26101 cCE("waccw",	e8001c0, 2, (RIWR, RIWR),	    rd_rn),
26102 cCE("waddbss",	e300180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26103 cCE("waddb",	e000180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26104 cCE("waddbus",	e100180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26105 cCE("waddhss",	e700180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26106 cCE("waddh",	e400180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26107 cCE("waddhus",	e500180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26108 cCE("waddwss",	eb00180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26109 cCE("waddw",	e800180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26110 cCE("waddwus",	e900180, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26111 cCE("waligni",	e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
26112 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26113 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26114 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26115 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26116 cCE("wand",	e200000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26117 cCE("wandn",	e300000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26118 cCE("wavg2b",	e800000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26119 cCE("wavg2br",	e900000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26120 cCE("wavg2h",	ec00000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26121 cCE("wavg2hr",	ed00000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26122 cCE("wcmpeqb",	e000060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26123 cCE("wcmpeqh",	e400060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26124 cCE("wcmpeqw",	e800060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26125 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26126 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26127 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26128 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26129 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26130 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26131 cCE("wldrb",	c100000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
26132 cCE("wldrh",	c500000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
26133 cCE("wldrw",	c100100, 2, (RIWR_RIWC, ADDR),	    iwmmxt_wldstw),
26134 cCE("wldrd",	c500100, 2, (RIWR, ADDR),	    iwmmxt_wldstd),
26135 cCE("wmacs",	e600100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26136 cCE("wmacsz",	e700100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26137 cCE("wmacu",	e400100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26138 cCE("wmacuz",	e500100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26139 cCE("wmadds",	ea00100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26140 cCE("wmaddu",	e800100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26141 cCE("wmaxsb",	e200160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26142 cCE("wmaxsh",	e600160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26143 cCE("wmaxsw",	ea00160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26144 cCE("wmaxub",	e000160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26145 cCE("wmaxuh",	e400160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26146 cCE("wmaxuw",	e800160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26147 cCE("wminsb",	e300160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26148 cCE("wminsh",	e700160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26149 cCE("wminsw",	eb00160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26150 cCE("wminub",	e100160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26151 cCE("wminuh",	e500160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26152 cCE("wminuw",	e900160, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26153 cCE("wmov",	e000000, 2, (RIWR, RIWR),	    iwmmxt_wmov),
26154 cCE("wmulsm",	e300100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26155 cCE("wmulsl",	e200100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26156 cCE("wmulum",	e100100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26157 cCE("wmulul",	e000100, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26158 cCE("wor",	e000000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26159 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26160 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26161 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26162 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26163 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26164 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26165 cCE("wrorh",	e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26166 cCE("wrorhg",	e700148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26167 cCE("wrorw",	eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26168 cCE("wrorwg",	eb00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26169 cCE("wrord",	ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26170 cCE("wrordg",	ef00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26171 cCE("wsadb",	e000120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26172 cCE("wsadbz",	e100120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26173 cCE("wsadh",	e400120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26174 cCE("wsadhz",	e500120, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26175 cCE("wshufh",	e0001e0, 3, (RIWR, RIWR, I255),	    iwmmxt_wshufh),
26176 cCE("wsllh",	e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26177 cCE("wsllhg",	e500148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26178 cCE("wsllw",	e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26179 cCE("wsllwg",	e900148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26180 cCE("wslld",	ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26181 cCE("wslldg",	ed00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26182 cCE("wsrah",	e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26183 cCE("wsrahg",	e400148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26184 cCE("wsraw",	e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26185 cCE("wsrawg",	e800148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26186 cCE("wsrad",	ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26187 cCE("wsradg",	ec00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26188 cCE("wsrlh",	e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26189 cCE("wsrlhg",	e600148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26190 cCE("wsrlw",	ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26191 cCE("wsrlwg",	ea00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26192 cCE("wsrld",	ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
26193 cCE("wsrldg",	ee00148, 3, (RIWR, RIWR, RIWG),	    rd_rn_rm),
26194 cCE("wstrb",	c000000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
26195 cCE("wstrh",	c400000, 2, (RIWR, ADDR),	    iwmmxt_wldstbh),
26196 cCE("wstrw",	c000100, 2, (RIWR_RIWC, ADDR),	    iwmmxt_wldstw),
26197 cCE("wstrd",	c400100, 2, (RIWR, ADDR),	    iwmmxt_wldstd),
26198 cCE("wsubbss",	e3001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26199 cCE("wsubb",	e0001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26200 cCE("wsubbus",	e1001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26201 cCE("wsubhss",	e7001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26202 cCE("wsubh",	e4001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26203 cCE("wsubhus",	e5001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26204 cCE("wsubwss",	eb001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26205 cCE("wsubw",	e8001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26206 cCE("wsubwus",	e9001a0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26207 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR),	    rd_rn),
26208 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR),	    rd_rn),
26209 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR),	    rd_rn),
26210 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR),	    rd_rn),
26211 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR),	    rd_rn),
26212 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR),	    rd_rn),
26213 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26214 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26215 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26216 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR),	    rd_rn),
26217 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR),	    rd_rn),
26218 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR),	    rd_rn),
26219 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR),	    rd_rn),
26220 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR),	    rd_rn),
26221 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR),	    rd_rn),
26222 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26223 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26224 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26225 cCE("wxor",	e100000, 3, (RIWR, RIWR, RIWR),	    rd_rn_rm),
26226 cCE("wzero",	e300000, 1, (RIWR),		    iwmmxt_wzero),
26227
26228#undef  ARM_VARIANT
26229#define ARM_VARIANT  & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2.  */
26230
26231 cCE("torvscb",   e12f190, 1, (RR),		    iwmmxt_tandorc),
26232 cCE("torvsch",   e52f190, 1, (RR),		    iwmmxt_tandorc),
26233 cCE("torvscw",   e92f190, 1, (RR),		    iwmmxt_tandorc),
26234 cCE("wabsb",     e2001c0, 2, (RIWR, RIWR),           rd_rn),
26235 cCE("wabsh",     e6001c0, 2, (RIWR, RIWR),           rd_rn),
26236 cCE("wabsw",     ea001c0, 2, (RIWR, RIWR),           rd_rn),
26237 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26238 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26239 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26240 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26241 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26242 cCE("waddhc",    e600180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26243 cCE("waddwc",    ea00180, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26244 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26245 cCE("wavg4",	e400000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26246 cCE("wavg4r",    e500000, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26247 cCE("wmaddsn",   ee00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26248 cCE("wmaddsx",   eb00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26249 cCE("wmaddun",   ec00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26250 cCE("wmaddux",   e900100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26251 cCE("wmerge",    e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
26252 cCE("wmiabb",    e0000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26253 cCE("wmiabt",    e1000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26254 cCE("wmiatb",    e2000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26255 cCE("wmiatt",    e3000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26256 cCE("wmiabbn",   e4000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26257 cCE("wmiabtn",   e5000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26258 cCE("wmiatbn",   e6000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26259 cCE("wmiattn",   e7000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26260 cCE("wmiawbb",   e800120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26261 cCE("wmiawbt",   e900120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26262 cCE("wmiawtb",   ea00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26263 cCE("wmiawtt",   eb00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26264 cCE("wmiawbbn",  ec00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26265 cCE("wmiawbtn",  ed00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26266 cCE("wmiawtbn",  ee00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26267 cCE("wmiawttn",  ef00120, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26268 cCE("wmulsmr",   ef00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26269 cCE("wmulumr",   ed00100, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26270 cCE("wmulwumr",  ec000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26271 cCE("wmulwsmr",  ee000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26272 cCE("wmulwum",   ed000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26273 cCE("wmulwsm",   ef000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26274 cCE("wmulwl",    eb000c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26275 cCE("wqmiabb",   e8000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26276 cCE("wqmiabt",   e9000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26277 cCE("wqmiatb",   ea000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26278 cCE("wqmiatt",   eb000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26279 cCE("wqmiabbn",  ec000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26280 cCE("wqmiabtn",  ed000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26281 cCE("wqmiatbn",  ee000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26282 cCE("wqmiattn",  ef000a0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26283 cCE("wqmulm",    e100080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26284 cCE("wqmulmr",   e300080, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26285 cCE("wqmulwm",   ec000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26286 cCE("wqmulwmr",  ee000e0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26287 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR),     rd_rn_rm),
26288
26289#undef  ARM_VARIANT
26290#define ARM_VARIANT  & arm_cext_maverick /* Cirrus Maverick instructions.  */
26291
26292 cCE("cfldrs",	c100400, 2, (RMF, ADDRGLDC),	      rd_cpaddr),
26293 cCE("cfldrd",	c500400, 2, (RMD, ADDRGLDC),	      rd_cpaddr),
26294 cCE("cfldr32",	c100500, 2, (RMFX, ADDRGLDC),	      rd_cpaddr),
26295 cCE("cfldr64",	c500500, 2, (RMDX, ADDRGLDC),	      rd_cpaddr),
26296 cCE("cfstrs",	c000400, 2, (RMF, ADDRGLDC),	      rd_cpaddr),
26297 cCE("cfstrd",	c400400, 2, (RMD, ADDRGLDC),	      rd_cpaddr),
26298 cCE("cfstr32",	c000500, 2, (RMFX, ADDRGLDC),	      rd_cpaddr),
26299 cCE("cfstr64",	c400500, 2, (RMDX, ADDRGLDC),	      rd_cpaddr),
26300 cCE("cfmvsr",	e000450, 2, (RMF, RR),		      rn_rd),
26301 cCE("cfmvrs",	e100450, 2, (RR, RMF),		      rd_rn),
26302 cCE("cfmvdlr",	e000410, 2, (RMD, RR),		      rn_rd),
26303 cCE("cfmvrdl",	e100410, 2, (RR, RMD),		      rd_rn),
26304 cCE("cfmvdhr",	e000430, 2, (RMD, RR),		      rn_rd),
26305 cCE("cfmvrdh",	e100430, 2, (RR, RMD),		      rd_rn),
26306 cCE("cfmv64lr",e000510, 2, (RMDX, RR),		      rn_rd),
26307 cCE("cfmvr64l",e100510, 2, (RR, RMDX),		      rd_rn),
26308 cCE("cfmv64hr",e000530, 2, (RMDX, RR),		      rn_rd),
26309 cCE("cfmvr64h",e100530, 2, (RR, RMDX),		      rd_rn),
26310 cCE("cfmval32",e200440, 2, (RMAX, RMFX),	      rd_rn),
26311 cCE("cfmv32al",e100440, 2, (RMFX, RMAX),	      rd_rn),
26312 cCE("cfmvam32",e200460, 2, (RMAX, RMFX),	      rd_rn),
26313 cCE("cfmv32am",e100460, 2, (RMFX, RMAX),	      rd_rn),
26314 cCE("cfmvah32",e200480, 2, (RMAX, RMFX),	      rd_rn),
26315 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX),	      rd_rn),
26316 cCE("cfmva32",	e2004a0, 2, (RMAX, RMFX),	      rd_rn),
26317 cCE("cfmv32a",	e1004a0, 2, (RMFX, RMAX),	      rd_rn),
26318 cCE("cfmva64",	e2004c0, 2, (RMAX, RMDX),	      rd_rn),
26319 cCE("cfmv64a",	e1004c0, 2, (RMDX, RMAX),	      rd_rn),
26320 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX),	      mav_dspsc),
26321 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS),	      rd),
26322 cCE("cfcpys",	e000400, 2, (RMF, RMF),		      rd_rn),
26323 cCE("cfcpyd",	e000420, 2, (RMD, RMD),		      rd_rn),
26324 cCE("cfcvtsd",	e000460, 2, (RMD, RMF),		      rd_rn),
26325 cCE("cfcvtds",	e000440, 2, (RMF, RMD),		      rd_rn),
26326 cCE("cfcvt32s",e000480, 2, (RMF, RMFX),	      rd_rn),
26327 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX),	      rd_rn),
26328 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX),	      rd_rn),
26329 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX),	      rd_rn),
26330 cCE("cfcvts32",e100580, 2, (RMFX, RMF),	      rd_rn),
26331 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD),	      rd_rn),
26332 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF),	      rd_rn),
26333 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD),	      rd_rn),
26334 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR),	      mav_triple),
26335 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR),	      mav_triple),
26336 cCE("cfsh32",	e000500, 3, (RMFX, RMFX, I63s),	      mav_shift),
26337 cCE("cfsh64",	e200500, 3, (RMDX, RMDX, I63s),	      mav_shift),
26338 cCE("cfcmps",	e100490, 3, (RR, RMF, RMF),	      rd_rn_rm),
26339 cCE("cfcmpd",	e1004b0, 3, (RR, RMD, RMD),	      rd_rn_rm),
26340 cCE("cfcmp32",	e100590, 3, (RR, RMFX, RMFX),	      rd_rn_rm),
26341 cCE("cfcmp64",	e1005b0, 3, (RR, RMDX, RMDX),	      rd_rn_rm),
26342 cCE("cfabss",	e300400, 2, (RMF, RMF),		      rd_rn),
26343 cCE("cfabsd",	e300420, 2, (RMD, RMD),		      rd_rn),
26344 cCE("cfnegs",	e300440, 2, (RMF, RMF),		      rd_rn),
26345 cCE("cfnegd",	e300460, 2, (RMD, RMD),		      rd_rn),
26346 cCE("cfadds",	e300480, 3, (RMF, RMF, RMF),	      rd_rn_rm),
26347 cCE("cfaddd",	e3004a0, 3, (RMD, RMD, RMD),	      rd_rn_rm),
26348 cCE("cfsubs",	e3004c0, 3, (RMF, RMF, RMF),	      rd_rn_rm),
26349 cCE("cfsubd",	e3004e0, 3, (RMD, RMD, RMD),	      rd_rn_rm),
26350 cCE("cfmuls",	e100400, 3, (RMF, RMF, RMF),	      rd_rn_rm),
26351 cCE("cfmuld",	e100420, 3, (RMD, RMD, RMD),	      rd_rn_rm),
26352 cCE("cfabs32",	e300500, 2, (RMFX, RMFX),	      rd_rn),
26353 cCE("cfabs64",	e300520, 2, (RMDX, RMDX),	      rd_rn),
26354 cCE("cfneg32",	e300540, 2, (RMFX, RMFX),	      rd_rn),
26355 cCE("cfneg64",	e300560, 2, (RMDX, RMDX),	      rd_rn),
26356 cCE("cfadd32",	e300580, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
26357 cCE("cfadd64",	e3005a0, 3, (RMDX, RMDX, RMDX),	      rd_rn_rm),
26358 cCE("cfsub32",	e3005c0, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
26359 cCE("cfsub64",	e3005e0, 3, (RMDX, RMDX, RMDX),	      rd_rn_rm),
26360 cCE("cfmul32",	e100500, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
26361 cCE("cfmul64",	e100520, 3, (RMDX, RMDX, RMDX),	      rd_rn_rm),
26362 cCE("cfmac32",	e100540, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
26363 cCE("cfmsc32",	e100560, 3, (RMFX, RMFX, RMFX),	      rd_rn_rm),
26364 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
26365 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
26366 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
26367 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
26368
26369 /* ARMv8.5-A instructions.  */
26370#undef  ARM_VARIANT
26371#define ARM_VARIANT   & arm_ext_sb
26372#undef  THUMB_VARIANT
26373#define THUMB_VARIANT & arm_ext_sb
26374 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
26375
26376#undef  ARM_VARIANT
26377#define ARM_VARIANT   & arm_ext_predres
26378#undef  THUMB_VARIANT
26379#define THUMB_VARIANT & arm_ext_predres
26380 CE("cfprctx", e070f93, 1, (RRnpc), rd),
26381 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
26382 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
26383
26384 /* ARMv8-M instructions.  */
26385#undef  ARM_VARIANT
26386#define ARM_VARIANT NULL
26387#undef  THUMB_VARIANT
26388#define THUMB_VARIANT & arm_ext_v8m
26389 ToU("sg",    e97fe97f,	0, (),		   noargs),
26390 ToC("blxns", 4784,	1, (RRnpc),	   t_blx),
26391 ToC("bxns",  4704,	1, (RRnpc),	   t_bx),
26392 ToC("tt",    e840f000,	2, (RRnpc, RRnpc), tt),
26393 ToC("ttt",   e840f040,	2, (RRnpc, RRnpc), tt),
26394 ToC("tta",   e840f080,	2, (RRnpc, RRnpc), tt),
26395 ToC("ttat",  e840f0c0,	2, (RRnpc, RRnpc), tt),
26396
26397 /* FP for ARMv8-M Mainline.  Enabled for ARMv8-M Mainline because the
26398    instructions behave as nop if no VFP is present.  */
26399#undef  THUMB_VARIANT
26400#define THUMB_VARIANT & arm_ext_v8m_main
26401 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
26402 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
26403
26404 /* Armv8.1-M Mainline instructions.  */
26405#undef  THUMB_VARIANT
26406#define THUMB_VARIANT & arm_ext_v8_1m_main
26407 toU("aut",   _aut, 3, (R12, LR, SP), t_pacbti),
26408 toU("autg",  _autg, 3, (RR, RR, RR), t_pacbti_nonop),
26409 ToU("bti",   f3af800f, 0, (), noargs),
26410 toU("bxaut", _bxaut, 3, (RR, RR, RR), t_pacbti_nonop),
26411 toU("pac",   _pac,   3, (R12, LR, SP), t_pacbti),
26412 toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti),
26413 toU("pacg",   _pacg,   3, (RR, RR, RR), t_pacbti_pacg),
26414 toU("cinc",  _cinc,  3, (RRnpcsp, RR_ZR, COND),	t_cond),
26415 toU("cinv",  _cinv,  3, (RRnpcsp, RR_ZR, COND),	t_cond),
26416 toU("cneg",  _cneg,  3, (RRnpcsp, RR_ZR, COND),	t_cond),
26417 toU("csel",  _csel,  4, (RRnpcsp, RR_ZR, RR_ZR, COND),	t_cond),
26418 toU("csetm", _csetm, 2, (RRnpcsp, COND),		t_cond),
26419 toU("cset",  _cset,  2, (RRnpcsp, COND),		t_cond),
26420 toU("csinc", _csinc, 4, (RRnpcsp, RR_ZR, RR_ZR, COND),	t_cond),
26421 toU("csinv", _csinv, 4, (RRnpcsp, RR_ZR, RR_ZR, COND),	t_cond),
26422 toU("csneg", _csneg, 4, (RRnpcsp, RR_ZR, RR_ZR, COND),	t_cond),
26423
26424 toC("bf",     _bf,	2, (EXPs, EXPs),	     t_branch_future),
26425 toU("bfcsel", _bfcsel,	4, (EXPs, EXPs, EXPs, COND), t_branch_future),
26426 toC("bfx",    _bfx,	2, (EXPs, RRnpcsp),	     t_branch_future),
26427 toC("bfl",    _bfl,	2, (EXPs, EXPs),	     t_branch_future),
26428 toC("bflx",   _bflx,	2, (EXPs, RRnpcsp),	     t_branch_future),
26429
26430 toU("dls", _dls, 2, (LR, RRnpcsp),	 t_loloop),
26431 toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
26432 toU("le",  _le,  2, (oLR, EXP),	 t_loloop),
26433
26434 ToC("clrm",	e89f0000, 1, (CLRMLST),  t_clrm),
26435 ToC("vscclrm",	ec9f0a00, 1, (VRSDVLST), t_vscclrm),
26436
26437#undef  THUMB_VARIANT
26438#define THUMB_VARIANT & mve_ext
26439 ToC("lsll",	ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
26440 ToC("lsrl",	ea50011f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
26441 ToC("asrl",	ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
26442 ToC("uqrshll",	ea51010d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
26443 ToC("sqrshrl",	ea51012d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
26444 ToC("uqshll",	ea51010f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
26445 ToC("urshrl",	ea51011f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
26446 ToC("srshrl",	ea51012f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
26447 ToC("sqshll",	ea51013f, 3, (RRe, RRo, I32),	      mve_scalar_shift),
26448 ToC("uqrshl",	ea500f0d, 2, (RRnpcsp, RRnpcsp),      mve_scalar_shift),
26449 ToC("sqrshr",	ea500f2d, 2, (RRnpcsp, RRnpcsp),      mve_scalar_shift),
26450 ToC("uqshl",	ea500f0f, 2, (RRnpcsp, I32),	      mve_scalar_shift),
26451 ToC("urshr",	ea500f1f, 2, (RRnpcsp, I32),	      mve_scalar_shift),
26452 ToC("srshr",	ea500f2f, 2, (RRnpcsp, I32),	      mve_scalar_shift),
26453 ToC("sqshl",	ea500f3f, 2, (RRnpcsp, I32),	      mve_scalar_shift),
26454
26455 ToC("vpt",	ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26456 ToC("vptt",	ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26457 ToC("vpte",	ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26458 ToC("vpttt",	ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26459 ToC("vptte",	ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26460 ToC("vptet",	ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26461 ToC("vptee",	ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26462 ToC("vptttt",	ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26463 ToC("vpttte",	ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26464 ToC("vpttet",	ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26465 ToC("vpttee",	ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26466 ToC("vptett",	ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26467 ToC("vptete",	ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26468 ToC("vpteet",	ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26469 ToC("vpteee",	ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
26470
26471 ToC("vpst",	fe710f4d, 0, (), mve_vpt),
26472 ToC("vpstt",	fe318f4d, 0, (), mve_vpt),
26473 ToC("vpste",	fe718f4d, 0, (), mve_vpt),
26474 ToC("vpsttt",	fe314f4d, 0, (), mve_vpt),
26475 ToC("vpstte",	fe31cf4d, 0, (), mve_vpt),
26476 ToC("vpstet",	fe71cf4d, 0, (), mve_vpt),
26477 ToC("vpstee",	fe714f4d, 0, (), mve_vpt),
26478 ToC("vpstttt",	fe312f4d, 0, (), mve_vpt),
26479 ToC("vpsttte", fe316f4d, 0, (), mve_vpt),
26480 ToC("vpsttet",	fe31ef4d, 0, (), mve_vpt),
26481 ToC("vpsttee",	fe31af4d, 0, (), mve_vpt),
26482 ToC("vpstett",	fe71af4d, 0, (), mve_vpt),
26483 ToC("vpstete",	fe71ef4d, 0, (), mve_vpt),
26484 ToC("vpsteet",	fe716f4d, 0, (), mve_vpt),
26485 ToC("vpsteee",	fe712f4d, 0, (), mve_vpt),
26486
26487 /* MVE and MVE FP only.  */
26488 mToC("vhcadd",	ee000f00,   4, (RMQ, RMQ, RMQ, EXPi),		  mve_vhcadd),
26489 mCEF(vctp,	_vctp,      1, (RRnpc),				  mve_vctp),
26490 mCEF(vadc,	_vadc,      3, (RMQ, RMQ, RMQ),			  mve_vadc),
26491 mCEF(vadci,	_vadci,     3, (RMQ, RMQ, RMQ),			  mve_vadc),
26492 mToC("vsbc",	fe300f00,   3, (RMQ, RMQ, RMQ),			  mve_vsbc),
26493 mToC("vsbci",	fe301f00,   3, (RMQ, RMQ, RMQ),			  mve_vsbc),
26494 mCEF(vmullb,	_vmullb,    3, (RMQ, RMQ, RMQ),			  mve_vmull),
26495 mCEF(vabav,	_vabav,	    3, (RRnpcsp, RMQ, RMQ),		  mve_vabav),
26496 mCEF(vmladav,	  _vmladav,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26497 mCEF(vmladava,	  _vmladava,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26498 mCEF(vmladavx,	  _vmladavx,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26499 mCEF(vmladavax,  _vmladavax,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26500 mCEF(vmlav,	  _vmladav,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26501 mCEF(vmlava,	  _vmladava,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26502 mCEF(vmlsdav,	  _vmlsdav,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26503 mCEF(vmlsdava,	  _vmlsdava,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26504 mCEF(vmlsdavx,	  _vmlsdavx,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26505 mCEF(vmlsdavax,  _vmlsdavax,	3, (RRe, RMQ, RMQ),		mve_vmladav),
26506
26507 mCEF(vst20,	_vst20,	    2, (MSTRLST2, ADDRMVE),		mve_vst_vld),
26508 mCEF(vst21,	_vst21,	    2, (MSTRLST2, ADDRMVE),		mve_vst_vld),
26509 mCEF(vst40,	_vst40,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
26510 mCEF(vst41,	_vst41,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
26511 mCEF(vst42,	_vst42,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
26512 mCEF(vst43,	_vst43,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
26513 mCEF(vld20,	_vld20,	    2, (MSTRLST2, ADDRMVE),		mve_vst_vld),
26514 mCEF(vld21,	_vld21,	    2, (MSTRLST2, ADDRMVE),		mve_vst_vld),
26515 mCEF(vld40,	_vld40,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
26516 mCEF(vld41,	_vld41,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
26517 mCEF(vld42,	_vld42,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
26518 mCEF(vld43,	_vld43,	    2, (MSTRLST4, ADDRMVE),		mve_vst_vld),
26519 mCEF(vstrb,	_vstrb,	    2, (RMQ, ADDRMVE),			mve_vstr_vldr),
26520 mCEF(vstrh,	_vstrh,	    2, (RMQ, ADDRMVE),			mve_vstr_vldr),
26521 mCEF(vstrw,	_vstrw,	    2, (RMQ, ADDRMVE),			mve_vstr_vldr),
26522 mCEF(vstrd,	_vstrd,	    2, (RMQ, ADDRMVE),			mve_vstr_vldr),
26523 mCEF(vldrb,	_vldrb,	    2, (RMQ, ADDRMVE),			mve_vstr_vldr),
26524 mCEF(vldrh,	_vldrh,	    2, (RMQ, ADDRMVE),			mve_vstr_vldr),
26525 mCEF(vldrw,	_vldrw,	    2, (RMQ, ADDRMVE),			mve_vstr_vldr),
26526 mCEF(vldrd,	_vldrd,	    2, (RMQ, ADDRMVE),			mve_vstr_vldr),
26527
26528 mCEF(vmovnt,	_vmovnt,    2, (RMQ, RMQ),			  mve_movn),
26529 mCEF(vmovnb,	_vmovnb,    2, (RMQ, RMQ),			  mve_movn),
26530 mCEF(vbrsr,	_vbrsr,     3, (RMQ, RMQ, RR),			  mve_vbrsr),
26531 mCEF(vaddlv,	_vaddlv,    3, (RRe, RRo, RMQ),			  mve_vaddlv),
26532 mCEF(vaddlva,	_vaddlva,   3, (RRe, RRo, RMQ),			  mve_vaddlv),
26533 mCEF(vaddv,	_vaddv,	    2, (RRe, RMQ),			  mve_vaddv),
26534 mCEF(vaddva,	_vaddva,    2, (RRe, RMQ),			  mve_vaddv),
26535 mCEF(vddup,	_vddup,	    3, (RMQ, RRe, EXPi),		  mve_viddup),
26536 mCEF(vdwdup,	_vdwdup,    4, (RMQ, RRe, RR, EXPi),		  mve_viddup),
26537 mCEF(vidup,	_vidup,	    3, (RMQ, RRe, EXPi),		  mve_viddup),
26538 mCEF(viwdup,	_viwdup,    4, (RMQ, RRe, RR, EXPi),		  mve_viddup),
26539 mToC("vmaxa",	ee330e81,   2, (RMQ, RMQ),			  mve_vmaxa_vmina),
26540 mToC("vmina",	ee331e81,   2, (RMQ, RMQ),			  mve_vmaxa_vmina),
26541 mCEF(vmaxv,	_vmaxv,	  2, (RR, RMQ),				  mve_vmaxv),
26542 mCEF(vmaxav,	_vmaxav,  2, (RR, RMQ),				  mve_vmaxv),
26543 mCEF(vminv,	_vminv,	  2, (RR, RMQ),				  mve_vmaxv),
26544 mCEF(vminav,	_vminav,  2, (RR, RMQ),				  mve_vmaxv),
26545
26546 mCEF(vmlaldav,	  _vmlaldav,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26547 mCEF(vmlaldava,  _vmlaldava,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26548 mCEF(vmlaldavx,  _vmlaldavx,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26549 mCEF(vmlaldavax, _vmlaldavax,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26550 mCEF(vmlalv,	  _vmlaldav,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26551 mCEF(vmlalva,	  _vmlaldava,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26552 mCEF(vmlsldav,	  _vmlsldav,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26553 mCEF(vmlsldava,  _vmlsldava,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26554 mCEF(vmlsldavx,  _vmlsldavx,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26555 mCEF(vmlsldavax, _vmlsldavax,	4, (RRe, RRo, RMQ, RMQ),	mve_vmlaldav),
26556 mToC("vrmlaldavh", ee800f00,	   4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26557 mToC("vrmlaldavha",ee800f20,	   4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26558 mCEF(vrmlaldavhx,  _vrmlaldavhx,  4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26559 mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26560 mToC("vrmlalvh",   ee800f00,	   4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26561 mToC("vrmlalvha",  ee800f20,	   4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26562 mCEF(vrmlsldavh,   _vrmlsldavh,   4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26563 mCEF(vrmlsldavha,  _vrmlsldavha,  4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26564 mCEF(vrmlsldavhx,  _vrmlsldavhx,  4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26565 mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ),  mve_vrmlaldavh),
26566
26567 mToC("vmlas",	  ee011e40,	3, (RMQ, RMQ, RR),		mve_vmlas),
26568 mToC("vmulh",	  ee010e01,	3, (RMQ, RMQ, RMQ),		mve_vmulh),
26569 mToC("vrmulh",	  ee011e01,	3, (RMQ, RMQ, RMQ),		mve_vmulh),
26570 mToC("vpnot",	  fe310f4d,	0, (),				mve_vpnot),
26571 mToC("vpsel",	  fe310f01,	3, (RMQ, RMQ, RMQ),		mve_vpsel),
26572
26573 mToC("vqdmladh",  ee000e00,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
26574 mToC("vqdmladhx", ee001e00,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
26575 mToC("vqrdmladh", ee000e01,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
26576 mToC("vqrdmladhx",ee001e01,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
26577 mToC("vqdmlsdh",  fe000e00,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
26578 mToC("vqdmlsdhx", fe001e00,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
26579 mToC("vqrdmlsdh", fe000e01,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
26580 mToC("vqrdmlsdhx",fe001e01,	3, (RMQ, RMQ, RMQ),		mve_vqdmladh),
26581 mToC("vqdmlah",   ee000e60,	3, (RMQ, RMQ, RR),		mve_vqdmlah),
26582 mToC("vqdmlash",  ee001e60,	3, (RMQ, RMQ, RR),		mve_vqdmlah),
26583 mToC("vqrdmlash", ee001e40,	3, (RMQ, RMQ, RR),		mve_vqdmlah),
26584 mToC("vqdmullt",  ee301f00,	3, (RMQ, RMQ, RMQRR),		mve_vqdmull),
26585 mToC("vqdmullb",  ee300f00,	3, (RMQ, RMQ, RMQRR),		mve_vqdmull),
26586 mCEF(vqmovnt,	  _vqmovnt,	2, (RMQ, RMQ),			mve_vqmovn),
26587 mCEF(vqmovnb,	  _vqmovnb,	2, (RMQ, RMQ),			mve_vqmovn),
26588 mCEF(vqmovunt,	  _vqmovunt,	2, (RMQ, RMQ),			mve_vqmovn),
26589 mCEF(vqmovunb,	  _vqmovunb,	2, (RMQ, RMQ),			mve_vqmovn),
26590
26591 mCEF(vshrnt,	  _vshrnt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26592 mCEF(vshrnb,	  _vshrnb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26593 mCEF(vrshrnt,	  _vrshrnt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26594 mCEF(vrshrnb,	  _vrshrnb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26595 mCEF(vqshrnt,	  _vqrshrnt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26596 mCEF(vqshrnb,	  _vqrshrnb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26597 mCEF(vqshrunt,	  _vqrshrunt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26598 mCEF(vqshrunb,	  _vqrshrunb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26599 mCEF(vqrshrnt,	  _vqrshrnt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26600 mCEF(vqrshrnb,	  _vqrshrnb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26601 mCEF(vqrshrunt,  _vqrshrunt,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26602 mCEF(vqrshrunb,  _vqrshrunb,	3, (RMQ, RMQ, I32z),	mve_vshrn),
26603
26604 mToC("vshlc",	    eea00fc0,	   3, (RMQ, RR, I32z),	    mve_vshlc),
26605 mToC("vshllt",	    ee201e00,	   3, (RMQ, RMQ, I32),	    mve_vshll),
26606 mToC("vshllb",	    ee200e00,	   3, (RMQ, RMQ, I32),	    mve_vshll),
26607
26608 toU("dlstp",	_dlstp, 2, (LR, RR),      t_loloop),
26609 toU("wlstp",	_wlstp, 3, (LR, RR, EXP), t_loloop),
26610 toU("letp",	_letp,  2, (LR, EXP),	  t_loloop),
26611 toU("lctp",	_lctp,  0, (),		  t_loloop),
26612
26613#undef THUMB_VARIANT
26614#define THUMB_VARIANT & mve_fp_ext
26615 mToC("vcmul", ee300e00,   4, (RMQ, RMQ, RMQ, EXPi),		  mve_vcmul),
26616 mToC("vfmas", ee311e40,   3, (RMQ, RMQ, RR),			  mve_vfmas),
26617 mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ),			  mve_vmaxnma_vminnma),
26618 mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ),			  mve_vmaxnma_vminnma),
26619 mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ),			  mve_vmaxnmv),
26620 mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ),			  mve_vmaxnmv),
26621 mToC("vminnmv", eeee0f80, 2, (RR, RMQ),			  mve_vmaxnmv),
26622 mToC("vminnmav",eeec0f80, 2, (RR, RMQ),			  mve_vmaxnmv),
26623
26624#undef  ARM_VARIANT
26625#define ARM_VARIANT  & fpu_vfp_ext_v1
26626#undef  THUMB_VARIANT
26627#define THUMB_VARIANT  & arm_ext_v6t2
26628
26629 mcCE(fcpyd,	eb00b40, 2, (RVD, RVD),	      vfp_dp_rd_rm),
26630
26631#undef  ARM_VARIANT
26632#define ARM_VARIANT  & fpu_vfp_ext_v1xd
26633
26634 mnCEF(vmla,     _vmla,    3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
26635 mnCEF(vmul,     _vmul,    3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
26636 MNCE(vmov,   0,	1, (VMOV),	      neon_mov),
26637 mcCE(fmrs,	e100a10, 2, (RR, RVS),	      vfp_reg_from_sp),
26638 mcCE(fmsr,	e000a10, 2, (RVS, RR),	      vfp_sp_from_reg),
26639 mcCE(fcpys,	eb00a40, 2, (RVS, RVS),	      vfp_sp_monadic),
26640
26641 mCEF(vmullt, _vmullt,	3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ),	mve_vmull),
26642 mnCEF(vadd,  _vadd,	3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR),	neon_addsub_if_i),
26643 mnCEF(vsub,  _vsub,	3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR),	neon_addsub_if_i),
26644
26645 MNCEF(vabs,  1b10300,	2, (RNSDQMQ, RNSDQMQ),	neon_abs_neg),
26646 MNCEF(vneg,  1b10380,	2, (RNSDQMQ, RNSDQMQ),	neon_abs_neg),
26647
26648 mCEF(vmovlt, _vmovlt,	1, (VMOV),		mve_movl),
26649 mCEF(vmovlb, _vmovlb,	1, (VMOV),		mve_movl),
26650
26651 mnCE(vcmp,      _vcmp,    3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ),    vfp_nsyn_cmp),
26652 mnCE(vcmpe,     _vcmpe,   3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ),    vfp_nsyn_cmp),
26653
26654#undef  ARM_VARIANT
26655#define ARM_VARIANT  & fpu_vfp_ext_v2
26656
26657 mcCE(fmsrr,	c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
26658 mcCE(fmrrs,	c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
26659 mcCE(fmdrr,	c400b10, 3, (RVD, RR, RR),    vfp_dp_rm_rd_rn),
26660 mcCE(fmrrd,	c500b10, 3, (RR, RR, RVD),    vfp_dp_rd_rn_rm),
26661
26662#undef  ARM_VARIANT
26663#define ARM_VARIANT    & fpu_vfp_ext_armv8xd
26664 mnUF(vcvta,  _vcvta,  2, (RNSDQMQ, oRNSDQMQ),		neon_cvta),
26665 mnUF(vcvtp,  _vcvta,  2, (RNSDQMQ, oRNSDQMQ),		neon_cvtp),
26666 mnUF(vcvtn,  _vcvta,  3, (RNSDQMQ, oRNSDQMQ, oI32z),	neon_cvtn),
26667 mnUF(vcvtm,  _vcvta,  2, (RNSDQMQ, oRNSDQMQ),		neon_cvtm),
26668 mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ),	vmaxnm),
26669 mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ),	vmaxnm),
26670
26671#undef	ARM_VARIANT
26672#define ARM_VARIANT & fpu_neon_ext_v1
26673 mnUF(vabd,      _vabd,		  3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
26674 mnUF(vabdl,     _vabdl,	  3, (RNQMQ, RNDMQ, RNDMQ),   neon_dyadic_long),
26675 mnUF(vaddl,     _vaddl,	  3, (RNSDQMQ, oRNSDMQ, RNSDMQR),  neon_dyadic_long),
26676 mnUF(vsubl,     _vsubl,	  3, (RNSDQMQ, oRNSDMQ, RNSDMQR),  neon_dyadic_long),
26677 mnUF(vand,      _vand,		  3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26678 mnUF(vbic,      _vbic,		  3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26679 mnUF(vorr,      _vorr,		  3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26680 mnUF(vorn,      _vorn,		  3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
26681 mnUF(veor,      _veor,		  3, (RNDQMQ, oRNDQMQ, RNDQMQ),      neon_logic),
26682 MNUF(vcls,      1b00400,	  2, (RNDQMQ, RNDQMQ),		     neon_cls),
26683 MNUF(vclz,      1b00480,	  2, (RNDQMQ, RNDQMQ),		     neon_clz),
26684 mnCE(vdup,      _vdup,		  2, (RNDQMQ, RR_RNSC),		     neon_dup),
26685 MNUF(vhadd,     00000000,	  3, (RNDQMQ, oRNDQMQ, RNDQMQR),  neon_dyadic_i_su),
26686 MNUF(vrhadd,    00000100,	  3, (RNDQMQ, oRNDQMQ, RNDQMQ),	  neon_dyadic_i_su),
26687 MNUF(vhsub,     00000200,	  3, (RNDQMQ, oRNDQMQ, RNDQMQR),  neon_dyadic_i_su),
26688 mnUF(vmin,      _vmin,    3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
26689 mnUF(vmax,      _vmax,    3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
26690 MNUF(vqadd,     0000010,  3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
26691 MNUF(vqsub,     0000210,  3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
26692 mnUF(vmvn,      _vmvn,    2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn),
26693 MNUF(vqabs,     1b00700,  2, (RNDQMQ, RNDQMQ),     neon_sat_abs_neg),
26694 MNUF(vqneg,     1b00780,  2, (RNDQMQ, RNDQMQ),     neon_sat_abs_neg),
26695 mnUF(vqrdmlah,  _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah),
26696 mnUF(vqdmulh,   _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
26697 mnUF(vqrdmulh,  _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
26698 MNUF(vqrshl,    0000510,  3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
26699 MNUF(vrshl,     0000500,  3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
26700 MNUF(vshr,      0800010,  3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
26701 MNUF(vrshr,     0800210,  3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
26702 MNUF(vsli,      1800510,  3, (RNDQMQ, oRNDQMQ, I63),  neon_sli),
26703 MNUF(vsri,      1800410,  3, (RNDQMQ, oRNDQMQ, I64z), neon_sri),
26704 MNUF(vrev64,    1b00000,  2, (RNDQMQ, RNDQMQ),     neon_rev),
26705 MNUF(vrev32,    1b00080,  2, (RNDQMQ, RNDQMQ),     neon_rev),
26706 MNUF(vrev16,    1b00100,  2, (RNDQMQ, RNDQMQ),     neon_rev),
26707 mnUF(vshl,	 _vshl,    3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_shl),
26708 mnUF(vqshl,     _vqshl,   3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_qshl),
26709 MNUF(vqshlu,    1800610,  3, (RNDQMQ, oRNDQMQ, I63),		 neon_qshlu_imm),
26710
26711#undef	ARM_VARIANT
26712#define ARM_VARIANT & arm_ext_v8_3
26713#undef	THUMB_VARIANT
26714#define	THUMB_VARIANT & arm_ext_v6t2_v8m
26715 MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
26716 MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
26717
26718#undef	ARM_VARIANT
26719#define ARM_VARIANT &arm_ext_bf16
26720#undef	THUMB_VARIANT
26721#define	THUMB_VARIANT &arm_ext_bf16
26722 TUF ("vdot", c000d00, fc000d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), vdot, vdot),
26723 TUF ("vmmla", c000c40, fc000c40, 3, (RNQ, RNQ, RNQ), vmmla, vmmla),
26724 TUF ("vfmab", c300810, fc300810, 3, (RNDQ, RNDQ, RNDQ_RNSC), bfloat_vfma, bfloat_vfma),
26725
26726#undef	ARM_VARIANT
26727#define ARM_VARIANT &arm_ext_i8mm
26728#undef	THUMB_VARIANT
26729#define	THUMB_VARIANT &arm_ext_i8mm
26730 TUF ("vsmmla", c200c40, fc200c40, 3, (RNQ, RNQ, RNQ), vsmmla, vsmmla),
26731 TUF ("vummla", c200c50, fc200c50, 3, (RNQ, RNQ, RNQ), vummla, vummla),
26732 TUF ("vusmmla", ca00c40, fca00c40, 3, (RNQ, RNQ, RNQ), vsmmla, vsmmla),
26733 TUF ("vusdot", c800d00, fc800d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), vusdot, vusdot),
26734 TUF ("vsudot", c800d10, fc800d10, 3, (RNDQ, RNDQ, RNSC), vsudot, vsudot),
26735
26736#undef	ARM_VARIANT
26737#undef	THUMB_VARIANT
26738#define	THUMB_VARIANT &arm_ext_cde
26739 ToC ("cx1", ee000000, 3, (RCP, APSR_RR, I8191), cx1),
26740 ToC ("cx1a", fe000000, 3, (RCP, APSR_RR, I8191), cx1a),
26741 ToC ("cx1d", ee000040, 4, (RCP, RR, APSR_RR, I8191), cx1d),
26742 ToC ("cx1da", fe000040, 4, (RCP, RR, APSR_RR, I8191), cx1da),
26743
26744 ToC ("cx2", ee400000, 4, (RCP, APSR_RR, APSR_RR, I511), cx2),
26745 ToC ("cx2a", fe400000, 4, (RCP, APSR_RR, APSR_RR, I511), cx2a),
26746 ToC ("cx2d", ee400040, 5, (RCP, RR, APSR_RR, APSR_RR, I511), cx2d),
26747 ToC ("cx2da", fe400040, 5, (RCP, RR, APSR_RR, APSR_RR, I511), cx2da),
26748
26749 ToC ("cx3", ee800000, 5, (RCP, APSR_RR, APSR_RR, APSR_RR, I63), cx3),
26750 ToC ("cx3a", fe800000, 5, (RCP, APSR_RR, APSR_RR, APSR_RR, I63), cx3a),
26751 ToC ("cx3d", ee800040, 6, (RCP, RR, APSR_RR, APSR_RR, APSR_RR, I63), cx3d),
26752 ToC ("cx3da", fe800040, 6, (RCP, RR, APSR_RR, APSR_RR, APSR_RR, I63), cx3da),
26753
26754 mToC ("vcx1", ec200000, 3, (RCP, RNSDMQ, I4095), vcx1),
26755 mToC ("vcx1a", fc200000, 3, (RCP, RNSDMQ, I4095), vcx1),
26756
26757 mToC ("vcx2", ec300000, 4, (RCP, RNSDMQ, RNSDMQ, I127), vcx2),
26758 mToC ("vcx2a", fc300000, 4, (RCP, RNSDMQ, RNSDMQ, I127), vcx2),
26759
26760 mToC ("vcx3", ec800000, 5, (RCP, RNSDMQ, RNSDMQ, RNSDMQ, I15), vcx3),
26761 mToC ("vcx3a", fc800000, 5, (RCP, RNSDMQ, RNSDMQ, RNSDMQ, I15), vcx3),
26762};
26763
26764#undef ARM_VARIANT
26765#undef THUMB_VARIANT
26766#undef TCE
26767#undef TUE
26768#undef TUF
26769#undef TCC
26770#undef cCE
26771#undef cCL
26772#undef C3E
26773#undef C3
26774#undef CE
26775#undef CM
26776#undef CL
26777#undef UE
26778#undef UF
26779#undef UT
26780#undef NUF
26781#undef nUF
26782#undef NCE
26783#undef nCE
26784#undef OPS0
26785#undef OPS1
26786#undef OPS2
26787#undef OPS3
26788#undef OPS4
26789#undef OPS5
26790#undef OPS6
26791#undef do_0
26792#undef ToC
26793#undef toC
26794#undef ToU
26795#undef toU
26796
26797/* MD interface: bits in the object file.  */
26798
26799/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26800   for use in the a.out file, and stores them in the array pointed to by buf.
26801   This knows about the endian-ness of the target machine and does
26802   THE RIGHT THING, whatever it is.  Possible values for n are 1 (byte)
26803   2 (short) and 4 (long)  Floating numbers are put out as a series of
26804   LITTLENUMS (shorts, here at least).	*/
26805
26806void
26807md_number_to_chars (char * buf, valueT val, int n)
26808{
26809  if (target_big_endian)
26810    number_to_chars_bigendian (buf, val, n);
26811  else
26812    number_to_chars_littleendian (buf, val, n);
26813}
26814
26815static valueT
26816md_chars_to_number (char * buf, int n)
26817{
26818  valueT result = 0;
26819  unsigned char * where = (unsigned char *) buf;
26820
26821  if (target_big_endian)
26822    {
26823      while (n--)
26824	{
26825	  result <<= 8;
26826	  result |= (*where++ & 255);
26827	}
26828    }
26829  else
26830    {
26831      while (n--)
26832	{
26833	  result <<= 8;
26834	  result |= (where[n] & 255);
26835	}
26836    }
26837
26838  return result;
26839}
26840
26841/* MD interface: Sections.  */
26842
26843/* Calculate the maximum variable size (i.e., excluding fr_fix)
26844   that an rs_machine_dependent frag may reach.  */
26845
26846unsigned int
26847arm_frag_max_var (fragS *fragp)
26848{
26849  /* We only use rs_machine_dependent for variable-size Thumb instructions,
26850     which are either THUMB_SIZE (2) or INSN_SIZE (4).
26851
26852     Note that we generate relaxable instructions even for cases that don't
26853     really need it, like an immediate that's a trivial constant.  So we're
26854     overestimating the instruction size for some of those cases.  Rather
26855     than putting more intelligence here, it would probably be better to
26856     avoid generating a relaxation frag in the first place when it can be
26857     determined up front that a short instruction will suffice.  */
26858
26859  gas_assert (fragp->fr_type == rs_machine_dependent);
26860  return INSN_SIZE;
26861}
26862
26863/* Estimate the size of a frag before relaxing.  Assume everything fits in
26864   2 bytes.  */
26865
26866int
26867md_estimate_size_before_relax (fragS * fragp,
26868			       segT    segtype ATTRIBUTE_UNUSED)
26869{
26870  fragp->fr_var = 2;
26871  return 2;
26872}
26873
26874/* Convert a machine dependent frag.  */
26875
26876void
26877md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
26878{
26879  unsigned long insn;
26880  unsigned long old_op;
26881  char *buf;
26882  expressionS exp;
26883  fixS *fixp;
26884  int reloc_type;
26885  int pc_rel;
26886  int opcode;
26887
26888  buf = fragp->fr_literal + fragp->fr_fix;
26889
26890  old_op = bfd_get_16(abfd, buf);
26891  if (fragp->fr_symbol)
26892    {
26893      exp.X_op = O_symbol;
26894      exp.X_add_symbol = fragp->fr_symbol;
26895    }
26896  else
26897    {
26898      exp.X_op = O_constant;
26899    }
26900  exp.X_add_number = fragp->fr_offset;
26901  opcode = fragp->fr_subtype;
26902  switch (opcode)
26903    {
26904    case T_MNEM_ldr_pc:
26905    case T_MNEM_ldr_pc2:
26906    case T_MNEM_ldr_sp:
26907    case T_MNEM_str_sp:
26908    case T_MNEM_ldr:
26909    case T_MNEM_ldrb:
26910    case T_MNEM_ldrh:
26911    case T_MNEM_str:
26912    case T_MNEM_strb:
26913    case T_MNEM_strh:
26914      if (fragp->fr_var == 4)
26915	{
26916	  insn = THUMB_OP32 (opcode);
26917	  if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
26918	    {
26919	      insn |= (old_op & 0x700) << 4;
26920	    }
26921	  else
26922	    {
26923	      insn |= (old_op & 7) << 12;
26924	      insn |= (old_op & 0x38) << 13;
26925	    }
26926	  insn |= 0x00000c00;
26927	  put_thumb32_insn (buf, insn);
26928	  reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
26929	}
26930      else
26931	{
26932	  reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
26933	}
26934      pc_rel = (opcode == T_MNEM_ldr_pc2);
26935      break;
26936    case T_MNEM_adr:
26937      /* Thumb bits should be set in the frag handling so we process them
26938	 after all symbols have been seen.  PR gas/25235.  */
26939      if (exp.X_op == O_symbol
26940	  && exp.X_add_symbol != NULL
26941	  && S_IS_DEFINED (exp.X_add_symbol)
26942	  && THUMB_IS_FUNC (exp.X_add_symbol))
26943	exp.X_add_number |= 1;
26944
26945      if (fragp->fr_var == 4)
26946	{
26947	  insn = THUMB_OP32 (opcode);
26948	  insn |= (old_op & 0xf0) << 4;
26949	  put_thumb32_insn (buf, insn);
26950	  reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
26951	}
26952      else
26953	{
26954	  reloc_type = BFD_RELOC_ARM_THUMB_ADD;
26955	  exp.X_add_number -= 4;
26956	}
26957      pc_rel = 1;
26958      break;
26959    case T_MNEM_mov:
26960    case T_MNEM_movs:
26961    case T_MNEM_cmp:
26962    case T_MNEM_cmn:
26963      if (fragp->fr_var == 4)
26964	{
26965	  int r0off = (opcode == T_MNEM_mov
26966		       || opcode == T_MNEM_movs) ? 0 : 8;
26967	  insn = THUMB_OP32 (opcode);
26968	  insn = (insn & 0xe1ffffff) | 0x10000000;
26969	  insn |= (old_op & 0x700) << r0off;
26970	  put_thumb32_insn (buf, insn);
26971	  reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
26972	}
26973      else
26974	{
26975	  reloc_type = BFD_RELOC_ARM_THUMB_IMM;
26976	}
26977      pc_rel = 0;
26978      break;
26979    case T_MNEM_b:
26980      if (fragp->fr_var == 4)
26981	{
26982	  insn = THUMB_OP32(opcode);
26983	  put_thumb32_insn (buf, insn);
26984	  reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
26985	}
26986      else
26987	reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
26988      pc_rel = 1;
26989      break;
26990    case T_MNEM_bcond:
26991      if (fragp->fr_var == 4)
26992	{
26993	  insn = THUMB_OP32(opcode);
26994	  insn |= (old_op & 0xf00) << 14;
26995	  put_thumb32_insn (buf, insn);
26996	  reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
26997	}
26998      else
26999	reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
27000      pc_rel = 1;
27001      break;
27002    case T_MNEM_add_sp:
27003    case T_MNEM_add_pc:
27004    case T_MNEM_inc_sp:
27005    case T_MNEM_dec_sp:
27006      if (fragp->fr_var == 4)
27007	{
27008	  /* ??? Choose between add and addw.  */
27009	  insn = THUMB_OP32 (opcode);
27010	  insn |= (old_op & 0xf0) << 4;
27011	  put_thumb32_insn (buf, insn);
27012	  if (opcode == T_MNEM_add_pc)
27013	    reloc_type = BFD_RELOC_ARM_T32_IMM12;
27014	  else
27015	    reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
27016	}
27017      else
27018	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
27019      pc_rel = 0;
27020      break;
27021
27022    case T_MNEM_addi:
27023    case T_MNEM_addis:
27024    case T_MNEM_subi:
27025    case T_MNEM_subis:
27026      if (fragp->fr_var == 4)
27027	{
27028	  insn = THUMB_OP32 (opcode);
27029	  insn |= (old_op & 0xf0) << 4;
27030	  insn |= (old_op & 0xf) << 16;
27031	  put_thumb32_insn (buf, insn);
27032	  if (insn & (1 << 20))
27033	    reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
27034	  else
27035	    reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
27036	}
27037      else
27038	reloc_type = BFD_RELOC_ARM_THUMB_ADD;
27039      pc_rel = 0;
27040      break;
27041    default:
27042      abort ();
27043    }
27044  fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
27045		      (enum bfd_reloc_code_real) reloc_type);
27046  fixp->fx_file = fragp->fr_file;
27047  fixp->fx_line = fragp->fr_line;
27048  fragp->fr_fix += fragp->fr_var;
27049
27050  /* Set whether we use thumb-2 ISA based on final relaxation results.  */
27051  if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
27052      && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
27053    ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
27054}
27055
27056/* Return the size of a relaxable immediate operand instruction.
27057   SHIFT and SIZE specify the form of the allowable immediate.  */
27058static int
27059relax_immediate (fragS *fragp, int size, int shift)
27060{
27061  offsetT offset;
27062  offsetT mask;
27063  offsetT low;
27064
27065  /* ??? Should be able to do better than this.  */
27066  if (fragp->fr_symbol)
27067    return 4;
27068
27069  low = (1 << shift) - 1;
27070  mask = (1 << (shift + size)) - (1 << shift);
27071  offset = fragp->fr_offset;
27072  /* Force misaligned offsets to 32-bit variant.  */
27073  if (offset & low)
27074    return 4;
27075  if (offset & ~mask)
27076    return 4;
27077  return 2;
27078}
27079
27080/* Get the address of a symbol during relaxation.  */
27081static addressT
27082relaxed_symbol_addr (fragS *fragp, long stretch)
27083{
27084  fragS *sym_frag;
27085  addressT addr;
27086  symbolS *sym;
27087
27088  sym = fragp->fr_symbol;
27089  sym_frag = symbol_get_frag (sym);
27090  know (S_GET_SEGMENT (sym) != absolute_section
27091	|| sym_frag == &zero_address_frag);
27092  addr = S_GET_VALUE (sym) + fragp->fr_offset;
27093
27094  /* If frag has yet to be reached on this pass, assume it will
27095     move by STRETCH just as we did.  If this is not so, it will
27096     be because some frag between grows, and that will force
27097     another pass.  */
27098
27099  if (stretch != 0
27100      && sym_frag->relax_marker != fragp->relax_marker)
27101    {
27102      fragS *f;
27103
27104      /* Adjust stretch for any alignment frag.  Note that if have
27105	 been expanding the earlier code, the symbol may be
27106	 defined in what appears to be an earlier frag.  FIXME:
27107	 This doesn't handle the fr_subtype field, which specifies
27108	 a maximum number of bytes to skip when doing an
27109	 alignment.  */
27110      for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
27111	{
27112	  if (f->fr_type == rs_align || f->fr_type == rs_align_code)
27113	    {
27114	      if (stretch < 0)
27115		stretch = - ((- stretch)
27116			     & ~ ((1 << (int) f->fr_offset) - 1));
27117	      else
27118		stretch &= ~ ((1 << (int) f->fr_offset) - 1);
27119	      if (stretch == 0)
27120		break;
27121	    }
27122	}
27123      if (f != NULL)
27124	addr += stretch;
27125    }
27126
27127  return addr;
27128}
27129
27130/* Return the size of a relaxable adr pseudo-instruction or PC-relative
27131   load.  */
27132static int
27133relax_adr (fragS *fragp, asection *sec, long stretch)
27134{
27135  addressT addr;
27136  offsetT val;
27137
27138  /* Assume worst case for symbols not known to be in the same section.  */
27139  if (fragp->fr_symbol == NULL
27140      || !S_IS_DEFINED (fragp->fr_symbol)
27141      || sec != S_GET_SEGMENT (fragp->fr_symbol)
27142      || S_IS_WEAK (fragp->fr_symbol)
27143      || THUMB_IS_FUNC (fragp->fr_symbol))
27144    return 4;
27145
27146  val = relaxed_symbol_addr (fragp, stretch);
27147  addr = fragp->fr_address + fragp->fr_fix;
27148  addr = (addr + 4) & ~3;
27149  /* Force misaligned targets to 32-bit variant.  */
27150  if (val & 3)
27151    return 4;
27152  val -= addr;
27153  if (val < 0 || val > 1020)
27154    return 4;
27155  return 2;
27156}
27157
27158/* Return the size of a relaxable add/sub immediate instruction.  */
27159static int
27160relax_addsub (fragS *fragp, asection *sec)
27161{
27162  char *buf;
27163  int op;
27164
27165  buf = fragp->fr_literal + fragp->fr_fix;
27166  op = bfd_get_16(sec->owner, buf);
27167  if ((op & 0xf) == ((op >> 4) & 0xf))
27168    return relax_immediate (fragp, 8, 0);
27169  else
27170    return relax_immediate (fragp, 3, 0);
27171}
27172
27173/* Return TRUE iff the definition of symbol S could be pre-empted
27174   (overridden) at link or load time.  */
27175static bool
27176symbol_preemptible (symbolS *s)
27177{
27178  /* Weak symbols can always be pre-empted.  */
27179  if (S_IS_WEAK (s))
27180    return true;
27181
27182  /* Non-global symbols cannot be pre-empted. */
27183  if (! S_IS_EXTERNAL (s))
27184    return false;
27185
27186#ifdef OBJ_ELF
27187  /* In ELF, a global symbol can be marked protected, or private.  In that
27188     case it can't be pre-empted (other definitions in the same link unit
27189     would violate the ODR).  */
27190  if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
27191    return false;
27192#endif
27193
27194  /* Other global symbols might be pre-empted.  */
27195  return true;
27196}
27197
27198/* Return the size of a relaxable branch instruction.  BITS is the
27199   size of the offset field in the narrow instruction.  */
27200
27201static int
27202relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
27203{
27204  addressT addr;
27205  offsetT val;
27206  offsetT limit;
27207
27208  /* Assume worst case for symbols not known to be in the same section.  */
27209  if (!S_IS_DEFINED (fragp->fr_symbol)
27210      || sec != S_GET_SEGMENT (fragp->fr_symbol)
27211      || S_IS_WEAK (fragp->fr_symbol))
27212    return 4;
27213
27214#ifdef OBJ_ELF
27215  /* A branch to a function in ARM state will require interworking.  */
27216  if (S_IS_DEFINED (fragp->fr_symbol)
27217      && ARM_IS_FUNC (fragp->fr_symbol))
27218      return 4;
27219#endif
27220
27221  if (symbol_preemptible (fragp->fr_symbol))
27222    return 4;
27223
27224  val = relaxed_symbol_addr (fragp, stretch);
27225  addr = fragp->fr_address + fragp->fr_fix + 4;
27226  val -= addr;
27227
27228  /* Offset is a signed value *2 */
27229  limit = 1 << bits;
27230  if (val >= limit || val < -limit)
27231    return 4;
27232  return 2;
27233}
27234
27235
27236/* Relax a machine dependent frag.  This returns the amount by which
27237   the current size of the frag should change.  */
27238
27239int
27240arm_relax_frag (asection *sec, fragS *fragp, long stretch)
27241{
27242  int oldsize;
27243  int newsize;
27244
27245  oldsize = fragp->fr_var;
27246  switch (fragp->fr_subtype)
27247    {
27248    case T_MNEM_ldr_pc2:
27249      newsize = relax_adr (fragp, sec, stretch);
27250      break;
27251    case T_MNEM_ldr_pc:
27252    case T_MNEM_ldr_sp:
27253    case T_MNEM_str_sp:
27254      newsize = relax_immediate (fragp, 8, 2);
27255      break;
27256    case T_MNEM_ldr:
27257    case T_MNEM_str:
27258      newsize = relax_immediate (fragp, 5, 2);
27259      break;
27260    case T_MNEM_ldrh:
27261    case T_MNEM_strh:
27262      newsize = relax_immediate (fragp, 5, 1);
27263      break;
27264    case T_MNEM_ldrb:
27265    case T_MNEM_strb:
27266      newsize = relax_immediate (fragp, 5, 0);
27267      break;
27268    case T_MNEM_adr:
27269      newsize = relax_adr (fragp, sec, stretch);
27270      break;
27271    case T_MNEM_mov:
27272    case T_MNEM_movs:
27273    case T_MNEM_cmp:
27274    case T_MNEM_cmn:
27275      newsize = relax_immediate (fragp, 8, 0);
27276      break;
27277    case T_MNEM_b:
27278      newsize = relax_branch (fragp, sec, 11, stretch);
27279      break;
27280    case T_MNEM_bcond:
27281      newsize = relax_branch (fragp, sec, 8, stretch);
27282      break;
27283    case T_MNEM_add_sp:
27284    case T_MNEM_add_pc:
27285      newsize = relax_immediate (fragp, 8, 2);
27286      break;
27287    case T_MNEM_inc_sp:
27288    case T_MNEM_dec_sp:
27289      newsize = relax_immediate (fragp, 7, 2);
27290      break;
27291    case T_MNEM_addi:
27292    case T_MNEM_addis:
27293    case T_MNEM_subi:
27294    case T_MNEM_subis:
27295      newsize = relax_addsub (fragp, sec);
27296      break;
27297    default:
27298      abort ();
27299    }
27300
27301  fragp->fr_var = newsize;
27302  /* Freeze wide instructions that are at or before the same location as
27303     in the previous pass.  This avoids infinite loops.
27304     Don't freeze them unconditionally because targets may be artificially
27305     misaligned by the expansion of preceding frags.  */
27306  if (stretch <= 0 && newsize > 2)
27307    {
27308      md_convert_frag (sec->owner, sec, fragp);
27309      frag_wane (fragp);
27310    }
27311
27312  return newsize - oldsize;
27313}
27314
27315/* Round up a section size to the appropriate boundary.	 */
27316
27317valueT
27318md_section_align (segT	 segment ATTRIBUTE_UNUSED,
27319		  valueT size)
27320{
27321  return size;
27322}
27323
27324/* This is called from HANDLE_ALIGN in write.c.	 Fill in the contents
27325   of an rs_align_code fragment.  */
27326
27327void
27328arm_handle_align (fragS * fragP)
27329{
27330  static unsigned char const arm_noop[2][2][4] =
27331    {
27332      {  /* ARMv1 */
27333	{0x00, 0x00, 0xa0, 0xe1},  /* LE */
27334	{0xe1, 0xa0, 0x00, 0x00},  /* BE */
27335      },
27336      {  /* ARMv6k */
27337	{0x00, 0xf0, 0x20, 0xe3},  /* LE */
27338	{0xe3, 0x20, 0xf0, 0x00},  /* BE */
27339      },
27340    };
27341  static unsigned char const thumb_noop[2][2][2] =
27342    {
27343      {  /* Thumb-1 */
27344	{0xc0, 0x46},  /* LE */
27345	{0x46, 0xc0},  /* BE */
27346      },
27347      {  /* Thumb-2 */
27348	{0x00, 0xbf},  /* LE */
27349	{0xbf, 0x00}   /* BE */
27350      }
27351    };
27352  static unsigned char const wide_thumb_noop[2][4] =
27353    {  /* Wide Thumb-2 */
27354      {0xaf, 0xf3, 0x00, 0x80},  /* LE */
27355      {0xf3, 0xaf, 0x80, 0x00},  /* BE */
27356    };
27357
27358  unsigned bytes, fix, noop_size;
27359  char * p;
27360  const unsigned char * noop;
27361  const unsigned char *narrow_noop = NULL;
27362#ifdef OBJ_ELF
27363  enum mstate state;
27364#endif
27365
27366  if (fragP->fr_type != rs_align_code)
27367    return;
27368
27369  bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
27370  p = fragP->fr_literal + fragP->fr_fix;
27371  fix = 0;
27372
27373  if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
27374    bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
27375
27376  gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
27377
27378  if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
27379    {
27380      if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
27381			       ? selected_cpu : arm_arch_none, arm_ext_v6t2))
27382	{
27383	  narrow_noop = thumb_noop[1][target_big_endian];
27384	  noop = wide_thumb_noop[target_big_endian];
27385	}
27386      else
27387	noop = thumb_noop[0][target_big_endian];
27388      noop_size = 2;
27389#ifdef OBJ_ELF
27390      state = MAP_THUMB;
27391#endif
27392    }
27393  else
27394    {
27395      noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
27396					   ? selected_cpu : arm_arch_none,
27397					   arm_ext_v6k) != 0]
27398		     [target_big_endian];
27399      noop_size = 4;
27400#ifdef OBJ_ELF
27401      state = MAP_ARM;
27402#endif
27403    }
27404
27405  fragP->fr_var = noop_size;
27406
27407  if (bytes & (noop_size - 1))
27408    {
27409      fix = bytes & (noop_size - 1);
27410#ifdef OBJ_ELF
27411      insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
27412#endif
27413      memset (p, 0, fix);
27414      p += fix;
27415      bytes -= fix;
27416    }
27417
27418  if (narrow_noop)
27419    {
27420      if (bytes & noop_size)
27421	{
27422	  /* Insert a narrow noop.  */
27423	  memcpy (p, narrow_noop, noop_size);
27424	  p += noop_size;
27425	  bytes -= noop_size;
27426	  fix += noop_size;
27427	}
27428
27429      /* Use wide noops for the remainder */
27430      noop_size = 4;
27431    }
27432
27433  while (bytes >= noop_size)
27434    {
27435      memcpy (p, noop, noop_size);
27436      p += noop_size;
27437      bytes -= noop_size;
27438      fix += noop_size;
27439    }
27440
27441  fragP->fr_fix += fix;
27442}
27443
27444/* Called from md_do_align.  Used to create an alignment
27445   frag in a code section.  */
27446
27447void
27448arm_frag_align_code (int n, int max)
27449{
27450  char * p;
27451
27452  /* We assume that there will never be a requirement
27453     to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes.  */
27454  if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
27455    {
27456      char err_msg[128];
27457
27458      sprintf (err_msg,
27459	_("alignments greater than %d bytes not supported in .text sections."),
27460	MAX_MEM_FOR_RS_ALIGN_CODE + 1);
27461      as_fatal ("%s", err_msg);
27462    }
27463
27464  p = frag_var (rs_align_code,
27465		MAX_MEM_FOR_RS_ALIGN_CODE,
27466		1,
27467		(relax_substateT) max,
27468		(symbolS *) NULL,
27469		(offsetT) n,
27470		(char *) NULL);
27471  *p = 0;
27472}
27473
27474/* Perform target specific initialisation of a frag.
27475   Note - despite the name this initialisation is not done when the frag
27476   is created, but only when its type is assigned.  A frag can be created
27477   and used a long time before its type is set, so beware of assuming that
27478   this initialisation is performed first.  */
27479
27480#ifndef OBJ_ELF
27481void
27482arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
27483{
27484  /* Record whether this frag is in an ARM or a THUMB area.  */
27485  fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
27486}
27487
27488#else /* OBJ_ELF is defined.  */
27489void
27490arm_init_frag (fragS * fragP, int max_chars)
27491{
27492  bool frag_thumb_mode;
27493
27494  /* If the current ARM vs THUMB mode has not already
27495     been recorded into this frag then do so now.  */
27496  if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
27497    fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
27498
27499  /* PR 21809: Do not set a mapping state for debug sections
27500     - it just confuses other tools.  */
27501  if (bfd_section_flags (now_seg) & SEC_DEBUGGING)
27502    return;
27503
27504  frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
27505
27506  /* Record a mapping symbol for alignment frags.  We will delete this
27507     later if the alignment ends up empty.  */
27508  switch (fragP->fr_type)
27509    {
27510    case rs_align:
27511    case rs_align_test:
27512    case rs_fill:
27513      mapping_state_2 (MAP_DATA, max_chars);
27514      break;
27515    case rs_align_code:
27516      mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
27517      break;
27518    default:
27519      break;
27520    }
27521}
27522
27523/* When we change sections we need to issue a new mapping symbol.  */
27524
27525void
27526arm_elf_change_section (void)
27527{
27528  /* Link an unlinked unwind index table section to the .text section.	*/
27529  if (elf_section_type (now_seg) == SHT_ARM_EXIDX
27530      && elf_linked_to_section (now_seg) == NULL)
27531    elf_linked_to_section (now_seg) = text_section;
27532}
27533
27534int
27535arm_elf_section_type (const char * str, size_t len)
27536{
27537  if (len == 5 && startswith (str, "exidx"))
27538    return SHT_ARM_EXIDX;
27539
27540  return -1;
27541}
27542
27543/* Code to deal with unwinding tables.	*/
27544
27545static void add_unwind_adjustsp (offsetT);
27546
27547/* Generate any deferred unwind frame offset.  */
27548
27549static void
27550flush_pending_unwind (void)
27551{
27552  offsetT offset;
27553
27554  offset = unwind.pending_offset;
27555  unwind.pending_offset = 0;
27556  if (offset != 0)
27557    add_unwind_adjustsp (offset);
27558}
27559
27560/* Add an opcode to this list for this function.  Two-byte opcodes should
27561   be passed as op[0] << 8 | op[1].  The list of opcodes is built in reverse
27562   order.  */
27563
27564static void
27565add_unwind_opcode (valueT op, int length)
27566{
27567  /* Add any deferred stack adjustment.	 */
27568  if (unwind.pending_offset)
27569    flush_pending_unwind ();
27570
27571  unwind.sp_restored = 0;
27572
27573  if (unwind.opcode_count + length > unwind.opcode_alloc)
27574    {
27575      unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
27576      if (unwind.opcodes)
27577	unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
27578				     unwind.opcode_alloc);
27579      else
27580	unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
27581    }
27582  while (length > 0)
27583    {
27584      length--;
27585      unwind.opcodes[unwind.opcode_count] = op & 0xff;
27586      op >>= 8;
27587      unwind.opcode_count++;
27588    }
27589}
27590
27591/* Add unwind opcodes to adjust the stack pointer.  */
27592
27593static void
27594add_unwind_adjustsp (offsetT offset)
27595{
27596  valueT op;
27597
27598  if (offset > 0x200)
27599    {
27600      /* We need at most 5 bytes to hold a 32-bit value in a uleb128.  */
27601      char bytes[5];
27602      int n;
27603      valueT o;
27604
27605      /* Long form: 0xb2, uleb128.  */
27606      /* This might not fit in a word so add the individual bytes,
27607	 remembering the list is built in reverse order.  */
27608      o = (valueT) ((offset - 0x204) >> 2);
27609      if (o == 0)
27610	add_unwind_opcode (0, 1);
27611
27612      /* Calculate the uleb128 encoding of the offset.	*/
27613      n = 0;
27614      while (o)
27615	{
27616	  bytes[n] = o & 0x7f;
27617	  o >>= 7;
27618	  if (o)
27619	    bytes[n] |= 0x80;
27620	  n++;
27621	}
27622      /* Add the insn.	*/
27623      for (; n; n--)
27624	add_unwind_opcode (bytes[n - 1], 1);
27625      add_unwind_opcode (0xb2, 1);
27626    }
27627  else if (offset > 0x100)
27628    {
27629      /* Two short opcodes.  */
27630      add_unwind_opcode (0x3f, 1);
27631      op = (offset - 0x104) >> 2;
27632      add_unwind_opcode (op, 1);
27633    }
27634  else if (offset > 0)
27635    {
27636      /* Short opcode.	*/
27637      op = (offset - 4) >> 2;
27638      add_unwind_opcode (op, 1);
27639    }
27640  else if (offset < 0)
27641    {
27642      offset = -offset;
27643      while (offset > 0x100)
27644	{
27645	  add_unwind_opcode (0x7f, 1);
27646	  offset -= 0x100;
27647	}
27648      op = ((offset - 4) >> 2) | 0x40;
27649      add_unwind_opcode (op, 1);
27650    }
27651}
27652
27653/* Finish the list of unwind opcodes for this function.	 */
27654
27655static void
27656finish_unwind_opcodes (void)
27657{
27658  valueT op;
27659
27660  if (unwind.fp_used)
27661    {
27662      /* Adjust sp as necessary.  */
27663      unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
27664      flush_pending_unwind ();
27665
27666      /* After restoring sp from the frame pointer.  */
27667      op = 0x90 | unwind.fp_reg;
27668      add_unwind_opcode (op, 1);
27669    }
27670  else
27671    flush_pending_unwind ();
27672}
27673
27674
27675/* Start an exception table entry.  If idx is nonzero this is an index table
27676   entry.  */
27677
27678static void
27679start_unwind_section (const segT text_seg, int idx)
27680{
27681  const char * text_name;
27682  const char * prefix;
27683  const char * prefix_once;
27684  struct elf_section_match match;
27685  char * sec_name;
27686  int type;
27687  int flags;
27688  int linkonce;
27689
27690  if (idx)
27691    {
27692      prefix = ELF_STRING_ARM_unwind;
27693      prefix_once = ELF_STRING_ARM_unwind_once;
27694      type = SHT_ARM_EXIDX;
27695    }
27696  else
27697    {
27698      prefix = ELF_STRING_ARM_unwind_info;
27699      prefix_once = ELF_STRING_ARM_unwind_info_once;
27700      type = SHT_PROGBITS;
27701    }
27702
27703  text_name = segment_name (text_seg);
27704  if (streq (text_name, ".text"))
27705    text_name = "";
27706
27707  if (startswith (text_name, ".gnu.linkonce.t."))
27708    {
27709      prefix = prefix_once;
27710      text_name += strlen (".gnu.linkonce.t.");
27711    }
27712
27713  sec_name = concat (prefix, text_name, (char *) NULL);
27714
27715  flags = SHF_ALLOC;
27716  linkonce = 0;
27717  memset (&match, 0, sizeof (match));
27718
27719  /* Handle COMDAT group.  */
27720  if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
27721    {
27722      match.group_name = elf_group_name (text_seg);
27723      if (match.group_name == NULL)
27724	{
27725	  as_bad (_("Group section `%s' has no group signature"),
27726		  segment_name (text_seg));
27727	  ignore_rest_of_line ();
27728	  return;
27729	}
27730      flags |= SHF_GROUP;
27731      linkonce = 1;
27732    }
27733
27734  obj_elf_change_section (sec_name, type, flags, 0, &match,
27735			  linkonce, 0);
27736
27737  /* Set the section link for index tables.  */
27738  if (idx)
27739    elf_linked_to_section (now_seg) = text_seg;
27740}
27741
27742
27743/* Start an unwind table entry.	 HAVE_DATA is nonzero if we have additional
27744   personality routine data.  Returns zero, or the index table value for
27745   an inline entry.  */
27746
27747static valueT
27748create_unwind_entry (int have_data)
27749{
27750  int size;
27751  addressT where;
27752  char *ptr;
27753  /* The current word of data.	*/
27754  valueT data;
27755  /* The number of bytes left in this word.  */
27756  int n;
27757
27758  finish_unwind_opcodes ();
27759
27760  /* Remember the current text section.	 */
27761  unwind.saved_seg = now_seg;
27762  unwind.saved_subseg = now_subseg;
27763
27764  start_unwind_section (now_seg, 0);
27765
27766  if (unwind.personality_routine == NULL)
27767    {
27768      if (unwind.personality_index == -2)
27769	{
27770	  if (have_data)
27771	    as_bad (_("handlerdata in cantunwind frame"));
27772	  return 1; /* EXIDX_CANTUNWIND.  */
27773	}
27774
27775      /* Use a default personality routine if none is specified.  */
27776      if (unwind.personality_index == -1)
27777	{
27778	  if (unwind.opcode_count > 3)
27779	    unwind.personality_index = 1;
27780	  else
27781	    unwind.personality_index = 0;
27782	}
27783
27784      /* Space for the personality routine entry.  */
27785      if (unwind.personality_index == 0)
27786	{
27787	  if (unwind.opcode_count > 3)
27788	    as_bad (_("too many unwind opcodes for personality routine 0"));
27789
27790	  if (!have_data)
27791	    {
27792	      /* All the data is inline in the index table.  */
27793	      data = 0x80;
27794	      n = 3;
27795	      while (unwind.opcode_count > 0)
27796		{
27797		  unwind.opcode_count--;
27798		  data = (data << 8) | unwind.opcodes[unwind.opcode_count];
27799		  n--;
27800		}
27801
27802	      /* Pad with "finish" opcodes.  */
27803	      while (n--)
27804		data = (data << 8) | 0xb0;
27805
27806	      return data;
27807	    }
27808	  size = 0;
27809	}
27810      else
27811	/* We get two opcodes "free" in the first word.	 */
27812	size = unwind.opcode_count - 2;
27813    }
27814  else
27815    {
27816      /* PR 16765: Missing or misplaced unwind directives can trigger this.  */
27817      if (unwind.personality_index != -1)
27818	{
27819	  as_bad (_("attempt to recreate an unwind entry"));
27820	  return 1;
27821	}
27822
27823      /* An extra byte is required for the opcode count.	*/
27824      size = unwind.opcode_count + 1;
27825    }
27826
27827  size = (size + 3) >> 2;
27828  if (size > 0xff)
27829    as_bad (_("too many unwind opcodes"));
27830
27831  frag_align (2, 0, 0);
27832  record_alignment (now_seg, 2);
27833  unwind.table_entry = expr_build_dot ();
27834
27835  /* Allocate the table entry.	*/
27836  ptr = frag_more ((size << 2) + 4);
27837  /* PR 13449: Zero the table entries in case some of them are not used.  */
27838  memset (ptr, 0, (size << 2) + 4);
27839  where = frag_now_fix () - ((size << 2) + 4);
27840
27841  switch (unwind.personality_index)
27842    {
27843    case -1:
27844      /* ??? Should this be a PLT generating relocation?  */
27845      /* Custom personality routine.  */
27846      fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
27847	       BFD_RELOC_ARM_PREL31);
27848
27849      where += 4;
27850      ptr += 4;
27851
27852      /* Set the first byte to the number of additional words.	*/
27853      data = size > 0 ? size - 1 : 0;
27854      n = 3;
27855      break;
27856
27857    /* ABI defined personality routines.  */
27858    case 0:
27859      /* Three opcodes bytes are packed into the first word.  */
27860      data = 0x80;
27861      n = 3;
27862      break;
27863
27864    case 1:
27865    case 2:
27866      /* The size and first two opcode bytes go in the first word.  */
27867      data = ((0x80 + unwind.personality_index) << 8) | size;
27868      n = 2;
27869      break;
27870
27871    default:
27872      /* Should never happen.  */
27873      abort ();
27874    }
27875
27876  /* Pack the opcodes into words (MSB first), reversing the list at the same
27877     time.  */
27878  while (unwind.opcode_count > 0)
27879    {
27880      if (n == 0)
27881	{
27882	  md_number_to_chars (ptr, data, 4);
27883	  ptr += 4;
27884	  n = 4;
27885	  data = 0;
27886	}
27887      unwind.opcode_count--;
27888      n--;
27889      data = (data << 8) | unwind.opcodes[unwind.opcode_count];
27890    }
27891
27892  /* Finish off the last word.	*/
27893  if (n < 4)
27894    {
27895      /* Pad with "finish" opcodes.  */
27896      while (n--)
27897	data = (data << 8) | 0xb0;
27898
27899      md_number_to_chars (ptr, data, 4);
27900    }
27901
27902  if (!have_data)
27903    {
27904      /* Add an empty descriptor if there is no user-specified data.   */
27905      ptr = frag_more (4);
27906      md_number_to_chars (ptr, 0, 4);
27907    }
27908
27909  return 0;
27910}
27911
27912
27913/* Initialize the DWARF-2 unwind information for this procedure.  */
27914
27915void
27916tc_arm_frame_initial_instructions (void)
27917{
27918  cfi_add_CFA_def_cfa (REG_SP, 0);
27919}
27920#endif /* OBJ_ELF */
27921
27922/* Convert REGNAME to a DWARF-2 register number.  */
27923
27924int
27925tc_arm_regname_to_dw2regnum (char *regname)
27926{
27927  int reg = arm_reg_parse (&regname, REG_TYPE_RN);
27928  if (reg != FAIL)
27929    return reg;
27930
27931  /* PR 16694: Allow VFP registers as well.  */
27932  reg = arm_reg_parse (&regname, REG_TYPE_VFS);
27933  if (reg != FAIL)
27934    return 64 + reg;
27935
27936  reg = arm_reg_parse (&regname, REG_TYPE_VFD);
27937  if (reg != FAIL)
27938    return reg + 256;
27939
27940  return FAIL;
27941}
27942
27943#ifdef TE_PE
27944void
27945tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
27946{
27947  expressionS exp;
27948
27949  exp.X_op = O_secrel;
27950  exp.X_add_symbol = symbol;
27951  exp.X_add_number = 0;
27952  emit_expr (&exp, size);
27953}
27954#endif
27955
27956/* MD interface: Symbol and relocation handling.  */
27957
27958/* Return the address within the segment that a PC-relative fixup is
27959   relative to.  For ARM, PC-relative fixups applied to instructions
27960   are generally relative to the location of the fixup plus 8 bytes.
27961   Thumb branches are offset by 4, and Thumb loads relative to PC
27962   require special handling.  */
27963
27964long
27965md_pcrel_from_section (fixS * fixP, segT seg)
27966{
27967  offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
27968
27969  /* If this is pc-relative and we are going to emit a relocation
27970     then we just want to put out any pipeline compensation that the linker
27971     will need.  Otherwise we want to use the calculated base.
27972     For WinCE we skip the bias for externals as well, since this
27973     is how the MS ARM-CE assembler behaves and we want to be compatible.  */
27974  if (fixP->fx_pcrel
27975      && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
27976	  || (arm_force_relocation (fixP)
27977#ifdef TE_WINCE
27978	      && !S_IS_EXTERNAL (fixP->fx_addsy)
27979#endif
27980	      )))
27981    base = 0;
27982
27983
27984  switch (fixP->fx_r_type)
27985    {
27986      /* PC relative addressing on the Thumb is slightly odd as the
27987	 bottom two bits of the PC are forced to zero for the
27988	 calculation.  This happens *after* application of the
27989	 pipeline offset.  However, Thumb adrl already adjusts for
27990	 this, so we need not do it again.  */
27991    case BFD_RELOC_ARM_THUMB_ADD:
27992      return base & ~3;
27993
27994    case BFD_RELOC_ARM_THUMB_OFFSET:
27995    case BFD_RELOC_ARM_T32_OFFSET_IMM:
27996    case BFD_RELOC_ARM_T32_ADD_PC12:
27997    case BFD_RELOC_ARM_T32_CP_OFF_IMM:
27998      return (base + 4) & ~3;
27999
28000      /* Thumb branches are simply offset by +4.  */
28001    case BFD_RELOC_THUMB_PCREL_BRANCH5:
28002    case BFD_RELOC_THUMB_PCREL_BRANCH7:
28003    case BFD_RELOC_THUMB_PCREL_BRANCH9:
28004    case BFD_RELOC_THUMB_PCREL_BRANCH12:
28005    case BFD_RELOC_THUMB_PCREL_BRANCH20:
28006    case BFD_RELOC_THUMB_PCREL_BRANCH25:
28007    case BFD_RELOC_THUMB_PCREL_BFCSEL:
28008    case BFD_RELOC_ARM_THUMB_BF17:
28009    case BFD_RELOC_ARM_THUMB_BF19:
28010    case BFD_RELOC_ARM_THUMB_BF13:
28011    case BFD_RELOC_ARM_THUMB_LOOP12:
28012      return base + 4;
28013
28014    case BFD_RELOC_THUMB_PCREL_BRANCH23:
28015      if (fixP->fx_addsy
28016	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28017	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
28018	  && ARM_IS_FUNC (fixP->fx_addsy)
28019	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
28020	base = fixP->fx_where + fixP->fx_frag->fr_address;
28021       return base + 4;
28022
28023      /* BLX is like branches above, but forces the low two bits of PC to
28024	 zero.  */
28025    case BFD_RELOC_THUMB_PCREL_BLX:
28026      if (fixP->fx_addsy
28027	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28028	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
28029	  && THUMB_IS_FUNC (fixP->fx_addsy)
28030	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
28031	base = fixP->fx_where + fixP->fx_frag->fr_address;
28032      return (base + 4) & ~3;
28033
28034      /* ARM mode branches are offset by +8.  However, the Windows CE
28035	 loader expects the relocation not to take this into account.  */
28036    case BFD_RELOC_ARM_PCREL_BLX:
28037      if (fixP->fx_addsy
28038	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28039	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
28040	  && ARM_IS_FUNC (fixP->fx_addsy)
28041	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
28042	base = fixP->fx_where + fixP->fx_frag->fr_address;
28043      return base + 8;
28044
28045    case BFD_RELOC_ARM_PCREL_CALL:
28046      if (fixP->fx_addsy
28047	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28048	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
28049	  && THUMB_IS_FUNC (fixP->fx_addsy)
28050	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
28051	base = fixP->fx_where + fixP->fx_frag->fr_address;
28052      return base + 8;
28053
28054    case BFD_RELOC_ARM_PCREL_BRANCH:
28055    case BFD_RELOC_ARM_PCREL_JUMP:
28056    case BFD_RELOC_ARM_PLT32:
28057#ifdef TE_WINCE
28058      /* When handling fixups immediately, because we have already
28059	 discovered the value of a symbol, or the address of the frag involved
28060	 we must account for the offset by +8, as the OS loader will never see the reloc.
28061	 see fixup_segment() in write.c
28062	 The S_IS_EXTERNAL test handles the case of global symbols.
28063	 Those need the calculated base, not just the pipe compensation the linker will need.  */
28064      if (fixP->fx_pcrel
28065	  && fixP->fx_addsy != NULL
28066	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28067	  && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
28068	return base + 8;
28069      return base;
28070#else
28071      return base + 8;
28072#endif
28073
28074
28075      /* ARM mode loads relative to PC are also offset by +8.  Unlike
28076	 branches, the Windows CE loader *does* expect the relocation
28077	 to take this into account.  */
28078    case BFD_RELOC_ARM_OFFSET_IMM:
28079    case BFD_RELOC_ARM_OFFSET_IMM8:
28080    case BFD_RELOC_ARM_HWLITERAL:
28081    case BFD_RELOC_ARM_LITERAL:
28082    case BFD_RELOC_ARM_CP_OFF_IMM:
28083      return base + 8;
28084
28085
28086      /* Other PC-relative relocations are un-offset.  */
28087    default:
28088      return base;
28089    }
28090}
28091
28092static bool flag_warn_syms = true;
28093
28094bool
28095arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
28096{
28097  /* PR 18347 - Warn if the user attempts to create a symbol with the same
28098     name as an ARM instruction.  Whilst strictly speaking it is allowed, it
28099     does mean that the resulting code might be very confusing to the reader.
28100     Also this warning can be triggered if the user omits an operand before
28101     an immediate address, eg:
28102
28103       LDR =foo
28104
28105     GAS treats this as an assignment of the value of the symbol foo to a
28106     symbol LDR, and so (without this code) it will not issue any kind of
28107     warning or error message.
28108
28109     Note - ARM instructions are case-insensitive but the strings in the hash
28110     table are all stored in lower case, so we must first ensure that name is
28111     lower case too.  */
28112  if (flag_warn_syms && arm_ops_hsh)
28113    {
28114      char * nbuf = strdup (name);
28115      char * p;
28116
28117      for (p = nbuf; *p; p++)
28118	*p = TOLOWER (*p);
28119      if (str_hash_find (arm_ops_hsh, nbuf) != NULL)
28120	{
28121	  static htab_t  already_warned = NULL;
28122
28123	  if (already_warned == NULL)
28124	    already_warned = str_htab_create ();
28125	  /* Only warn about the symbol once.  To keep the code
28126	     simple we let str_hash_insert do the lookup for us.  */
28127	  if (str_hash_find (already_warned, nbuf) == NULL)
28128	    {
28129	      as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
28130	      str_hash_insert (already_warned, nbuf, NULL, 0);
28131	    }
28132	}
28133      else
28134	free (nbuf);
28135    }
28136
28137  return false;
28138}
28139
28140/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28141   Otherwise we have no need to default values of symbols.  */
28142
28143symbolS *
28144md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
28145{
28146#ifdef OBJ_ELF
28147  if (name[0] == '_' && name[1] == 'G'
28148      && streq (name, GLOBAL_OFFSET_TABLE_NAME))
28149    {
28150      if (!GOT_symbol)
28151	{
28152	  if (symbol_find (name))
28153	    as_bad (_("GOT already in the symbol table"));
28154
28155	  GOT_symbol = symbol_new (name, undefined_section,
28156				   &zero_address_frag, 0);
28157	}
28158
28159      return GOT_symbol;
28160    }
28161#endif
28162
28163  return NULL;
28164}
28165
28166/* Subroutine of md_apply_fix.	 Check to see if an immediate can be
28167   computed as two separate immediate values, added together.  We
28168   already know that this value cannot be computed by just one ARM
28169   instruction.	 */
28170
28171static unsigned int
28172validate_immediate_twopart (unsigned int   val,
28173			    unsigned int * highpart)
28174{
28175  unsigned int a;
28176  unsigned int i;
28177
28178  for (i = 0; i < 32; i += 2)
28179    if (((a = rotate_left (val, i)) & 0xff) != 0)
28180      {
28181	if (a & 0xff00)
28182	  {
28183	    if (a & ~ 0xffff)
28184	      continue;
28185	    * highpart = (a  >> 8) | ((i + 24) << 7);
28186	  }
28187	else if (a & 0xff0000)
28188	  {
28189	    if (a & 0xff000000)
28190	      continue;
28191	    * highpart = (a >> 16) | ((i + 16) << 7);
28192	  }
28193	else
28194	  {
28195	    gas_assert (a & 0xff000000);
28196	    * highpart = (a >> 24) | ((i + 8) << 7);
28197	  }
28198
28199	return (a & 0xff) | (i << 7);
28200      }
28201
28202  return FAIL;
28203}
28204
28205static int
28206validate_offset_imm (unsigned int val, int hwse)
28207{
28208  if ((hwse && val > 255) || val > 4095)
28209    return FAIL;
28210  return val;
28211}
28212
28213/* Subroutine of md_apply_fix.	 Do those data_ops which can take a
28214   negative immediate constant by altering the instruction.  A bit of
28215   a hack really.
28216	MOV <-> MVN
28217	AND <-> BIC
28218	ADC <-> SBC
28219	by inverting the second operand, and
28220	ADD <-> SUB
28221	CMP <-> CMN
28222	by negating the second operand.	 */
28223
28224static int
28225negate_data_op (unsigned long * instruction,
28226		unsigned long	value)
28227{
28228  int op, new_inst;
28229  unsigned long negated, inverted;
28230
28231  negated = encode_arm_immediate (-value);
28232  inverted = encode_arm_immediate (~value);
28233
28234  op = (*instruction >> DATA_OP_SHIFT) & 0xf;
28235  switch (op)
28236    {
28237      /* First negates.	 */
28238    case OPCODE_SUB:		 /* ADD <-> SUB	 */
28239      new_inst = OPCODE_ADD;
28240      value = negated;
28241      break;
28242
28243    case OPCODE_ADD:
28244      new_inst = OPCODE_SUB;
28245      value = negated;
28246      break;
28247
28248    case OPCODE_CMP:		 /* CMP <-> CMN	 */
28249      new_inst = OPCODE_CMN;
28250      value = negated;
28251      break;
28252
28253    case OPCODE_CMN:
28254      new_inst = OPCODE_CMP;
28255      value = negated;
28256      break;
28257
28258      /* Now Inverted ops.  */
28259    case OPCODE_MOV:		 /* MOV <-> MVN	 */
28260      new_inst = OPCODE_MVN;
28261      value = inverted;
28262      break;
28263
28264    case OPCODE_MVN:
28265      new_inst = OPCODE_MOV;
28266      value = inverted;
28267      break;
28268
28269    case OPCODE_AND:		 /* AND <-> BIC	 */
28270      new_inst = OPCODE_BIC;
28271      value = inverted;
28272      break;
28273
28274    case OPCODE_BIC:
28275      new_inst = OPCODE_AND;
28276      value = inverted;
28277      break;
28278
28279    case OPCODE_ADC:		  /* ADC <-> SBC  */
28280      new_inst = OPCODE_SBC;
28281      value = inverted;
28282      break;
28283
28284    case OPCODE_SBC:
28285      new_inst = OPCODE_ADC;
28286      value = inverted;
28287      break;
28288
28289      /* We cannot do anything.	 */
28290    default:
28291      return FAIL;
28292    }
28293
28294  if (value == (unsigned) FAIL)
28295    return FAIL;
28296
28297  *instruction &= OPCODE_MASK;
28298  *instruction |= new_inst << DATA_OP_SHIFT;
28299  return value;
28300}
28301
28302/* Like negate_data_op, but for Thumb-2.   */
28303
28304static unsigned int
28305thumb32_negate_data_op (valueT *instruction, unsigned int value)
28306{
28307  unsigned int op, new_inst;
28308  unsigned int rd;
28309  unsigned int negated, inverted;
28310
28311  negated = encode_thumb32_immediate (-value);
28312  inverted = encode_thumb32_immediate (~value);
28313
28314  rd = (*instruction >> 8) & 0xf;
28315  op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
28316  switch (op)
28317    {
28318      /* ADD <-> SUB.  Includes CMP <-> CMN.  */
28319    case T2_OPCODE_SUB:
28320      new_inst = T2_OPCODE_ADD;
28321      value = negated;
28322      break;
28323
28324    case T2_OPCODE_ADD:
28325      new_inst = T2_OPCODE_SUB;
28326      value = negated;
28327      break;
28328
28329      /* ORR <-> ORN.  Includes MOV <-> MVN.  */
28330    case T2_OPCODE_ORR:
28331      new_inst = T2_OPCODE_ORN;
28332      value = inverted;
28333      break;
28334
28335    case T2_OPCODE_ORN:
28336      new_inst = T2_OPCODE_ORR;
28337      value = inverted;
28338      break;
28339
28340      /* AND <-> BIC.  TST has no inverted equivalent.  */
28341    case T2_OPCODE_AND:
28342      new_inst = T2_OPCODE_BIC;
28343      if (rd == 15)
28344	value = FAIL;
28345      else
28346	value = inverted;
28347      break;
28348
28349    case T2_OPCODE_BIC:
28350      new_inst = T2_OPCODE_AND;
28351      value = inverted;
28352      break;
28353
28354      /* ADC <-> SBC  */
28355    case T2_OPCODE_ADC:
28356      new_inst = T2_OPCODE_SBC;
28357      value = inverted;
28358      break;
28359
28360    case T2_OPCODE_SBC:
28361      new_inst = T2_OPCODE_ADC;
28362      value = inverted;
28363      break;
28364
28365      /* We cannot do anything.	 */
28366    default:
28367      return FAIL;
28368    }
28369
28370  if (value == (unsigned int)FAIL)
28371    return FAIL;
28372
28373  *instruction &= T2_OPCODE_MASK;
28374  *instruction |= new_inst << T2_DATA_OP_SHIFT;
28375  return value;
28376}
28377
28378/* Read a 32-bit thumb instruction from buf.  */
28379
28380static unsigned long
28381get_thumb32_insn (char * buf)
28382{
28383  unsigned long insn;
28384  insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
28385  insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28386
28387  return insn;
28388}
28389
28390/* We usually want to set the low bit on the address of thumb function
28391   symbols.  In particular .word foo - . should have the low bit set.
28392   Generic code tries to fold the difference of two symbols to
28393   a constant.  Prevent this and force a relocation when the first symbols
28394   is a thumb function.  */
28395
28396bool
28397arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
28398{
28399  if (op == O_subtract
28400      && l->X_op == O_symbol
28401      && r->X_op == O_symbol
28402      && THUMB_IS_FUNC (l->X_add_symbol))
28403    {
28404      l->X_op = O_subtract;
28405      l->X_op_symbol = r->X_add_symbol;
28406      l->X_add_number -= r->X_add_number;
28407      return true;
28408    }
28409
28410  /* Process as normal.  */
28411  return false;
28412}
28413
28414/* Encode Thumb2 unconditional branches and calls. The encoding
28415   for the 2 are identical for the immediate values.  */
28416
28417static void
28418encode_thumb2_b_bl_offset (char * buf, offsetT value)
28419{
28420#define T2I1I2MASK  ((1 << 13) | (1 << 11))
28421  offsetT newval;
28422  offsetT newval2;
28423  addressT S, I1, I2, lo, hi;
28424
28425  S = (value >> 24) & 0x01;
28426  I1 = (value >> 23) & 0x01;
28427  I2 = (value >> 22) & 0x01;
28428  hi = (value >> 12) & 0x3ff;
28429  lo = (value >> 1) & 0x7ff;
28430  newval   = md_chars_to_number (buf, THUMB_SIZE);
28431  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28432  newval  |= (S << 10) | hi;
28433  newval2 &=  ~T2I1I2MASK;
28434  newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
28435  md_number_to_chars (buf, newval, THUMB_SIZE);
28436  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28437}
28438
28439void
28440md_apply_fix (fixS *	fixP,
28441	       valueT * valP,
28442	       segT	seg)
28443{
28444  valueT	 value = * valP;
28445  valueT	 newval;
28446  unsigned int	 newimm;
28447  unsigned long	 temp;
28448  int		 sign;
28449  char *	 buf = fixP->fx_where + fixP->fx_frag->fr_literal;
28450
28451  gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
28452
28453  /* Note whether this will delete the relocation.  */
28454
28455  if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
28456    fixP->fx_done = 1;
28457
28458  /* On a 64-bit host, silently truncate 'value' to 32 bits for
28459     consistency with the behaviour on 32-bit hosts.  Remember value
28460     for emit_reloc.  */
28461  value &= 0xffffffff;
28462  value ^= 0x80000000;
28463  value -= 0x80000000;
28464
28465  *valP = value;
28466  fixP->fx_addnumber = value;
28467
28468  /* Same treatment for fixP->fx_offset.  */
28469  fixP->fx_offset &= 0xffffffff;
28470  fixP->fx_offset ^= 0x80000000;
28471  fixP->fx_offset -= 0x80000000;
28472
28473  switch (fixP->fx_r_type)
28474    {
28475    case BFD_RELOC_NONE:
28476      /* This will need to go in the object file.  */
28477      fixP->fx_done = 0;
28478      break;
28479
28480    case BFD_RELOC_ARM_IMMEDIATE:
28481      /* We claim that this fixup has been processed here,
28482	 even if in fact we generate an error because we do
28483	 not have a reloc for it, so tc_gen_reloc will reject it.  */
28484      fixP->fx_done = 1;
28485
28486      if (fixP->fx_addsy)
28487	{
28488	  const char *msg = 0;
28489
28490	  if (! S_IS_DEFINED (fixP->fx_addsy))
28491	    msg = _("undefined symbol %s used as an immediate value");
28492	  else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
28493	    msg = _("symbol %s is in a different section");
28494	  else if (S_IS_WEAK (fixP->fx_addsy))
28495	    msg = _("symbol %s is weak and may be overridden later");
28496
28497	  if (msg)
28498	    {
28499	      as_bad_where (fixP->fx_file, fixP->fx_line,
28500			    msg, S_GET_NAME (fixP->fx_addsy));
28501	      break;
28502	    }
28503	}
28504
28505      temp = md_chars_to_number (buf, INSN_SIZE);
28506
28507      /* If the offset is negative, we should use encoding A2 for ADR.  */
28508      if ((temp & 0xfff0000) == 0x28f0000 && (offsetT) value < 0)
28509	newimm = negate_data_op (&temp, value);
28510      else
28511	{
28512	  newimm = encode_arm_immediate (value);
28513
28514	  /* If the instruction will fail, see if we can fix things up by
28515	     changing the opcode.  */
28516	  if (newimm == (unsigned int) FAIL)
28517	    newimm = negate_data_op (&temp, value);
28518	  /* MOV accepts both ARM modified immediate (A1 encoding) and
28519	     UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28520	     When disassembling, MOV is preferred when there is no encoding
28521	     overlap.  */
28522	  if (newimm == (unsigned int) FAIL
28523	      && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
28524	      && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
28525	      && !((temp >> SBIT_SHIFT) & 0x1)
28526	      && value <= 0xffff)
28527	    {
28528	      /* Clear bits[23:20] to change encoding from A1 to A2.  */
28529	      temp &= 0xff0fffff;
28530	      /* Encoding high 4bits imm.  Code below will encode the remaining
28531		 low 12bits.  */
28532	      temp |= (value & 0x0000f000) << 4;
28533	      newimm = value & 0x00000fff;
28534	    }
28535	}
28536
28537      if (newimm == (unsigned int) FAIL)
28538	{
28539	  as_bad_where (fixP->fx_file, fixP->fx_line,
28540			_("invalid constant (%lx) after fixup"),
28541			(unsigned long) value);
28542	  break;
28543	}
28544
28545      newimm |= (temp & 0xfffff000);
28546      md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
28547      break;
28548
28549    case BFD_RELOC_ARM_ADRL_IMMEDIATE:
28550      {
28551	unsigned int highpart = 0;
28552	unsigned int newinsn  = 0xe1a00000; /* nop.  */
28553
28554	if (fixP->fx_addsy)
28555	  {
28556	    const char *msg = 0;
28557
28558	    if (! S_IS_DEFINED (fixP->fx_addsy))
28559	      msg = _("undefined symbol %s used as an immediate value");
28560	    else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
28561	      msg = _("symbol %s is in a different section");
28562	    else if (S_IS_WEAK (fixP->fx_addsy))
28563	      msg = _("symbol %s is weak and may be overridden later");
28564
28565	    if (msg)
28566	      {
28567		as_bad_where (fixP->fx_file, fixP->fx_line,
28568			      msg, S_GET_NAME (fixP->fx_addsy));
28569		break;
28570	      }
28571	  }
28572
28573	newimm = encode_arm_immediate (value);
28574	temp = md_chars_to_number (buf, INSN_SIZE);
28575
28576	/* If the instruction will fail, see if we can fix things up by
28577	   changing the opcode.	 */
28578	if (newimm == (unsigned int) FAIL
28579	    && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
28580	  {
28581	    /* No ?  OK - try using two ADD instructions to generate
28582	       the value.  */
28583	    newimm = validate_immediate_twopart (value, & highpart);
28584
28585	    /* Yes - then make sure that the second instruction is
28586	       also an add.  */
28587	    if (newimm != (unsigned int) FAIL)
28588	      newinsn = temp;
28589	    /* Still No ?  Try using a negated value.  */
28590	    else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
28591	      temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
28592	    /* Otherwise - give up.  */
28593	    else
28594	      {
28595		as_bad_where (fixP->fx_file, fixP->fx_line,
28596			      _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28597			      (long) value);
28598		break;
28599	      }
28600
28601	    /* Replace the first operand in the 2nd instruction (which
28602	       is the PC) with the destination register.  We have
28603	       already added in the PC in the first instruction and we
28604	       do not want to do it again.  */
28605	    newinsn &= ~ 0xf0000;
28606	    newinsn |= ((newinsn & 0x0f000) << 4);
28607	  }
28608
28609	newimm |= (temp & 0xfffff000);
28610	md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
28611
28612	highpart |= (newinsn & 0xfffff000);
28613	md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
28614      }
28615      break;
28616
28617    case BFD_RELOC_ARM_OFFSET_IMM:
28618      if (!fixP->fx_done && seg->use_rela_p)
28619	value = 0;
28620      /* Fall through.  */
28621
28622    case BFD_RELOC_ARM_LITERAL:
28623      sign = (offsetT) value > 0;
28624
28625      if ((offsetT) value < 0)
28626	value = - value;
28627
28628      if (validate_offset_imm (value, 0) == FAIL)
28629	{
28630	  if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
28631	    as_bad_where (fixP->fx_file, fixP->fx_line,
28632			  _("invalid literal constant: pool needs to be closer"));
28633	  else
28634	    as_bad_where (fixP->fx_file, fixP->fx_line,
28635			  _("bad immediate value for offset (%ld)"),
28636			  (long) value);
28637	  break;
28638	}
28639
28640      newval = md_chars_to_number (buf, INSN_SIZE);
28641      if (value == 0)
28642	newval &= 0xfffff000;
28643      else
28644	{
28645	  newval &= 0xff7ff000;
28646	  newval |= value | (sign ? INDEX_UP : 0);
28647	}
28648      md_number_to_chars (buf, newval, INSN_SIZE);
28649      break;
28650
28651    case BFD_RELOC_ARM_OFFSET_IMM8:
28652    case BFD_RELOC_ARM_HWLITERAL:
28653      sign = (offsetT) value > 0;
28654
28655      if ((offsetT) value < 0)
28656	value = - value;
28657
28658      if (validate_offset_imm (value, 1) == FAIL)
28659	{
28660	  if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
28661	    as_bad_where (fixP->fx_file, fixP->fx_line,
28662			  _("invalid literal constant: pool needs to be closer"));
28663	  else
28664	    as_bad_where (fixP->fx_file, fixP->fx_line,
28665			  _("bad immediate value for 8-bit offset (%ld)"),
28666			  (long) value);
28667	  break;
28668	}
28669
28670      newval = md_chars_to_number (buf, INSN_SIZE);
28671      if (value == 0)
28672	newval &= 0xfffff0f0;
28673      else
28674	{
28675	  newval &= 0xff7ff0f0;
28676	  newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
28677	}
28678      md_number_to_chars (buf, newval, INSN_SIZE);
28679      break;
28680
28681    case BFD_RELOC_ARM_T32_OFFSET_U8:
28682      if (value > 1020 || value % 4 != 0)
28683	as_bad_where (fixP->fx_file, fixP->fx_line,
28684		      _("bad immediate value for offset (%ld)"), (long) value);
28685      value /= 4;
28686
28687      newval = md_chars_to_number (buf+2, THUMB_SIZE);
28688      newval |= value;
28689      md_number_to_chars (buf+2, newval, THUMB_SIZE);
28690      break;
28691
28692    case BFD_RELOC_ARM_T32_OFFSET_IMM:
28693      /* This is a complicated relocation used for all varieties of Thumb32
28694	 load/store instruction with immediate offset:
28695
28696	 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28697						   *4, optional writeback(W)
28698						   (doubleword load/store)
28699
28700	 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28701	 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28702	 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28703	 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28704	 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28705
28706	 Uppercase letters indicate bits that are already encoded at
28707	 this point.  Lowercase letters are our problem.  For the
28708	 second block of instructions, the secondary opcode nybble
28709	 (bits 8..11) is present, and bit 23 is zero, even if this is
28710	 a PC-relative operation.  */
28711      newval = md_chars_to_number (buf, THUMB_SIZE);
28712      newval <<= 16;
28713      newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
28714
28715      if ((newval & 0xf0000000) == 0xe0000000)
28716	{
28717	  /* Doubleword load/store: 8-bit offset, scaled by 4.  */
28718	  if ((offsetT) value >= 0)
28719	    newval |= (1 << 23);
28720	  else
28721	    value = -value;
28722	  if (value % 4 != 0)
28723	    {
28724	      as_bad_where (fixP->fx_file, fixP->fx_line,
28725			    _("offset not a multiple of 4"));
28726	      break;
28727	    }
28728	  value /= 4;
28729	  if (value > 0xff)
28730	    {
28731	      as_bad_where (fixP->fx_file, fixP->fx_line,
28732			    _("offset out of range"));
28733	      break;
28734	    }
28735	  newval &= ~0xff;
28736	}
28737      else if ((newval & 0x000f0000) == 0x000f0000)
28738	{
28739	  /* PC-relative, 12-bit offset.  */
28740	  if ((offsetT) value >= 0)
28741	    newval |= (1 << 23);
28742	  else
28743	    value = -value;
28744	  if (value > 0xfff)
28745	    {
28746	      as_bad_where (fixP->fx_file, fixP->fx_line,
28747			    _("offset out of range"));
28748	      break;
28749	    }
28750	  newval &= ~0xfff;
28751	}
28752      else if ((newval & 0x00000100) == 0x00000100)
28753	{
28754	  /* Writeback: 8-bit, +/- offset.  */
28755	  if ((offsetT) value >= 0)
28756	    newval |= (1 << 9);
28757	  else
28758	    value = -value;
28759	  if (value > 0xff)
28760	    {
28761	      as_bad_where (fixP->fx_file, fixP->fx_line,
28762			    _("offset out of range"));
28763	      break;
28764	    }
28765	  newval &= ~0xff;
28766	}
28767      else if ((newval & 0x00000f00) == 0x00000e00)
28768	{
28769	  /* T-instruction: positive 8-bit offset.  */
28770	  if (value > 0xff)
28771	    {
28772	      as_bad_where (fixP->fx_file, fixP->fx_line,
28773			    _("offset out of range"));
28774	      break;
28775	    }
28776	  newval &= ~0xff;
28777	  newval |= value;
28778	}
28779      else
28780	{
28781	  /* Positive 12-bit or negative 8-bit offset.  */
28782	  unsigned int limit;
28783	  if ((offsetT) value >= 0)
28784	    {
28785	      newval |= (1 << 23);
28786	      limit = 0xfff;
28787	    }
28788	  else
28789	    {
28790	      value = -value;
28791	      limit = 0xff;
28792	    }
28793	  if (value > limit)
28794	    {
28795	      as_bad_where (fixP->fx_file, fixP->fx_line,
28796			    _("offset out of range"));
28797	      break;
28798	    }
28799	  newval &= ~limit;
28800	}
28801
28802      newval |= value;
28803      md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
28804      md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
28805      break;
28806
28807    case BFD_RELOC_ARM_SHIFT_IMM:
28808      newval = md_chars_to_number (buf, INSN_SIZE);
28809      if (value > 32
28810	  || (value == 32
28811	      && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
28812	{
28813	  as_bad_where (fixP->fx_file, fixP->fx_line,
28814			_("shift expression is too large"));
28815	  break;
28816	}
28817
28818      if (value == 0)
28819	/* Shifts of zero must be done as lsl.	*/
28820	newval &= ~0x60;
28821      else if (value == 32)
28822	value = 0;
28823      newval &= 0xfffff07f;
28824      newval |= (value & 0x1f) << 7;
28825      md_number_to_chars (buf, newval, INSN_SIZE);
28826      break;
28827
28828    case BFD_RELOC_ARM_T32_IMMEDIATE:
28829    case BFD_RELOC_ARM_T32_ADD_IMM:
28830    case BFD_RELOC_ARM_T32_IMM12:
28831    case BFD_RELOC_ARM_T32_ADD_PC12:
28832      /* We claim that this fixup has been processed here,
28833	 even if in fact we generate an error because we do
28834	 not have a reloc for it, so tc_gen_reloc will reject it.  */
28835      fixP->fx_done = 1;
28836
28837      if (fixP->fx_addsy
28838	  && ! S_IS_DEFINED (fixP->fx_addsy))
28839	{
28840	  as_bad_where (fixP->fx_file, fixP->fx_line,
28841			_("undefined symbol %s used as an immediate value"),
28842			S_GET_NAME (fixP->fx_addsy));
28843	  break;
28844	}
28845
28846      newval = md_chars_to_number (buf, THUMB_SIZE);
28847      newval <<= 16;
28848      newval |= md_chars_to_number (buf+2, THUMB_SIZE);
28849
28850      newimm = FAIL;
28851      if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
28852	   /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28853	      Thumb2 modified immediate encoding (T2).  */
28854	   && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
28855	  || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
28856	{
28857	  newimm = encode_thumb32_immediate (value);
28858	  if (newimm == (unsigned int) FAIL)
28859	    newimm = thumb32_negate_data_op (&newval, value);
28860	}
28861      if (newimm == (unsigned int) FAIL)
28862	{
28863	  if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
28864	    {
28865	      /* Turn add/sum into addw/subw.  */
28866	      if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
28867		newval = (newval & 0xfeffffff) | 0x02000000;
28868	      /* No flat 12-bit imm encoding for addsw/subsw.  */
28869	      if ((newval & 0x00100000) == 0)
28870		{
28871		  /* 12 bit immediate for addw/subw.  */
28872		  if ((offsetT) value < 0)
28873		    {
28874		      value = -value;
28875		      newval ^= 0x00a00000;
28876		    }
28877		  if (value > 0xfff)
28878		    newimm = (unsigned int) FAIL;
28879		  else
28880		    newimm = value;
28881		}
28882	    }
28883	  else
28884	    {
28885	      /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28886		 UINT16 (T3 encoding), MOVW only accepts UINT16.  When
28887		 disassembling, MOV is preferred when there is no encoding
28888		 overlap.  */
28889	      if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
28890		  /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28891		     but with the Rn field [19:16] set to 1111.  */
28892		  && (((newval >> 16) & 0xf) == 0xf)
28893		  && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
28894		  && !((newval >> T2_SBIT_SHIFT) & 0x1)
28895		  && value <= 0xffff)
28896		{
28897		  /* Toggle bit[25] to change encoding from T2 to T3.  */
28898		  newval ^= 1 << 25;
28899		  /* Clear bits[19:16].  */
28900		  newval &= 0xfff0ffff;
28901		  /* Encoding high 4bits imm.  Code below will encode the
28902		     remaining low 12bits.  */
28903		  newval |= (value & 0x0000f000) << 4;
28904		  newimm = value & 0x00000fff;
28905		}
28906	    }
28907	}
28908
28909      if (newimm == (unsigned int)FAIL)
28910	{
28911	  as_bad_where (fixP->fx_file, fixP->fx_line,
28912			_("invalid constant (%lx) after fixup"),
28913			(unsigned long) value);
28914	  break;
28915	}
28916
28917      newval |= (newimm & 0x800) << 15;
28918      newval |= (newimm & 0x700) << 4;
28919      newval |= (newimm & 0x0ff);
28920
28921      md_number_to_chars (buf,   (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
28922      md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
28923      break;
28924
28925    case BFD_RELOC_ARM_SMC:
28926      if (value > 0xf)
28927	as_bad_where (fixP->fx_file, fixP->fx_line,
28928		      _("invalid smc expression"));
28929
28930      newval = md_chars_to_number (buf, INSN_SIZE);
28931      newval |= (value & 0xf);
28932      md_number_to_chars (buf, newval, INSN_SIZE);
28933      break;
28934
28935    case BFD_RELOC_ARM_HVC:
28936      if (value > 0xffff)
28937	as_bad_where (fixP->fx_file, fixP->fx_line,
28938		      _("invalid hvc expression"));
28939      newval = md_chars_to_number (buf, INSN_SIZE);
28940      newval |= (value & 0xf) | ((value & 0xfff0) << 4);
28941      md_number_to_chars (buf, newval, INSN_SIZE);
28942      break;
28943
28944    case BFD_RELOC_ARM_SWI:
28945      if (fixP->tc_fix_data != 0)
28946	{
28947	  if (value > 0xff)
28948	    as_bad_where (fixP->fx_file, fixP->fx_line,
28949			  _("invalid swi expression"));
28950	  newval = md_chars_to_number (buf, THUMB_SIZE);
28951	  newval |= value;
28952	  md_number_to_chars (buf, newval, THUMB_SIZE);
28953	}
28954      else
28955	{
28956	  if (value > 0x00ffffff)
28957	    as_bad_where (fixP->fx_file, fixP->fx_line,
28958			  _("invalid swi expression"));
28959	  newval = md_chars_to_number (buf, INSN_SIZE);
28960	  newval |= value;
28961	  md_number_to_chars (buf, newval, INSN_SIZE);
28962	}
28963      break;
28964
28965    case BFD_RELOC_ARM_MULTI:
28966      if (value > 0xffff)
28967	as_bad_where (fixP->fx_file, fixP->fx_line,
28968		      _("invalid expression in load/store multiple"));
28969      newval = value | md_chars_to_number (buf, INSN_SIZE);
28970      md_number_to_chars (buf, newval, INSN_SIZE);
28971      break;
28972
28973#ifdef OBJ_ELF
28974    case BFD_RELOC_ARM_PCREL_CALL:
28975
28976      if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
28977	  && fixP->fx_addsy
28978	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
28979	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28980	  && THUMB_IS_FUNC (fixP->fx_addsy))
28981	/* Flip the bl to blx. This is a simple flip
28982	   bit here because we generate PCREL_CALL for
28983	   unconditional bls.  */
28984	{
28985	  newval = md_chars_to_number (buf, INSN_SIZE);
28986	  newval = newval | 0x10000000;
28987	  md_number_to_chars (buf, newval, INSN_SIZE);
28988	  temp = 1;
28989	  fixP->fx_done = 1;
28990	}
28991      else
28992	temp = 3;
28993      goto arm_branch_common;
28994
28995    case BFD_RELOC_ARM_PCREL_JUMP:
28996      if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
28997	  && fixP->fx_addsy
28998	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
28999	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29000	  && THUMB_IS_FUNC (fixP->fx_addsy))
29001	{
29002	  /* This would map to a bl<cond>, b<cond>,
29003	     b<always> to a Thumb function. We
29004	     need to force a relocation for this particular
29005	     case.  */
29006	  newval = md_chars_to_number (buf, INSN_SIZE);
29007	  fixP->fx_done = 0;
29008	}
29009      /* Fall through.  */
29010
29011    case BFD_RELOC_ARM_PLT32:
29012#endif
29013    case BFD_RELOC_ARM_PCREL_BRANCH:
29014      temp = 3;
29015      goto arm_branch_common;
29016
29017    case BFD_RELOC_ARM_PCREL_BLX:
29018
29019      temp = 1;
29020      if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
29021	  && fixP->fx_addsy
29022	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
29023	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29024	  && ARM_IS_FUNC (fixP->fx_addsy))
29025	{
29026	  /* Flip the blx to a bl and warn.  */
29027	  const char *name = S_GET_NAME (fixP->fx_addsy);
29028	  newval = 0xeb000000;
29029	  as_warn_where (fixP->fx_file, fixP->fx_line,
29030			 _("blx to '%s' an ARM ISA state function changed to bl"),
29031			  name);
29032	  md_number_to_chars (buf, newval, INSN_SIZE);
29033	  temp = 3;
29034	  fixP->fx_done = 1;
29035	}
29036
29037#ifdef OBJ_ELF
29038       if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
29039	 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
29040#endif
29041
29042    arm_branch_common:
29043      /* We are going to store value (shifted right by two) in the
29044	 instruction, in a 24 bit, signed field.  Bits 26 through 32 either
29045	 all clear or all set and bit 0 must be clear.  For B/BL bit 1 must
29046	 also be clear.  */
29047      if (value & temp)
29048	as_bad_where (fixP->fx_file, fixP->fx_line,
29049		      _("misaligned branch destination"));
29050      if ((value & 0xfe000000) != 0
29051	  && (value & 0xfe000000) != 0xfe000000)
29052	as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
29053
29054      if (fixP->fx_done || !seg->use_rela_p)
29055	{
29056	  newval = md_chars_to_number (buf, INSN_SIZE);
29057	  newval |= (value >> 2) & 0x00ffffff;
29058	  /* Set the H bit on BLX instructions.  */
29059	  if (temp == 1)
29060	    {
29061	      if (value & 2)
29062		newval |= 0x01000000;
29063	      else
29064		newval &= ~0x01000000;
29065	    }
29066	  md_number_to_chars (buf, newval, INSN_SIZE);
29067	}
29068      break;
29069
29070    case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
29071      /* CBZ can only branch forward.  */
29072
29073      /* Attempts to use CBZ to branch to the next instruction
29074	 (which, strictly speaking, are prohibited) will be turned into
29075	 no-ops.
29076
29077	 FIXME: It may be better to remove the instruction completely and
29078	 perform relaxation.  */
29079      if ((offsetT) value == -2)
29080	{
29081	  newval = md_chars_to_number (buf, THUMB_SIZE);
29082	  newval = 0xbf00; /* NOP encoding T1 */
29083	  md_number_to_chars (buf, newval, THUMB_SIZE);
29084	}
29085      else
29086	{
29087	  if (value & ~0x7e)
29088	    as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
29089
29090	  if (fixP->fx_done || !seg->use_rela_p)
29091	    {
29092	      newval = md_chars_to_number (buf, THUMB_SIZE);
29093	      newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
29094	      md_number_to_chars (buf, newval, THUMB_SIZE);
29095	    }
29096	}
29097      break;
29098
29099    case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch.	*/
29100      if (out_of_range_p (value, 8))
29101	as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
29102
29103      if (fixP->fx_done || !seg->use_rela_p)
29104	{
29105	  newval = md_chars_to_number (buf, THUMB_SIZE);
29106	  newval |= (value & 0x1ff) >> 1;
29107	  md_number_to_chars (buf, newval, THUMB_SIZE);
29108	}
29109      break;
29110
29111    case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch.  */
29112      if (out_of_range_p (value, 11))
29113	as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
29114
29115      if (fixP->fx_done || !seg->use_rela_p)
29116	{
29117	  newval = md_chars_to_number (buf, THUMB_SIZE);
29118	  newval |= (value & 0xfff) >> 1;
29119	  md_number_to_chars (buf, newval, THUMB_SIZE);
29120	}
29121      break;
29122
29123    /* This relocation is misnamed, it should be BRANCH21.  */
29124    case BFD_RELOC_THUMB_PCREL_BRANCH20:
29125      if (fixP->fx_addsy
29126	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29127	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
29128	  && ARM_IS_FUNC (fixP->fx_addsy)
29129	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
29130	{
29131	  /* Force a relocation for a branch 20 bits wide.  */
29132	  fixP->fx_done = 0;
29133	}
29134      if (out_of_range_p (value, 20))
29135	as_bad_where (fixP->fx_file, fixP->fx_line,
29136		      _("conditional branch out of range"));
29137
29138      if (fixP->fx_done || !seg->use_rela_p)
29139	{
29140	  offsetT newval2;
29141	  addressT S, J1, J2, lo, hi;
29142
29143	  S  = (value & 0x00100000) >> 20;
29144	  J2 = (value & 0x00080000) >> 19;
29145	  J1 = (value & 0x00040000) >> 18;
29146	  hi = (value & 0x0003f000) >> 12;
29147	  lo = (value & 0x00000ffe) >> 1;
29148
29149	  newval   = md_chars_to_number (buf, THUMB_SIZE);
29150	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29151	  newval  |= (S << 10) | hi;
29152	  newval2 |= (J1 << 13) | (J2 << 11) | lo;
29153	  md_number_to_chars (buf, newval, THUMB_SIZE);
29154	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29155	}
29156      break;
29157
29158    case BFD_RELOC_THUMB_PCREL_BLX:
29159      /* If there is a blx from a thumb state function to
29160	 another thumb function flip this to a bl and warn
29161	 about it.  */
29162
29163      if (fixP->fx_addsy
29164	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
29165	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29166	  && THUMB_IS_FUNC (fixP->fx_addsy))
29167	{
29168	  const char *name = S_GET_NAME (fixP->fx_addsy);
29169	  as_warn_where (fixP->fx_file, fixP->fx_line,
29170			 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29171			 name);
29172	  newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29173	  newval = newval | 0x1000;
29174	  md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
29175	  fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
29176	  fixP->fx_done = 1;
29177	}
29178
29179
29180      goto thumb_bl_common;
29181
29182    case BFD_RELOC_THUMB_PCREL_BRANCH23:
29183      /* A bl from Thumb state ISA to an internal ARM state function
29184	 is converted to a blx.  */
29185      if (fixP->fx_addsy
29186	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29187	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
29188	  && ARM_IS_FUNC (fixP->fx_addsy)
29189	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
29190	{
29191	  newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29192	  newval = newval & ~0x1000;
29193	  md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
29194	  fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
29195	  fixP->fx_done = 1;
29196	}
29197
29198    thumb_bl_common:
29199
29200      if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
29201	/* For a BLX instruction, make sure that the relocation is rounded up
29202	   to a word boundary.  This follows the semantics of the instruction
29203	   which specifies that bit 1 of the target address will come from bit
29204	   1 of the base address.  */
29205	value = (value + 3) & ~ 3;
29206
29207#ifdef OBJ_ELF
29208       if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
29209	   && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
29210	 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
29211#endif
29212
29213      if (out_of_range_p (value, 22))
29214	{
29215	  if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
29216	    as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
29217	  else if (out_of_range_p (value, 24))
29218	    as_bad_where (fixP->fx_file, fixP->fx_line,
29219			  _("Thumb2 branch out of range"));
29220	}
29221
29222      if (fixP->fx_done || !seg->use_rela_p)
29223	encode_thumb2_b_bl_offset (buf, value);
29224
29225      break;
29226
29227    case BFD_RELOC_THUMB_PCREL_BRANCH25:
29228      if (out_of_range_p (value, 24))
29229	as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
29230
29231      if (fixP->fx_done || !seg->use_rela_p)
29232	  encode_thumb2_b_bl_offset (buf, value);
29233
29234      break;
29235
29236    case BFD_RELOC_8:
29237      if (fixP->fx_done || !seg->use_rela_p)
29238	*buf = value;
29239      break;
29240
29241    case BFD_RELOC_16:
29242      if (fixP->fx_done || !seg->use_rela_p)
29243	md_number_to_chars (buf, value, 2);
29244      break;
29245
29246#ifdef OBJ_ELF
29247    case BFD_RELOC_ARM_TLS_CALL:
29248    case BFD_RELOC_ARM_THM_TLS_CALL:
29249    case BFD_RELOC_ARM_TLS_DESCSEQ:
29250    case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
29251    case BFD_RELOC_ARM_TLS_GOTDESC:
29252    case BFD_RELOC_ARM_TLS_GD32:
29253    case BFD_RELOC_ARM_TLS_LE32:
29254    case BFD_RELOC_ARM_TLS_IE32:
29255    case BFD_RELOC_ARM_TLS_LDM32:
29256    case BFD_RELOC_ARM_TLS_LDO32:
29257      S_SET_THREAD_LOCAL (fixP->fx_addsy);
29258      break;
29259
29260      /* Same handling as above, but with the arm_fdpic guard.  */
29261    case BFD_RELOC_ARM_TLS_GD32_FDPIC:
29262    case BFD_RELOC_ARM_TLS_IE32_FDPIC:
29263    case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
29264      if (arm_fdpic)
29265	{
29266	  S_SET_THREAD_LOCAL (fixP->fx_addsy);
29267	}
29268      else
29269	{
29270	  as_bad_where (fixP->fx_file, fixP->fx_line,
29271			_("Relocation supported only in FDPIC mode"));
29272	}
29273      break;
29274
29275    case BFD_RELOC_ARM_GOT32:
29276    case BFD_RELOC_ARM_GOTOFF:
29277      break;
29278
29279    case BFD_RELOC_ARM_GOT_PREL:
29280      if (fixP->fx_done || !seg->use_rela_p)
29281	md_number_to_chars (buf, value, 4);
29282      break;
29283
29284    case BFD_RELOC_ARM_TARGET2:
29285      /* TARGET2 is not partial-inplace, so we need to write the
29286	 addend here for REL targets, because it won't be written out
29287	 during reloc processing later.  */
29288      if (fixP->fx_done || !seg->use_rela_p)
29289	md_number_to_chars (buf, fixP->fx_offset, 4);
29290      break;
29291
29292      /* Relocations for FDPIC.  */
29293    case BFD_RELOC_ARM_GOTFUNCDESC:
29294    case BFD_RELOC_ARM_GOTOFFFUNCDESC:
29295    case BFD_RELOC_ARM_FUNCDESC:
29296      if (arm_fdpic)
29297	{
29298	  if (fixP->fx_done || !seg->use_rela_p)
29299	    md_number_to_chars (buf, 0, 4);
29300	}
29301      else
29302	{
29303	  as_bad_where (fixP->fx_file, fixP->fx_line,
29304			_("Relocation supported only in FDPIC mode"));
29305      }
29306      break;
29307#endif
29308
29309    case BFD_RELOC_RVA:
29310    case BFD_RELOC_32:
29311    case BFD_RELOC_ARM_TARGET1:
29312    case BFD_RELOC_ARM_ROSEGREL32:
29313    case BFD_RELOC_ARM_SBREL32:
29314    case BFD_RELOC_32_PCREL:
29315#ifdef TE_PE
29316    case BFD_RELOC_32_SECREL:
29317#endif
29318      if (fixP->fx_done || !seg->use_rela_p)
29319#ifdef TE_WINCE
29320	/* For WinCE we only do this for pcrel fixups.  */
29321	if (fixP->fx_done || fixP->fx_pcrel)
29322#endif
29323	  md_number_to_chars (buf, value, 4);
29324      break;
29325
29326#ifdef OBJ_ELF
29327    case BFD_RELOC_ARM_PREL31:
29328      if (fixP->fx_done || !seg->use_rela_p)
29329	{
29330	  newval = md_chars_to_number (buf, 4) & 0x80000000;
29331	  if ((value ^ (value >> 1)) & 0x40000000)
29332	    {
29333	      as_bad_where (fixP->fx_file, fixP->fx_line,
29334			    _("rel31 relocation overflow"));
29335	    }
29336	  newval |= value & 0x7fffffff;
29337	  md_number_to_chars (buf, newval, 4);
29338	}
29339      break;
29340#endif
29341
29342    case BFD_RELOC_ARM_CP_OFF_IMM:
29343    case BFD_RELOC_ARM_T32_CP_OFF_IMM:
29344    case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
29345      if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
29346	newval = md_chars_to_number (buf, INSN_SIZE);
29347      else
29348	newval = get_thumb32_insn (buf);
29349      if ((newval & 0x0f200f00) == 0x0d000900)
29350	{
29351	  /* This is a fp16 vstr/vldr.  The immediate offset in the mnemonic
29352	     has permitted values that are multiples of 2, in the range -510
29353	     to 510.  */
29354	  if (value + 510 > 510 + 510 || (value & 1))
29355	    as_bad_where (fixP->fx_file, fixP->fx_line,
29356			  _("co-processor offset out of range"));
29357	}
29358      else if ((newval & 0xfe001f80) == 0xec000f80)
29359	{
29360	  if (value + 511 > 512 + 511 || (value & 3))
29361	    as_bad_where (fixP->fx_file, fixP->fx_line,
29362			  _("co-processor offset out of range"));
29363	}
29364      else if (value + 1023 > 1023 + 1023 || (value & 3))
29365	as_bad_where (fixP->fx_file, fixP->fx_line,
29366		      _("co-processor offset out of range"));
29367    cp_off_common:
29368      sign = (offsetT) value > 0;
29369      if ((offsetT) value < 0)
29370	value = -value;
29371      if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29372	  || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
29373	newval = md_chars_to_number (buf, INSN_SIZE);
29374      else
29375	newval = get_thumb32_insn (buf);
29376      if (value == 0)
29377	{
29378	  if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
29379	    newval &= 0xffffff80;
29380	  else
29381	    newval &= 0xffffff00;
29382	}
29383      else
29384	{
29385	  if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
29386	    newval &= 0xff7fff80;
29387	  else
29388	    newval &= 0xff7fff00;
29389	  if ((newval & 0x0f200f00) == 0x0d000900)
29390	    {
29391	      /* This is a fp16 vstr/vldr.
29392
29393		 It requires the immediate offset in the instruction is shifted
29394		 left by 1 to be a half-word offset.
29395
29396		 Here, left shift by 1 first, and later right shift by 2
29397		 should get the right offset.  */
29398	      value <<= 1;
29399	    }
29400	  newval |= (value >> 2) | (sign ? INDEX_UP : 0);
29401	}
29402      if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29403	  || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
29404	md_number_to_chars (buf, newval, INSN_SIZE);
29405      else
29406	put_thumb32_insn (buf, newval);
29407      break;
29408
29409    case BFD_RELOC_ARM_CP_OFF_IMM_S2:
29410    case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
29411      if (value + 255 > 255 + 255)
29412	as_bad_where (fixP->fx_file, fixP->fx_line,
29413		      _("co-processor offset out of range"));
29414      value *= 4;
29415      goto cp_off_common;
29416
29417    case BFD_RELOC_ARM_THUMB_OFFSET:
29418      newval = md_chars_to_number (buf, THUMB_SIZE);
29419      /* Exactly what ranges, and where the offset is inserted depends
29420	 on the type of instruction, we can establish this from the
29421	 top 4 bits.  */
29422      switch (newval >> 12)
29423	{
29424	case 4: /* PC load.  */
29425	  /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29426	     forced to zero for these loads; md_pcrel_from has already
29427	     compensated for this.  */
29428	  if (value & 3)
29429	    as_bad_where (fixP->fx_file, fixP->fx_line,
29430			  _("invalid offset, target not word aligned (0x%08lX)"),
29431			  (((unsigned long) fixP->fx_frag->fr_address
29432			    + (unsigned long) fixP->fx_where) & ~3)
29433			  + (unsigned long) value);
29434	  else if (get_recorded_alignment (seg) < 2)
29435	    as_warn_where (fixP->fx_file, fixP->fx_line,
29436			   _("section does not have enough alignment to ensure safe PC-relative loads"));
29437
29438	  if (value & ~0x3fc)
29439	    as_bad_where (fixP->fx_file, fixP->fx_line,
29440			  _("invalid offset, value too big (0x%08lX)"),
29441			  (long) value);
29442
29443	  newval |= value >> 2;
29444	  break;
29445
29446	case 9: /* SP load/store.  */
29447	  if (value & ~0x3fc)
29448	    as_bad_where (fixP->fx_file, fixP->fx_line,
29449			  _("invalid offset, value too big (0x%08lX)"),
29450			  (long) value);
29451	  newval |= value >> 2;
29452	  break;
29453
29454	case 6: /* Word load/store.  */
29455	  if (value & ~0x7c)
29456	    as_bad_where (fixP->fx_file, fixP->fx_line,
29457			  _("invalid offset, value too big (0x%08lX)"),
29458			  (long) value);
29459	  newval |= value << 4; /* 6 - 2.  */
29460	  break;
29461
29462	case 7: /* Byte load/store.  */
29463	  if (value & ~0x1f)
29464	    as_bad_where (fixP->fx_file, fixP->fx_line,
29465			  _("invalid offset, value too big (0x%08lX)"),
29466			  (long) value);
29467	  newval |= value << 6;
29468	  break;
29469
29470	case 8: /* Halfword load/store.	 */
29471	  if (value & ~0x3e)
29472	    as_bad_where (fixP->fx_file, fixP->fx_line,
29473			  _("invalid offset, value too big (0x%08lX)"),
29474			  (long) value);
29475	  newval |= value << 5; /* 6 - 1.  */
29476	  break;
29477
29478	default:
29479	  as_bad_where (fixP->fx_file, fixP->fx_line,
29480			"Unable to process relocation for thumb opcode: %lx",
29481			(unsigned long) newval);
29482	  break;
29483	}
29484      md_number_to_chars (buf, newval, THUMB_SIZE);
29485      break;
29486
29487    case BFD_RELOC_ARM_THUMB_ADD:
29488      /* This is a complicated relocation, since we use it for all of
29489	 the following immediate relocations:
29490
29491	    3bit ADD/SUB
29492	    8bit ADD/SUB
29493	    9bit ADD/SUB SP word-aligned
29494	   10bit ADD PC/SP word-aligned
29495
29496	 The type of instruction being processed is encoded in the
29497	 instruction field:
29498
29499	   0x8000  SUB
29500	   0x00F0  Rd
29501	   0x000F  Rs
29502      */
29503      newval = md_chars_to_number (buf, THUMB_SIZE);
29504      {
29505	int rd = (newval >> 4) & 0xf;
29506	int rs = newval & 0xf;
29507	int subtract = !!(newval & 0x8000);
29508
29509	/* Check for HI regs, only very restricted cases allowed:
29510	   Adjusting SP, and using PC or SP to get an address.	*/
29511	if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
29512	    || (rs > 7 && rs != REG_SP && rs != REG_PC))
29513	  as_bad_where (fixP->fx_file, fixP->fx_line,
29514			_("invalid Hi register with immediate"));
29515
29516	/* If value is negative, choose the opposite instruction.  */
29517	if ((offsetT) value < 0)
29518	  {
29519	    value = -value;
29520	    subtract = !subtract;
29521	    if ((offsetT) value < 0)
29522	      as_bad_where (fixP->fx_file, fixP->fx_line,
29523			    _("immediate value out of range"));
29524	  }
29525
29526	if (rd == REG_SP)
29527	  {
29528 	    if (value & ~0x1fc)
29529	      as_bad_where (fixP->fx_file, fixP->fx_line,
29530			    _("invalid immediate for stack address calculation"));
29531	    newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
29532	    newval |= value >> 2;
29533	  }
29534	else if (rs == REG_PC || rs == REG_SP)
29535	  {
29536	    /* PR gas/18541.  If the addition is for a defined symbol
29537	       within range of an ADR instruction then accept it.  */
29538	    if (subtract
29539		&& value == 4
29540		&& fixP->fx_addsy != NULL)
29541	      {
29542		subtract = 0;
29543
29544		if (! S_IS_DEFINED (fixP->fx_addsy)
29545		    || S_GET_SEGMENT (fixP->fx_addsy) != seg
29546		    || S_IS_WEAK (fixP->fx_addsy))
29547		  {
29548		    as_bad_where (fixP->fx_file, fixP->fx_line,
29549				  _("address calculation needs a strongly defined nearby symbol"));
29550		  }
29551		else
29552		  {
29553		    offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
29554
29555		    /* Round up to the next 4-byte boundary.  */
29556		    if (v & 3)
29557		      v = (v + 3) & ~ 3;
29558		    else
29559		      v += 4;
29560		    v = S_GET_VALUE (fixP->fx_addsy) - v;
29561
29562		    if (v & ~0x3fc)
29563		      {
29564			as_bad_where (fixP->fx_file, fixP->fx_line,
29565				      _("symbol too far away"));
29566		      }
29567		    else
29568		      {
29569			fixP->fx_done = 1;
29570			value = v;
29571		      }
29572		  }
29573	      }
29574
29575	    if (subtract || value & ~0x3fc)
29576	      as_bad_where (fixP->fx_file, fixP->fx_line,
29577			    _("invalid immediate for address calculation (value = 0x%08lX)"),
29578			    (unsigned long) (subtract ? - value : value));
29579	    newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
29580	    newval |= rd << 8;
29581	    newval |= value >> 2;
29582	  }
29583	else if (rs == rd)
29584	  {
29585	    if (value & ~0xff)
29586	      as_bad_where (fixP->fx_file, fixP->fx_line,
29587			    _("immediate value out of range"));
29588	    newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
29589	    newval |= (rd << 8) | value;
29590	  }
29591	else
29592	  {
29593	    if (value & ~0x7)
29594	      as_bad_where (fixP->fx_file, fixP->fx_line,
29595			    _("immediate value out of range"));
29596	    newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
29597	    newval |= rd | (rs << 3) | (value << 6);
29598	  }
29599      }
29600      md_number_to_chars (buf, newval, THUMB_SIZE);
29601      break;
29602
29603    case BFD_RELOC_ARM_THUMB_IMM:
29604      newval = md_chars_to_number (buf, THUMB_SIZE);
29605      if (value > 255)
29606	as_bad_where (fixP->fx_file, fixP->fx_line,
29607		      _("invalid immediate: %ld is out of range"),
29608		      (long) value);
29609      newval |= value;
29610      md_number_to_chars (buf, newval, THUMB_SIZE);
29611      break;
29612
29613    case BFD_RELOC_ARM_THUMB_SHIFT:
29614      /* 5bit shift value (0..32).  LSL cannot take 32.	 */
29615      newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
29616      temp = newval & 0xf800;
29617      if (value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
29618	as_bad_where (fixP->fx_file, fixP->fx_line,
29619		      _("invalid shift value: %ld"), (long) value);
29620      /* Shifts of zero must be encoded as LSL.	 */
29621      if (value == 0)
29622	newval = (newval & 0x003f) | T_OPCODE_LSL_I;
29623      /* Shifts of 32 are encoded as zero.  */
29624      else if (value == 32)
29625	value = 0;
29626      newval |= value << 6;
29627      md_number_to_chars (buf, newval, THUMB_SIZE);
29628      break;
29629
29630    case BFD_RELOC_VTABLE_INHERIT:
29631    case BFD_RELOC_VTABLE_ENTRY:
29632      fixP->fx_done = 0;
29633      return;
29634
29635    case BFD_RELOC_ARM_MOVW:
29636    case BFD_RELOC_ARM_MOVT:
29637    case BFD_RELOC_ARM_THUMB_MOVW:
29638    case BFD_RELOC_ARM_THUMB_MOVT:
29639      if (fixP->fx_done || !seg->use_rela_p)
29640	{
29641	  /* REL format relocations are limited to a 16-bit addend.  */
29642	  if (!fixP->fx_done)
29643	    {
29644	      if (value + 0x8000 > 0x7fff + 0x8000)
29645		  as_bad_where (fixP->fx_file, fixP->fx_line,
29646				_("offset out of range"));
29647	    }
29648	  else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
29649		   || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
29650	    {
29651	      value >>= 16;
29652	    }
29653
29654	  if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
29655	      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
29656	    {
29657	      newval = get_thumb32_insn (buf);
29658	      newval &= 0xfbf08f00;
29659	      newval |= (value & 0xf000) << 4;
29660	      newval |= (value & 0x0800) << 15;
29661	      newval |= (value & 0x0700) << 4;
29662	      newval |= (value & 0x00ff);
29663	      put_thumb32_insn (buf, newval);
29664	    }
29665	  else
29666	    {
29667	      newval = md_chars_to_number (buf, 4);
29668	      newval &= 0xfff0f000;
29669	      newval |= value & 0x0fff;
29670	      newval |= (value & 0xf000) << 4;
29671	      md_number_to_chars (buf, newval, 4);
29672	    }
29673	}
29674      return;
29675
29676   case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
29677   case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
29678   case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
29679   case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
29680      gas_assert (!fixP->fx_done);
29681      {
29682	bfd_vma insn;
29683	bool is_mov;
29684	bfd_vma encoded_addend = value;
29685
29686	/* Check that addend can be encoded in instruction.  */
29687	if (!seg->use_rela_p && value > 255)
29688	  as_bad_where (fixP->fx_file, fixP->fx_line,
29689			_("the offset 0x%08lX is not representable"),
29690			(unsigned long) encoded_addend);
29691
29692	/* Extract the instruction.  */
29693	insn = md_chars_to_number (buf, THUMB_SIZE);
29694	is_mov = (insn & 0xf800) == 0x2000;
29695
29696	/* Encode insn.  */
29697	if (is_mov)
29698	  {
29699	    if (!seg->use_rela_p)
29700	      insn |= encoded_addend;
29701	  }
29702	else
29703	  {
29704	    int rd, rs;
29705
29706	    /* Extract the instruction.  */
29707	     /* Encoding is the following
29708		0x8000  SUB
29709		0x00F0  Rd
29710		0x000F  Rs
29711	     */
29712	     /* The following conditions must be true :
29713		- ADD
29714		- Rd == Rs
29715		- Rd <= 7
29716	     */
29717	    rd = (insn >> 4) & 0xf;
29718	    rs = insn & 0xf;
29719	    if ((insn & 0x8000) || (rd != rs) || rd > 7)
29720	      as_bad_where (fixP->fx_file, fixP->fx_line,
29721			_("Unable to process relocation for thumb opcode: %lx"),
29722			(unsigned long) insn);
29723
29724	    /* Encode as ADD immediate8 thumb 1 code.  */
29725	    insn = 0x3000 | (rd << 8);
29726
29727	    /* Place the encoded addend into the first 8 bits of the
29728	       instruction.  */
29729	    if (!seg->use_rela_p)
29730	      insn |= encoded_addend;
29731	  }
29732
29733	/* Update the instruction.  */
29734	md_number_to_chars (buf, insn, THUMB_SIZE);
29735      }
29736      break;
29737
29738   case BFD_RELOC_ARM_ALU_PC_G0_NC:
29739   case BFD_RELOC_ARM_ALU_PC_G0:
29740   case BFD_RELOC_ARM_ALU_PC_G1_NC:
29741   case BFD_RELOC_ARM_ALU_PC_G1:
29742   case BFD_RELOC_ARM_ALU_PC_G2:
29743   case BFD_RELOC_ARM_ALU_SB_G0_NC:
29744   case BFD_RELOC_ARM_ALU_SB_G0:
29745   case BFD_RELOC_ARM_ALU_SB_G1_NC:
29746   case BFD_RELOC_ARM_ALU_SB_G1:
29747   case BFD_RELOC_ARM_ALU_SB_G2:
29748     gas_assert (!fixP->fx_done);
29749     if (!seg->use_rela_p)
29750       {
29751	 bfd_vma insn;
29752	 bfd_vma encoded_addend;
29753	 bfd_vma addend_abs = llabs ((offsetT) value);
29754
29755	 /* Check that the absolute value of the addend can be
29756	    expressed as an 8-bit constant plus a rotation.  */
29757	 encoded_addend = encode_arm_immediate (addend_abs);
29758	 if (encoded_addend == (unsigned int) FAIL)
29759	   as_bad_where (fixP->fx_file, fixP->fx_line,
29760			 _("the offset 0x%08lX is not representable"),
29761			 (unsigned long) addend_abs);
29762
29763	 /* Extract the instruction.  */
29764	 insn = md_chars_to_number (buf, INSN_SIZE);
29765
29766	 /* If the addend is positive, use an ADD instruction.
29767	    Otherwise use a SUB.  Take care not to destroy the S bit.  */
29768	 insn &= 0xff1fffff;
29769	 if ((offsetT) value < 0)
29770	   insn |= 1 << 22;
29771	 else
29772	   insn |= 1 << 23;
29773
29774	 /* Place the encoded addend into the first 12 bits of the
29775	    instruction.  */
29776	 insn &= 0xfffff000;
29777	 insn |= encoded_addend;
29778
29779	 /* Update the instruction.  */
29780	 md_number_to_chars (buf, insn, INSN_SIZE);
29781       }
29782     break;
29783
29784    case BFD_RELOC_ARM_LDR_PC_G0:
29785    case BFD_RELOC_ARM_LDR_PC_G1:
29786    case BFD_RELOC_ARM_LDR_PC_G2:
29787    case BFD_RELOC_ARM_LDR_SB_G0:
29788    case BFD_RELOC_ARM_LDR_SB_G1:
29789    case BFD_RELOC_ARM_LDR_SB_G2:
29790      gas_assert (!fixP->fx_done);
29791      if (!seg->use_rela_p)
29792	{
29793	  bfd_vma insn;
29794	  bfd_vma addend_abs = llabs ((offsetT) value);
29795
29796	  /* Check that the absolute value of the addend can be
29797	     encoded in 12 bits.  */
29798	  if (addend_abs >= 0x1000)
29799	    as_bad_where (fixP->fx_file, fixP->fx_line,
29800			  _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29801			  (unsigned long) addend_abs);
29802
29803	  /* Extract the instruction.  */
29804	  insn = md_chars_to_number (buf, INSN_SIZE);
29805
29806	  /* If the addend is negative, clear bit 23 of the instruction.
29807	     Otherwise set it.  */
29808	  if ((offsetT) value < 0)
29809	    insn &= ~(1 << 23);
29810	  else
29811	    insn |= 1 << 23;
29812
29813	  /* Place the absolute value of the addend into the first 12 bits
29814	     of the instruction.  */
29815	  insn &= 0xfffff000;
29816	  insn |= addend_abs;
29817
29818	  /* Update the instruction.  */
29819	  md_number_to_chars (buf, insn, INSN_SIZE);
29820	}
29821      break;
29822
29823    case BFD_RELOC_ARM_LDRS_PC_G0:
29824    case BFD_RELOC_ARM_LDRS_PC_G1:
29825    case BFD_RELOC_ARM_LDRS_PC_G2:
29826    case BFD_RELOC_ARM_LDRS_SB_G0:
29827    case BFD_RELOC_ARM_LDRS_SB_G1:
29828    case BFD_RELOC_ARM_LDRS_SB_G2:
29829      gas_assert (!fixP->fx_done);
29830      if (!seg->use_rela_p)
29831	{
29832	  bfd_vma insn;
29833	  bfd_vma addend_abs = llabs ((offsetT) value);
29834
29835	  /* Check that the absolute value of the addend can be
29836	     encoded in 8 bits.  */
29837	  if (addend_abs >= 0x100)
29838	    as_bad_where (fixP->fx_file, fixP->fx_line,
29839			  _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29840			  (unsigned long) addend_abs);
29841
29842	  /* Extract the instruction.  */
29843	  insn = md_chars_to_number (buf, INSN_SIZE);
29844
29845	  /* If the addend is negative, clear bit 23 of the instruction.
29846	     Otherwise set it.  */
29847	  if ((offsetT) value < 0)
29848	    insn &= ~(1 << 23);
29849	  else
29850	    insn |= 1 << 23;
29851
29852	  /* Place the first four bits of the absolute value of the addend
29853	     into the first 4 bits of the instruction, and the remaining
29854	     four into bits 8 .. 11.  */
29855	  insn &= 0xfffff0f0;
29856	  insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
29857
29858	  /* Update the instruction.  */
29859	  md_number_to_chars (buf, insn, INSN_SIZE);
29860	}
29861      break;
29862
29863    case BFD_RELOC_ARM_LDC_PC_G0:
29864    case BFD_RELOC_ARM_LDC_PC_G1:
29865    case BFD_RELOC_ARM_LDC_PC_G2:
29866    case BFD_RELOC_ARM_LDC_SB_G0:
29867    case BFD_RELOC_ARM_LDC_SB_G1:
29868    case BFD_RELOC_ARM_LDC_SB_G2:
29869      gas_assert (!fixP->fx_done);
29870      if (!seg->use_rela_p)
29871	{
29872	  bfd_vma insn;
29873	  bfd_vma addend_abs = llabs ((offsetT) value);
29874
29875	  /* Check that the absolute value of the addend is a multiple of
29876	     four and, when divided by four, fits in 8 bits.  */
29877	  if (addend_abs & 0x3)
29878	    as_bad_where (fixP->fx_file, fixP->fx_line,
29879			  _("bad offset 0x%08lX (must be word-aligned)"),
29880			  (unsigned long) addend_abs);
29881
29882	  if ((addend_abs >> 2) > 0xff)
29883	    as_bad_where (fixP->fx_file, fixP->fx_line,
29884			  _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29885			  (unsigned long) addend_abs);
29886
29887	  /* Extract the instruction.  */
29888	  insn = md_chars_to_number (buf, INSN_SIZE);
29889
29890	  /* If the addend is negative, clear bit 23 of the instruction.
29891	     Otherwise set it.  */
29892	  if ((offsetT) value < 0)
29893	    insn &= ~(1 << 23);
29894	  else
29895	    insn |= 1 << 23;
29896
29897	  /* Place the addend (divided by four) into the first eight
29898	     bits of the instruction.  */
29899	  insn &= 0xfffffff0;
29900	  insn |= addend_abs >> 2;
29901
29902	  /* Update the instruction.  */
29903	  md_number_to_chars (buf, insn, INSN_SIZE);
29904	}
29905      break;
29906
29907    case BFD_RELOC_THUMB_PCREL_BRANCH5:
29908      if (fixP->fx_addsy
29909	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29910	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
29911	  && ARM_IS_FUNC (fixP->fx_addsy)
29912	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29913	{
29914	  /* Force a relocation for a branch 5 bits wide.  */
29915	  fixP->fx_done = 0;
29916	}
29917      if (v8_1_branch_value_check (value, 5, false) == FAIL)
29918	as_bad_where (fixP->fx_file, fixP->fx_line,
29919		      BAD_BRANCH_OFF);
29920
29921      if (fixP->fx_done || !seg->use_rela_p)
29922	{
29923	  addressT boff = value >> 1;
29924
29925	  newval  = md_chars_to_number (buf, THUMB_SIZE);
29926	  newval |= (boff << 7);
29927	  md_number_to_chars (buf, newval, THUMB_SIZE);
29928	}
29929      break;
29930
29931    case BFD_RELOC_THUMB_PCREL_BFCSEL:
29932      if (fixP->fx_addsy
29933	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29934	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
29935	  && ARM_IS_FUNC (fixP->fx_addsy)
29936	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29937	{
29938	  fixP->fx_done = 0;
29939	}
29940      if ((value & ~0x7f) && ((value & ~0x3f) != (valueT) ~0x3f))
29941	as_bad_where (fixP->fx_file, fixP->fx_line,
29942		      _("branch out of range"));
29943
29944      if (fixP->fx_done || !seg->use_rela_p)
29945	{
29946	  newval  = md_chars_to_number (buf, THUMB_SIZE);
29947
29948	  addressT boff = ((newval & 0x0780) >> 7) << 1;
29949	  addressT diff = value - boff;
29950
29951	  if (diff == 4)
29952	    {
29953	      newval |= 1 << 1; /* T bit.  */
29954	    }
29955	  else if (diff != 2)
29956	    {
29957	      as_bad_where (fixP->fx_file, fixP->fx_line,
29958			    _("out of range label-relative fixup value"));
29959	    }
29960	  md_number_to_chars (buf, newval, THUMB_SIZE);
29961	}
29962      break;
29963
29964    case BFD_RELOC_ARM_THUMB_BF17:
29965      if (fixP->fx_addsy
29966	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29967	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
29968	  && ARM_IS_FUNC (fixP->fx_addsy)
29969	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29970	{
29971	  /* Force a relocation for a branch 17 bits wide.  */
29972	  fixP->fx_done = 0;
29973	}
29974
29975      if (v8_1_branch_value_check (value, 17, true) == FAIL)
29976	as_bad_where (fixP->fx_file, fixP->fx_line,
29977		      BAD_BRANCH_OFF);
29978
29979      if (fixP->fx_done || !seg->use_rela_p)
29980	{
29981	  offsetT newval2;
29982	  addressT immA, immB, immC;
29983
29984	  immA = (value & 0x0001f000) >> 12;
29985	  immB = (value & 0x00000ffc) >> 2;
29986	  immC = (value & 0x00000002) >> 1;
29987
29988	  newval   = md_chars_to_number (buf, THUMB_SIZE);
29989	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29990	  newval  |= immA;
29991	  newval2 |= (immC << 11) | (immB << 1);
29992	  md_number_to_chars (buf, newval, THUMB_SIZE);
29993	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29994	}
29995      break;
29996
29997    case BFD_RELOC_ARM_THUMB_BF19:
29998      if (fixP->fx_addsy
29999	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
30000	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
30001	  && ARM_IS_FUNC (fixP->fx_addsy)
30002	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
30003	{
30004	  /* Force a relocation for a branch 19 bits wide.  */
30005	  fixP->fx_done = 0;
30006	}
30007
30008      if (v8_1_branch_value_check (value, 19, true) == FAIL)
30009	as_bad_where (fixP->fx_file, fixP->fx_line,
30010		      BAD_BRANCH_OFF);
30011
30012      if (fixP->fx_done || !seg->use_rela_p)
30013	{
30014	  offsetT newval2;
30015	  addressT immA, immB, immC;
30016
30017	  immA = (value & 0x0007f000) >> 12;
30018	  immB = (value & 0x00000ffc) >> 2;
30019	  immC = (value & 0x00000002) >> 1;
30020
30021	  newval   = md_chars_to_number (buf, THUMB_SIZE);
30022	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
30023	  newval  |= immA;
30024	  newval2 |= (immC << 11) | (immB << 1);
30025	  md_number_to_chars (buf, newval, THUMB_SIZE);
30026	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
30027	}
30028      break;
30029
30030    case BFD_RELOC_ARM_THUMB_BF13:
30031      if (fixP->fx_addsy
30032	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
30033	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
30034	  && ARM_IS_FUNC (fixP->fx_addsy)
30035	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
30036	{
30037	  /* Force a relocation for a branch 13 bits wide.  */
30038	  fixP->fx_done = 0;
30039	}
30040
30041      if (v8_1_branch_value_check (value, 13, true) == FAIL)
30042	as_bad_where (fixP->fx_file, fixP->fx_line,
30043		      BAD_BRANCH_OFF);
30044
30045      if (fixP->fx_done || !seg->use_rela_p)
30046	{
30047	  offsetT newval2;
30048	  addressT immA, immB, immC;
30049
30050	  immA = (value & 0x00001000) >> 12;
30051	  immB = (value & 0x00000ffc) >> 2;
30052	  immC = (value & 0x00000002) >> 1;
30053
30054	  newval   = md_chars_to_number (buf, THUMB_SIZE);
30055	  newval2  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
30056	  newval  |= immA;
30057	  newval2 |= (immC << 11) | (immB << 1);
30058	  md_number_to_chars (buf, newval, THUMB_SIZE);
30059	  md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
30060	}
30061      break;
30062
30063    case BFD_RELOC_ARM_THUMB_LOOP12:
30064      if (fixP->fx_addsy
30065	  && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
30066	  && !S_FORCE_RELOC (fixP->fx_addsy, true)
30067	  && ARM_IS_FUNC (fixP->fx_addsy)
30068	  && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
30069	{
30070	  /* Force a relocation for a branch 12 bits wide.  */
30071	  fixP->fx_done = 0;
30072	}
30073
30074      bfd_vma insn = get_thumb32_insn (buf);
30075      /* le lr, <label>, le <label> or letp lr, <label> */
30076      if (((insn & 0xffffffff) == 0xf00fc001)
30077	  || ((insn & 0xffffffff) == 0xf02fc001)
30078	  || ((insn & 0xffffffff) == 0xf01fc001))
30079	value = -value;
30080
30081      if (v8_1_branch_value_check (value, 12, false) == FAIL)
30082	as_bad_where (fixP->fx_file, fixP->fx_line,
30083		      BAD_BRANCH_OFF);
30084      if (fixP->fx_done || !seg->use_rela_p)
30085	{
30086	  addressT imml, immh;
30087
30088	  immh = (value & 0x00000ffc) >> 2;
30089	  imml = (value & 0x00000002) >> 1;
30090
30091	  newval  = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
30092	  newval |= (imml << 11) | (immh << 1);
30093	  md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
30094	}
30095      break;
30096
30097    case BFD_RELOC_ARM_V4BX:
30098      /* This will need to go in the object file.  */
30099      fixP->fx_done = 0;
30100      break;
30101
30102    case BFD_RELOC_UNUSED:
30103    default:
30104      as_bad_where (fixP->fx_file, fixP->fx_line,
30105		    _("bad relocation fixup type (%d)"), fixP->fx_r_type);
30106    }
30107}
30108
30109/* Translate internal representation of relocation info to BFD target
30110   format.  */
30111
30112arelent *
30113tc_gen_reloc (asection *section, fixS *fixp)
30114{
30115  arelent * reloc;
30116  bfd_reloc_code_real_type code;
30117
30118  reloc = XNEW (arelent);
30119
30120  reloc->sym_ptr_ptr = XNEW (asymbol *);
30121  *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
30122  reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
30123
30124  if (fixp->fx_pcrel)
30125    {
30126      if (section->use_rela_p)
30127	fixp->fx_offset -= md_pcrel_from_section (fixp, section);
30128      else
30129	fixp->fx_offset = reloc->address;
30130    }
30131  reloc->addend = fixp->fx_offset;
30132
30133  switch (fixp->fx_r_type)
30134    {
30135    case BFD_RELOC_8:
30136      if (fixp->fx_pcrel)
30137	{
30138	  code = BFD_RELOC_8_PCREL;
30139	  break;
30140	}
30141      /* Fall through.  */
30142
30143    case BFD_RELOC_16:
30144      if (fixp->fx_pcrel)
30145	{
30146	  code = BFD_RELOC_16_PCREL;
30147	  break;
30148	}
30149      /* Fall through.  */
30150
30151    case BFD_RELOC_32:
30152      if (fixp->fx_pcrel)
30153	{
30154	  code = BFD_RELOC_32_PCREL;
30155	  break;
30156	}
30157      /* Fall through.  */
30158
30159    case BFD_RELOC_ARM_MOVW:
30160      if (fixp->fx_pcrel)
30161	{
30162	  code = BFD_RELOC_ARM_MOVW_PCREL;
30163	  break;
30164	}
30165      /* Fall through.  */
30166
30167    case BFD_RELOC_ARM_MOVT:
30168      if (fixp->fx_pcrel)
30169	{
30170	  code = BFD_RELOC_ARM_MOVT_PCREL;
30171	  break;
30172	}
30173      /* Fall through.  */
30174
30175    case BFD_RELOC_ARM_THUMB_MOVW:
30176      if (fixp->fx_pcrel)
30177	{
30178	  code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
30179	  break;
30180	}
30181      /* Fall through.  */
30182
30183    case BFD_RELOC_ARM_THUMB_MOVT:
30184      if (fixp->fx_pcrel)
30185	{
30186	  code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
30187	  break;
30188	}
30189      /* Fall through.  */
30190
30191    case BFD_RELOC_NONE:
30192    case BFD_RELOC_ARM_PCREL_BRANCH:
30193    case BFD_RELOC_ARM_PCREL_BLX:
30194    case BFD_RELOC_RVA:
30195    case BFD_RELOC_THUMB_PCREL_BRANCH7:
30196    case BFD_RELOC_THUMB_PCREL_BRANCH9:
30197    case BFD_RELOC_THUMB_PCREL_BRANCH12:
30198    case BFD_RELOC_THUMB_PCREL_BRANCH20:
30199    case BFD_RELOC_THUMB_PCREL_BRANCH23:
30200    case BFD_RELOC_THUMB_PCREL_BRANCH25:
30201    case BFD_RELOC_VTABLE_ENTRY:
30202    case BFD_RELOC_VTABLE_INHERIT:
30203#ifdef TE_PE
30204    case BFD_RELOC_32_SECREL:
30205#endif
30206      code = fixp->fx_r_type;
30207      break;
30208
30209    case BFD_RELOC_THUMB_PCREL_BLX:
30210#ifdef OBJ_ELF
30211      if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
30212	code = BFD_RELOC_THUMB_PCREL_BRANCH23;
30213      else
30214#endif
30215	code = BFD_RELOC_THUMB_PCREL_BLX;
30216      break;
30217
30218    case BFD_RELOC_ARM_LITERAL:
30219    case BFD_RELOC_ARM_HWLITERAL:
30220      /* If this is called then the a literal has
30221	 been referenced across a section boundary.  */
30222      as_bad_where (fixp->fx_file, fixp->fx_line,
30223		    _("literal referenced across section boundary"));
30224      return NULL;
30225
30226#ifdef OBJ_ELF
30227    case BFD_RELOC_ARM_TLS_CALL:
30228    case BFD_RELOC_ARM_THM_TLS_CALL:
30229    case BFD_RELOC_ARM_TLS_DESCSEQ:
30230    case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
30231    case BFD_RELOC_ARM_GOT32:
30232    case BFD_RELOC_ARM_GOTOFF:
30233    case BFD_RELOC_ARM_GOT_PREL:
30234    case BFD_RELOC_ARM_PLT32:
30235    case BFD_RELOC_ARM_TARGET1:
30236    case BFD_RELOC_ARM_ROSEGREL32:
30237    case BFD_RELOC_ARM_SBREL32:
30238    case BFD_RELOC_ARM_PREL31:
30239    case BFD_RELOC_ARM_TARGET2:
30240    case BFD_RELOC_ARM_TLS_LDO32:
30241    case BFD_RELOC_ARM_PCREL_CALL:
30242    case BFD_RELOC_ARM_PCREL_JUMP:
30243    case BFD_RELOC_ARM_ALU_PC_G0_NC:
30244    case BFD_RELOC_ARM_ALU_PC_G0:
30245    case BFD_RELOC_ARM_ALU_PC_G1_NC:
30246    case BFD_RELOC_ARM_ALU_PC_G1:
30247    case BFD_RELOC_ARM_ALU_PC_G2:
30248    case BFD_RELOC_ARM_LDR_PC_G0:
30249    case BFD_RELOC_ARM_LDR_PC_G1:
30250    case BFD_RELOC_ARM_LDR_PC_G2:
30251    case BFD_RELOC_ARM_LDRS_PC_G0:
30252    case BFD_RELOC_ARM_LDRS_PC_G1:
30253    case BFD_RELOC_ARM_LDRS_PC_G2:
30254    case BFD_RELOC_ARM_LDC_PC_G0:
30255    case BFD_RELOC_ARM_LDC_PC_G1:
30256    case BFD_RELOC_ARM_LDC_PC_G2:
30257    case BFD_RELOC_ARM_ALU_SB_G0_NC:
30258    case BFD_RELOC_ARM_ALU_SB_G0:
30259    case BFD_RELOC_ARM_ALU_SB_G1_NC:
30260    case BFD_RELOC_ARM_ALU_SB_G1:
30261    case BFD_RELOC_ARM_ALU_SB_G2:
30262    case BFD_RELOC_ARM_LDR_SB_G0:
30263    case BFD_RELOC_ARM_LDR_SB_G1:
30264    case BFD_RELOC_ARM_LDR_SB_G2:
30265    case BFD_RELOC_ARM_LDRS_SB_G0:
30266    case BFD_RELOC_ARM_LDRS_SB_G1:
30267    case BFD_RELOC_ARM_LDRS_SB_G2:
30268    case BFD_RELOC_ARM_LDC_SB_G0:
30269    case BFD_RELOC_ARM_LDC_SB_G1:
30270    case BFD_RELOC_ARM_LDC_SB_G2:
30271    case BFD_RELOC_ARM_V4BX:
30272    case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
30273    case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
30274    case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
30275    case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
30276    case BFD_RELOC_ARM_GOTFUNCDESC:
30277    case BFD_RELOC_ARM_GOTOFFFUNCDESC:
30278    case BFD_RELOC_ARM_FUNCDESC:
30279    case BFD_RELOC_ARM_THUMB_BF17:
30280    case BFD_RELOC_ARM_THUMB_BF19:
30281    case BFD_RELOC_ARM_THUMB_BF13:
30282      code = fixp->fx_r_type;
30283      break;
30284
30285    case BFD_RELOC_ARM_TLS_GOTDESC:
30286    case BFD_RELOC_ARM_TLS_GD32:
30287    case BFD_RELOC_ARM_TLS_GD32_FDPIC:
30288    case BFD_RELOC_ARM_TLS_LE32:
30289    case BFD_RELOC_ARM_TLS_IE32:
30290    case BFD_RELOC_ARM_TLS_IE32_FDPIC:
30291    case BFD_RELOC_ARM_TLS_LDM32:
30292    case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
30293      /* BFD will include the symbol's address in the addend.
30294	 But we don't want that, so subtract it out again here.  */
30295      if (!S_IS_COMMON (fixp->fx_addsy))
30296	reloc->addend -= (*reloc->sym_ptr_ptr)->value;
30297      code = fixp->fx_r_type;
30298      break;
30299#endif
30300
30301    case BFD_RELOC_ARM_IMMEDIATE:
30302      as_bad_where (fixp->fx_file, fixp->fx_line,
30303		    _("internal relocation (type: IMMEDIATE) not fixed up"));
30304      return NULL;
30305
30306    case BFD_RELOC_ARM_ADRL_IMMEDIATE:
30307      as_bad_where (fixp->fx_file, fixp->fx_line,
30308		    _("ADRL used for a symbol not defined in the same file"));
30309      return NULL;
30310
30311    case BFD_RELOC_THUMB_PCREL_BRANCH5:
30312    case BFD_RELOC_THUMB_PCREL_BFCSEL:
30313    case BFD_RELOC_ARM_THUMB_LOOP12:
30314      as_bad_where (fixp->fx_file, fixp->fx_line,
30315		    _("%s used for a symbol not defined in the same file"),
30316		    bfd_get_reloc_code_name (fixp->fx_r_type));
30317      return NULL;
30318
30319    case BFD_RELOC_ARM_OFFSET_IMM:
30320      if (section->use_rela_p)
30321	{
30322	  code = fixp->fx_r_type;
30323	  break;
30324	}
30325
30326      if (fixp->fx_addsy != NULL
30327	  && !S_IS_DEFINED (fixp->fx_addsy)
30328	  && S_IS_LOCAL (fixp->fx_addsy))
30329	{
30330	  as_bad_where (fixp->fx_file, fixp->fx_line,
30331			_("undefined local label `%s'"),
30332			S_GET_NAME (fixp->fx_addsy));
30333	  return NULL;
30334	}
30335
30336      as_bad_where (fixp->fx_file, fixp->fx_line,
30337		    _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30338      return NULL;
30339
30340    default:
30341      {
30342	const char * type;
30343
30344	switch (fixp->fx_r_type)
30345	  {
30346	  case BFD_RELOC_NONE:		   type = "NONE";	  break;
30347	  case BFD_RELOC_ARM_OFFSET_IMM8:  type = "OFFSET_IMM8";  break;
30348	  case BFD_RELOC_ARM_SHIFT_IMM:	   type = "SHIFT_IMM";	  break;
30349	  case BFD_RELOC_ARM_SMC:	   type = "SMC";	  break;
30350	  case BFD_RELOC_ARM_SWI:	   type = "SWI";	  break;
30351	  case BFD_RELOC_ARM_MULTI:	   type = "MULTI";	  break;
30352	  case BFD_RELOC_ARM_CP_OFF_IMM:   type = "CP_OFF_IMM";	  break;
30353	  case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
30354	  case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
30355	  case BFD_RELOC_ARM_THUMB_ADD:	   type = "THUMB_ADD";	  break;
30356	  case BFD_RELOC_ARM_THUMB_SHIFT:  type = "THUMB_SHIFT";  break;
30357	  case BFD_RELOC_ARM_THUMB_IMM:	   type = "THUMB_IMM";	  break;
30358	  case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
30359	  default:			   type = _("<unknown>"); break;
30360	  }
30361	as_bad_where (fixp->fx_file, fixp->fx_line,
30362		      _("cannot represent %s relocation in this object file format"),
30363		      type);
30364	return NULL;
30365      }
30366    }
30367
30368#ifdef OBJ_ELF
30369  if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
30370      && GOT_symbol
30371      && fixp->fx_addsy == GOT_symbol)
30372    {
30373      code = BFD_RELOC_ARM_GOTPC;
30374      reloc->addend = fixp->fx_offset = reloc->address;
30375    }
30376#endif
30377
30378  reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
30379
30380  if (reloc->howto == NULL)
30381    {
30382      as_bad_where (fixp->fx_file, fixp->fx_line,
30383		    _("cannot represent %s relocation in this object file format"),
30384		    bfd_get_reloc_code_name (code));
30385      return NULL;
30386    }
30387
30388  /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30389     vtable entry to be used in the relocation's section offset.  */
30390  if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
30391    reloc->address = fixp->fx_offset;
30392
30393  return reloc;
30394}
30395
30396/* This fix_new is called by cons via TC_CONS_FIX_NEW.	*/
30397
30398void
30399cons_fix_new_arm (fragS *	frag,
30400		  int		where,
30401		  int		size,
30402		  expressionS * exp,
30403		  bfd_reloc_code_real_type reloc)
30404{
30405  int pcrel = 0;
30406
30407  /* Pick a reloc.
30408     FIXME: @@ Should look at CPU word size.  */
30409  switch (size)
30410    {
30411    case 1:
30412      reloc = BFD_RELOC_8;
30413      break;
30414    case 2:
30415      reloc = BFD_RELOC_16;
30416      break;
30417    case 4:
30418    default:
30419      reloc = BFD_RELOC_32;
30420      break;
30421    case 8:
30422      reloc = BFD_RELOC_64;
30423      break;
30424    }
30425
30426#ifdef TE_PE
30427  if (exp->X_op == O_secrel)
30428  {
30429    exp->X_op = O_symbol;
30430    reloc = BFD_RELOC_32_SECREL;
30431  }
30432#endif
30433
30434  fix_new_exp (frag, where, size, exp, pcrel, reloc);
30435}
30436
30437#if defined (OBJ_COFF)
30438void
30439arm_validate_fix (fixS * fixP)
30440{
30441  /* If the destination of the branch is a defined symbol which does not have
30442     the THUMB_FUNC attribute, then we must be calling a function which has
30443     the (interfacearm) attribute.  We look for the Thumb entry point to that
30444     function and change the branch to refer to that function instead.	*/
30445  if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
30446      && fixP->fx_addsy != NULL
30447      && S_IS_DEFINED (fixP->fx_addsy)
30448      && ! THUMB_IS_FUNC (fixP->fx_addsy))
30449    {
30450      fixP->fx_addsy = find_real_start (fixP->fx_addsy);
30451    }
30452}
30453#endif
30454
30455
30456int
30457arm_force_relocation (struct fix * fixp)
30458{
30459#if defined (OBJ_COFF) && defined (TE_PE)
30460  if (fixp->fx_r_type == BFD_RELOC_RVA)
30461    return 1;
30462#endif
30463
30464  /* In case we have a call or a branch to a function in ARM ISA mode from
30465     a thumb function or vice-versa force the relocation. These relocations
30466     are cleared off for some cores that might have blx and simple transformations
30467     are possible.  */
30468
30469#ifdef OBJ_ELF
30470  switch (fixp->fx_r_type)
30471    {
30472    case BFD_RELOC_ARM_PCREL_JUMP:
30473    case BFD_RELOC_ARM_PCREL_CALL:
30474    case BFD_RELOC_THUMB_PCREL_BLX:
30475      if (THUMB_IS_FUNC (fixp->fx_addsy))
30476	return 1;
30477      break;
30478
30479    case BFD_RELOC_ARM_PCREL_BLX:
30480    case BFD_RELOC_THUMB_PCREL_BRANCH25:
30481    case BFD_RELOC_THUMB_PCREL_BRANCH20:
30482    case BFD_RELOC_THUMB_PCREL_BRANCH23:
30483      if (ARM_IS_FUNC (fixp->fx_addsy))
30484	return 1;
30485      break;
30486
30487    default:
30488      break;
30489    }
30490#endif
30491
30492  /* Resolve these relocations even if the symbol is extern or weak.
30493     Technically this is probably wrong due to symbol preemption.
30494     In practice these relocations do not have enough range to be useful
30495     at dynamic link time, and some code (e.g. in the Linux kernel)
30496     expects these references to be resolved.  */
30497  if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
30498      || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
30499      || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
30500      || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
30501      || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
30502      || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
30503      || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
30504      || fixp->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH12
30505      || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
30506      || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
30507      || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
30508      || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
30509      || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
30510      || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
30511      || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
30512    return 0;
30513
30514  /* Always leave these relocations for the linker.  */
30515  if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
30516       && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
30517      || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
30518    return 1;
30519
30520  /* Always generate relocations against function symbols.  */
30521  if (fixp->fx_r_type == BFD_RELOC_32
30522      && fixp->fx_addsy
30523      && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
30524    return 1;
30525
30526  return generic_force_reloc (fixp);
30527}
30528
30529#if defined (OBJ_ELF) || defined (OBJ_COFF)
30530/* Relocations against function names must be left unadjusted,
30531   so that the linker can use this information to generate interworking
30532   stubs.  The MIPS version of this function
30533   also prevents relocations that are mips-16 specific, but I do not
30534   know why it does this.
30535
30536   FIXME:
30537   There is one other problem that ought to be addressed here, but
30538   which currently is not:  Taking the address of a label (rather
30539   than a function) and then later jumping to that address.  Such
30540   addresses also ought to have their bottom bit set (assuming that
30541   they reside in Thumb code), but at the moment they will not.	 */
30542
30543bool
30544arm_fix_adjustable (fixS * fixP)
30545{
30546  if (fixP->fx_addsy == NULL)
30547    return 1;
30548
30549  /* Preserve relocations against symbols with function type.  */
30550  if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
30551    return false;
30552
30553  if (THUMB_IS_FUNC (fixP->fx_addsy)
30554      && fixP->fx_subsy == NULL)
30555    return false;
30556
30557  /* We need the symbol name for the VTABLE entries.  */
30558  if (	 fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
30559      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
30560    return false;
30561
30562  /* Don't allow symbols to be discarded on GOT related relocs.	 */
30563  if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
30564      || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
30565      || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
30566      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
30567      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
30568      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
30569      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
30570      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
30571      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
30572      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
30573      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
30574      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
30575      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
30576      || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
30577      || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
30578      || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
30579      || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
30580    return false;
30581
30582  /* Similarly for group relocations.  */
30583  if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
30584       && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
30585      || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
30586    return false;
30587
30588  /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols.  */
30589  if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
30590      || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
30591      || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
30592      || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
30593      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
30594      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
30595      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
30596      || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
30597    return false;
30598
30599  /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30600     offsets, so keep these symbols.  */
30601  if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30602      && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
30603    return false;
30604
30605  return true;
30606}
30607#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30608
30609#ifdef OBJ_ELF
30610const char *
30611elf32_arm_target_format (void)
30612{
30613#if defined (TE_VXWORKS)
30614  return (target_big_endian
30615	  ? "elf32-bigarm-vxworks"
30616	  : "elf32-littlearm-vxworks");
30617#elif defined (TE_NACL)
30618  return (target_big_endian
30619	  ? "elf32-bigarm-nacl"
30620	  : "elf32-littlearm-nacl");
30621#else
30622  if (arm_fdpic)
30623    {
30624      if (target_big_endian)
30625	return "elf32-bigarm-fdpic";
30626      else
30627	return "elf32-littlearm-fdpic";
30628    }
30629  else
30630    {
30631      if (target_big_endian)
30632	return "elf32-bigarm";
30633      else
30634	return "elf32-littlearm";
30635    }
30636#endif
30637}
30638
30639void
30640armelf_frob_symbol (symbolS * symp,
30641		    int *     puntp)
30642{
30643  elf_frob_symbol (symp, puntp);
30644}
30645#endif
30646
30647/* MD interface: Finalization.	*/
30648
30649void
30650arm_cleanup (void)
30651{
30652  literal_pool * pool;
30653
30654  /* Ensure that all the predication blocks are properly closed.  */
30655  check_pred_blocks_finished ();
30656
30657  for (pool = list_of_pools; pool; pool = pool->next)
30658    {
30659      /* Put it at the end of the relevant section.  */
30660      subseg_set (pool->section, pool->sub_section);
30661#ifdef OBJ_ELF
30662      arm_elf_change_section ();
30663#endif
30664      s_ltorg (0);
30665    }
30666}
30667
30668#ifdef OBJ_ELF
30669/* Remove any excess mapping symbols generated for alignment frags in
30670   SEC.  We may have created a mapping symbol before a zero byte
30671   alignment; remove it if there's a mapping symbol after the
30672   alignment.  */
30673static void
30674check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
30675		       void *dummy ATTRIBUTE_UNUSED)
30676{
30677  segment_info_type *seginfo = seg_info (sec);
30678  fragS *fragp;
30679
30680  if (seginfo == NULL || seginfo->frchainP == NULL)
30681    return;
30682
30683  for (fragp = seginfo->frchainP->frch_root;
30684       fragp != NULL;
30685       fragp = fragp->fr_next)
30686    {
30687      symbolS *sym = fragp->tc_frag_data.last_map;
30688      fragS *next = fragp->fr_next;
30689
30690      /* Variable-sized frags have been converted to fixed size by
30691	 this point.  But if this was variable-sized to start with,
30692	 there will be a fixed-size frag after it.  So don't handle
30693	 next == NULL.  */
30694      if (sym == NULL || next == NULL)
30695	continue;
30696
30697      if (S_GET_VALUE (sym) < next->fr_address)
30698	/* Not at the end of this frag.  */
30699	continue;
30700      know (S_GET_VALUE (sym) == next->fr_address);
30701
30702      do
30703	{
30704	  if (next->tc_frag_data.first_map != NULL)
30705	    {
30706	      /* Next frag starts with a mapping symbol.  Discard this
30707		 one.  */
30708	      symbol_remove (sym, &symbol_rootP, &symbol_lastP);
30709	      break;
30710	    }
30711
30712	  if (next->fr_next == NULL)
30713	    {
30714	      /* This mapping symbol is at the end of the section.  Discard
30715		 it.  */
30716	      know (next->fr_fix == 0 && next->fr_var == 0);
30717	      symbol_remove (sym, &symbol_rootP, &symbol_lastP);
30718	      break;
30719	    }
30720
30721	  /* As long as we have empty frags without any mapping symbols,
30722	     keep looking.  */
30723	  /* If the next frag is non-empty and does not start with a
30724	     mapping symbol, then this mapping symbol is required.  */
30725	  if (next->fr_address != next->fr_next->fr_address)
30726	    break;
30727
30728	  next = next->fr_next;
30729	}
30730      while (next != NULL);
30731    }
30732}
30733#endif
30734
30735/* Adjust the symbol table.  This marks Thumb symbols as distinct from
30736   ARM ones.  */
30737
30738void
30739arm_adjust_symtab (void)
30740{
30741#ifdef OBJ_COFF
30742  symbolS * sym;
30743
30744  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
30745    {
30746      if (ARM_IS_THUMB (sym))
30747	{
30748	  if (THUMB_IS_FUNC (sym))
30749	    {
30750	      /* Mark the symbol as a Thumb function.  */
30751	      if (   S_GET_STORAGE_CLASS (sym) == C_STAT
30752		  || S_GET_STORAGE_CLASS (sym) == C_LABEL)  /* This can happen!	 */
30753		S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
30754
30755	      else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
30756		S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
30757	      else
30758		as_bad (_("%s: unexpected function type: %d"),
30759			S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
30760	    }
30761	  else switch (S_GET_STORAGE_CLASS (sym))
30762	    {
30763	    case C_EXT:
30764	      S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
30765	      break;
30766	    case C_STAT:
30767	      S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
30768	      break;
30769	    case C_LABEL:
30770	      S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
30771	      break;
30772	    default:
30773	      /* Do nothing.  */
30774	      break;
30775	    }
30776	}
30777
30778      if (ARM_IS_INTERWORK (sym))
30779	coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
30780    }
30781#endif
30782#ifdef OBJ_ELF
30783  symbolS * sym;
30784  char	    bind;
30785
30786  for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
30787    {
30788      if (ARM_IS_THUMB (sym))
30789	{
30790	  elf_symbol_type * elf_sym;
30791
30792	  elf_sym = elf_symbol (symbol_get_bfdsym (sym));
30793	  bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
30794
30795	  if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
30796		BFD_ARM_SPECIAL_SYM_TYPE_ANY))
30797	    {
30798	      /* If it's a .thumb_func, declare it as so,
30799		 otherwise tag label as .code 16.  */
30800	      if (THUMB_IS_FUNC (sym))
30801		ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
30802					 ST_BRANCH_TO_THUMB);
30803	      else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
30804		elf_sym->internal_elf_sym.st_info =
30805		  ELF_ST_INFO (bind, STT_ARM_16BIT);
30806	    }
30807	}
30808    }
30809
30810  /* Remove any overlapping mapping symbols generated by alignment frags.  */
30811  bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
30812  /* Now do generic ELF adjustments.  */
30813  elf_adjust_symtab ();
30814#endif
30815}
30816
30817/* MD interface: Initialization.  */
30818
30819static void
30820set_constant_flonums (void)
30821{
30822  int i;
30823
30824  for (i = 0; i < NUM_FLOAT_VALS; i++)
30825    if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
30826      abort ();
30827}
30828
30829/* Auto-select Thumb mode if it's the only available instruction set for the
30830   given architecture.  */
30831
30832static void
30833autoselect_thumb_from_cpu_variant (void)
30834{
30835  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
30836    opcode_select (16);
30837}
30838
30839void
30840md_begin (void)
30841{
30842  unsigned mach;
30843  unsigned int i;
30844
30845  arm_ops_hsh = str_htab_create ();
30846  arm_cond_hsh = str_htab_create ();
30847  arm_vcond_hsh = str_htab_create ();
30848  arm_shift_hsh = str_htab_create ();
30849  arm_psr_hsh = str_htab_create ();
30850  arm_v7m_psr_hsh = str_htab_create ();
30851  arm_reg_hsh = str_htab_create ();
30852  arm_reloc_hsh = str_htab_create ();
30853  arm_barrier_opt_hsh = str_htab_create ();
30854
30855  for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
30856    if (str_hash_find (arm_ops_hsh, insns[i].template_name) == NULL)
30857      str_hash_insert (arm_ops_hsh, insns[i].template_name, insns + i, 0);
30858  for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
30859    str_hash_insert (arm_cond_hsh, conds[i].template_name, conds + i, 0);
30860  for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
30861    str_hash_insert (arm_vcond_hsh, vconds[i].template_name, vconds + i, 0);
30862  for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
30863    str_hash_insert (arm_shift_hsh, shift_names[i].name, shift_names + i, 0);
30864  for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
30865    str_hash_insert (arm_psr_hsh, psrs[i].template_name, psrs + i, 0);
30866  for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
30867    str_hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
30868		     v7m_psrs + i, 0);
30869  for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
30870    str_hash_insert (arm_reg_hsh, reg_names[i].name, reg_names + i, 0);
30871  for (i = 0;
30872       i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
30873       i++)
30874    str_hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
30875		     barrier_opt_names + i, 0);
30876#ifdef OBJ_ELF
30877  for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
30878    {
30879      struct reloc_entry * entry = reloc_names + i;
30880
30881      if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
30882	/* This makes encode_branch() use the EABI versions of this relocation.  */
30883	entry->reloc = BFD_RELOC_UNUSED;
30884
30885      str_hash_insert (arm_reloc_hsh, entry->name, entry, 0);
30886    }
30887#endif
30888
30889  set_constant_flonums ();
30890
30891  /* Set the cpu variant based on the command-line options.  We prefer
30892     -mcpu= over -march= if both are set (as for GCC); and we prefer
30893     -mfpu= over any other way of setting the floating point unit.
30894     Use of legacy options with new options are faulted.  */
30895  if (legacy_cpu)
30896    {
30897      if (mcpu_cpu_opt || march_cpu_opt)
30898	as_bad (_("use of old and new-style options to set CPU type"));
30899
30900      selected_arch = *legacy_cpu;
30901    }
30902  else if (mcpu_cpu_opt)
30903    {
30904      selected_arch = *mcpu_cpu_opt;
30905      selected_ext = *mcpu_ext_opt;
30906    }
30907  else if (march_cpu_opt)
30908    {
30909      selected_arch = *march_cpu_opt;
30910      selected_ext = *march_ext_opt;
30911    }
30912  ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
30913
30914  if (legacy_fpu)
30915    {
30916      if (mfpu_opt)
30917	as_bad (_("use of old and new-style options to set FPU type"));
30918
30919      selected_fpu = *legacy_fpu;
30920    }
30921  else if (mfpu_opt)
30922    selected_fpu = *mfpu_opt;
30923  else
30924    {
30925#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30926	|| defined (TE_NetBSD) || defined (TE_VXWORKS))
30927      /* Some environments specify a default FPU.  If they don't, infer it
30928	 from the processor.  */
30929      if (mcpu_fpu_opt)
30930	selected_fpu = *mcpu_fpu_opt;
30931      else if (march_fpu_opt)
30932	selected_fpu = *march_fpu_opt;
30933#else
30934      selected_fpu = fpu_default;
30935#endif
30936    }
30937
30938  if (ARM_FEATURE_ZERO (selected_fpu))
30939    {
30940      if (!no_cpu_selected ())
30941	selected_fpu = fpu_default;
30942      else
30943	selected_fpu = fpu_arch_fpa;
30944    }
30945
30946#ifdef CPU_DEFAULT
30947  if (ARM_FEATURE_ZERO (selected_arch))
30948    {
30949      selected_arch = cpu_default;
30950      selected_cpu = selected_arch;
30951    }
30952  ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
30953#else
30954  /*  Autodection of feature mode: allow all features in cpu_variant but leave
30955      selected_cpu unset.  It will be set in aeabi_set_public_attributes ()
30956      after all instruction have been processed and we can decide what CPU
30957      should be selected.  */
30958  if (ARM_FEATURE_ZERO (selected_arch))
30959    ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
30960  else
30961    ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
30962#endif
30963
30964  autoselect_thumb_from_cpu_variant ();
30965
30966  arm_arch_used = thumb_arch_used = arm_arch_none;
30967
30968#if defined OBJ_COFF || defined OBJ_ELF
30969  {
30970    unsigned int flags = 0;
30971
30972#if defined OBJ_ELF
30973    flags = meabi_flags;
30974
30975    switch (meabi_flags)
30976      {
30977      case EF_ARM_EABI_UNKNOWN:
30978#endif
30979	/* Set the flags in the private structure.  */
30980	if (uses_apcs_26)      flags |= F_APCS26;
30981	if (support_interwork) flags |= F_INTERWORK;
30982	if (uses_apcs_float)   flags |= F_APCS_FLOAT;
30983	if (pic_code)	       flags |= F_PIC;
30984	if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
30985	  flags |= F_SOFT_FLOAT;
30986
30987	switch (mfloat_abi_opt)
30988	  {
30989	  case ARM_FLOAT_ABI_SOFT:
30990	  case ARM_FLOAT_ABI_SOFTFP:
30991	    flags |= F_SOFT_FLOAT;
30992	    break;
30993
30994	  case ARM_FLOAT_ABI_HARD:
30995	    if (flags & F_SOFT_FLOAT)
30996	      as_bad (_("hard-float conflicts with specified fpu"));
30997	    break;
30998	  }
30999
31000	/* Using pure-endian doubles (even if soft-float).	*/
31001	if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
31002	  flags |= F_VFP_FLOAT;
31003
31004#if defined OBJ_ELF
31005	if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
31006	    flags |= EF_ARM_MAVERICK_FLOAT;
31007	break;
31008
31009      case EF_ARM_EABI_VER4:
31010      case EF_ARM_EABI_VER5:
31011	/* No additional flags to set.	*/
31012	break;
31013
31014      default:
31015	abort ();
31016      }
31017#endif
31018    bfd_set_private_flags (stdoutput, flags);
31019
31020    /* We have run out flags in the COFF header to encode the
31021       status of ATPCS support, so instead we create a dummy,
31022       empty, debug section called .arm.atpcs.	*/
31023    if (atpcs)
31024      {
31025	asection * sec;
31026
31027	sec = bfd_make_section (stdoutput, ".arm.atpcs");
31028
31029	if (sec != NULL)
31030	  {
31031	    bfd_set_section_flags (sec, SEC_READONLY | SEC_DEBUGGING);
31032	    bfd_set_section_size (sec, 0);
31033	    bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
31034	  }
31035      }
31036  }
31037#endif
31038
31039  /* Record the CPU type as well.  */
31040  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
31041    mach = bfd_mach_arm_iWMMXt2;
31042  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
31043    mach = bfd_mach_arm_iWMMXt;
31044  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
31045    mach = bfd_mach_arm_XScale;
31046  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
31047    mach = bfd_mach_arm_ep9312;
31048  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
31049    mach = bfd_mach_arm_5TE;
31050  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
31051    {
31052      if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
31053	mach = bfd_mach_arm_5T;
31054      else
31055	mach = bfd_mach_arm_5;
31056    }
31057  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
31058    {
31059      if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
31060	mach = bfd_mach_arm_4T;
31061      else
31062	mach = bfd_mach_arm_4;
31063    }
31064  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
31065    mach = bfd_mach_arm_3M;
31066  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
31067    mach = bfd_mach_arm_3;
31068  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
31069    mach = bfd_mach_arm_2a;
31070  else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
31071    mach = bfd_mach_arm_2;
31072  else
31073    mach = bfd_mach_arm_unknown;
31074
31075  bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
31076}
31077
31078/* Command line processing.  */
31079
31080/* md_parse_option
31081      Invocation line includes a switch not recognized by the base assembler.
31082      See if it's a processor-specific option.
31083
31084      This routine is somewhat complicated by the need for backwards
31085      compatibility (since older releases of gcc can't be changed).
31086      The new options try to make the interface as compatible as
31087      possible with GCC.
31088
31089      New options (supported) are:
31090
31091	      -mcpu=<cpu name>		 Assemble for selected processor
31092	      -march=<architecture name> Assemble for selected architecture
31093	      -mfpu=<fpu architecture>	 Assemble for selected FPU.
31094	      -EB/-mbig-endian		 Big-endian
31095	      -EL/-mlittle-endian	 Little-endian
31096	      -k			 Generate PIC code
31097	      -mthumb			 Start in Thumb mode
31098	      -mthumb-interwork		 Code supports ARM/Thumb interworking
31099
31100	      -m[no-]warn-deprecated     Warn about deprecated features
31101	      -m[no-]warn-syms		 Warn when symbols match instructions
31102
31103      For now we will also provide support for:
31104
31105	      -mapcs-32			 32-bit Program counter
31106	      -mapcs-26			 26-bit Program counter
31107	      -macps-float		 Floats passed in FP registers
31108	      -mapcs-reentrant		 Reentrant code
31109	      -matpcs
31110      (sometime these will probably be replaced with -mapcs=<list of options>
31111      and -matpcs=<list of options>)
31112
31113      The remaining options are only supported for back-wards compatibility.
31114      Cpu variants, the arm part is optional:
31115	      -m[arm]1		      Currently not supported.
31116	      -m[arm]2, -m[arm]250    Arm 2 and Arm 250 processor
31117	      -m[arm]3		      Arm 3 processor
31118	      -m[arm]6[xx],	      Arm 6 processors
31119	      -m[arm]7[xx][t][[d]m]   Arm 7 processors
31120	      -m[arm]8[10]	      Arm 8 processors
31121	      -m[arm]9[20][tdmi]      Arm 9 processors
31122	      -mstrongarm[110[0]]     StrongARM processors
31123	      -mxscale		      XScale processors
31124	      -m[arm]v[2345[t[e]]]    Arm architectures
31125	      -mall		      All (except the ARM1)
31126      FP variants:
31127	      -mfpa10, -mfpa11	      FPA10 and 11 co-processor instructions
31128	      -mfpe-old		      (No float load/store multiples)
31129	      -mvfpxd		      VFP Single precision
31130	      -mvfp		      All VFP
31131	      -mno-fpu		      Disable all floating point instructions
31132
31133      The following CPU names are recognized:
31134	      arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31135	      arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31136	      arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31137	      arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31138	      arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31139	      arm10t arm10e, arm1020t, arm1020e, arm10200e,
31140	      strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31141
31142      */
31143
31144const char * md_shortopts = "m:k";
31145
31146#ifdef ARM_BI_ENDIAN
31147#define OPTION_EB (OPTION_MD_BASE + 0)
31148#define OPTION_EL (OPTION_MD_BASE + 1)
31149#else
31150#if TARGET_BYTES_BIG_ENDIAN
31151#define OPTION_EB (OPTION_MD_BASE + 0)
31152#else
31153#define OPTION_EL (OPTION_MD_BASE + 1)
31154#endif
31155#endif
31156#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31157#define OPTION_FDPIC (OPTION_MD_BASE + 3)
31158
31159struct option md_longopts[] =
31160{
31161#ifdef OPTION_EB
31162  {"EB", no_argument, NULL, OPTION_EB},
31163#endif
31164#ifdef OPTION_EL
31165  {"EL", no_argument, NULL, OPTION_EL},
31166#endif
31167  {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
31168#ifdef OBJ_ELF
31169  {"fdpic", no_argument, NULL, OPTION_FDPIC},
31170#endif
31171  {NULL, no_argument, NULL, 0}
31172};
31173
31174size_t md_longopts_size = sizeof (md_longopts);
31175
31176struct arm_option_table
31177{
31178  const char *  option;		/* Option name to match.  */
31179  const char *  help;		/* Help information.  */
31180  int *         var;		/* Variable to change.	*/
31181  int	        value;		/* What to change it to.  */
31182  const char *  deprecated;	/* If non-null, print this message.  */
31183};
31184
31185struct arm_option_table arm_opts[] =
31186{
31187  {"k",	     N_("generate PIC code"),	   &pic_code,	 1, NULL},
31188  {"mthumb", N_("assemble Thumb code"),	   &thumb_mode,	 1, NULL},
31189  {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31190   &support_interwork, 1, NULL},
31191  {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
31192  {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
31193  {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
31194   1, NULL},
31195  {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
31196  {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
31197  {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
31198  {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
31199   NULL},
31200
31201  /* These are recognized by the assembler, but have no affect on code.	 */
31202  {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
31203  {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
31204
31205  {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
31206  {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31207   &warn_on_deprecated, 0, NULL},
31208
31209  {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31210   " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it, 1, NULL},
31211  {"mno-warn-restrict-it", NULL, &warn_on_restrict_it, 0, NULL},
31212
31213  {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), true, NULL},
31214  {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), false, NULL},
31215  {NULL, NULL, NULL, 0, NULL}
31216};
31217
31218struct arm_legacy_option_table
31219{
31220  const char *              option;		/* Option name to match.  */
31221  const arm_feature_set	**  var;		/* Variable to change.	*/
31222  const arm_feature_set	    value;		/* What to change it to.  */
31223  const char *              deprecated;		/* If non-null, print this message.  */
31224};
31225
31226const struct arm_legacy_option_table arm_legacy_opts[] =
31227{
31228  /* DON'T add any new processors to this list -- we want the whole list
31229     to go away...  Add them to the processors table instead.  */
31230  {"marm1",	 &legacy_cpu, ARM_ARCH_V1,  N_("use -mcpu=arm1")},
31231  {"m1",	 &legacy_cpu, ARM_ARCH_V1,  N_("use -mcpu=arm1")},
31232  {"marm2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -mcpu=arm2")},
31233  {"m2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -mcpu=arm2")},
31234  {"marm250",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
31235  {"m250",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
31236  {"marm3",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
31237  {"m3",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
31238  {"marm6",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm6")},
31239  {"m6",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm6")},
31240  {"marm600",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm600")},
31241  {"m600",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm600")},
31242  {"marm610",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm610")},
31243  {"m610",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm610")},
31244  {"marm620",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm620")},
31245  {"m620",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm620")},
31246  {"marm7",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7")},
31247  {"m7",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7")},
31248  {"marm70",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm70")},
31249  {"m70",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm70")},
31250  {"marm700",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700")},
31251  {"m700",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700")},
31252  {"marm700i",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700i")},
31253  {"m700i",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm700i")},
31254  {"marm710",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710")},
31255  {"m710",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710")},
31256  {"marm710c",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710c")},
31257  {"m710c",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm710c")},
31258  {"marm720",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm720")},
31259  {"m720",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm720")},
31260  {"marm7d",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7d")},
31261  {"m7d",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7d")},
31262  {"marm7di",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7di")},
31263  {"m7di",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7di")},
31264  {"marm7m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
31265  {"m7m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
31266  {"marm7dm",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
31267  {"m7dm",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
31268  {"marm7dmi",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
31269  {"m7dmi",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
31270  {"marm7100",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7100")},
31271  {"m7100",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7100")},
31272  {"marm7500",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500")},
31273  {"m7500",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500")},
31274  {"marm7500fe", &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500fe")},
31275  {"m7500fe",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -mcpu=arm7500fe")},
31276  {"marm7t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31277  {"m7t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31278  {"marm7tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31279  {"m7tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
31280  {"marm710t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
31281  {"m710t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
31282  {"marm720t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
31283  {"m720t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
31284  {"marm740t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
31285  {"m740t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
31286  {"marm8",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm8")},
31287  {"m8",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm8")},
31288  {"marm810",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm810")},
31289  {"m810",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=arm810")},
31290  {"marm9",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
31291  {"m9",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
31292  {"marm9tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
31293  {"m9tdmi",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
31294  {"marm920",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
31295  {"m920",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
31296  {"marm940",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
31297  {"m940",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
31298  {"mstrongarm", &legacy_cpu, ARM_ARCH_V4,  N_("use -mcpu=strongarm")},
31299  {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
31300   N_("use -mcpu=strongarm110")},
31301  {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
31302   N_("use -mcpu=strongarm1100")},
31303  {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
31304   N_("use -mcpu=strongarm1110")},
31305  {"mxscale",	 &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
31306  {"miwmmxt",	 &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
31307  {"mall",	 &legacy_cpu, ARM_ANY,	       N_("use -mcpu=all")},
31308
31309  /* Architecture variants -- don't add any more to this list either.  */
31310  {"mv2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -march=armv2")},
31311  {"marmv2",	 &legacy_cpu, ARM_ARCH_V2,  N_("use -march=armv2")},
31312  {"mv2a",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
31313  {"marmv2a",	 &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
31314  {"mv3",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -march=armv3")},
31315  {"marmv3",	 &legacy_cpu, ARM_ARCH_V3,  N_("use -march=armv3")},
31316  {"mv3m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
31317  {"marmv3m",	 &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
31318  {"mv4",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -march=armv4")},
31319  {"marmv4",	 &legacy_cpu, ARM_ARCH_V4,  N_("use -march=armv4")},
31320  {"mv4t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
31321  {"marmv4t",	 &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
31322  {"mv5",	 &legacy_cpu, ARM_ARCH_V5,  N_("use -march=armv5")},
31323  {"marmv5",	 &legacy_cpu, ARM_ARCH_V5,  N_("use -march=armv5")},
31324  {"mv5t",	 &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
31325  {"marmv5t",	 &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
31326  {"mv5e",	 &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
31327  {"marmv5e",	 &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
31328
31329  /* Floating point variants -- don't add any more to this list either.	 */
31330  {"mfpe-old",   &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
31331  {"mfpa10",     &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
31332  {"mfpa11",     &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
31333  {"mno-fpu",    &legacy_fpu, ARM_ARCH_NONE,
31334   N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31335
31336  {NULL, NULL, ARM_ARCH_NONE, NULL}
31337};
31338
31339struct arm_cpu_option_table
31340{
31341  const char *           name;
31342  size_t                 name_len;
31343  const arm_feature_set	 value;
31344  const arm_feature_set	 ext;
31345  /* For some CPUs we assume an FPU unless the user explicitly sets
31346     -mfpu=...	*/
31347  const arm_feature_set	 default_fpu;
31348  /* The canonical name of the CPU, or NULL to use NAME converted to upper
31349     case.  */
31350  const char *           canonical_name;
31351};
31352
31353/* This list should, at a minimum, contain all the cpu names
31354   recognized by GCC.  */
31355#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31356
31357static const struct arm_cpu_option_table arm_cpus[] =
31358{
31359  ARM_CPU_OPT ("all",		  NULL,		       ARM_ANY,
31360	       ARM_ARCH_NONE,
31361	       FPU_ARCH_FPA),
31362  ARM_CPU_OPT ("arm1",		  NULL,		       ARM_ARCH_V1,
31363	       ARM_ARCH_NONE,
31364	       FPU_ARCH_FPA),
31365  ARM_CPU_OPT ("arm2",		  NULL,		       ARM_ARCH_V2,
31366	       ARM_ARCH_NONE,
31367	       FPU_ARCH_FPA),
31368  ARM_CPU_OPT ("arm250",	  NULL,		       ARM_ARCH_V2S,
31369	       ARM_ARCH_NONE,
31370	       FPU_ARCH_FPA),
31371  ARM_CPU_OPT ("arm3",		  NULL,		       ARM_ARCH_V2S,
31372	       ARM_ARCH_NONE,
31373	       FPU_ARCH_FPA),
31374  ARM_CPU_OPT ("arm6",		  NULL,		       ARM_ARCH_V3,
31375	       ARM_ARCH_NONE,
31376	       FPU_ARCH_FPA),
31377  ARM_CPU_OPT ("arm60",		  NULL,		       ARM_ARCH_V3,
31378	       ARM_ARCH_NONE,
31379	       FPU_ARCH_FPA),
31380  ARM_CPU_OPT ("arm600",	  NULL,		       ARM_ARCH_V3,
31381	       ARM_ARCH_NONE,
31382	       FPU_ARCH_FPA),
31383  ARM_CPU_OPT ("arm610",	  NULL,		       ARM_ARCH_V3,
31384	       ARM_ARCH_NONE,
31385	       FPU_ARCH_FPA),
31386  ARM_CPU_OPT ("arm620",	  NULL,		       ARM_ARCH_V3,
31387	       ARM_ARCH_NONE,
31388	       FPU_ARCH_FPA),
31389  ARM_CPU_OPT ("arm7",		  NULL,		       ARM_ARCH_V3,
31390	       ARM_ARCH_NONE,
31391	       FPU_ARCH_FPA),
31392  ARM_CPU_OPT ("arm7m",		  NULL,		       ARM_ARCH_V3M,
31393	       ARM_ARCH_NONE,
31394	       FPU_ARCH_FPA),
31395  ARM_CPU_OPT ("arm7d",		  NULL,		       ARM_ARCH_V3,
31396	       ARM_ARCH_NONE,
31397	       FPU_ARCH_FPA),
31398  ARM_CPU_OPT ("arm7dm",	  NULL,		       ARM_ARCH_V3M,
31399	       ARM_ARCH_NONE,
31400	       FPU_ARCH_FPA),
31401  ARM_CPU_OPT ("arm7di",	  NULL,		       ARM_ARCH_V3,
31402	       ARM_ARCH_NONE,
31403	       FPU_ARCH_FPA),
31404  ARM_CPU_OPT ("arm7dmi",	  NULL,		       ARM_ARCH_V3M,
31405	       ARM_ARCH_NONE,
31406	       FPU_ARCH_FPA),
31407  ARM_CPU_OPT ("arm70",		  NULL,		       ARM_ARCH_V3,
31408	       ARM_ARCH_NONE,
31409	       FPU_ARCH_FPA),
31410  ARM_CPU_OPT ("arm700",	  NULL,		       ARM_ARCH_V3,
31411	       ARM_ARCH_NONE,
31412	       FPU_ARCH_FPA),
31413  ARM_CPU_OPT ("arm700i",	  NULL,		       ARM_ARCH_V3,
31414	       ARM_ARCH_NONE,
31415	       FPU_ARCH_FPA),
31416  ARM_CPU_OPT ("arm710",	  NULL,		       ARM_ARCH_V3,
31417	       ARM_ARCH_NONE,
31418	       FPU_ARCH_FPA),
31419  ARM_CPU_OPT ("arm710t",	  NULL,		       ARM_ARCH_V4T,
31420	       ARM_ARCH_NONE,
31421	       FPU_ARCH_FPA),
31422  ARM_CPU_OPT ("arm720",	  NULL,		       ARM_ARCH_V3,
31423	       ARM_ARCH_NONE,
31424	       FPU_ARCH_FPA),
31425  ARM_CPU_OPT ("arm720t",	  NULL,		       ARM_ARCH_V4T,
31426	       ARM_ARCH_NONE,
31427	       FPU_ARCH_FPA),
31428  ARM_CPU_OPT ("arm740t",	  NULL,		       ARM_ARCH_V4T,
31429	       ARM_ARCH_NONE,
31430	       FPU_ARCH_FPA),
31431  ARM_CPU_OPT ("arm710c",	  NULL,		       ARM_ARCH_V3,
31432	       ARM_ARCH_NONE,
31433	       FPU_ARCH_FPA),
31434  ARM_CPU_OPT ("arm7100",	  NULL,		       ARM_ARCH_V3,
31435	       ARM_ARCH_NONE,
31436	       FPU_ARCH_FPA),
31437  ARM_CPU_OPT ("arm7500",	  NULL,		       ARM_ARCH_V3,
31438	       ARM_ARCH_NONE,
31439	       FPU_ARCH_FPA),
31440  ARM_CPU_OPT ("arm7500fe",	  NULL,		       ARM_ARCH_V3,
31441	       ARM_ARCH_NONE,
31442	       FPU_ARCH_FPA),
31443  ARM_CPU_OPT ("arm7t",		  NULL,		       ARM_ARCH_V4T,
31444	       ARM_ARCH_NONE,
31445	       FPU_ARCH_FPA),
31446  ARM_CPU_OPT ("arm7tdmi",	  NULL,		       ARM_ARCH_V4T,
31447	       ARM_ARCH_NONE,
31448	       FPU_ARCH_FPA),
31449  ARM_CPU_OPT ("arm7tdmi-s",	  NULL,		       ARM_ARCH_V4T,
31450	       ARM_ARCH_NONE,
31451	       FPU_ARCH_FPA),
31452  ARM_CPU_OPT ("arm8",		  NULL,		       ARM_ARCH_V4,
31453	       ARM_ARCH_NONE,
31454	       FPU_ARCH_FPA),
31455  ARM_CPU_OPT ("arm810",	  NULL,		       ARM_ARCH_V4,
31456	       ARM_ARCH_NONE,
31457	       FPU_ARCH_FPA),
31458  ARM_CPU_OPT ("strongarm",	  NULL,		       ARM_ARCH_V4,
31459	       ARM_ARCH_NONE,
31460	       FPU_ARCH_FPA),
31461  ARM_CPU_OPT ("strongarm1",	  NULL,		       ARM_ARCH_V4,
31462	       ARM_ARCH_NONE,
31463	       FPU_ARCH_FPA),
31464  ARM_CPU_OPT ("strongarm110",	  NULL,		       ARM_ARCH_V4,
31465	       ARM_ARCH_NONE,
31466	       FPU_ARCH_FPA),
31467  ARM_CPU_OPT ("strongarm1100",	  NULL,		       ARM_ARCH_V4,
31468	       ARM_ARCH_NONE,
31469	       FPU_ARCH_FPA),
31470  ARM_CPU_OPT ("strongarm1110",	  NULL,		       ARM_ARCH_V4,
31471	       ARM_ARCH_NONE,
31472	       FPU_ARCH_FPA),
31473  ARM_CPU_OPT ("arm9",		  NULL,		       ARM_ARCH_V4T,
31474	       ARM_ARCH_NONE,
31475	       FPU_ARCH_FPA),
31476  ARM_CPU_OPT ("arm920",	  "ARM920T",	       ARM_ARCH_V4T,
31477	       ARM_ARCH_NONE,
31478	       FPU_ARCH_FPA),
31479  ARM_CPU_OPT ("arm920t",	  NULL,		       ARM_ARCH_V4T,
31480	       ARM_ARCH_NONE,
31481	       FPU_ARCH_FPA),
31482  ARM_CPU_OPT ("arm922t",	  NULL,		       ARM_ARCH_V4T,
31483	       ARM_ARCH_NONE,
31484	       FPU_ARCH_FPA),
31485  ARM_CPU_OPT ("arm940t",	  NULL,		       ARM_ARCH_V4T,
31486	       ARM_ARCH_NONE,
31487	       FPU_ARCH_FPA),
31488  ARM_CPU_OPT ("arm9tdmi",	  NULL,		       ARM_ARCH_V4T,
31489	       ARM_ARCH_NONE,
31490	       FPU_ARCH_FPA),
31491  ARM_CPU_OPT ("fa526",		  NULL,		       ARM_ARCH_V4,
31492	       ARM_ARCH_NONE,
31493	       FPU_ARCH_FPA),
31494  ARM_CPU_OPT ("fa626",		  NULL,		       ARM_ARCH_V4,
31495	       ARM_ARCH_NONE,
31496	       FPU_ARCH_FPA),
31497
31498  /* For V5 or later processors we default to using VFP; but the user
31499     should really set the FPU type explicitly.	 */
31500  ARM_CPU_OPT ("arm9e-r0",	  NULL,		       ARM_ARCH_V5TExP,
31501	       ARM_ARCH_NONE,
31502	       FPU_ARCH_VFP_V2),
31503  ARM_CPU_OPT ("arm9e",		  NULL,		       ARM_ARCH_V5TE,
31504	       ARM_ARCH_NONE,
31505	       FPU_ARCH_VFP_V2),
31506  ARM_CPU_OPT ("arm926ej",	  "ARM926EJ-S",	       ARM_ARCH_V5TEJ,
31507	       ARM_ARCH_NONE,
31508	       FPU_ARCH_VFP_V2),
31509  ARM_CPU_OPT ("arm926ejs",	  "ARM926EJ-S",	       ARM_ARCH_V5TEJ,
31510	       ARM_ARCH_NONE,
31511	       FPU_ARCH_VFP_V2),
31512  ARM_CPU_OPT ("arm926ej-s",	  NULL,		       ARM_ARCH_V5TEJ,
31513	       ARM_ARCH_NONE,
31514	       FPU_ARCH_VFP_V2),
31515  ARM_CPU_OPT ("arm946e-r0",	  NULL,		       ARM_ARCH_V5TExP,
31516	       ARM_ARCH_NONE,
31517	       FPU_ARCH_VFP_V2),
31518  ARM_CPU_OPT ("arm946e",	  "ARM946E-S",	       ARM_ARCH_V5TE,
31519	       ARM_ARCH_NONE,
31520	       FPU_ARCH_VFP_V2),
31521  ARM_CPU_OPT ("arm946e-s",	  NULL,		       ARM_ARCH_V5TE,
31522	       ARM_ARCH_NONE,
31523	       FPU_ARCH_VFP_V2),
31524  ARM_CPU_OPT ("arm966e-r0",	  NULL,		       ARM_ARCH_V5TExP,
31525	       ARM_ARCH_NONE,
31526	       FPU_ARCH_VFP_V2),
31527  ARM_CPU_OPT ("arm966e",	  "ARM966E-S",	       ARM_ARCH_V5TE,
31528	       ARM_ARCH_NONE,
31529	       FPU_ARCH_VFP_V2),
31530  ARM_CPU_OPT ("arm966e-s",	  NULL,		       ARM_ARCH_V5TE,
31531	       ARM_ARCH_NONE,
31532	       FPU_ARCH_VFP_V2),
31533  ARM_CPU_OPT ("arm968e-s",	  NULL,		       ARM_ARCH_V5TE,
31534	       ARM_ARCH_NONE,
31535	       FPU_ARCH_VFP_V2),
31536  ARM_CPU_OPT ("arm10t",	  NULL,		       ARM_ARCH_V5T,
31537	       ARM_ARCH_NONE,
31538	       FPU_ARCH_VFP_V1),
31539  ARM_CPU_OPT ("arm10tdmi",	  NULL,		       ARM_ARCH_V5T,
31540	       ARM_ARCH_NONE,
31541	       FPU_ARCH_VFP_V1),
31542  ARM_CPU_OPT ("arm10e",	  NULL,		       ARM_ARCH_V5TE,
31543	       ARM_ARCH_NONE,
31544	       FPU_ARCH_VFP_V2),
31545  ARM_CPU_OPT ("arm1020",	  "ARM1020E",	       ARM_ARCH_V5TE,
31546	       ARM_ARCH_NONE,
31547	       FPU_ARCH_VFP_V2),
31548  ARM_CPU_OPT ("arm1020t",	  NULL,		       ARM_ARCH_V5T,
31549	       ARM_ARCH_NONE,
31550	       FPU_ARCH_VFP_V1),
31551  ARM_CPU_OPT ("arm1020e",	  NULL,		       ARM_ARCH_V5TE,
31552	       ARM_ARCH_NONE,
31553	       FPU_ARCH_VFP_V2),
31554  ARM_CPU_OPT ("arm1022e",	  NULL,		       ARM_ARCH_V5TE,
31555	       ARM_ARCH_NONE,
31556	       FPU_ARCH_VFP_V2),
31557  ARM_CPU_OPT ("arm1026ejs",	  "ARM1026EJ-S",       ARM_ARCH_V5TEJ,
31558	       ARM_ARCH_NONE,
31559	       FPU_ARCH_VFP_V2),
31560  ARM_CPU_OPT ("arm1026ej-s",	  NULL,		       ARM_ARCH_V5TEJ,
31561	       ARM_ARCH_NONE,
31562	       FPU_ARCH_VFP_V2),
31563  ARM_CPU_OPT ("fa606te",	  NULL,		       ARM_ARCH_V5TE,
31564	       ARM_ARCH_NONE,
31565	       FPU_ARCH_VFP_V2),
31566  ARM_CPU_OPT ("fa616te",	  NULL,		       ARM_ARCH_V5TE,
31567	       ARM_ARCH_NONE,
31568	       FPU_ARCH_VFP_V2),
31569  ARM_CPU_OPT ("fa626te",	  NULL,		       ARM_ARCH_V5TE,
31570	       ARM_ARCH_NONE,
31571	       FPU_ARCH_VFP_V2),
31572  ARM_CPU_OPT ("fmp626",	  NULL,		       ARM_ARCH_V5TE,
31573	       ARM_ARCH_NONE,
31574	       FPU_ARCH_VFP_V2),
31575  ARM_CPU_OPT ("fa726te",	  NULL,		       ARM_ARCH_V5TE,
31576	       ARM_ARCH_NONE,
31577	       FPU_ARCH_VFP_V2),
31578  ARM_CPU_OPT ("arm1136js",	  "ARM1136J-S",	       ARM_ARCH_V6,
31579	       ARM_ARCH_NONE,
31580	       FPU_NONE),
31581  ARM_CPU_OPT ("arm1136j-s",	  NULL,		       ARM_ARCH_V6,
31582	       ARM_ARCH_NONE,
31583	       FPU_NONE),
31584  ARM_CPU_OPT ("arm1136jfs",	  "ARM1136JF-S",       ARM_ARCH_V6,
31585	       ARM_ARCH_NONE,
31586	       FPU_ARCH_VFP_V2),
31587  ARM_CPU_OPT ("arm1136jf-s",	  NULL,		       ARM_ARCH_V6,
31588	       ARM_ARCH_NONE,
31589	       FPU_ARCH_VFP_V2),
31590  ARM_CPU_OPT ("mpcore",	  "MPCore",	       ARM_ARCH_V6K,
31591	       ARM_ARCH_NONE,
31592	       FPU_ARCH_VFP_V2),
31593  ARM_CPU_OPT ("mpcorenovfp",	  "MPCore",	       ARM_ARCH_V6K,
31594	       ARM_ARCH_NONE,
31595	       FPU_NONE),
31596  ARM_CPU_OPT ("arm1156t2-s",	  NULL,		       ARM_ARCH_V6T2,
31597	       ARM_ARCH_NONE,
31598	       FPU_NONE),
31599  ARM_CPU_OPT ("arm1156t2f-s",	  NULL,		       ARM_ARCH_V6T2,
31600	       ARM_ARCH_NONE,
31601	       FPU_ARCH_VFP_V2),
31602  ARM_CPU_OPT ("arm1176jz-s",	  NULL,		       ARM_ARCH_V6KZ,
31603	       ARM_ARCH_NONE,
31604	       FPU_NONE),
31605  ARM_CPU_OPT ("arm1176jzf-s",	  NULL,		       ARM_ARCH_V6KZ,
31606	       ARM_ARCH_NONE,
31607	       FPU_ARCH_VFP_V2),
31608  ARM_CPU_OPT ("cortex-a5",	  "Cortex-A5",	       ARM_ARCH_V7A,
31609	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31610	       FPU_NONE),
31611  ARM_CPU_OPT ("cortex-a7",	  "Cortex-A7",	       ARM_ARCH_V7VE,
31612	       ARM_ARCH_NONE,
31613	       FPU_ARCH_NEON_VFP_V4),
31614  ARM_CPU_OPT ("cortex-a8",	  "Cortex-A8",	       ARM_ARCH_V7A,
31615	       ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
31616	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
31617  ARM_CPU_OPT ("cortex-a9",	  "Cortex-A9",	       ARM_ARCH_V7A,
31618	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31619	       ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
31620  ARM_CPU_OPT ("cortex-a12",	  "Cortex-A12",	       ARM_ARCH_V7VE,
31621	       ARM_ARCH_NONE,
31622	       FPU_ARCH_NEON_VFP_V4),
31623  ARM_CPU_OPT ("cortex-a15",	  "Cortex-A15",	       ARM_ARCH_V7VE,
31624	       ARM_ARCH_NONE,
31625	       FPU_ARCH_NEON_VFP_V4),
31626  ARM_CPU_OPT ("cortex-a17",	  "Cortex-A17",	       ARM_ARCH_V7VE,
31627	       ARM_ARCH_NONE,
31628	       FPU_ARCH_NEON_VFP_V4),
31629  ARM_CPU_OPT ("cortex-a32",	  "Cortex-A32",	       ARM_ARCH_V8A,
31630	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31631	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31632  ARM_CPU_OPT ("cortex-a35",	  "Cortex-A35",	       ARM_ARCH_V8A,
31633	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31634	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31635  ARM_CPU_OPT ("cortex-a53",	  "Cortex-A53",	       ARM_ARCH_V8A,
31636	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31637	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31638  ARM_CPU_OPT ("cortex-a55",    "Cortex-A55",	       ARM_ARCH_V8_2A,
31639	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31640	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31641  ARM_CPU_OPT ("cortex-a57",	  "Cortex-A57",	       ARM_ARCH_V8A,
31642	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31643	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31644  ARM_CPU_OPT ("cortex-a72",	  "Cortex-A72",	       ARM_ARCH_V8A,
31645	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31646	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31647  ARM_CPU_OPT ("cortex-a73",	  "Cortex-A73",	       ARM_ARCH_V8A,
31648	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31649	      FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31650  ARM_CPU_OPT ("cortex-a75",    "Cortex-A75",	       ARM_ARCH_V8_2A,
31651	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31652	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31653  ARM_CPU_OPT ("cortex-a76",    "Cortex-A76",	       ARM_ARCH_V8_2A,
31654	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31655	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31656  ARM_CPU_OPT ("cortex-a76ae",    "Cortex-A76AE",      ARM_ARCH_V8_2A,
31657	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31658	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31659  ARM_CPU_OPT ("cortex-a77",    "Cortex-A77",	       ARM_ARCH_V8_2A,
31660	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31661	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31662  ARM_CPU_OPT ("cortex-a78",   "Cortex-A78",	       ARM_ARCH_V8_2A,
31663	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
31664	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31665  ARM_CPU_OPT ("cortex-a78ae",   "Cortex-A78AE",	   ARM_ARCH_V8_2A,
31666	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
31667	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31668  ARM_CPU_OPT ("cortex-a78c",   "Cortex-A78C",	   ARM_ARCH_V8_2A,
31669	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
31670	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31671  ARM_CPU_OPT ("cortex-a710",   "Cortex-A710",	   ARM_ARCH_V9A,
31672	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31673				    | ARM_EXT2_BF16
31674				    | ARM_EXT2_I8MM),
31675	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31676  ARM_CPU_OPT ("ares",    "Ares",	       ARM_ARCH_V8_2A,
31677	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31678	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31679  ARM_CPU_OPT ("cortex-r4",	  "Cortex-R4",	       ARM_ARCH_V7R,
31680	       ARM_ARCH_NONE,
31681	       FPU_NONE),
31682  ARM_CPU_OPT ("cortex-r4f",	  "Cortex-R4F",	       ARM_ARCH_V7R,
31683	       ARM_ARCH_NONE,
31684	       FPU_ARCH_VFP_V3D16),
31685  ARM_CPU_OPT ("cortex-r5",	  "Cortex-R5",	       ARM_ARCH_V7R,
31686	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
31687	       FPU_NONE),
31688  ARM_CPU_OPT ("cortex-r7",	  "Cortex-R7",	       ARM_ARCH_V7R,
31689	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
31690	       FPU_ARCH_VFP_V3D16),
31691  ARM_CPU_OPT ("cortex-r8",	  "Cortex-R8",	       ARM_ARCH_V7R,
31692	       ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
31693	       FPU_ARCH_VFP_V3D16),
31694  ARM_CPU_OPT ("cortex-r52",	  "Cortex-R52",	       ARM_ARCH_V8R,
31695	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31696	      FPU_ARCH_NEON_VFP_ARMV8),
31697  ARM_CPU_OPT ("cortex-r52plus",	  "Cortex-R52+",	       ARM_ARCH_V8R,
31698	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31699	      FPU_ARCH_NEON_VFP_ARMV8),
31700  ARM_CPU_OPT ("cortex-m35p",	  "Cortex-M35P",       ARM_ARCH_V8M_MAIN,
31701	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31702	       FPU_NONE),
31703  ARM_CPU_OPT ("cortex-m33",	  "Cortex-M33",	       ARM_ARCH_V8M_MAIN,
31704	       ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31705	       FPU_NONE),
31706  ARM_CPU_OPT ("cortex-m23",	  "Cortex-M23",	       ARM_ARCH_V8M_BASE,
31707	       ARM_ARCH_NONE,
31708	       FPU_NONE),
31709  ARM_CPU_OPT ("cortex-m7",	  "Cortex-M7",	       ARM_ARCH_V7EM,
31710	       ARM_ARCH_NONE,
31711	       FPU_NONE),
31712  ARM_CPU_OPT ("cortex-m4",	  "Cortex-M4",	       ARM_ARCH_V7EM,
31713	       ARM_ARCH_NONE,
31714	       FPU_NONE),
31715  ARM_CPU_OPT ("cortex-m3",	  "Cortex-M3",	       ARM_ARCH_V7M,
31716	       ARM_ARCH_NONE,
31717	       FPU_NONE),
31718  ARM_CPU_OPT ("cortex-m1",	  "Cortex-M1",	       ARM_ARCH_V6SM,
31719	       ARM_ARCH_NONE,
31720	       FPU_NONE),
31721  ARM_CPU_OPT ("cortex-m0",	  "Cortex-M0",	       ARM_ARCH_V6SM,
31722	       ARM_ARCH_NONE,
31723	       FPU_NONE),
31724  ARM_CPU_OPT ("cortex-m0plus",	  "Cortex-M0+",	       ARM_ARCH_V6SM,
31725	       ARM_ARCH_NONE,
31726	       FPU_NONE),
31727  ARM_CPU_OPT ("cortex-x1",   "Cortex-X1",	       ARM_ARCH_V8_2A,
31728	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST | ARM_EXT2_SB),
31729	       FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31730  ARM_CPU_OPT ("exynos-m1",	  "Samsung Exynos M1", ARM_ARCH_V8A,
31731	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31732	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31733  ARM_CPU_OPT ("neoverse-n1",    "Neoverse N1",	       ARM_ARCH_V8_2A,
31734	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31735	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
31736  ARM_CPU_OPT ("neoverse-n2",	 "Neoverse N2",	       ARM_ARCH_V8_5A,
31737	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31738				    | ARM_EXT2_BF16
31739				    | ARM_EXT2_I8MM),
31740	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
31741  ARM_CPU_OPT ("neoverse-v1", "Neoverse V1", ARM_ARCH_V8_4A,
31742	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31743				    | ARM_EXT2_BF16
31744				    | ARM_EXT2_I8MM),
31745	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4),
31746  /* ??? XSCALE is really an architecture.  */
31747  ARM_CPU_OPT ("xscale",	  NULL,		       ARM_ARCH_XSCALE,
31748	       ARM_ARCH_NONE,
31749	       FPU_ARCH_VFP_V2),
31750
31751  /* ??? iwmmxt is not a processor.  */
31752  ARM_CPU_OPT ("iwmmxt",	  NULL,		       ARM_ARCH_IWMMXT,
31753	       ARM_ARCH_NONE,
31754	       FPU_ARCH_VFP_V2),
31755  ARM_CPU_OPT ("iwmmxt2",	  NULL,		       ARM_ARCH_IWMMXT2,
31756	       ARM_ARCH_NONE,
31757	       FPU_ARCH_VFP_V2),
31758  ARM_CPU_OPT ("i80200",	  NULL,		       ARM_ARCH_XSCALE,
31759	       ARM_ARCH_NONE,
31760	       FPU_ARCH_VFP_V2),
31761
31762  /* Maverick.  */
31763  ARM_CPU_OPT ("ep9312",	  "ARM920T",
31764	       ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
31765	       ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
31766
31767  /* Marvell processors.  */
31768  ARM_CPU_OPT ("marvell-pj4",	  NULL,		       ARM_ARCH_V7A,
31769	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31770	       FPU_ARCH_VFP_V3D16),
31771  ARM_CPU_OPT ("marvell-whitney", NULL,		       ARM_ARCH_V7A,
31772	       ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
31773	       FPU_ARCH_NEON_VFP_V4),
31774
31775  /* APM X-Gene family.  */
31776  ARM_CPU_OPT ("xgene1",	  "APM X-Gene 1",      ARM_ARCH_V8A,
31777	       ARM_ARCH_NONE,
31778	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31779  ARM_CPU_OPT ("xgene2",	  "APM X-Gene 2",      ARM_ARCH_V8A,
31780	       ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC),
31781	       FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
31782
31783  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
31784};
31785#undef ARM_CPU_OPT
31786
31787struct arm_ext_table
31788{
31789  const char *		  name;
31790  size_t		  name_len;
31791  const arm_feature_set	  merge;
31792  const arm_feature_set	  clear;
31793};
31794
31795struct arm_arch_option_table
31796{
31797  const char *			name;
31798  size_t			name_len;
31799  const arm_feature_set		value;
31800  const arm_feature_set		default_fpu;
31801  const struct arm_ext_table *	ext_table;
31802};
31803
31804/* Used to add support for +E and +noE extension.  */
31805#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31806/* Used to add support for a +E extension.  */
31807#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31808/* Used to add support for a +noE extension.  */
31809#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31810
31811#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31812			    ~0 & ~FPU_ENDIAN_PURE)
31813
31814static const struct arm_ext_table armv5te_ext_table[] =
31815{
31816  ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
31817  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31818};
31819
31820static const struct arm_ext_table armv7_ext_table[] =
31821{
31822  ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
31823  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31824};
31825
31826static const struct arm_ext_table armv7ve_ext_table[] =
31827{
31828  ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
31829  ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
31830  ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
31831  ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
31832  ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
31833  ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),  /* Alias for +fp.  */
31834  ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
31835
31836  ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
31837	   ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
31838
31839  /* Aliases for +simd.  */
31840  ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
31841
31842  ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31843  ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31844  ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
31845
31846  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31847};
31848
31849static const struct arm_ext_table armv7a_ext_table[] =
31850{
31851  ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
31852  ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp.  */
31853  ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
31854  ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
31855  ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
31856  ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
31857  ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
31858
31859  ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
31860	   ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
31861
31862  /* Aliases for +simd.  */
31863  ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31864  ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
31865
31866  ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
31867  ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
31868
31869  ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
31870  ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
31871  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31872};
31873
31874static const struct arm_ext_table armv7r_ext_table[] =
31875{
31876  ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
31877  ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp.  */
31878  ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
31879  ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp.  */
31880  ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
31881  ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
31882  ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
31883	   ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
31884  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31885};
31886
31887static const struct arm_ext_table armv7em_ext_table[] =
31888{
31889  ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
31890  /* Alias for +fp, used to be known as fpv4-sp-d16.  */
31891  ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
31892  ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
31893  ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
31894  ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
31895  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31896};
31897
31898static const struct arm_ext_table armv8a_ext_table[] =
31899{
31900  ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC)),
31901  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
31902  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
31903	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31904
31905  /* Armv8-a does not allow an FP implementation without SIMD, so the user
31906     should use the +simd option to turn on FP.  */
31907  ARM_REMOVE ("fp", ALL_FP),
31908  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31909  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31910  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31911};
31912
31913
31914static const struct arm_ext_table armv81a_ext_table[] =
31915{
31916  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
31917  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
31918	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31919
31920  /* Armv8-a does not allow an FP implementation without SIMD, so the user
31921     should use the +simd option to turn on FP.  */
31922  ARM_REMOVE ("fp", ALL_FP),
31923  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31924  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31925  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31926};
31927
31928static const struct arm_ext_table armv82a_ext_table[] =
31929{
31930  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
31931  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
31932  ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
31933  ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31934  ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
31935  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
31936	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31937  ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31938
31939  /* Armv8-a does not allow an FP implementation without SIMD, so the user
31940     should use the +simd option to turn on FP.  */
31941  ARM_REMOVE ("fp", ALL_FP),
31942  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31943  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31944  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31945};
31946
31947static const struct arm_ext_table armv84a_ext_table[] =
31948{
31949  ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31950  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
31951  ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31952  ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
31953  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
31954	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31955
31956  /* Armv8-a does not allow an FP implementation without SIMD, so the user
31957     should use the +simd option to turn on FP.  */
31958  ARM_REMOVE ("fp", ALL_FP),
31959  ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
31960  ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
31961  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31962};
31963
31964static const struct arm_ext_table armv85a_ext_table[] =
31965{
31966  ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31967  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
31968  ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31969  ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
31970  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
31971	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31972
31973  /* Armv8-a does not allow an FP implementation without SIMD, so the user
31974     should use the +simd option to turn on FP.  */
31975  ARM_REMOVE ("fp", ALL_FP),
31976  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31977};
31978
31979static const struct arm_ext_table armv86a_ext_table[] =
31980{
31981  ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
31982  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
31983};
31984
31985#define armv87a_ext_table armv86a_ext_table
31986#define armv88a_ext_table armv87a_ext_table
31987
31988static const struct arm_ext_table armv9a_ext_table[] =
31989{
31990  ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
31991  ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
31992  ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16)),
31993  ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM)),
31994  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
31995	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
31996
31997  /* Armv9-a does not allow an FP implementation without SIMD, so the user
31998     should use the +simd option to turn on FP.  */
31999  ARM_REMOVE ("fp", ALL_FP),
32000  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
32001};
32002
32003#define armv91a_ext_table armv86a_ext_table
32004#define armv92a_ext_table armv91a_ext_table
32005#define armv93a_ext_table armv92a_ext_table
32006
32007#define CDE_EXTENSIONS \
32008  ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
32009  ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
32010  ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
32011  ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
32012  ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
32013  ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
32014  ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
32015  ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
32016
32017static const struct arm_ext_table armv8m_main_ext_table[] =
32018{
32019  ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
32020		  ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
32021  ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
32022  ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
32023  CDE_EXTENSIONS,
32024  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
32025};
32026
32027
32028static const struct arm_ext_table armv8_1m_main_ext_table[] =
32029{
32030  ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP),
32031		  ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP)),
32032  ARM_EXT ("fp",
32033	   ARM_FEATURE (0, ARM_EXT2_FP16_INST,
32034			FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
32035	   ALL_FP),
32036  ARM_ADD ("fp.dp",
32037	   ARM_FEATURE (0, ARM_EXT2_FP16_INST,
32038			FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
32039  ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP, ARM_EXT2_MVE, 0),
32040	   ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE | ARM_EXT2_MVE_FP)),
32041  ARM_ADD ("mve.fp",
32042	   ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP,
32043			ARM_EXT2_FP16_INST | ARM_EXT2_MVE | ARM_EXT2_MVE_FP,
32044			FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
32045  CDE_EXTENSIONS,
32046  ARM_ADD ("pacbti", ARM_FEATURE_CORE_HIGH_HIGH (ARM_AEXT3_V8_1M_MAIN_PACBTI)),
32047  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
32048};
32049
32050#undef CDE_EXTENSIONS
32051
32052static const struct arm_ext_table armv8r_ext_table[] =
32053{
32054  ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC)),
32055  ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
32056  ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
32057	   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
32058  ARM_REMOVE ("fp", ALL_FP),
32059  ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
32060  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
32061};
32062
32063/* This list should, at a minimum, contain all the architecture names
32064   recognized by GCC.  */
32065#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
32066#define ARM_ARCH_OPT2(N, V, DF, ext) \
32067  { N, sizeof (N) - 1, V, DF, ext##_ext_table }
32068
32069static const struct arm_arch_option_table arm_archs[] =
32070{
32071  ARM_ARCH_OPT ("all",		  ARM_ANY,		FPU_ARCH_FPA),
32072  ARM_ARCH_OPT ("armv1",	  ARM_ARCH_V1,		FPU_ARCH_FPA),
32073  ARM_ARCH_OPT ("armv2",	  ARM_ARCH_V2,		FPU_ARCH_FPA),
32074  ARM_ARCH_OPT ("armv2a",	  ARM_ARCH_V2S,		FPU_ARCH_FPA),
32075  ARM_ARCH_OPT ("armv2s",	  ARM_ARCH_V2S,		FPU_ARCH_FPA),
32076  ARM_ARCH_OPT ("armv3",	  ARM_ARCH_V3,		FPU_ARCH_FPA),
32077  ARM_ARCH_OPT ("armv3m",	  ARM_ARCH_V3M,		FPU_ARCH_FPA),
32078  ARM_ARCH_OPT ("armv4",	  ARM_ARCH_V4,		FPU_ARCH_FPA),
32079  ARM_ARCH_OPT ("armv4xm",	  ARM_ARCH_V4xM,	FPU_ARCH_FPA),
32080  ARM_ARCH_OPT ("armv4t",	  ARM_ARCH_V4T,		FPU_ARCH_FPA),
32081  ARM_ARCH_OPT ("armv4txm",	  ARM_ARCH_V4TxM,	FPU_ARCH_FPA),
32082  ARM_ARCH_OPT ("armv5",	  ARM_ARCH_V5,		FPU_ARCH_VFP),
32083  ARM_ARCH_OPT ("armv5t",	  ARM_ARCH_V5T,		FPU_ARCH_VFP),
32084  ARM_ARCH_OPT ("armv5txm",	  ARM_ARCH_V5TxM,	FPU_ARCH_VFP),
32085  ARM_ARCH_OPT2 ("armv5te",	  ARM_ARCH_V5TE,	FPU_ARCH_VFP,	armv5te),
32086  ARM_ARCH_OPT2 ("armv5texp",	  ARM_ARCH_V5TExP,	FPU_ARCH_VFP, armv5te),
32087  ARM_ARCH_OPT2 ("armv5tej",	  ARM_ARCH_V5TEJ,	FPU_ARCH_VFP,	armv5te),
32088  ARM_ARCH_OPT2 ("armv6",	  ARM_ARCH_V6,		FPU_ARCH_VFP,	armv5te),
32089  ARM_ARCH_OPT2 ("armv6j",	  ARM_ARCH_V6,		FPU_ARCH_VFP,	armv5te),
32090  ARM_ARCH_OPT2 ("armv6k",	  ARM_ARCH_V6K,		FPU_ARCH_VFP,	armv5te),
32091  ARM_ARCH_OPT2 ("armv6z",	  ARM_ARCH_V6Z,		FPU_ARCH_VFP,	armv5te),
32092  /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
32093     kept to preserve existing behaviour.  */
32094  ARM_ARCH_OPT2 ("armv6kz",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP,	armv5te),
32095  ARM_ARCH_OPT2 ("armv6zk",	  ARM_ARCH_V6KZ,	FPU_ARCH_VFP,	armv5te),
32096  ARM_ARCH_OPT2 ("armv6t2",	  ARM_ARCH_V6T2,	FPU_ARCH_VFP,	armv5te),
32097  ARM_ARCH_OPT2 ("armv6kt2",	  ARM_ARCH_V6KT2,	FPU_ARCH_VFP,	armv5te),
32098  ARM_ARCH_OPT2 ("armv6zt2",	  ARM_ARCH_V6ZT2,	FPU_ARCH_VFP,	armv5te),
32099  /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
32100     kept to preserve existing behaviour.  */
32101  ARM_ARCH_OPT2 ("armv6kzt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP,	armv5te),
32102  ARM_ARCH_OPT2 ("armv6zkt2",	  ARM_ARCH_V6KZT2,	FPU_ARCH_VFP,	armv5te),
32103  ARM_ARCH_OPT ("armv6-m",	  ARM_ARCH_V6M,		FPU_ARCH_VFP),
32104  ARM_ARCH_OPT ("armv6s-m",	  ARM_ARCH_V6SM,	FPU_ARCH_VFP),
32105  ARM_ARCH_OPT2 ("armv7",	  ARM_ARCH_V7,		FPU_ARCH_VFP, armv7),
32106  /* The official spelling of the ARMv7 profile variants is the dashed form.
32107     Accept the non-dashed form for compatibility with old toolchains.  */
32108  ARM_ARCH_OPT2 ("armv7a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP, armv7a),
32109  ARM_ARCH_OPT2 ("armv7ve",	  ARM_ARCH_V7VE,	FPU_ARCH_VFP, armv7ve),
32110  ARM_ARCH_OPT2 ("armv7r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP, armv7r),
32111  ARM_ARCH_OPT ("armv7m",	  ARM_ARCH_V7M,		FPU_ARCH_VFP),
32112  ARM_ARCH_OPT2 ("armv7-a",	  ARM_ARCH_V7A,		FPU_ARCH_VFP, armv7a),
32113  ARM_ARCH_OPT2 ("armv7-r",	  ARM_ARCH_V7R,		FPU_ARCH_VFP, armv7r),
32114  ARM_ARCH_OPT ("armv7-m",	  ARM_ARCH_V7M,		FPU_ARCH_VFP),
32115  ARM_ARCH_OPT2 ("armv7e-m",	  ARM_ARCH_V7EM,	FPU_ARCH_VFP, armv7em),
32116  ARM_ARCH_OPT ("armv8-m.base",	  ARM_ARCH_V8M_BASE,	FPU_ARCH_VFP),
32117  ARM_ARCH_OPT2 ("armv8-m.main",  ARM_ARCH_V8M_MAIN,	FPU_ARCH_VFP,
32118		 armv8m_main),
32119  ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN,	FPU_ARCH_VFP,
32120		 armv8_1m_main),
32121  ARM_ARCH_OPT2 ("armv8-a",	  ARM_ARCH_V8A,		FPU_ARCH_VFP, armv8a),
32122  ARM_ARCH_OPT2 ("armv8.1-a",	  ARM_ARCH_V8_1A,	FPU_ARCH_VFP, armv81a),
32123  ARM_ARCH_OPT2 ("armv8.2-a",	  ARM_ARCH_V8_2A,	FPU_ARCH_VFP, armv82a),
32124  ARM_ARCH_OPT2 ("armv8.3-a",	  ARM_ARCH_V8_3A,	FPU_ARCH_VFP, armv82a),
32125  ARM_ARCH_OPT2 ("armv8-r",	  ARM_ARCH_V8R,		FPU_ARCH_VFP, armv8r),
32126  ARM_ARCH_OPT2 ("armv8.4-a",	  ARM_ARCH_V8_4A,	FPU_ARCH_VFP, armv84a),
32127  ARM_ARCH_OPT2 ("armv8.5-a",	  ARM_ARCH_V8_5A,	FPU_ARCH_VFP, armv85a),
32128  ARM_ARCH_OPT2 ("armv8.6-a",	  ARM_ARCH_V8_6A,	FPU_ARCH_VFP, armv86a),
32129  ARM_ARCH_OPT2 ("armv8.7-a",	  ARM_ARCH_V8_7A,	FPU_ARCH_VFP, armv87a),
32130  ARM_ARCH_OPT2 ("armv8.8-a",	  ARM_ARCH_V8_8A,	FPU_ARCH_VFP, armv88a),
32131  ARM_ARCH_OPT2 ("armv9-a",	  ARM_ARCH_V9A,		FPU_ARCH_VFP, armv9a),
32132  ARM_ARCH_OPT2 ("armv9.1-a",	  ARM_ARCH_V9_1A,	FPU_ARCH_VFP, armv91a),
32133  ARM_ARCH_OPT2 ("armv9.2-a",	  ARM_ARCH_V9_2A,	FPU_ARCH_VFP, armv92a),
32134  ARM_ARCH_OPT2 ("armv9.3-a",	  ARM_ARCH_V9_2A,	FPU_ARCH_VFP, armv93a),
32135  ARM_ARCH_OPT ("xscale",	  ARM_ARCH_XSCALE,	FPU_ARCH_VFP),
32136  ARM_ARCH_OPT ("iwmmxt",	  ARM_ARCH_IWMMXT,	FPU_ARCH_VFP),
32137  ARM_ARCH_OPT ("iwmmxt2",	  ARM_ARCH_IWMMXT2,	FPU_ARCH_VFP),
32138  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
32139};
32140#undef ARM_ARCH_OPT
32141
32142/* ISA extensions in the co-processor and main instruction set space.  */
32143
32144struct arm_option_extension_value_table
32145{
32146  const char *           name;
32147  size_t                 name_len;
32148  const arm_feature_set  merge_value;
32149  const arm_feature_set  clear_value;
32150  /* List of architectures for which an extension is available.  ARM_ARCH_NONE
32151     indicates that an extension is available for all architectures while
32152     ARM_ANY marks an empty entry.  */
32153  const arm_feature_set  allowed_archs[2];
32154};
32155
32156/* The following table must be in alphabetical order with a NULL last entry.  */
32157
32158#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
32159#define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
32160
32161/* DEPRECATED: Refrain from using this table to add any new extensions, instead
32162   use the context sensitive approach using arm_ext_table's.  */
32163static const struct arm_option_extension_value_table arm_extensions[] =
32164{
32165  ARM_EXT_OPT ("crc",	 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC),
32166			 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC),
32167			 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
32168  ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
32169			 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
32170				   ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
32171  ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
32172			  ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
32173			  ARM_ARCH_V8_2A),
32174  ARM_EXT_OPT ("dsp",	ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
32175			ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
32176			ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
32177  ARM_EXT_OPT ("fp",     FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
32178				   ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
32179  ARM_EXT_OPT ("fp16",  ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
32180			ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
32181			ARM_ARCH_V8_2A),
32182  ARM_EXT_OPT ("fp16fml",  ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32183						  | ARM_EXT2_FP16_FML),
32184			   ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32185						  | ARM_EXT2_FP16_FML),
32186			   ARM_ARCH_V8_2A),
32187  ARM_EXT_OPT2 ("idiv",	ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
32188			ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
32189			ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
32190			ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
32191  /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
32192     Thumb divide instruction.  Due to this having the same name as the
32193     previous entry, this will be ignored when doing command-line parsing and
32194     only considered by build attribute selection code.  */
32195  ARM_EXT_OPT ("idiv",	ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
32196			ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
32197			ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
32198  ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
32199			ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
32200  ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
32201			ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
32202  ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
32203			ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
32204  ARM_EXT_OPT2 ("mp",	ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
32205			ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
32206			ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
32207			ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
32208  ARM_EXT_OPT ("os",	ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
32209			ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
32210				   ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
32211  ARM_EXT_OPT ("pan",	ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
32212			ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
32213			ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
32214  ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
32215			ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
32216			ARM_ARCH_V8A),
32217  ARM_EXT_OPT ("ras",	ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
32218			ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
32219			ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
32220  ARM_EXT_OPT ("rdma",  FPU_ARCH_NEON_VFP_ARMV8_1,
32221			ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
32222			ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
32223  ARM_EXT_OPT ("sb",	ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
32224			ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
32225			ARM_ARCH_V8A),
32226  ARM_EXT_OPT2 ("sec",	ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
32227			ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
32228			ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
32229			ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
32230  ARM_EXT_OPT ("simd",  FPU_ARCH_NEON_VFP_ARMV8,
32231			ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
32232			ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
32233  ARM_EXT_OPT ("virt",	ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
32234				     | ARM_EXT_DIV),
32235			ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
32236				   ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
32237  ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
32238			ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
32239  { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
32240};
32241#undef ARM_EXT_OPT
32242
32243/* ISA floating-point and Advanced SIMD extensions.  */
32244struct arm_option_fpu_value_table
32245{
32246  const char *           name;
32247  const arm_feature_set  value;
32248};
32249
32250/* This list should, at a minimum, contain all the fpu names
32251   recognized by GCC.  */
32252static const struct arm_option_fpu_value_table arm_fpus[] =
32253{
32254  {"softfpa",		FPU_NONE},
32255  {"fpe",		FPU_ARCH_FPE},
32256  {"fpe2",		FPU_ARCH_FPE},
32257  {"fpe3",		FPU_ARCH_FPA},	/* Third release supports LFM/SFM.  */
32258  {"fpa",		FPU_ARCH_FPA},
32259  {"fpa10",		FPU_ARCH_FPA},
32260  {"fpa11",		FPU_ARCH_FPA},
32261  {"arm7500fe",		FPU_ARCH_FPA},
32262  {"softvfp",		FPU_ARCH_VFP},
32263  {"softvfp+vfp",	FPU_ARCH_VFP_V2},
32264  {"vfp",		FPU_ARCH_VFP_V2},
32265  {"vfp9",		FPU_ARCH_VFP_V2},
32266  {"vfp3",		FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3.  */
32267  {"vfp10",		FPU_ARCH_VFP_V2},
32268  {"vfp10-r0",		FPU_ARCH_VFP_V1},
32269  {"vfpxd",		FPU_ARCH_VFP_V1xD},
32270  {"vfpv2",		FPU_ARCH_VFP_V2},
32271  {"vfpv3",		FPU_ARCH_VFP_V3},
32272  {"vfpv3-fp16",	FPU_ARCH_VFP_V3_FP16},
32273  {"vfpv3-d16",		FPU_ARCH_VFP_V3D16},
32274  {"vfpv3-d16-fp16",	FPU_ARCH_VFP_V3D16_FP16},
32275  {"vfpv3xd",		FPU_ARCH_VFP_V3xD},
32276  {"vfpv3xd-fp16",	FPU_ARCH_VFP_V3xD_FP16},
32277  {"arm1020t",		FPU_ARCH_VFP_V1},
32278  {"arm1020e",		FPU_ARCH_VFP_V2},
32279  {"arm1136jfs",	FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s.  */
32280  {"arm1136jf-s",	FPU_ARCH_VFP_V2},
32281  {"maverick",		FPU_ARCH_MAVERICK},
32282  {"neon",		FPU_ARCH_VFP_V3_PLUS_NEON_V1},
32283  {"neon-vfpv3",	FPU_ARCH_VFP_V3_PLUS_NEON_V1},
32284  {"neon-fp16",		FPU_ARCH_NEON_FP16},
32285  {"vfpv4",		FPU_ARCH_VFP_V4},
32286  {"vfpv4-d16",		FPU_ARCH_VFP_V4D16},
32287  {"fpv4-sp-d16",	FPU_ARCH_VFP_V4_SP_D16},
32288  {"fpv5-d16",		FPU_ARCH_VFP_V5D16},
32289  {"fpv5-sp-d16",	FPU_ARCH_VFP_V5_SP_D16},
32290  {"neon-vfpv4",	FPU_ARCH_NEON_VFP_V4},
32291  {"fp-armv8",		FPU_ARCH_VFP_ARMV8},
32292  {"neon-fp-armv8",	FPU_ARCH_NEON_VFP_ARMV8},
32293  {"crypto-neon-fp-armv8",
32294			FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
32295  {"neon-fp-armv8.1",	FPU_ARCH_NEON_VFP_ARMV8_1},
32296  {"crypto-neon-fp-armv8.1",
32297			FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
32298  {NULL,		ARM_ARCH_NONE}
32299};
32300
32301struct arm_option_value_table
32302{
32303  const char *name;
32304  long value;
32305};
32306
32307static const struct arm_option_value_table arm_float_abis[] =
32308{
32309  {"hard",	ARM_FLOAT_ABI_HARD},
32310  {"softfp",	ARM_FLOAT_ABI_SOFTFP},
32311  {"soft",	ARM_FLOAT_ABI_SOFT},
32312  {NULL,	0}
32313};
32314
32315#ifdef OBJ_ELF
32316/* We only know how to output GNU and ver 4/5 (AAELF) formats.  */
32317static const struct arm_option_value_table arm_eabis[] =
32318{
32319  {"gnu",	EF_ARM_EABI_UNKNOWN},
32320  {"4",		EF_ARM_EABI_VER4},
32321  {"5",		EF_ARM_EABI_VER5},
32322  {NULL,	0}
32323};
32324#endif
32325
32326struct arm_long_option_table
32327{
32328  const char *option;			/* Substring to match.	*/
32329  const char *help;			/* Help information.  */
32330  bool (*func) (const char *subopt);	/* Function to decode sub-option.  */
32331  const char *deprecated;		/* If non-null, print this message.  */
32332};
32333
32334static bool
32335arm_parse_extension (const char *str, const arm_feature_set *opt_set,
32336		     arm_feature_set *ext_set,
32337		     const struct arm_ext_table *ext_table)
32338{
32339  /* We insist on extensions being specified in alphabetical order, and with
32340     extensions being added before being removed.  We achieve this by having
32341     the global ARM_EXTENSIONS table in alphabetical order, and using the
32342     ADDING_VALUE variable to indicate whether we are adding an extension (1)
32343     or removing it (0) and only allowing it to change in the order
32344     -1 -> 1 -> 0.  */
32345  const struct arm_option_extension_value_table * opt = NULL;
32346  const arm_feature_set arm_any = ARM_ANY;
32347  int adding_value = -1;
32348
32349  while (str != NULL && *str != 0)
32350    {
32351      const char *ext;
32352      size_t len;
32353
32354      if (*str != '+')
32355	{
32356	  as_bad (_("invalid architectural extension"));
32357	  return false;
32358	}
32359
32360      str++;
32361      ext = strchr (str, '+');
32362
32363      if (ext != NULL)
32364	len = ext - str;
32365      else
32366	len = strlen (str);
32367
32368      if (len >= 2 && startswith (str, "no"))
32369	{
32370	  if (adding_value != 0)
32371	    {
32372	      adding_value = 0;
32373	      opt = arm_extensions;
32374	    }
32375
32376	  len -= 2;
32377	  str += 2;
32378	}
32379      else if (len > 0)
32380	{
32381	  if (adding_value == -1)
32382	    {
32383	      adding_value = 1;
32384	      opt = arm_extensions;
32385	    }
32386	  else if (adding_value != 1)
32387	    {
32388	      as_bad (_("must specify extensions to add before specifying "
32389			"those to remove"));
32390	      return false;
32391	    }
32392	}
32393
32394      if (len == 0)
32395	{
32396	  as_bad (_("missing architectural extension"));
32397	  return false;
32398	}
32399
32400      gas_assert (adding_value != -1);
32401      gas_assert (opt != NULL);
32402
32403      if (ext_table != NULL)
32404	{
32405	  const struct arm_ext_table * ext_opt = ext_table;
32406	  bool found = false;
32407	  for (; ext_opt->name != NULL; ext_opt++)
32408	    if (ext_opt->name_len == len
32409		&& strncmp (ext_opt->name, str, len) == 0)
32410	      {
32411		if (adding_value)
32412		  {
32413		    if (ARM_FEATURE_ZERO (ext_opt->merge))
32414			/* TODO: Option not supported.  When we remove the
32415			   legacy table this case should error out.  */
32416			continue;
32417
32418		    ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
32419		  }
32420		else
32421		  {
32422		    if (ARM_FEATURE_ZERO (ext_opt->clear))
32423			/* TODO: Option not supported.  When we remove the
32424			   legacy table this case should error out.  */
32425			continue;
32426		    ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
32427		  }
32428		found = true;
32429		break;
32430	      }
32431	  if (found)
32432	    {
32433	      str = ext;
32434	      continue;
32435	    }
32436	}
32437
32438      /* Scan over the options table trying to find an exact match. */
32439      for (; opt->name != NULL; opt++)
32440	if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
32441	  {
32442	    int i, nb_allowed_archs =
32443	      sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
32444	    /* Check we can apply the extension to this architecture.  */
32445	    for (i = 0; i < nb_allowed_archs; i++)
32446	      {
32447		/* Empty entry.  */
32448		if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
32449		  continue;
32450		if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
32451		  break;
32452	      }
32453	    if (i == nb_allowed_archs)
32454	      {
32455		as_bad (_("extension does not apply to the base architecture"));
32456		return false;
32457	      }
32458
32459	    /* Add or remove the extension.  */
32460	    if (adding_value)
32461	      ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
32462	    else
32463	      ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
32464
32465	    /* Allowing Thumb division instructions for ARMv7 in autodetection
32466	       rely on this break so that duplicate extensions (extensions
32467	       with the same name as a previous extension in the list) are not
32468	       considered for command-line parsing.  */
32469	    break;
32470	  }
32471
32472      if (opt->name == NULL)
32473	{
32474	  /* Did we fail to find an extension because it wasn't specified in
32475	     alphabetical order, or because it does not exist?  */
32476
32477	  for (opt = arm_extensions; opt->name != NULL; opt++)
32478	    if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
32479	      break;
32480
32481	  if (opt->name == NULL)
32482	    as_bad (_("unknown architectural extension `%s'"), str);
32483	  else
32484	    as_bad (_("architectural extensions must be specified in "
32485		      "alphabetical order"));
32486
32487	  return false;
32488	}
32489      else
32490	{
32491	  /* We should skip the extension we've just matched the next time
32492	     round.  */
32493	  opt++;
32494	}
32495
32496      str = ext;
32497    };
32498
32499  return true;
32500}
32501
32502static bool
32503arm_parse_fp16_opt (const char *str)
32504{
32505  if (strcasecmp (str, "ieee") == 0)
32506    fp16_format = ARM_FP16_FORMAT_IEEE;
32507  else if (strcasecmp (str, "alternative") == 0)
32508    fp16_format = ARM_FP16_FORMAT_ALTERNATIVE;
32509  else
32510    {
32511      as_bad (_("unrecognised float16 format \"%s\""), str);
32512      return false;
32513    }
32514
32515  return true;
32516}
32517
32518static bool
32519arm_parse_cpu (const char *str)
32520{
32521  const struct arm_cpu_option_table *opt;
32522  const char *ext = strchr (str, '+');
32523  size_t len;
32524
32525  if (ext != NULL)
32526    len = ext - str;
32527  else
32528    len = strlen (str);
32529
32530  if (len == 0)
32531    {
32532      as_bad (_("missing cpu name `%s'"), str);
32533      return false;
32534    }
32535
32536  for (opt = arm_cpus; opt->name != NULL; opt++)
32537    if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
32538      {
32539	mcpu_cpu_opt = &opt->value;
32540	if (mcpu_ext_opt == NULL)
32541	  mcpu_ext_opt = XNEW (arm_feature_set);
32542	*mcpu_ext_opt = opt->ext;
32543	mcpu_fpu_opt = &opt->default_fpu;
32544	if (opt->canonical_name)
32545	  {
32546	    gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
32547	    strcpy (selected_cpu_name, opt->canonical_name);
32548	  }
32549	else
32550	  {
32551	    size_t i;
32552
32553	    if (len >= sizeof selected_cpu_name)
32554	      len = (sizeof selected_cpu_name) - 1;
32555
32556	    for (i = 0; i < len; i++)
32557	      selected_cpu_name[i] = TOUPPER (opt->name[i]);
32558	    selected_cpu_name[i] = 0;
32559	  }
32560
32561	if (ext != NULL)
32562	  return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
32563
32564	return true;
32565      }
32566
32567  as_bad (_("unknown cpu `%s'"), str);
32568  return false;
32569}
32570
32571static bool
32572arm_parse_arch (const char *str)
32573{
32574  const struct arm_arch_option_table *opt;
32575  const char *ext = strchr (str, '+');
32576  size_t len;
32577
32578  if (ext != NULL)
32579    len = ext - str;
32580  else
32581    len = strlen (str);
32582
32583  if (len == 0)
32584    {
32585      as_bad (_("missing architecture name `%s'"), str);
32586      return false;
32587    }
32588
32589  for (opt = arm_archs; opt->name != NULL; opt++)
32590    if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
32591      {
32592	march_cpu_opt = &opt->value;
32593	if (march_ext_opt == NULL)
32594	  march_ext_opt = XNEW (arm_feature_set);
32595	*march_ext_opt = arm_arch_none;
32596	march_fpu_opt = &opt->default_fpu;
32597	selected_ctx_ext_table = opt->ext_table;
32598	strcpy (selected_cpu_name, opt->name);
32599
32600	if (ext != NULL)
32601	  return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
32602				      opt->ext_table);
32603
32604	return true;
32605      }
32606
32607  as_bad (_("unknown architecture `%s'\n"), str);
32608  return false;
32609}
32610
32611static bool
32612arm_parse_fpu (const char * str)
32613{
32614  const struct arm_option_fpu_value_table * opt;
32615
32616  for (opt = arm_fpus; opt->name != NULL; opt++)
32617    if (streq (opt->name, str))
32618      {
32619	mfpu_opt = &opt->value;
32620	return true;
32621      }
32622
32623  as_bad (_("unknown floating point format `%s'\n"), str);
32624  return false;
32625}
32626
32627static bool
32628arm_parse_float_abi (const char * str)
32629{
32630  const struct arm_option_value_table * opt;
32631
32632  for (opt = arm_float_abis; opt->name != NULL; opt++)
32633    if (streq (opt->name, str))
32634      {
32635	mfloat_abi_opt = opt->value;
32636	return true;
32637      }
32638
32639  as_bad (_("unknown floating point abi `%s'\n"), str);
32640  return false;
32641}
32642
32643#ifdef OBJ_ELF
32644static bool
32645arm_parse_eabi (const char * str)
32646{
32647  const struct arm_option_value_table *opt;
32648
32649  for (opt = arm_eabis; opt->name != NULL; opt++)
32650    if (streq (opt->name, str))
32651      {
32652	meabi_flags = opt->value;
32653	return true;
32654      }
32655  as_bad (_("unknown EABI `%s'\n"), str);
32656  return false;
32657}
32658#endif
32659
32660static bool
32661arm_parse_it_mode (const char * str)
32662{
32663  bool ret = true;
32664
32665  if (streq ("arm", str))
32666    implicit_it_mode = IMPLICIT_IT_MODE_ARM;
32667  else if (streq ("thumb", str))
32668    implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
32669  else if (streq ("always", str))
32670    implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
32671  else if (streq ("never", str))
32672    implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
32673  else
32674    {
32675      as_bad (_("unknown implicit IT mode `%s', should be "\
32676		"arm, thumb, always, or never."), str);
32677      ret = false;
32678    }
32679
32680  return ret;
32681}
32682
32683static bool
32684arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
32685{
32686  codecomposer_syntax = true;
32687  arm_comment_chars[0] = ';';
32688  arm_line_separator_chars[0] = 0;
32689  return true;
32690}
32691
32692struct arm_long_option_table arm_long_opts[] =
32693{
32694  {"mcpu=", N_("<cpu name>\t  assemble for CPU <cpu name>"),
32695   arm_parse_cpu, NULL},
32696  {"march=", N_("<arch name>\t  assemble for architecture <arch name>"),
32697   arm_parse_arch, NULL},
32698  {"mfpu=", N_("<fpu name>\t  assemble for FPU architecture <fpu name>"),
32699   arm_parse_fpu, NULL},
32700  {"mfloat-abi=", N_("<abi>\t  assemble for floating point ABI <abi>"),
32701   arm_parse_float_abi, NULL},
32702#ifdef OBJ_ELF
32703  {"meabi=", N_("<ver>\t\t  assemble for eabi version <ver>"),
32704   arm_parse_eabi, NULL},
32705#endif
32706  {"mimplicit-it=", N_("<mode>\t  controls implicit insertion of IT instructions"),
32707   arm_parse_it_mode, NULL},
32708  {"mccs", N_("\t\t\t  TI CodeComposer Studio syntax compatibility mode"),
32709   arm_ccs_mode, NULL},
32710  {"mfp16-format=",
32711   N_("[ieee|alternative]\n\
32712                          set the encoding for half precision floating point "
32713			  "numbers to IEEE\n\
32714                          or Arm alternative format."),
32715   arm_parse_fp16_opt, NULL },
32716  {NULL, NULL, 0, NULL}
32717};
32718
32719int
32720md_parse_option (int c, const char * arg)
32721{
32722  struct arm_option_table *opt;
32723  const struct arm_legacy_option_table *fopt;
32724  struct arm_long_option_table *lopt;
32725
32726  switch (c)
32727    {
32728#ifdef OPTION_EB
32729    case OPTION_EB:
32730      target_big_endian = 1;
32731      break;
32732#endif
32733
32734#ifdef OPTION_EL
32735    case OPTION_EL:
32736      target_big_endian = 0;
32737      break;
32738#endif
32739
32740    case OPTION_FIX_V4BX:
32741      fix_v4bx = true;
32742      break;
32743
32744#ifdef OBJ_ELF
32745    case OPTION_FDPIC:
32746      arm_fdpic = true;
32747      break;
32748#endif /* OBJ_ELF */
32749
32750    case 'a':
32751      /* Listing option.  Just ignore these, we don't support additional
32752	 ones.	*/
32753      return 0;
32754
32755    default:
32756      for (opt = arm_opts; opt->option != NULL; opt++)
32757	{
32758	  if (c == opt->option[0]
32759	      && ((arg == NULL && opt->option[1] == 0)
32760		  || streq (arg, opt->option + 1)))
32761	    {
32762	      /* If the option is deprecated, tell the user.  */
32763	      if (warn_on_deprecated && opt->deprecated != NULL)
32764		as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
32765			   arg ? arg : "", _(opt->deprecated));
32766
32767	      if (opt->var != NULL)
32768		*opt->var = opt->value;
32769
32770	      return 1;
32771	    }
32772	}
32773
32774      for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
32775	{
32776	  if (c == fopt->option[0]
32777	      && ((arg == NULL && fopt->option[1] == 0)
32778		  || streq (arg, fopt->option + 1)))
32779	    {
32780	      /* If the option is deprecated, tell the user.  */
32781	      if (warn_on_deprecated && fopt->deprecated != NULL)
32782		as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
32783			   arg ? arg : "", _(fopt->deprecated));
32784
32785	      if (fopt->var != NULL)
32786		*fopt->var = &fopt->value;
32787
32788	      return 1;
32789	    }
32790	}
32791
32792      for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
32793	{
32794	  /* These options are expected to have an argument.  */
32795	  if (c == lopt->option[0]
32796	      && arg != NULL
32797	      && strncmp (arg, lopt->option + 1,
32798			  strlen (lopt->option + 1)) == 0)
32799	    {
32800	      /* If the option is deprecated, tell the user.  */
32801	      if (warn_on_deprecated && lopt->deprecated != NULL)
32802		as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
32803			   _(lopt->deprecated));
32804
32805	      /* Call the sup-option parser.  */
32806	      return lopt->func (arg + strlen (lopt->option) - 1);
32807	    }
32808	}
32809
32810      return 0;
32811    }
32812
32813  return 1;
32814}
32815
32816void
32817md_show_usage (FILE * fp)
32818{
32819  struct arm_option_table *opt;
32820  struct arm_long_option_table *lopt;
32821
32822  fprintf (fp, _(" ARM-specific assembler options:\n"));
32823
32824  for (opt = arm_opts; opt->option != NULL; opt++)
32825    if (opt->help != NULL)
32826      fprintf (fp, "  -%-23s%s\n", opt->option, _(opt->help));
32827
32828  for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
32829    if (lopt->help != NULL)
32830      fprintf (fp, "  -%s%s\n", lopt->option, _(lopt->help));
32831
32832#ifdef OPTION_EB
32833  fprintf (fp, _("\
32834  -EB                     assemble code for a big-endian cpu\n"));
32835#endif
32836
32837#ifdef OPTION_EL
32838  fprintf (fp, _("\
32839  -EL                     assemble code for a little-endian cpu\n"));
32840#endif
32841
32842  fprintf (fp, _("\
32843  --fix-v4bx              Allow BX in ARMv4 code\n"));
32844
32845#ifdef OBJ_ELF
32846  fprintf (fp, _("\
32847  --fdpic                 generate an FDPIC object file\n"));
32848#endif /* OBJ_ELF */
32849}
32850
32851#ifdef OBJ_ELF
32852
32853typedef struct
32854{
32855  int val;
32856  arm_feature_set flags;
32857} cpu_arch_ver_table;
32858
32859/* Mapping from CPU features to EABI CPU arch values.  Table must be sorted
32860   chronologically for architectures, with an exception for ARMv6-M and
32861   ARMv6S-M due to legacy reasons.  No new architecture should have a
32862   special case.  This allows for build attribute selection results to be
32863   stable when new architectures are added.  */
32864static const cpu_arch_ver_table cpu_arch_ver[] =
32865{
32866    {TAG_CPU_ARCH_PRE_V4,     ARM_ARCH_V1},
32867    {TAG_CPU_ARCH_PRE_V4,     ARM_ARCH_V2},
32868    {TAG_CPU_ARCH_PRE_V4,     ARM_ARCH_V2S},
32869    {TAG_CPU_ARCH_PRE_V4,     ARM_ARCH_V3},
32870    {TAG_CPU_ARCH_PRE_V4,     ARM_ARCH_V3M},
32871    {TAG_CPU_ARCH_V4,	      ARM_ARCH_V4xM},
32872    {TAG_CPU_ARCH_V4,	      ARM_ARCH_V4},
32873    {TAG_CPU_ARCH_V4T,	      ARM_ARCH_V4TxM},
32874    {TAG_CPU_ARCH_V4T,	      ARM_ARCH_V4T},
32875    {TAG_CPU_ARCH_V5T,	      ARM_ARCH_V5xM},
32876    {TAG_CPU_ARCH_V5T,	      ARM_ARCH_V5},
32877    {TAG_CPU_ARCH_V5T,	      ARM_ARCH_V5TxM},
32878    {TAG_CPU_ARCH_V5T,	      ARM_ARCH_V5T},
32879    {TAG_CPU_ARCH_V5TE,	      ARM_ARCH_V5TExP},
32880    {TAG_CPU_ARCH_V5TE,	      ARM_ARCH_V5TE},
32881    {TAG_CPU_ARCH_V5TEJ,      ARM_ARCH_V5TEJ},
32882    {TAG_CPU_ARCH_V6,	      ARM_ARCH_V6},
32883    {TAG_CPU_ARCH_V6KZ,	      ARM_ARCH_V6Z},
32884    {TAG_CPU_ARCH_V6KZ,	      ARM_ARCH_V6KZ},
32885    {TAG_CPU_ARCH_V6K,	      ARM_ARCH_V6K},
32886    {TAG_CPU_ARCH_V6T2,	      ARM_ARCH_V6T2},
32887    {TAG_CPU_ARCH_V6T2,	      ARM_ARCH_V6KT2},
32888    {TAG_CPU_ARCH_V6T2,	      ARM_ARCH_V6ZT2},
32889    {TAG_CPU_ARCH_V6T2,	      ARM_ARCH_V6KZT2},
32890
32891    /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32892       always selected build attributes to match those of ARMv6-M
32893       (resp. ARMv6S-M).  However, due to these architectures being a strict
32894       subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32895       would be selected when fully respecting chronology of architectures.
32896       It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32897       move them before ARMv7 architectures.  */
32898    {TAG_CPU_ARCH_V6_M,	      ARM_ARCH_V6M},
32899    {TAG_CPU_ARCH_V6S_M,      ARM_ARCH_V6SM},
32900
32901    {TAG_CPU_ARCH_V7,	      ARM_ARCH_V7},
32902    {TAG_CPU_ARCH_V7,	      ARM_ARCH_V7A},
32903    {TAG_CPU_ARCH_V7,	      ARM_ARCH_V7R},
32904    {TAG_CPU_ARCH_V7,	      ARM_ARCH_V7M},
32905    {TAG_CPU_ARCH_V7,	      ARM_ARCH_V7VE},
32906    {TAG_CPU_ARCH_V7E_M,      ARM_ARCH_V7EM},
32907    {TAG_CPU_ARCH_V8,	      ARM_ARCH_V8A},
32908    {TAG_CPU_ARCH_V8,	      ARM_ARCH_V8_1A},
32909    {TAG_CPU_ARCH_V8,	      ARM_ARCH_V8_2A},
32910    {TAG_CPU_ARCH_V8,	      ARM_ARCH_V8_3A},
32911    {TAG_CPU_ARCH_V8M_BASE,   ARM_ARCH_V8M_BASE},
32912    {TAG_CPU_ARCH_V8M_MAIN,   ARM_ARCH_V8M_MAIN},
32913    {TAG_CPU_ARCH_V8R,	      ARM_ARCH_V8R},
32914    {TAG_CPU_ARCH_V8,	      ARM_ARCH_V8_4A},
32915    {TAG_CPU_ARCH_V8,	      ARM_ARCH_V8_5A},
32916    {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
32917    {TAG_CPU_ARCH_V8,	    ARM_ARCH_V8_6A},
32918    {TAG_CPU_ARCH_V8,	    ARM_ARCH_V8_7A},
32919    {TAG_CPU_ARCH_V8,	    ARM_ARCH_V8_8A},
32920    {TAG_CPU_ARCH_V9,	    ARM_ARCH_V9A},
32921    {TAG_CPU_ARCH_V9,	    ARM_ARCH_V9_1A},
32922    {TAG_CPU_ARCH_V9,	    ARM_ARCH_V9_2A},
32923    {TAG_CPU_ARCH_V9,	    ARM_ARCH_V9_3A},
32924    {-1,		    ARM_ARCH_NONE}
32925};
32926
32927/* Set an attribute if it has not already been set by the user.  */
32928
32929static void
32930aeabi_set_attribute_int (int tag, int value)
32931{
32932  if (tag < 1
32933      || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
32934      || !attributes_set_explicitly[tag])
32935    bfd_elf_add_proc_attr_int (stdoutput, tag, value);
32936}
32937
32938static void
32939aeabi_set_attribute_string (int tag, const char *value)
32940{
32941  if (tag < 1
32942      || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
32943      || !attributes_set_explicitly[tag])
32944    bfd_elf_add_proc_attr_string (stdoutput, tag, value);
32945}
32946
32947/* Return whether features in the *NEEDED feature set are available via
32948   extensions for the architecture whose feature set is *ARCH_FSET.  */
32949
32950static bool
32951have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
32952			    const arm_feature_set *needed)
32953{
32954  int i, nb_allowed_archs;
32955  arm_feature_set ext_fset;
32956  const struct arm_option_extension_value_table *opt;
32957
32958  ext_fset = arm_arch_none;
32959  for (opt = arm_extensions; opt->name != NULL; opt++)
32960    {
32961      /* Extension does not provide any feature we need.  */
32962      if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
32963	continue;
32964
32965      nb_allowed_archs =
32966	sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
32967      for (i = 0; i < nb_allowed_archs; i++)
32968	{
32969	  /* Empty entry.  */
32970	  if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
32971	    break;
32972
32973	  /* Extension is available, add it.  */
32974	  if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
32975	    ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
32976	}
32977    }
32978
32979  /* Can we enable all features in *needed?  */
32980  return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
32981}
32982
32983/* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32984   a given architecture feature set *ARCH_EXT_FSET including extension feature
32985   set *EXT_FSET.  Selection logic used depend on EXACT_MATCH:
32986   - if true, check for an exact match of the architecture modulo extensions;
32987   - otherwise, select build attribute value of the first superset
32988     architecture released so that results remains stable when new architectures
32989     are added.
32990   For -march/-mcpu=all the build attribute value of the most featureful
32991   architecture is returned.  Tag_CPU_arch_profile result is returned in
32992   PROFILE.  */
32993
32994static int
32995get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
32996			      const arm_feature_set *ext_fset,
32997			      char *profile, int exact_match)
32998{
32999  arm_feature_set arch_fset;
33000  const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
33001
33002  /* Select most featureful architecture with all its extensions if building
33003     for -march=all as the feature sets used to set build attributes.  */
33004  if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
33005    {
33006      /* Force revisiting of decision for each new architecture.  */
33007      gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V9);
33008      *profile = 'A';
33009      return TAG_CPU_ARCH_V9;
33010    }
33011
33012  ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
33013
33014  for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
33015    {
33016      arm_feature_set known_arch_fset;
33017
33018      ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
33019      if (exact_match)
33020	{
33021	  /* Base architecture match user-specified architecture and
33022	     extensions, eg. ARMv6S-M matching -march=armv6-m+os.  */
33023	  if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
33024	    {
33025	      p_ver_ret = p_ver;
33026	      goto found;
33027	    }
33028	  /* Base architecture match user-specified architecture only
33029	     (eg. ARMv6-M in the same case as above).  Record it in case we
33030	     find a match with above condition.  */
33031	  else if (p_ver_ret == NULL
33032		   && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
33033	    p_ver_ret = p_ver;
33034	}
33035      else
33036	{
33037
33038	  /* Architecture has all features wanted.  */
33039	  if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
33040	    {
33041	      arm_feature_set added_fset;
33042
33043	      /* Compute features added by this architecture over the one
33044		 recorded in p_ver_ret.  */
33045	      if (p_ver_ret != NULL)
33046		ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
33047				   p_ver_ret->flags);
33048	      /* First architecture that match incl. with extensions, or the
33049		 only difference in features over the recorded match is
33050		 features that were optional and are now mandatory.  */
33051	      if (p_ver_ret == NULL
33052		  || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
33053		{
33054		  p_ver_ret = p_ver;
33055		  goto found;
33056		}
33057	    }
33058	  else if (p_ver_ret == NULL)
33059	    {
33060	      arm_feature_set needed_ext_fset;
33061
33062	      ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
33063
33064	      /* Architecture has all features needed when using some
33065		 extensions.  Record it and continue searching in case there
33066		 exist an architecture providing all needed features without
33067		 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
33068		 OS extension).  */
33069	      if (have_ext_for_needed_feat_p (&known_arch_fset,
33070					      &needed_ext_fset))
33071		p_ver_ret = p_ver;
33072	    }
33073	}
33074    }
33075
33076  if (p_ver_ret == NULL)
33077    return -1;
33078
33079 found:
33080  /* Tag_CPU_arch_profile.  */
33081  if (!ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8r)
33082      && (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
33083          || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
33084          || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
33085              && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only))))
33086    *profile = 'A';
33087  else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r)
33088      || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8r))
33089    *profile = 'R';
33090  else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
33091    *profile = 'M';
33092  else
33093    *profile = '\0';
33094  return p_ver_ret->val;
33095}
33096
33097/* Set the public EABI object attributes.  */
33098
33099static void
33100aeabi_set_public_attributes (void)
33101{
33102  char profile = '\0';
33103  int arch = -1;
33104  int virt_sec = 0;
33105  int fp16_optional = 0;
33106  int skip_exact_match = 0;
33107  arm_feature_set flags, flags_arch, flags_ext;
33108
33109  /* Autodetection mode, choose the architecture based the instructions
33110     actually used.  */
33111  if (no_cpu_selected ())
33112    {
33113      ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
33114
33115      if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
33116	ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
33117
33118      if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
33119	ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
33120
33121      /* Code run during relaxation relies on selected_cpu being set.  */
33122      ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
33123      flags_ext = arm_arch_none;
33124      ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
33125      selected_ext = flags_ext;
33126      selected_cpu = flags;
33127    }
33128  /* Otherwise, choose the architecture based on the capabilities of the
33129     requested cpu.  */
33130  else
33131    {
33132      ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
33133      ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
33134      flags_ext = selected_ext;
33135      flags = selected_cpu;
33136    }
33137  ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
33138
33139  /* Allow the user to override the reported architecture.  */
33140  if (!ARM_FEATURE_ZERO (selected_object_arch))
33141    {
33142      ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
33143      flags_ext = arm_arch_none;
33144    }
33145  else
33146    skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
33147
33148  /* When this function is run again after relaxation has happened there is no
33149     way to determine whether an architecture or CPU was specified by the user:
33150     - selected_cpu is set above for relaxation to work;
33151     - march_cpu_opt is not set if only -mcpu or .cpu is used;
33152     - mcpu_cpu_opt is set to arm_arch_any for autodetection.
33153     Therefore, if not in -march=all case we first try an exact match and fall
33154     back to autodetection.  */
33155  if (!skip_exact_match)
33156    arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
33157  if (arch == -1)
33158    arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
33159  if (arch == -1)
33160    as_bad (_("no architecture contains all the instructions used\n"));
33161
33162  /* Tag_CPU_name.  */
33163  if (selected_cpu_name[0])
33164    {
33165      char *q;
33166
33167      q = selected_cpu_name;
33168      if (startswith (q, "armv"))
33169	{
33170	  int i;
33171
33172	  q += 4;
33173	  for (i = 0; q[i]; i++)
33174	    q[i] = TOUPPER (q[i]);
33175	}
33176      aeabi_set_attribute_string (Tag_CPU_name, q);
33177    }
33178
33179  /* Tag_CPU_arch.  */
33180  aeabi_set_attribute_int (Tag_CPU_arch, arch);
33181
33182  /* Tag_CPU_arch_profile.  */
33183  if (profile != '\0')
33184    aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
33185
33186  /* Tag_DSP_extension.  */
33187  if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
33188    aeabi_set_attribute_int (Tag_DSP_extension, 1);
33189
33190  ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
33191  /* Tag_ARM_ISA_use.  */
33192  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
33193      || ARM_FEATURE_ZERO (flags_arch))
33194    aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
33195
33196  /* Tag_THUMB_ISA_use.  */
33197  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
33198      || ARM_FEATURE_ZERO (flags_arch))
33199    {
33200      int thumb_isa_use;
33201
33202      if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
33203	  && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
33204	thumb_isa_use = 3;
33205      else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
33206	thumb_isa_use = 2;
33207      else
33208	thumb_isa_use = 1;
33209      aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
33210    }
33211
33212  /* Tag_VFP_arch.  */
33213  if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
33214    aeabi_set_attribute_int (Tag_VFP_arch,
33215			     ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
33216			     ? 7 : 8);
33217  else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
33218    aeabi_set_attribute_int (Tag_VFP_arch,
33219			     ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
33220			     ? 5 : 6);
33221  else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
33222    {
33223      fp16_optional = 1;
33224      aeabi_set_attribute_int (Tag_VFP_arch, 3);
33225    }
33226  else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
33227    {
33228      aeabi_set_attribute_int (Tag_VFP_arch, 4);
33229      fp16_optional = 1;
33230    }
33231  else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
33232    aeabi_set_attribute_int (Tag_VFP_arch, 2);
33233  else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
33234	   || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
33235    aeabi_set_attribute_int (Tag_VFP_arch, 1);
33236
33237  /* Tag_ABI_HardFP_use.  */
33238  if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
33239      && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
33240    aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
33241
33242  /* Tag_WMMX_arch.  */
33243  if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
33244    aeabi_set_attribute_int (Tag_WMMX_arch, 2);
33245  else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
33246    aeabi_set_attribute_int (Tag_WMMX_arch, 1);
33247
33248  /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch).  */
33249  if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
33250    aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
33251  else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
33252    aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
33253  else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
33254    {
33255      if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
33256	{
33257	  aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
33258	}
33259      else
33260	{
33261	  aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
33262	  fp16_optional = 1;
33263	}
33264    }
33265
33266  if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext))
33267    aeabi_set_attribute_int (Tag_MVE_arch, 2);
33268  else if (ARM_CPU_HAS_FEATURE (flags, mve_ext))
33269    aeabi_set_attribute_int (Tag_MVE_arch, 1);
33270
33271  /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch).  */
33272  if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
33273    aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
33274
33275  /* Tag_DIV_use.
33276
33277     We set Tag_DIV_use to two when integer divide instructions have been used
33278     in ARM state, or when Thumb integer divide instructions have been used,
33279     but we have no architecture profile set, nor have we any ARM instructions.
33280
33281     For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33282     by the base architecture.
33283
33284     For new architectures we will have to check these tests.  */
33285  gas_assert (arch <= TAG_CPU_ARCH_V9);
33286  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
33287      || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
33288    aeabi_set_attribute_int (Tag_DIV_use, 0);
33289  else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
33290	   || (profile == '\0'
33291	       && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
33292	       && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
33293    aeabi_set_attribute_int (Tag_DIV_use, 2);
33294
33295  /* Tag_MP_extension_use.  */
33296  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
33297    aeabi_set_attribute_int (Tag_MPextension_use, 1);
33298
33299  /* Tag Virtualization_use.  */
33300  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
33301    virt_sec |= 1;
33302  if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
33303    virt_sec |= 2;
33304  if (virt_sec != 0)
33305    aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
33306
33307  if (fp16_format != ARM_FP16_FORMAT_DEFAULT)
33308    aeabi_set_attribute_int (Tag_ABI_FP_16bit_format, fp16_format);
33309}
33310
33311/* Post relaxation hook.  Recompute ARM attributes now that relaxation is
33312   finished and free extension feature bits which will not be used anymore.  */
33313
33314void
33315arm_md_post_relax (void)
33316{
33317  aeabi_set_public_attributes ();
33318  XDELETE (mcpu_ext_opt);
33319  mcpu_ext_opt = NULL;
33320  XDELETE (march_ext_opt);
33321  march_ext_opt = NULL;
33322}
33323
33324/* Add the default contents for the .ARM.attributes section.  */
33325
33326void
33327arm_md_end (void)
33328{
33329  if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
33330    return;
33331
33332  aeabi_set_public_attributes ();
33333}
33334#endif /* OBJ_ELF */
33335
33336/* Parse a .cpu directive.  */
33337
33338static void
33339s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
33340{
33341  const struct arm_cpu_option_table *opt;
33342  char *name;
33343  char saved_char;
33344
33345  name = input_line_pointer;
33346  while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33347    input_line_pointer++;
33348  saved_char = *input_line_pointer;
33349  *input_line_pointer = 0;
33350
33351  /* Skip the first "all" entry.  */
33352  for (opt = arm_cpus + 1; opt->name != NULL; opt++)
33353    if (streq (opt->name, name))
33354      {
33355	selected_arch = opt->value;
33356	selected_ext = opt->ext;
33357	ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
33358	if (opt->canonical_name)
33359	  strcpy (selected_cpu_name, opt->canonical_name);
33360	else
33361	  {
33362	    int i;
33363	    for (i = 0; opt->name[i]; i++)
33364	      selected_cpu_name[i] = TOUPPER (opt->name[i]);
33365
33366	    selected_cpu_name[i] = 0;
33367	  }
33368	ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33369
33370	*input_line_pointer = saved_char;
33371	demand_empty_rest_of_line ();
33372	return;
33373      }
33374  as_bad (_("unknown cpu `%s'"), name);
33375  *input_line_pointer = saved_char;
33376  ignore_rest_of_line ();
33377}
33378
33379/* Parse a .arch directive.  */
33380
33381static void
33382s_arm_arch (int ignored ATTRIBUTE_UNUSED)
33383{
33384  const struct arm_arch_option_table *opt;
33385  char saved_char;
33386  char *name;
33387
33388  name = input_line_pointer;
33389  while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33390    input_line_pointer++;
33391  saved_char = *input_line_pointer;
33392  *input_line_pointer = 0;
33393
33394  /* Skip the first "all" entry.  */
33395  for (opt = arm_archs + 1; opt->name != NULL; opt++)
33396    if (streq (opt->name, name))
33397      {
33398	selected_arch = opt->value;
33399	selected_ctx_ext_table = opt->ext_table;
33400	selected_ext = arm_arch_none;
33401	selected_cpu = selected_arch;
33402	strcpy (selected_cpu_name, opt->name);
33403	ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33404	*input_line_pointer = saved_char;
33405	demand_empty_rest_of_line ();
33406	return;
33407      }
33408
33409  as_bad (_("unknown architecture `%s'\n"), name);
33410  *input_line_pointer = saved_char;
33411  ignore_rest_of_line ();
33412}
33413
33414/* Parse a .object_arch directive.  */
33415
33416static void
33417s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
33418{
33419  const struct arm_arch_option_table *opt;
33420  char saved_char;
33421  char *name;
33422
33423  name = input_line_pointer;
33424  while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33425    input_line_pointer++;
33426  saved_char = *input_line_pointer;
33427  *input_line_pointer = 0;
33428
33429  /* Skip the first "all" entry.  */
33430  for (opt = arm_archs + 1; opt->name != NULL; opt++)
33431    if (streq (opt->name, name))
33432      {
33433	selected_object_arch = opt->value;
33434	*input_line_pointer = saved_char;
33435	demand_empty_rest_of_line ();
33436	return;
33437      }
33438
33439  as_bad (_("unknown architecture `%s'\n"), name);
33440  *input_line_pointer = saved_char;
33441  ignore_rest_of_line ();
33442}
33443
33444/* Parse a .arch_extension directive.  */
33445
33446static void
33447s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
33448{
33449  const struct arm_option_extension_value_table *opt;
33450  char saved_char;
33451  char *name;
33452  int adding_value = 1;
33453
33454  name = input_line_pointer;
33455  while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33456    input_line_pointer++;
33457  saved_char = *input_line_pointer;
33458  *input_line_pointer = 0;
33459
33460  if (strlen (name) >= 2
33461      && startswith (name, "no"))
33462    {
33463      adding_value = 0;
33464      name += 2;
33465    }
33466
33467  /* Check the context specific extension table */
33468  if (selected_ctx_ext_table)
33469    {
33470      const struct arm_ext_table * ext_opt;
33471      for (ext_opt = selected_ctx_ext_table; ext_opt->name != NULL; ext_opt++)
33472        {
33473          if (streq (ext_opt->name, name))
33474	    {
33475	      if (adding_value)
33476		{
33477		  if (ARM_FEATURE_ZERO (ext_opt->merge))
33478		    /* TODO: Option not supported.  When we remove the
33479		    legacy table this case should error out.  */
33480		    continue;
33481		  ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
33482					  ext_opt->merge);
33483		}
33484	      else
33485		ARM_CLEAR_FEATURE (selected_ext, selected_ext, ext_opt->clear);
33486
33487	      ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
33488	      ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33489	      *input_line_pointer = saved_char;
33490	      demand_empty_rest_of_line ();
33491	      return;
33492	    }
33493	}
33494    }
33495
33496  for (opt = arm_extensions; opt->name != NULL; opt++)
33497    if (streq (opt->name, name))
33498      {
33499	int i, nb_allowed_archs =
33500	  sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
33501	for (i = 0; i < nb_allowed_archs; i++)
33502	  {
33503	    /* Empty entry.  */
33504	    if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
33505	      continue;
33506	    if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
33507	      break;
33508	  }
33509
33510	if (i == nb_allowed_archs)
33511	  {
33512	    as_bad (_("architectural extension `%s' is not allowed for the "
33513		      "current base architecture"), name);
33514	    break;
33515	  }
33516
33517	if (adding_value)
33518	  ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
33519				  opt->merge_value);
33520	else
33521	  ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
33522
33523	ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
33524	ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33525	*input_line_pointer = saved_char;
33526	demand_empty_rest_of_line ();
33527	/* Allowing Thumb division instructions for ARMv7 in autodetection rely
33528	   on this return so that duplicate extensions (extensions with the
33529	   same name as a previous extension in the list) are not considered
33530	   for command-line parsing.  */
33531	return;
33532      }
33533
33534  if (opt->name == NULL)
33535    as_bad (_("unknown architecture extension `%s'\n"), name);
33536
33537  *input_line_pointer = saved_char;
33538  ignore_rest_of_line ();
33539}
33540
33541/* Parse a .fpu directive.  */
33542
33543static void
33544s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
33545{
33546  const struct arm_option_fpu_value_table *opt;
33547  char saved_char;
33548  char *name;
33549
33550  name = input_line_pointer;
33551  while (*input_line_pointer && !ISSPACE (*input_line_pointer))
33552    input_line_pointer++;
33553  saved_char = *input_line_pointer;
33554  *input_line_pointer = 0;
33555
33556  for (opt = arm_fpus; opt->name != NULL; opt++)
33557    if (streq (opt->name, name))
33558      {
33559	selected_fpu = opt->value;
33560	ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, fpu_any);
33561#ifndef CPU_DEFAULT
33562	if (no_cpu_selected ())
33563	  ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
33564	else
33565#endif
33566	  ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
33567	*input_line_pointer = saved_char;
33568	demand_empty_rest_of_line ();
33569	return;
33570      }
33571
33572  as_bad (_("unknown floating point format `%s'\n"), name);
33573  *input_line_pointer = saved_char;
33574  ignore_rest_of_line ();
33575}
33576
33577/* Copy symbol information.  */
33578
33579void
33580arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
33581{
33582  ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
33583}
33584
33585#ifdef OBJ_ELF
33586/* Given a symbolic attribute NAME, return the proper integer value.
33587   Returns -1 if the attribute is not known.  */
33588
33589int
33590arm_convert_symbolic_attribute (const char *name)
33591{
33592  static const struct
33593  {
33594    const char * name;
33595    const int    tag;
33596  }
33597  attribute_table[] =
33598    {
33599      /* When you modify this table you should
33600	 also modify the list in doc/c-arm.texi.  */
33601#define T(tag) {#tag, tag}
33602      T (Tag_CPU_raw_name),
33603      T (Tag_CPU_name),
33604      T (Tag_CPU_arch),
33605      T (Tag_CPU_arch_profile),
33606      T (Tag_ARM_ISA_use),
33607      T (Tag_THUMB_ISA_use),
33608      T (Tag_FP_arch),
33609      T (Tag_VFP_arch),
33610      T (Tag_WMMX_arch),
33611      T (Tag_Advanced_SIMD_arch),
33612      T (Tag_PCS_config),
33613      T (Tag_ABI_PCS_R9_use),
33614      T (Tag_ABI_PCS_RW_data),
33615      T (Tag_ABI_PCS_RO_data),
33616      T (Tag_ABI_PCS_GOT_use),
33617      T (Tag_ABI_PCS_wchar_t),
33618      T (Tag_ABI_FP_rounding),
33619      T (Tag_ABI_FP_denormal),
33620      T (Tag_ABI_FP_exceptions),
33621      T (Tag_ABI_FP_user_exceptions),
33622      T (Tag_ABI_FP_number_model),
33623      T (Tag_ABI_align_needed),
33624      T (Tag_ABI_align8_needed),
33625      T (Tag_ABI_align_preserved),
33626      T (Tag_ABI_align8_preserved),
33627      T (Tag_ABI_enum_size),
33628      T (Tag_ABI_HardFP_use),
33629      T (Tag_ABI_VFP_args),
33630      T (Tag_ABI_WMMX_args),
33631      T (Tag_ABI_optimization_goals),
33632      T (Tag_ABI_FP_optimization_goals),
33633      T (Tag_compatibility),
33634      T (Tag_CPU_unaligned_access),
33635      T (Tag_FP_HP_extension),
33636      T (Tag_VFP_HP_extension),
33637      T (Tag_ABI_FP_16bit_format),
33638      T (Tag_MPextension_use),
33639      T (Tag_DIV_use),
33640      T (Tag_nodefaults),
33641      T (Tag_also_compatible_with),
33642      T (Tag_conformance),
33643      T (Tag_T2EE_use),
33644      T (Tag_Virtualization_use),
33645      T (Tag_DSP_extension),
33646      T (Tag_MVE_arch),
33647      T (Tag_PAC_extension),
33648      T (Tag_BTI_extension),
33649      T (Tag_BTI_use),
33650      T (Tag_PACRET_use),
33651      /* We deliberately do not include Tag_MPextension_use_legacy.  */
33652#undef T
33653    };
33654  unsigned int i;
33655
33656  if (name == NULL)
33657    return -1;
33658
33659  for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
33660    if (streq (name, attribute_table[i].name))
33661      return attribute_table[i].tag;
33662
33663  return -1;
33664}
33665
33666/* Apply sym value for relocations only in the case that they are for
33667   local symbols in the same segment as the fixup and you have the
33668   respective architectural feature for blx and simple switches.  */
33669
33670int
33671arm_apply_sym_value (struct fix * fixP, segT this_seg)
33672{
33673  if (fixP->fx_addsy
33674      && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
33675      /* PR 17444: If the local symbol is in a different section then a reloc
33676	 will always be generated for it, so applying the symbol value now
33677	 will result in a double offset being stored in the relocation.  */
33678      && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
33679      && !S_FORCE_RELOC (fixP->fx_addsy, true))
33680    {
33681      switch (fixP->fx_r_type)
33682	{
33683	case BFD_RELOC_ARM_PCREL_BLX:
33684	case BFD_RELOC_THUMB_PCREL_BRANCH23:
33685	  if (ARM_IS_FUNC (fixP->fx_addsy))
33686	    return 1;
33687	  break;
33688
33689	case BFD_RELOC_ARM_PCREL_CALL:
33690	case BFD_RELOC_THUMB_PCREL_BLX:
33691	  if (THUMB_IS_FUNC (fixP->fx_addsy))
33692	    return 1;
33693	  break;
33694
33695	default:
33696	  break;
33697	}
33698
33699    }
33700  return 0;
33701}
33702#endif /* OBJ_ELF */
33703