Searched refs:REG_WR (Results 1 - 10 of 10) sorted by relevance
/netbsd-current/sys/arch/evbarm/stand/bootimx23/ |
H A D | power_prep.c | 99 REG_WR(PWR_5VCTRL, tmp_r); 101 REG_WR(PWR_5VCTRL_S, HW_POWER_5VCTRL_PWRUP_VBUS_CMPS); 104 REG_WR(PWR_5VCTRL_S, HW_POWER_5VCTRL_VBUSVALID_5VDETECT); 127 REG_WR(PWR_LOOPCTRL_S, HW_POWER_LOOPCTRL_TOGGLE_DIF | 133 REG_WR(PWR_MINPWR_S, HW_POWER_MINPWR_DOUBLE_FETS); 135 REG_WR(PWR_5VCTRL_S, __SHIFTIN(4, HW_POWER_5VCTRL_HEADROOM_ADJ)); 140 REG_WR(PWR_DCLIMITS, tmp_r); 156 REG_WR(PWR_DCDC4P2, tmp_r); 158 REG_WR(PWR_CHARGE_S, HW_POWER_CHARGE_ENABLE_LOAD); 161 REG_WR(PWR_5VCTRL_ [all...] |
H A D | pinctrl_prep.c | 107 REG_WR(CTRL_C, (HW_PINCTRL_CTRL_SFTRST | HW_PINCTRL_CTRL_CLKGATE)); 113 REG_WR(CTRL_MUX4_C, 0xfffc0000); /* A00:06 */ 114 REG_WR(CTRL_MUX5_C, 0xfc3fffff); /* A07:12, BA0:1, CASN, CE0N, 116 REG_WR(CTRL_MUX6_C, 0xffffffff); /* D00:15 */ 117 REG_WR(CTRL_MUX7_C, 0xfff); /* DQM0:1, DQS0:1, CLK, CLKN */ 122 REG_WR(CTRL_DRV9, 0x22222220); /* A00:06 */ 123 REG_WR(CTRL_DRV10, 0x22222222); /* A07:A12, BA0:1 */ 124 REG_WR(CTRL_DRV11, 0x22200222); /* CASN, CE0N, CE1N, CKE, RASN, WEN */ 125 REG_WR(CTRL_DRV12, 0x22222222); /* D00:07 */ 126 REG_WR(CTRL_DRV1 [all...] |
H A D | clock_prep.c | 71 REG_WR(CLKCTRL_PLL0_S, HW_CLKCTRL_PLLCTRL0_POWER); 81 REG_WR(CLKCTRL_SEQ_C, HW_CLKCTRL_CLKSEQ_BYPASS_CPU); 88 REG_WR(CLKCTRL_SEQ_C, HW_CLKCTRL_CLKSEQ_BYPASS_EMI); 95 REG_WR(CLKCTRL_SEQ_C, HW_CLKCTRL_CLKSEQ_BYPASS_SSP); 102 REG_WR(CLKCTRL_SEQ_C, HW_CLKCTRL_CLKSEQ_BYPASS_SAIF); 120 REG_WR(CLKCTRL_HBUS, tmp_r); 177 REG_WR(CLKCTRL_EMI, tmp_r); 191 REG_WR(CLKCTRL_SSP, tmp_r); 199 REG_WR(CLKCTRL_SSP, tmp_r);
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H A D | boot_prep.c | 49 REG_WR(HW_DIGCTL_BASE + HW_DIGCTL_CTRL_CLR,
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H A D | emi_prep.c | 66 REG_WR(HW_EMI_CTRL_BASE + HW_EMI_CTRL_CLR, HW_EMI_CTRL_SFTRST); 71 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, tmp_r); 78 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, tmp_r); 88 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL16, tmp_r); 92 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL16, tmp_r);
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H A D | common.h | 36 #define REG_WR(reg, val) \ macro
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H A D | args_prep.c | 113 REG_WR(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS_CLR, 0xFFFFFFFF);
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/netbsd-current/sys/arch/evbarm/imx23_olinuxino/ |
H A D | imx23_olinuxino_machdep.c | 83 #define REG_WR(reg, val) \ macro 246 REG_WR(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU, 265 REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 10000); 266 REG_WR(HW_RTC_BASE + HW_RTC_CTRL_SET, HW_RTC_CTRL_WATCHDOGEN); 267 REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 0); 327 REG_WR(PWR_VDDIOCTRL, tmp_r); 333 REG_WR(PWR_VDDIOCTRL, tmp_r); 342 REG_WR(PWR_VDDIOCTRL, tmp_r); 346 REG_WR(PWR_CTRL_C, HW_POWER_CTRL_VDDIO_BO_IRQ); 350 REG_WR(PWR_VDDIOCTR [all...] |
/netbsd-current/sys/dev/pci/ |
H A D | if_bnx.c | 1067 REG_WR(sc, BNX_CTX_CTX_DATA, ctx_val); 1068 REG_WR(sc, BNX_CTX_CTX_CTRL, 1086 REG_WR(sc, BNX_CTX_DATA_ADR, offset); 1087 REG_WR(sc, BNX_CTX_DATA, ctx_val); 1120 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1129 REG_WR(sc, BNX_EMAC_MDIO_COMM, data); 1162 REG_WR(sc, BNX_EMAC_MDIO_MODE, data); 1204 REG_WR(sc, BNX_EMAC_MDIO_MODE, val1); 1213 REG_WR(sc, BNX_EMAC_MDIO_COMM, val1); 1235 REG_WR(s [all...] |
H A D | if_bnxvar.h | 85 #define REG_WR(sc, reg, val) bus_space_write_4(sc->bnx_btag, sc->bnx_bhandle, reg, val) macro 91 #define BNX_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x))) 92 #define BNX_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
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Completed in 209 milliseconds