1/* $Id: imx23_olinuxino_machdep.c,v 1.16 2024/03/05 14:15:29 thorpej Exp $ */
2
3/*
4 * Copyright (c) 2012 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Petri Laakso.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#include "opt_arm_debug.h"
33#include "opt_imx.h"
34
35#include <sys/bus.h>
36#include <sys/cdefs.h>
37#include <sys/device.h>
38#include <sys/mount.h>
39#include <sys/reboot.h>
40#include <sys/systm.h>
41#include <sys/termios.h>
42#include <sys/types.h>
43
44#include <uvm/uvm_prot.h>
45
46#include <machine/bootconfig.h>
47#include <machine/db_machdep.h>
48#include <machine/pmap.h>
49
50#include <arm/armreg.h>
51#include <arm/cpu.h>
52#include <arm/cpufunc.h>
53#include <arm/locore.h>
54
55#include <arm/arm32/machdep.h>
56#include <arm/arm32/pte.h>
57
58#include <arm/imx/imx23_clkctrlreg.h>
59#include <arm/imx/imx23_digctlreg.h>
60#include <arm/imx/imx23_rtcreg.h>
61#include <arm/imx/imx23_uartdbgreg.h>
62#include <arm/imx/imx23var.h>
63
64#include "plcom.h"
65#if (NPLCOM > 0)
66#include <evbarm/dev/plcomreg.h>
67#include <evbarm/dev/plcomvar.h>
68#endif
69
70#include "opt_evbarm_boardtype.h"
71#include "opt_machdep.h"
72
73#define	KERNEL_VM_BASE	(KERNEL_BASE + 0x8000000)
74#define	KERNEL_VM_SIZE	0x20000000
75
76#define L1_PAGE_TABLE (DRAM_BASE + MEMSIZE * 1024 * 1024 - L1_TABLE_SIZE)
77#define BOOTIMX23_ARGS (L1_PAGE_TABLE - MAX_BOOT_STRING - 1)
78
79#define PLCONMODE ((TTYDEF_CFLAG & ~(CSIZE | CSTOPB | PARENB)) | CS8) /* 8N1 */
80#define PLCONSPEED 115200
81
82#define REG_RD(reg) *(volatile uint32_t *)(reg)
83#define REG_WR(reg, val)						\
84do {									\
85	*(volatile uint32_t *)((reg)) = val;				\
86} while (0)
87
88#define KERNEL_BASE_PHYS ((paddr_t)&KERNEL_BASE_phys)
89#define KERNEL_BASE_VIRT ((vaddr_t)&KERNEL_BASE_virt)
90
91/*
92 * Static device map for i.MX23 peripheral address space.
93 */
94static const struct pmap_devmap devmap[] = {
95	DEVMAP_ENTRY(
96		APBH_BASE,		/* Virtual address. */
97		APBH_BASE,		/* Physical address. */
98		APBH_SIZE + APBX_SIZE	/* APBX located after APBH. */
99	),
100	DEVMAP_ENTRY_END
101};
102
103static struct plcom_instance imx23_pi = {
104	.pi_type = PLCOM_TYPE_PL011,
105	.pi_iot = &imx23_bus_space,
106	.pi_size = PL011COM_UART_SIZE,
107	.pi_iobase = HW_UARTDBG_BASE
108};
109
110extern char KERNEL_BASE_phys;
111extern char KERNEL_BASE_virt;
112BootConfig bootconfig;
113char *boot_args;
114static char kernel_boot_args[MAX_BOOT_STRING];
115
116#define SSP_DIV 2
117#define IO_FRAC 27
118
119static void power_vddio_from_dcdc(int, int);
120static void set_ssp_div(unsigned int);
121static void set_io_frac(unsigned int);
122static void bypass_ssp(void);
123
124/*
125 * Initialize ARM and return new SVC stack pointer.
126 */
127vaddr_t
128initarm(void *arg)
129{
130        psize_t ram_size;
131
132	if (set_cpufuncs())
133		panic("set_cpufuncs failed");
134
135	kern_vtopdiff = KERNEL_BASE - KERNEL_BASE_PHYS;
136
137	pmap_devmap_register(devmap);
138	consinit();
139
140#define BDSTR(s)	_BDSTR(s)
141#define _BDSTR(s)	#s
142	printf("\nNetBSD/evbarm (" BDSTR(EVBARM_BOARDTYPE) ") booting ...\n");
143#undef BDSTR
144#undef _BDSTR
145
146	/*
147	 * SSP_CLK setup was postponed here from bootimx23 because SB wasn't
148	 * able to load kernel if clocks were changed.
149	 */
150	power_vddio_from_dcdc(3300, 2925);
151	set_ssp_div(SSP_DIV);
152	set_io_frac(IO_FRAC);
153	bypass_ssp();
154
155	cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
156
157	/* Copy boot arguments passed from bootimx23. */
158	boot_args = (char *)KERN_PHYSTOV(BOOTIMX23_ARGS);
159	memcpy(kernel_boot_args, boot_args, MAX_BOOT_STRING);
160#ifdef BOOT_ARGS
161	strcpy(kernel_boot_args, BOOT_ARGS);
162#endif
163	boot_args = kernel_boot_args;
164#ifdef VERBOSE_INIT_ARM
165	printf("boot_args @ %lx: '%s'\n", KERN_PHYSTOV(BOOTIMX23_ARGS),
166	    boot_args);
167#endif
168	parse_mi_bootargs(boot_args);
169
170	ram_size = MEMSIZE * 1024 * 1024;
171
172	bootconfig.dramblocks = 1;
173	bootconfig.dram[0].address = DRAM_BASE;
174	bootconfig.dram[0].pages = ram_size / PAGE_SIZE;
175	bootconfig.dram[0].flags = BOOT_DRAM_CAN_DMA;
176
177        arm32_bootmem_init(bootconfig.dram[0].address, ram_size,
178            ((vsize_t)&KERNEL_BASE_phys));
179
180        arm32_kernel_vm_init(KERNEL_VM_BASE, ARM_VECTORS_HIGH, 0, devmap,
181	    false);
182
183        return initarm_common(KERNEL_VM_BASE, KERNEL_VM_SIZE, NULL, 0);
184}
185
186/*
187 * Initialize console.
188 */
189void
190consinit(void)
191{
192	/* consinit() is called from also from the main(). */
193	static int consinit_called = 0;
194
195	if (consinit_called)
196		return;
197
198	plcomcnattach(&imx23_pi, PLCONSPEED, IMX23_UART_CLK, PLCONMODE, 0);
199
200	consinit_called = 1;
201
202	return;
203}
204
205/*
206 * Reboot or halt the system.
207 */
208void
209cpu_reboot(int howto, char *bootstr)
210{
211	static int cpu_reboot_called = 0;
212
213	boothowto |= howto;
214
215	/*
216	 * If this is the first invocation of cpu_reboot() and the RB_NOSYNC
217	 * flag is not set in howto; sync and unmount the system disks by
218	 * calling vfs_shutdown(9) and set the time of day clock by calling
219	 * resettodr(9).
220	 */
221	if (!cpu_reboot_called && !(boothowto & RB_NOSYNC)) {
222		vfs_shutdown();
223	}
224
225	cpu_reboot_called = 1;
226
227	IRQdisable;	/* FIQ's stays on because they are special. */
228
229	/*
230	 * If rebooting after a crash (i.e., if RB_DUMP is set in howto, but
231	 * RB_HALT is not), save a system crash dump.
232	 */
233	if ((boothowto & RB_DUMP) && !(boothowto & RB_HALT)) {
234		panic("please implement crash dump!"); // XXX
235		for(;;);
236		/* NOTREACHED */
237	}
238
239	/* Run any shutdown hooks by calling pmf_system_shutdown(9). */
240	pmf_system_shutdown(boothowto);
241
242	printf("system %s.\n", boothowto & RB_HALT ? "halted" : "rebooted");
243
244	if (boothowto & RB_HALT) {
245		/* Enable i.MX233 wait-for-interrupt mode. */
246		REG_WR(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU,
247		    (REG_RD(HW_CLKCTRL_BASE + HW_CLKCTRL_CPU) |
248		    HW_CLKCTRL_CPU_INTERRUPT_WAIT));
249
250		/* Disable FIQ's and wait for interrupt (which never arrives) */
251		__asm volatile(				\
252		    "mrs r0, cpsr\n\t"			\
253		    "orr r0, #0x40\n\t"			\
254		    "msr cpsr_c, r0\n\t"		\
255		    "mov r0, #0\n\t"			\
256		    "mcr p15, 0, r0, c7, c0, 4\n\t"
257		);
258
259		for(;;);
260
261		/* NOT REACHED */
262	}
263
264	/* Reboot the system. */
265	REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 10000);
266	REG_WR(HW_RTC_BASE + HW_RTC_CTRL_SET, HW_RTC_CTRL_WATCHDOGEN);
267	REG_WR(HW_RTC_BASE + HW_RTC_WATCHDOG, 0);
268
269	for(;;);
270
271	/* NOT REACHED */
272}
273
274/*
275 * Delay us microseconds.
276 */
277void
278delay(unsigned int us)
279{
280	uint32_t start;
281	uint32_t now;
282	uint32_t elapsed;
283	uint32_t total;
284	uint32_t last;
285
286	total = 0;
287	last = 0;
288	start = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS);
289
290	do {
291		now = REG_RD(HW_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS);
292
293		if (start <= now)
294			elapsed = now - start;
295		else	/* Take care of overflow. */
296			elapsed = (UINT32_MAX - start) + 1 + now;
297
298		total += elapsed - last;
299		last = elapsed;
300
301	} while (total < us);
302
303	return;
304}
305#include <arm/imx/imx23_powerreg.h>
306#define PWR_VDDIOCTRL   (HW_POWER_BASE + HW_POWER_VDDIOCTRL)
307#define PWR_CTRL        (HW_POWER_BASE + HW_POWER_CTRL)
308#define PWR_CTRL_S      (HW_POWER_BASE + HW_POWER_CTRL_SET)
309#define PWR_CTRL_C      (HW_POWER_BASE + HW_POWER_CTRL_CLR)
310
311static void
312power_vddio_from_dcdc(int target, int brownout)
313{
314        uint32_t tmp_r;
315
316        /* BO_OFFSET must be within 2700mV - 3475mV */
317        if (brownout > 3475)
318                brownout = 3475;
319        else if (brownout < 2700)
320                brownout = 2700;
321
322
323        /* Set LINREG_OFFSET one step below TRG. */
324        tmp_r = REG_RD(PWR_VDDIOCTRL);
325        tmp_r &= ~HW_POWER_VDDIOCTRL_LINREG_OFFSET;
326        tmp_r |= __SHIFTIN(2, HW_POWER_VDDIOCTRL_LINREG_OFFSET);
327        REG_WR(PWR_VDDIOCTRL, tmp_r);
328        delay(10000);
329
330        /* Enable VDDIO switching converter output. */
331        tmp_r = REG_RD(PWR_VDDIOCTRL);
332        tmp_r &= ~HW_POWER_VDDIOCTRL_DISABLE_FET;
333        REG_WR(PWR_VDDIOCTRL, tmp_r);
334        delay(10000);
335
336        /* Set target voltage and brownout level. */
337        tmp_r = REG_RD(PWR_VDDIOCTRL);
338        tmp_r &= ~(HW_POWER_VDDIOCTRL_BO_OFFSET | HW_POWER_VDDIOCTRL_TRG);
339        tmp_r |= __SHIFTIN(((target - brownout) / 25),
340                HW_POWER_VDDIOCTRL_BO_OFFSET);
341        tmp_r |= __SHIFTIN(((target - 2800) / 25), HW_POWER_VDDIOCTRL_TRG);
342        REG_WR(PWR_VDDIOCTRL, tmp_r);
343        delay(10000);
344
345        /* Enable PWDN_BRNOUT. */
346        REG_WR(PWR_CTRL_C, HW_POWER_CTRL_VDDIO_BO_IRQ);
347
348        tmp_r = REG_RD(PWR_VDDIOCTRL);
349        tmp_r |= HW_POWER_VDDIOCTRL_PWDN_BRNOUT;
350        REG_WR(PWR_VDDIOCTRL, tmp_r);
351
352        return;
353}
354#include <arm/imx/imx23_clkctrlreg.h>
355#define CLKCTRL_SSP     (HW_CLKCTRL_BASE + HW_CLKCTRL_SSP)
356#define CLKCTRL_FRAC    (HW_CLKCTRL_BASE + HW_CLKCTRL_FRAC)
357#define CLKCTRL_SEQ_C   (HW_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ_CLR)
358
359static
360void set_ssp_div(unsigned int div)
361{
362        uint32_t tmp_r;
363
364        tmp_r = REG_RD(CLKCTRL_SSP);
365        tmp_r &= ~HW_CLKCTRL_SSP_CLKGATE;
366        REG_WR(CLKCTRL_SSP, tmp_r);
367
368        while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY)
369                ;
370
371        tmp_r = REG_RD(CLKCTRL_SSP);
372        tmp_r &= ~HW_CLKCTRL_SSP_DIV;
373        tmp_r |= __SHIFTIN(div, HW_CLKCTRL_SSP_DIV);
374        REG_WR(CLKCTRL_SSP, tmp_r);
375
376        while (REG_RD(CLKCTRL_SSP) & HW_CLKCTRL_SSP_BUSY)
377                ;
378
379        return;
380
381}
382static
383void set_io_frac(unsigned int frac)
384{
385        uint8_t *io_frac;
386        uint32_t tmp_r;
387
388        io_frac = (uint8_t *)(CLKCTRL_FRAC);
389        io_frac++; /* emi */
390        io_frac++; /* pix */
391        io_frac++; /* io */
392        tmp_r = (*io_frac)<<24;
393        tmp_r &= ~(HW_CLKCTRL_FRAC_CLKGATEIO | HW_CLKCTRL_FRAC_IOFRAC);
394        tmp_r |= __SHIFTIN(frac, HW_CLKCTRL_FRAC_IOFRAC);
395
396        *io_frac = (uint8_t)(tmp_r>>24);
397
398        return;
399}
400static
401void bypass_ssp(void)
402{
403        REG_WR(CLKCTRL_SEQ_C, HW_CLKCTRL_CLKSEQ_BYPASS_SSP);
404
405        return;
406}
407
408
409