1/* $Id: emi_prep.c,v 1.3 2013/10/07 17:36:40 matt Exp $ */ 2 3/* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Petri Laakso. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31#include <sys/cdefs.h> 32#include <sys/param.h> 33#include <sys/types.h> 34 35#include <arm/imx/imx23_emireg.h> 36 37#include "common.h" 38 39static void init_dram_registers(void); 40static uint32_t get_dram_int_status(void); 41 42#define DRAM_REGS 41 43 44uint32_t dram_regs[DRAM_REGS] = { 45 0x01010001, 0x00010100, 0x01000101, 0x00000001, 46 0x00000101, 0x00000000, 0x00010000, 0x01000001, 47 0x00000000, 0x00000001, 0x07000200, 0x00070202, 48 0x02020000, 0x04040a01, 0x00000201, 0x02040000, 49 0x02000000, 0x19000f08, 0x0d0d0000, 0x02021313, 50 0x02061521, 0x0000000a, 0x00080008, 0x00200020, 51 0x00200020, 0x00200020, 0x000003f7, 0x00000000, 52 0x00000000, 0x00000020, 0x00000020, 0x00c80000, 53 0x000a23cd, 0x000000c8, 0x00006665, 0x00000000, 54 0x00000101, 0x00040001, 0x00000000, 0x00000000, 55 0x00010000 56}; 57 58/* 59 * Initialize DRAM memory. 60 */ 61int 62emi_prep(void) 63{ 64 uint32_t tmp_r; 65 66 REG_WR(HW_EMI_CTRL_BASE + HW_EMI_CTRL_CLR, HW_EMI_CTRL_SFTRST); 67 delay(10000); 68 69 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL08); 70 tmp_r &= ~(HW_DRAM_CTL08_START | HW_DRAM_CTL08_SREFRESH); 71 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, tmp_r); 72 73 init_dram_registers(); 74 75 /* START */ 76 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL08); 77 tmp_r |= HW_DRAM_CTL08_START; 78 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL08, tmp_r); 79 80 delay(20000); 81 82 /* 83 * Set memory power-down with memory 84 * clock gating mode (Mode 2). 85 */ 86 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL16); 87 tmp_r |= (1 << 19); 88 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL16, tmp_r); 89 90 tmp_r = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL16); 91 tmp_r |= (1<<11); 92 REG_WR(HW_DRAM_BASE + HW_DRAM_CTL16, tmp_r); 93 94 /* Wait until DRAM initialization is complete. */ 95 while(!(get_dram_int_status() & (1<<2))); 96 97 delay(20000); 98 99 return 0; 100} 101/* 102 * Set DRAM register values. 103 */ 104static void 105init_dram_registers(void) 106{ 107 volatile uint32_t *dram_r; 108 int i; 109 110 dram_r = (uint32_t *)(HW_DRAM_BASE); 111 112 for (i=0; i < DRAM_REGS; i++) { 113 /* Skip ctrl register 8, obsolete registers 27 and 28, 114 * read only register 35 */ 115 if (i == 8 || i == 27 || i == 28 || i == 35) 116 continue; 117 *(dram_r + i) = dram_regs[i]; 118 } 119 120 /* Set tRAS lockout on. */ 121 *(dram_r + 8) |= HW_DRAM_CTL08_TRAS_LOCKOUT; 122 123 return; 124} 125/* 126 * Return DRAM controller interrupt status register. 127 */ 128static uint32_t 129get_dram_int_status(void) 130{ 131 uint32_t reg; 132 133 reg = REG_RD(HW_DRAM_BASE + HW_DRAM_CTL18); 134 return __SHIFTOUT(reg, HW_DRAM_CTL18_INT_STATUS); 135} 136