/netbsd-current/sys/external/bsd/compiler_rt/dist/lib/sanitizer_common/tests/ |
H A D | sanitizer_ring_buffer_test.cc | 37 RingBuffer<T> *RB; local 40 RB = RingBuffer<T>::New(Size); 41 EXPECT_EQ(RB->size(), Size); 42 RB->Delete(); 45 RB = RingBuffer<T>::New(4); 46 EXPECT_EQ(RB->size(), 4U); 48 EXPECT_EQ((int64_t)(*RB)[0], (int64_t)a0); \ 49 EXPECT_EQ((int64_t)(*RB)[1], (int64_t)a1); \ 50 EXPECT_EQ((int64_t)(*RB)[2], (int64_t)a2); \ 51 EXPECT_EQ((int64_t)(*RB)[ [all...] |
/netbsd-current/external/gpl3/gdb.old/dist/opcodes/ |
H A D | ppc-opc.c | 148 /* The BA and BB fields in an XL form instruction or the RA and RB fields or 1350 /* The RS and RB fields in an X form instruction when they must be the same. 1377 /* The RB field in an lswx instruction, which has special value 2255 /* The RA and RB fields in a VX form instruction when they must be the same. 2725 /* The RB field in an X, XO, M, or MDS form instruction. */ macro 2726 #define RB RAOPT + 1 2730 /* The RS and RB fields in an X form instruction when they must be the same. 2732 #define RSB RB + 1 2735 /* The RB field in an lswx instruction, which has special value 2740 /* The RB fiel [all...] |
H A D | arc-tbl.h | 23 { "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, 29 { "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 35 { "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, 41 { "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, 47 { "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 53 { "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, 77 { "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, 83 { "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 89 { "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, 98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, R [all...] |
H A D | arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC } 31 #define ARG_32BIT_ZARBRC { ZA, RB, RC } 32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC } 33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } 34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } 35 #define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 } 36 #define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 } 38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM } 40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } 42 #define ARG_32BIT_RBRBLIMM { RB, RBdu [all...] |
H A D | arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }}, 86 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }}, 89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }}, 95 { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }}, 98 { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }}, 101 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }}, 113 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }}, 119 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }}, 122 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }}, 128 { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_2 [all...] |
H A D | or1k-opc.c | 238 { { MNEM, ' ', OP (RB), 0 } }, 244 { { MNEM, ' ', OP (RB), 0 } }, 328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } }, 376 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 382 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 388 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 394 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 400 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 412 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 424 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), [all...] |
/netbsd-current/external/gpl3/gdb/dist/opcodes/ |
H A D | ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or 1615 /* The RS and RB fields in an X form instruction when they must be the same. 1642 /* The RB field in an lswx instruction, which has special value 2835 /* The RA and RB fields in a VX form instruction when they must be the same. 3373 /* The RB field in an X, XO, M, or MDS form instruction. */ macro 3374 #define RB RAOPT + 1 3378 /* The RS and RB fields in an X form instruction when they must be the same. 3380 #define RSB RB + 1 3383 /* The RB field in an lswx instruction, which has special value 3388 /* The RB fiel [all...] |
H A D | arc-tbl.h | 23 { "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, 29 { "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 35 { "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, 41 { "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, 47 { "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 53 { "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, 77 { "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, 83 { "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 89 { "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, 98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, R [all...] |
H A D | arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC } 31 #define ARG_32BIT_ZARBRC { ZA, RB, RC } 32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC } 33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } 34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } 35 #define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 } 36 #define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 } 38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM } 40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } 42 #define ARG_32BIT_RBRBLIMM { RB, RBdu [all...] |
H A D | arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }}, 86 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }}, 89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }}, 95 { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }}, 98 { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }}, 101 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }}, 113 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }}, 119 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }}, 122 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }}, 128 { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_2 [all...] |
H A D | or1k-opc.c | 238 { { MNEM, ' ', OP (RB), 0 } }, 244 { { MNEM, ' ', OP (RB), 0 } }, 328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } }, 376 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 382 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 388 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 394 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 400 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 412 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 424 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), [all...] |
/netbsd-current/external/gpl3/binutils/dist/opcodes/ |
H A D | ppc-opc.c | 149 /* The BA and BB fields in an XL form instruction or the RA and RB fields or 1615 /* The RS and RB fields in an X form instruction when they must be the same. 1642 /* The RB field in an lswx instruction, which has special value 2835 /* The RA and RB fields in a VX form instruction when they must be the same. 3373 /* The RB field in an X, XO, M, or MDS form instruction. */ 3374 #define RB RAOPT + 1 3378 /* The RS and RB fields in an X form instruction when they must be the same. 3380 #define RSB RB + 1 3383 /* The RB field in an lswx instruction, which has special value 3388 /* The RB fiel 3294 #define RB macro [all...] |
H A D | arc-tbl.h | 23 { "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, 29 { "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 35 { "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, 41 { "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, 47 { "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 53 { "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, 77 { "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, 83 { "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 89 { "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, 98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, R [all...] |
H A D | arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC } 31 #define ARG_32BIT_ZARBRC { ZA, RB, RC } 32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC } 33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } 34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } 35 #define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 } 36 #define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 } 38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM } 40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } 42 #define ARG_32BIT_RBRBLIMM { RB, RBdu [all...] |
H A D | arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }}, 86 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }}, 89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }}, 95 { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }}, 98 { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }}, 101 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }}, 113 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }}, 119 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }}, 122 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }}, 128 { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_2 [all...] |
H A D | or1k-opc.c | 238 { { MNEM, ' ', OP (RB), 0 } }, 244 { { MNEM, ' ', OP (RB), 0 } }, 328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } }, 376 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 382 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 388 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 394 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 400 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 412 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 424 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), [all...] |
/netbsd-current/external/gpl3/binutils.old/dist/opcodes/ |
H A D | ppc-opc.c | 148 /* The BA and BB fields in an XL form instruction or the RA and RB fields or 1594 /* The RS and RB fields in an X form instruction when they must be the same. 1621 /* The RB field in an lswx instruction, which has special value 2769 /* The RA and RB fields in a VX form instruction when they must be the same. 3294 /* The RB field in an X, XO, M, or MDS form instruction. */ macro 3295 #define RB RAOPT + 1 3299 /* The RS and RB fields in an X form instruction when they must be the same. 3301 #define RSB RB + 1 3304 /* The RB field in an lswx instruction, which has special value 3309 /* The RB fiel [all...] |
H A D | arc-tbl.h | 23 { "abs", 0x202F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, 29 { "abs", 0x206F0009, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 35 { "abs", 0x202F0F89, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, 41 { "abss", 0x282F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, RC }, { C_F }}, 47 { "abss", 0x286F0005, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 53 { "abss", 0x282F0F85, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE, { RB, LIMM }, { C_F }}, 77 { "abssw", 0x282F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, RC }, { C_F }}, 83 { "abssw", 0x286F0004, 0xF8FF003F, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, UIMM6_20 }, { C_F }}, 89 { "abssw", 0x282F0F84, 0xF8FF0FFF, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700, ARITH, NONE, { RB, LIMM }, { C_F }}, 98 { "acm", 0x30280000, 0xF8FF0000, ARC_OPCODE_ARC700, ARITH, NONE, { RA, RB, R [all...] |
H A D | arc-ext-tbl.h | 30 #define ARG_32BIT_RARBRC { RA, RB, RC } 31 #define ARG_32BIT_ZARBRC { ZA, RB, RC } 32 #define ARG_32BIT_RBRBRC { RB, RBdup, RC } 33 #define ARG_32BIT_RARBU6 { RA, RB, UIMM6_20 } 34 #define ARG_32BIT_ZARBU6 { ZA, RB, UIMM6_20 } 35 #define ARG_32BIT_RBRBU6 { RB, RBdup, UIMM6_20 } 36 #define ARG_32BIT_RBRBS12 { RB, RBdup, SIMM12_20 } 38 #define ARG_32BIT_RARBLIMM { RA, RB, LIMM } 40 #define ARG_32BIT_ZARBLIMM { ZA, RB, LIMM } 42 #define ARG_32BIT_RBRBLIMM { RB, RBdu [all...] |
H A D | arc-nps400-tbl.h | 80 { "rflt", 0x382e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { 0 }}, 86 { "rflt", 0x386e0000, 0xf8ff8000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, NPS_RFLT_UIMM6 }, { 0 }}, 89 { "rflt", 0x382e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { 0 }}, 95 { "rflt", 0x386e003e, 0xf8ff803f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, NPS_RFLT_UIMM6 }, { 0 }}, 98 { "rflt", 0x382e0fbe, 0xf8ff8fff, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, LIMM }, { 0 }}, 101 { "rflt", 0x382e0f80, 0xf8ff8fc0, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, LIMM }, { 0 }}, 113 { "crc16", 0x38330000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, RC }, { C_NPS_R }}, 119 { "crc16", 0x38730000, 0xf8ff0000, ARC_OPCODE_ARC700, BITOP, NPS400, { RA, RB, UIMM6_20 }, { C_NPS_R }}, 122 { "crc16", 0x3833003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, RC }, { C_NPS_R }}, 128 { "crc16", 0x3873003e, 0xf8ff003f, ARC_OPCODE_ARC700, BITOP, NPS400, { ZA, RB, UIMM6_2 [all...] |
H A D | or1k-opc.c | 238 { { MNEM, ' ', OP (RB), 0 } }, 244 { { MNEM, ' ', OP (RB), 0 } }, 328 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } }, 376 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 382 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 388 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 394 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }, 400 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 412 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), 0 } }, 424 { { MNEM, ' ', OP (RD), ',', OP (RA), ',', OP (RB), [all...] |
/netbsd-current/external/bsd/flex/dist/examples/manual/ |
H A D | expr.lex | 26 ")" return(RB);
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H A D | expr.y | 19 %token LB RB 42 | LB exp RB { $$ = $2; }
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/netbsd-current/external/apache2/llvm/dist/clang/lib/Rewrite/ |
H A D | HTMLRewrite.cpp | 58 void html::HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E, argument 62 RB.InsertTextAfter(B, StartTag); 63 RB.InsertTextBefore(E, EndTag); 77 RB.InsertTextBefore(LastNonWhiteSpace+1, EndTag); 96 RB.InsertTextAfter(i, StartTag); 116 RewriteBuffer &RB = R.getEditBuffer(FID); local 129 RB.ReplaceText(FilePos, 1, " "); 133 RB.ReplaceText(FilePos, 1, "<hr>"); 142 RB.ReplaceText(FilePos, 1, 146 RB 209 AddLineNumber(RewriteBuffer &RB, unsigned LineNo, unsigned B, unsigned E) argument 233 RewriteBuffer &RB = R.getEditBuffer(FID); local [all...] |
/netbsd-current/external/apache2/llvm/dist/clang/lib/Frontend/Rewrite/ |
H A D | RewriteMacros.cpp | 94 RewriteBuffer &RB = Rewrite.getEditBuffer(SM.getMainFileID()); 133 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); 139 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//"); 169 RB.InsertTextAfter(RawOffs, &" /*"[HasSpace]); 187 RB.InsertTextBefore(EndPos, "*/"); 203 RB.InsertTextBefore(InsertPos, Expansion);
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