1/* ppc-opc.c -- PowerPC opcode list 2 Copyright (C) 1994-2022 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 20 MA 02110-1301, USA. */ 21 22#include "sysdep.h" 23#include <stdio.h> 24#include "opcode/ppc.h" 25#include "opintl.h" 26 27/* This file holds the PowerPC opcode table. The opcode table 28 includes almost all of the extended instruction mnemonics. This 29 permits the disassembler to use them, and simplifies the assembler 30 logic, at the cost of increasing the table size. The table is 31 strictly constant data, so the compiler should be able to put it in 32 the text segment. 33 34 This file also holds the operand table. All knowledge about 35 inserting operands into instructions and vice-versa is kept in this 36 file. */ 37 38/* The functions used to insert and extract complicated operands. */ 39 40/* The ARX, ARY, RX and RY operands are alternate encodings of GPRs. */ 41 42static uint64_t 43insert_arx (uint64_t insn, 44 int64_t value, 45 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 46 const char **errmsg ATTRIBUTE_UNUSED) 47{ 48 value -= 8; 49 if (value < 0 || value >= 16) 50 { 51 *errmsg = _("invalid register"); 52 value = 0xf; 53 } 54 return insn | value; 55} 56 57static int64_t 58extract_arx (uint64_t insn, 59 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 60 int *invalid ATTRIBUTE_UNUSED) 61{ 62 return (insn & 0xf) + 8; 63} 64 65static uint64_t 66insert_ary (uint64_t insn, 67 int64_t value, 68 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 69 const char **errmsg ATTRIBUTE_UNUSED) 70{ 71 value -= 8; 72 if (value < 0 || value >= 16) 73 { 74 *errmsg = _("invalid register"); 75 value = 0xf; 76 } 77 return insn | (value << 4); 78} 79 80static int64_t 81extract_ary (uint64_t insn, 82 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 83 int *invalid ATTRIBUTE_UNUSED) 84{ 85 return ((insn >> 4) & 0xf) + 8; 86} 87 88static uint64_t 89insert_rx (uint64_t insn, 90 int64_t value, 91 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 92 const char **errmsg) 93{ 94 if (value >= 0 && value < 8) 95 ; 96 else if (value >= 24 && value <= 31) 97 value -= 16; 98 else 99 { 100 *errmsg = _("invalid register"); 101 value = 0xf; 102 } 103 return insn | value; 104} 105 106static int64_t 107extract_rx (uint64_t insn, 108 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 109 int *invalid ATTRIBUTE_UNUSED) 110{ 111 int64_t value = insn & 0xf; 112 if (value >= 0 && value < 8) 113 return value; 114 else 115 return value + 16; 116} 117 118static uint64_t 119insert_ry (uint64_t insn, 120 int64_t value, 121 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 122 const char **errmsg) 123{ 124 if (value >= 0 && value < 8) 125 ; 126 else if (value >= 24 && value <= 31) 127 value -= 16; 128 else 129 { 130 *errmsg = _("invalid register"); 131 value = 0xf; 132 } 133 return insn | (value << 4); 134} 135 136static int64_t 137extract_ry (uint64_t insn, 138 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 139 int *invalid ATTRIBUTE_UNUSED) 140{ 141 int64_t value = (insn >> 4) & 0xf; 142 if (value >= 0 && value < 8) 143 return value; 144 else 145 return value + 16; 146} 147 148/* The BA and BB fields in an XL form instruction or the RA and RB fields or 149 VRA and VRB fields in a VX form instruction when they must be the same. 150 This is used for extended mnemonics like crclr. The extraction function 151 enforces that the fields are the same. */ 152 153static uint64_t 154insert_bab (uint64_t insn, 155 int64_t value, 156 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 157 const char **errmsg ATTRIBUTE_UNUSED) 158{ 159 value &= 0x1f; 160 return insn | (value << 16) | (value << 11); 161} 162 163static int64_t 164extract_bab (uint64_t insn, 165 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 166 int *invalid) 167{ 168 int64_t ba = (insn >> 16) & 0x1f; 169 int64_t bb = (insn >> 11) & 0x1f; 170 171 if (ba != bb) 172 *invalid = 1; 173 return ba; 174} 175 176/* The BT, BA and BB fields in an XL form instruction when they must all be 177 the same. This is used for extended mnemonics like crclr. The extraction 178 function enforces that the fields are the same. */ 179 180static uint64_t 181insert_btab (uint64_t insn, 182 int64_t value, 183 ppc_cpu_t dialect, 184 const char **errmsg) 185{ 186 value &= 0x1f; 187 return (value << 21) | insert_bab (insn, value, dialect, errmsg); 188} 189 190static int64_t 191extract_btab (uint64_t insn, 192 ppc_cpu_t dialect, 193 int *invalid) 194{ 195 int64_t bt = (insn >> 21) & 0x1f; 196 int64_t bab = extract_bab (insn, dialect, invalid); 197 198 if (bt != bab) 199 *invalid = 1; 200 return bt; 201} 202 203/* The BD field in a B form instruction when the - modifier is used. 204 This modifier means that the branch is not expected to be taken. 205 For chips built to versions of the architecture prior to version 2 206 (ie. not Power4 compatible), we set the y bit of the BO field to 1 207 if the offset is negative. When extracting, we require that the y 208 bit be 1 and that the offset be positive, since if the y bit is 0 209 we just want to print the normal form of the instruction. 210 Power4 compatible targets use two bits, "a", and "t", instead of 211 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 212 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 213 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 214 for branch on CTR. We only handle the taken/not-taken hint here. 215 Note that we don't relax the conditions tested here when 216 disassembling with -Many because insns using extract_bdm and 217 extract_bdp always occur in pairs. One or the other will always 218 be valid. */ 219 220#define ISA_V2 (PPC_OPCODE_POWER4 | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) 221 222static uint64_t 223insert_bdm (uint64_t insn, 224 int64_t value, 225 ppc_cpu_t dialect, 226 const char **errmsg ATTRIBUTE_UNUSED) 227{ 228 if ((dialect & ISA_V2) == 0) 229 { 230 if ((value & 0x8000) != 0) 231 insn |= 1 << 21; 232 } 233 else 234 { 235 if ((insn & (0x14 << 21)) == (0x04 << 21)) 236 insn |= 0x02 << 21; 237 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 238 insn |= 0x08 << 21; 239 } 240 return insn | (value & 0xfffc); 241} 242 243static int64_t 244extract_bdm (uint64_t insn, 245 ppc_cpu_t dialect, 246 int *invalid) 247{ 248 if ((dialect & ISA_V2) == 0) 249 { 250 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 251 *invalid = 1; 252 } 253 else 254 { 255 if ((insn & (0x17 << 21)) != (0x06 << 21) 256 && (insn & (0x1d << 21)) != (0x18 << 21)) 257 *invalid = 1; 258 } 259 260 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 261} 262 263/* The BD field in a B form instruction when the + modifier is used. 264 This is like BDM, above, except that the branch is expected to be 265 taken. */ 266 267static uint64_t 268insert_bdp (uint64_t insn, 269 int64_t value, 270 ppc_cpu_t dialect, 271 const char **errmsg ATTRIBUTE_UNUSED) 272{ 273 if ((dialect & ISA_V2) == 0) 274 { 275 if ((value & 0x8000) == 0) 276 insn |= 1 << 21; 277 } 278 else 279 { 280 if ((insn & (0x14 << 21)) == (0x04 << 21)) 281 insn |= 0x03 << 21; 282 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 283 insn |= 0x09 << 21; 284 } 285 return insn | (value & 0xfffc); 286} 287 288static int64_t 289extract_bdp (uint64_t insn, 290 ppc_cpu_t dialect, 291 int *invalid) 292{ 293 if ((dialect & ISA_V2) == 0) 294 { 295 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 296 *invalid = 1; 297 } 298 else 299 { 300 if ((insn & (0x17 << 21)) != (0x07 << 21) 301 && (insn & (0x1d << 21)) != (0x19 << 21)) 302 *invalid = 1; 303 } 304 305 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 306} 307 308static inline int 309valid_bo_pre_v2 (int64_t value) 310{ 311 /* Certain encodings have bits that are required to be zero. 312 These are (z must be zero, y may be anything): 313 0000y 314 0001y 315 001zy 316 0100y 317 0101y 318 011zy 319 1z00y 320 1z01y 321 1z1zz 322 */ 323 if ((value & 0x14) == 0) 324 /* BO: 0000y, 0001y, 0100y, 0101y. */ 325 return 1; 326 else if ((value & 0x14) == 0x4) 327 /* BO: 001zy, 011zy. */ 328 return (value & 0x2) == 0; 329 else if ((value & 0x14) == 0x10) 330 /* BO: 1z00y, 1z01y. */ 331 return (value & 0x8) == 0; 332 else 333 /* BO: 1z1zz. */ 334 return value == 0x14; 335} 336 337static inline int 338valid_bo_post_v2 (int64_t value) 339{ 340 /* Certain encodings have bits that are required to be zero. 341 These are (z must be zero, a & t may be anything): 342 0000z 343 0001z 344 001at 345 0100z 346 0101z 347 011at 348 1a00t 349 1a01t 350 1z1zz 351 */ 352 if ((value & 0x14) == 0) 353 /* BO: 0000z, 0001z, 0100z, 0101z. */ 354 return (value & 0x1) == 0; 355 else if ((value & 0x14) == 0x14) 356 /* BO: 1z1zz. */ 357 return value == 0x14; 358 else if ((value & 0x14) == 0x4) 359 /* BO: 001at, 011at, with "at" == 0b01 being reserved. */ 360 return (value & 0x3) != 1; 361 else if ((value & 0x14) == 0x10) 362 /* BO: 1a00t, 1a01t, with "at" == 0b01 being reserved. */ 363 return (value & 0x9) != 1; 364 else 365 return 1; 366} 367 368/* Check for legal values of a BO field. */ 369 370static int 371valid_bo (int64_t value, ppc_cpu_t dialect, int extract) 372{ 373 int valid_y = valid_bo_pre_v2 (value); 374 int valid_at = valid_bo_post_v2 (value); 375 376 /* When disassembling with -Many, accept either encoding on the 377 second pass through opcodes. */ 378 if (extract && dialect == ~(ppc_cpu_t) PPC_OPCODE_ANY) 379 return valid_y || valid_at; 380 if ((dialect & ISA_V2) == 0) 381 return valid_y; 382 else 383 return valid_at; 384} 385 386/* The BO field in a B form instruction. Warn about attempts to set 387 the field to an illegal value. */ 388 389static uint64_t 390insert_bo (uint64_t insn, 391 int64_t value, 392 ppc_cpu_t dialect, 393 const char **errmsg) 394{ 395 if (!valid_bo (value, dialect, 0)) 396 *errmsg = _("invalid conditional option"); 397 else if (PPC_OP (insn) == 19 398 && (((insn >> 1) & 0x3ff) == 528) && ! (value & 4)) 399 *errmsg = _("invalid counter access"); 400 return insn | ((value & 0x1f) << 21); 401} 402 403static int64_t 404extract_bo (uint64_t insn, 405 ppc_cpu_t dialect, 406 int *invalid) 407{ 408 int64_t value = (insn >> 21) & 0x1f; 409 if (!valid_bo (value, dialect, 1)) 410 *invalid = 1; 411 return value; 412} 413 414/* For the given BO value, return a bit mask detailing which bits 415 define the branch hints. */ 416 417static int64_t 418get_bo_hint_mask (int64_t bo, ppc_cpu_t dialect) 419{ 420 if ((dialect & ISA_V2) == 0) 421 { 422 if ((bo & 0x14) != 0x14) 423 /* BO: 0000y, 0001y, 001zy, 0100y, 0101y, 011zy, 1z00y, 1z01y . */ 424 return 1; 425 else 426 /* BO: 1z1zz. */ 427 return 0; 428 } 429 else 430 { 431 if ((bo & 0x14) == 0x4) 432 /* BO: 001at, 011at. */ 433 return 0x3; 434 else if ((bo & 0x14) == 0x10) 435 /* BO: 1a00t, 1a01t. */ 436 return 0x9; 437 else 438 /* BO: 0000z, 0001z, 0100z, 0101z, 1z1zz. */ 439 return 0; 440 } 441} 442 443/* The BO field in a B form instruction when the + or - modifier is used. */ 444 445static uint64_t 446insert_boe (uint64_t insn, 447 int64_t value, 448 ppc_cpu_t dialect, 449 const char **errmsg, 450 int branch_taken) 451{ 452 int64_t implied_hint; 453 int64_t hint_mask = get_bo_hint_mask (value, dialect); 454 455 if (branch_taken) 456 implied_hint = hint_mask; 457 else 458 implied_hint = hint_mask & ~1; 459 460 /* The branch hint bit(s) in the BO field must either be zero or exactly 461 match the branch hint bits implied by the '+' or '-' modifier. */ 462 if (implied_hint == 0) 463 *errmsg = _("BO value implies no branch hint, when using + or - modifier"); 464 else if ((value & hint_mask) != 0 465 && (value & hint_mask) != implied_hint) 466 { 467 if ((dialect & ISA_V2) == 0) 468 *errmsg = _("attempt to set y bit when using + or - modifier"); 469 else 470 *errmsg = _("attempt to set 'at' bits when using + or - modifier"); 471 } 472 473 value |= implied_hint; 474 475 return insert_bo (insn, value, dialect, errmsg); 476} 477 478static int64_t 479extract_boe (uint64_t insn, 480 ppc_cpu_t dialect, 481 int *invalid, 482 int branch_taken) 483{ 484 int64_t value = (insn >> 21) & 0x1f; 485 int64_t implied_hint; 486 int64_t hint_mask = get_bo_hint_mask (value, dialect); 487 488 if (branch_taken) 489 implied_hint = hint_mask; 490 else 491 implied_hint = hint_mask & ~1; 492 493 if (!valid_bo (value, dialect, 1) 494 || implied_hint == 0 495 || (value & hint_mask) != implied_hint) 496 *invalid = 1; 497 return value; 498} 499 500/* The BO field in a B form instruction when the - modifier is used. */ 501 502static uint64_t 503insert_bom (uint64_t insn, 504 int64_t value, 505 ppc_cpu_t dialect, 506 const char **errmsg) 507{ 508 return insert_boe (insn, value, dialect, errmsg, 0); 509} 510 511static int64_t 512extract_bom (uint64_t insn, 513 ppc_cpu_t dialect, 514 int *invalid) 515{ 516 return extract_boe (insn, dialect, invalid, 0); 517} 518 519/* The BO field in a B form instruction when the + modifier is used. */ 520 521static uint64_t 522insert_bop (uint64_t insn, 523 int64_t value, 524 ppc_cpu_t dialect, 525 const char **errmsg) 526{ 527 return insert_boe (insn, value, dialect, errmsg, 1); 528} 529 530static int64_t 531extract_bop (uint64_t insn, 532 ppc_cpu_t dialect, 533 int *invalid) 534{ 535 return extract_boe (insn, dialect, invalid, 1); 536} 537 538/* The DCMX field in a X form instruction when the field is split 539 into separate DC, DM and DX fields. */ 540 541static uint64_t 542insert_dcmxs (uint64_t insn, 543 int64_t value, 544 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 545 const char **errmsg ATTRIBUTE_UNUSED) 546{ 547 return (insn 548 | ((value & 0x1f) << 16) 549 | ((value & 0x20) >> 3) 550 | (value & 0x40)); 551} 552 553static int64_t 554extract_dcmxs (uint64_t insn, 555 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 556 int *invalid ATTRIBUTE_UNUSED) 557{ 558 return (insn & 0x40) | ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); 559} 560 561/* The DW field in a X form instruction when the field is split 562 into separate D and DX fields. */ 563 564static uint64_t 565insert_dw (uint64_t insn, 566 int64_t value, 567 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 568 const char **errmsg ATTRIBUTE_UNUSED) 569{ 570 /* DW offsets must be in the range [-512, -8] and be a multiple of 8. */ 571 if (value < -512 572 || value > -8 573 || (value & 0x7) != 0) 574 *errmsg = _("invalid offset: must be in the range [-512, -8] " 575 "and be a multiple of 8"); 576 577 return insn | ((value & 0xf8) << 18) | ((value >> 8) & 1); 578} 579 580static int64_t 581extract_dw (uint64_t insn, 582 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 583 int *invalid ATTRIBUTE_UNUSED) 584{ 585 int64_t dw = ((insn & 1) << 8) | ((insn >> 18) & 0xf8); 586 return dw - 512; 587} 588 589/* The D field in a DX form instruction when the field is split 590 into separate D0, D1 and D2 fields. */ 591 592static uint64_t 593insert_dxd (uint64_t insn, 594 int64_t value, 595 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 596 const char **errmsg ATTRIBUTE_UNUSED) 597{ 598 return insn | (value & 0xffc1) | ((value & 0x3e) << 15); 599} 600 601static int64_t 602extract_dxd (uint64_t insn, 603 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 604 int *invalid ATTRIBUTE_UNUSED) 605{ 606 uint64_t dxd = (insn & 0xffc1) | ((insn >> 15) & 0x3e); 607 return (dxd ^ 0x8000) - 0x8000; 608} 609 610static uint64_t 611insert_dxdn (uint64_t insn, 612 int64_t value, 613 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 614 const char **errmsg ATTRIBUTE_UNUSED) 615{ 616 return insert_dxd (insn, -value, dialect, errmsg); 617} 618 619static int64_t 620extract_dxdn (uint64_t insn, 621 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 622 int *invalid) 623{ 624 return -extract_dxd (insn, dialect, invalid); 625} 626 627/* The D field in a 64-bit D form prefix instruction when the field is split 628 into separate D0 and D1 fields. */ 629 630static uint64_t 631insert_d34 (uint64_t insn, 632 int64_t value, 633 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 634 const char **errmsg ATTRIBUTE_UNUSED) 635{ 636 return insn | ((value & 0x3ffff0000ULL) << 16) | (value & 0xffff); 637} 638 639static int64_t 640extract_d34 (uint64_t insn, 641 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 642 int *invalid ATTRIBUTE_UNUSED) 643{ 644 int64_t mask = 1ULL << 33; 645 int64_t value = ((insn >> 16) & 0x3ffff0000ULL) | (insn & 0xffff); 646 value = (value ^ mask) - mask; 647 return value; 648} 649 650/* The NSI34 field in an 8-byte D form prefix instruction. This is the same 651 as the SI34 field, only negated. The extraction function always marks it 652 as invalid, since we never want to recognize an instruction which uses 653 a field of this type. */ 654 655static uint64_t 656insert_nsi34 (uint64_t insn, 657 int64_t value, 658 ppc_cpu_t dialect, 659 const char **errmsg) 660{ 661 return insert_d34 (insn, -value, dialect, errmsg); 662} 663 664static int64_t 665extract_nsi34 (uint64_t insn, 666 ppc_cpu_t dialect, 667 int *invalid) 668{ 669 int64_t value = extract_d34 (insn, dialect, invalid); 670 *invalid = 1; 671 return -value; 672} 673 674/* The split IMM32 field in a vector splat insn. */ 675 676static uint64_t 677insert_imm32 (uint64_t insn, 678 int64_t value, 679 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 680 const char **errmsg ATTRIBUTE_UNUSED) 681{ 682 return insn | ((value & 0xffff0000) << 16) | (value & 0xffff); 683} 684 685static int64_t 686extract_imm32 (uint64_t insn, 687 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 688 int *invalid ATTRIBUTE_UNUSED) 689{ 690 return (insn & 0xffff) | ((insn >> 16) & 0xffff0000); 691} 692 693/* The R field in an 8-byte prefix instruction when there are restrictions 694 between R's value and the RA value (ie, they cannot both be non zero). */ 695 696static uint64_t 697insert_pcrel (uint64_t insn, 698 int64_t value, 699 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 700 const char **errmsg) 701{ 702 value &= 0x1; 703 int64_t ra = (insn >> 16) & 0x1f; 704 if (ra != 0 && value != 0) 705 *errmsg = _("invalid R operand"); 706 707 return insn | (value << 52); 708} 709 710static int64_t 711extract_pcrel (uint64_t insn, 712 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 713 int *invalid) 714{ 715 /* If called with *invalid < 0 to return the value for missing 716 operands, *invalid will be the negative count of missing operands 717 including this one. Return a default value of 1 if the PRA0/PRAQ 718 operand was also omitted (ie. *invalid is -2). Return a default 719 value of 0 if the PRA0/PRAQ operand was not omitted 720 (ie. *invalid is -1). */ 721 if (*invalid < 0) 722 return ~ *invalid & 1; 723 724 int64_t ra = (insn >> 16) & 0x1f; 725 int64_t pcrel = (insn >> 52) & 0x1; 726 if (ra != 0 && pcrel != 0) 727 *invalid = 1; 728 729 return pcrel; 730} 731 732/* Variant of extract_pcrel that sets invalid for R bit set. The idea 733 is to disassemble "paddi rt,0,offset,1" as "pla rt,offset". */ 734 735static int64_t 736extract_pcrel0 (uint64_t insn, 737 ppc_cpu_t dialect, 738 int *invalid) 739{ 740 int64_t pcrel = extract_pcrel (insn, dialect, invalid); 741 if (pcrel) 742 *invalid = 1; 743 return pcrel; 744} 745 746/* FXM mask in mfcr and mtcrf instructions. */ 747 748static uint64_t 749insert_fxm (uint64_t insn, 750 int64_t value, 751 ppc_cpu_t dialect, 752 const char **errmsg) 753{ 754 /* If we're handling the mfocrf and mtocrf insns ensure that exactly 755 one bit of the mask field is set. */ 756 if ((insn & (1 << 20)) != 0) 757 { 758 if (value == 0 || (value & -value) != value) 759 { 760 *errmsg = _("invalid mask field"); 761 value = 0; 762 } 763 } 764 765 /* If only one bit of the FXM field is set, we can use the new form 766 of the instruction, which is faster. Unlike the Power4 branch hint 767 encoding, this is not backward compatible. Do not generate the 768 new form unless -mpower4 has been given, or -many and the two 769 operand form of mfcr was used. */ 770 else if (value > 0 771 && (value & -value) == value 772 && ((dialect & PPC_OPCODE_POWER4) != 0 773 || ((dialect & PPC_OPCODE_ANY) != 0 774 && (insn & (0x3ff << 1)) == 19 << 1))) 775 insn |= 1 << 20; 776 777 /* Any other value on mfcr is an error. */ 778 else if ((insn & (0x3ff << 1)) == 19 << 1) 779 { 780 /* A value of -1 means we used the one operand form of 781 mfcr which is valid. */ 782 if (value != -1) 783 *errmsg = _("invalid mfcr mask"); 784 value = 0; 785 } 786 787 return insn | ((value & 0xff) << 12); 788} 789 790static int64_t 791extract_fxm (uint64_t insn, 792 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 793 int *invalid) 794{ 795 /* Return a value of -1 for a missing optional operand, which is 796 used as a flag by insert_fxm. */ 797 if (*invalid < 0) 798 return -1; 799 800 int64_t mask = (insn >> 12) & 0xff; 801 /* Is this a Power4 insn? */ 802 if ((insn & (1 << 20)) != 0) 803 { 804 /* Exactly one bit of MASK should be set. */ 805 if (mask == 0 || (mask & -mask) != mask) 806 *invalid = 1; 807 } 808 809 /* Check that non-power4 form of mfcr has a zero MASK. */ 810 else if ((insn & (0x3ff << 1)) == 19 << 1) 811 { 812 if (mask != 0) 813 *invalid = 1; 814 else 815 mask = -1; 816 } 817 818 return mask; 819} 820 821/* L field in the paste. instruction. */ 822 823static uint64_t 824insert_l1opt (uint64_t insn, 825 int64_t value, 826 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 827 const char **errmsg ATTRIBUTE_UNUSED) 828{ 829 return insn | ((value & 1) << 21); 830} 831 832static int64_t 833extract_l1opt (uint64_t insn, 834 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 835 int *invalid) 836{ 837 /* Return a value of 1 for a missing optional operand. */ 838 if (*invalid < 0) 839 return 1; 840 841 return (insn >> 21) & 1; 842} 843 844static uint64_t 845insert_li20 (uint64_t insn, 846 int64_t value, 847 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 848 const char **errmsg ATTRIBUTE_UNUSED) 849{ 850 return (insn 851 | ((value & 0xf0000) >> 5) 852 | ((value & 0x0f800) << 5) 853 | (value & 0x7ff)); 854} 855 856static int64_t 857extract_li20 (uint64_t insn, 858 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 859 int *invalid ATTRIBUTE_UNUSED) 860{ 861 return ((((insn << 5) & 0xf0000) 862 | ((insn >> 5) & 0xf800) 863 | (insn & 0x7ff)) ^ 0x80000) - 0x80000; 864} 865 866/* The 2-bit/3-bit L or 2-bit WC field in a SYNC, DCBF or WAIT instruction. 867 For SYNC, some L values are reserved: 868 * Values 6 and 7 are reserved on newer server cpus. 869 * Value 3 is reserved on all server cpus. 870 * Value 2 is reserved on all other cpus. 871 For DCBF, some L values are reserved: 872 * Values 2, 5 and 7 are reserved on all cpus. 873 For WAIT, some WC values are reserved: 874 * Value 3 is reserved on all server cpus. 875 * Values 1 and 2 are reserved on older server cpus. */ 876 877static uint64_t 878insert_ls (uint64_t insn, 879 int64_t value, 880 ppc_cpu_t dialect, 881 const char **errmsg) 882{ 883 int64_t mask; 884 885 if (((insn >> 1) & 0x3ff) == 598) 886 { 887 /* For SYNC, some L values are illegal. */ 888 mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3; 889 890 /* If the value is within range, check for other illegal values. */ 891 if ((value & mask) == value) 892 switch (value) 893 { 894 case 2: 895 if (dialect & PPC_OPCODE_POWER4) 896 break; 897 /* Fall through. */ 898 case 3: 899 case 6: 900 case 7: 901 *errmsg = _("illegal L operand value"); 902 break; 903 default: 904 break; 905 } 906 } 907 else if (((insn >> 1) & 0x3ff) == 86) 908 { 909 /* For DCBF, some L values are illegal. */ 910 mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3; 911 912 /* If the value is within range, check for other illegal values. */ 913 if ((value & mask) == value) 914 switch (value) 915 { 916 case 2: 917 case 5: 918 case 7: 919 *errmsg = _("illegal L operand value"); 920 break; 921 default: 922 break; 923 } 924 } 925 else 926 { 927 /* For WAIT, some WC values are illegal. */ 928 mask = 0x3; 929 930 /* If the value is within range, check for other illegal values. */ 931 if ((dialect & PPC_OPCODE_A2) == 0 932 && (dialect & PPC_OPCODE_E500MC) == 0 933 && (value & mask) == value) 934 switch (value) 935 { 936 case 1: 937 case 2: 938 if (dialect & PPC_OPCODE_POWER10) 939 break; 940 /* Fall through. */ 941 case 3: 942 *errmsg = _("illegal WC operand value"); 943 break; 944 default: 945 break; 946 } 947 } 948 949 return insn | ((value & mask) << 21); 950} 951 952static int64_t 953extract_ls (uint64_t insn, 954 ppc_cpu_t dialect, 955 int *invalid) 956{ 957 uint64_t value; 958 959 /* Missing optional operands have a value of zero. */ 960 if (*invalid < 0) 961 return 0; 962 963 if (((insn >> 1) & 0x3ff) == 598) 964 { 965 /* For SYNC, some L values are illegal. */ 966 int64_t mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3; 967 968 value = (insn >> 21) & mask; 969 switch (value) 970 { 971 case 2: 972 if (dialect & PPC_OPCODE_POWER4) 973 break; 974 /* Fall through. */ 975 case 3: 976 case 6: 977 case 7: 978 *invalid = 1; 979 break; 980 default: 981 break; 982 } 983 } 984 else if (((insn >> 1) & 0x3ff) == 86) 985 { 986 /* For DCBF, some L values are illegal. */ 987 int64_t mask = (dialect & PPC_OPCODE_POWER10) ? 0x7 : 0x3; 988 989 value = (insn >> 21) & mask; 990 switch (value) 991 { 992 case 2: 993 case 5: 994 case 7: 995 *invalid = 1; 996 break; 997 default: 998 break; 999 } 1000 } 1001 else 1002 { 1003 /* For WAIT, some WC values are illegal. */ 1004 value = (insn >> 21) & 0x3; 1005 if ((dialect & PPC_OPCODE_A2) == 0 1006 && (dialect & PPC_OPCODE_E500MC) == 0) 1007 switch (value) 1008 { 1009 case 1: 1010 case 2: 1011 if (dialect & PPC_OPCODE_POWER10) 1012 break; 1013 /* Fall through. */ 1014 case 3: 1015 *invalid = 1; 1016 break; 1017 default: 1018 break; 1019 } 1020 } 1021 1022 return value; 1023} 1024 1025/* The 4-bit E field in a sync instruction that accepts 2 operands. 1026 If ESYNC is non-zero, then the L field must be either 0 or 1 and 1027 the complement of ESYNC-bit2. */ 1028 1029static uint64_t 1030insert_esync (uint64_t insn, 1031 int64_t value, 1032 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1033 const char **errmsg) 1034{ 1035 uint64_t ls = (insn >> 21) & 0x03; 1036 1037 if (value != 0 1038 && ((~value >> 1) & 0x1) != ls) 1039 *errmsg = _("incompatible L operand value"); 1040 1041 return insn | ((value & 0xf) << 16); 1042} 1043 1044static int64_t 1045extract_esync (uint64_t insn, 1046 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1047 int *invalid) 1048{ 1049 /* Missing optional operands have a value of zero. */ 1050 if (*invalid < 0) 1051 return 0; 1052 1053 uint64_t ls = (insn >> 21) & 0x3; 1054 uint64_t value = (insn >> 16) & 0xf; 1055 if (value != 0 1056 && ((~value >> 1) & 0x1) != ls) 1057 *invalid = 1; 1058 return value; 1059} 1060 1061/* The n operand of clrrwi, which sets the ME field to 31 - n. */ 1062 1063static uint64_t 1064insert_crwn (uint64_t insn, 1065 int64_t value, 1066 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1067 const char **errmsg ATTRIBUTE_UNUSED) 1068{ 1069 return insn | ((~value & 0x1f) << 1); 1070} 1071 1072static int64_t 1073extract_crwn (uint64_t insn, 1074 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1075 int *invalid ATTRIBUTE_UNUSED) 1076{ 1077 return ~(insn >> 1) & 0x1f; 1078} 1079 1080/* The n operand of extlwi, which sets the ME field to n - 1. */ 1081 1082static uint64_t 1083insert_elwn (uint64_t insn, 1084 int64_t value, 1085 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1086 const char **errmsg ATTRIBUTE_UNUSED) 1087{ 1088 return insn | (((value - 1) & 0x1f) << 1); 1089} 1090 1091static int64_t 1092extract_elwn (uint64_t insn, 1093 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1094 int *invalid ATTRIBUTE_UNUSED) 1095{ 1096 return ((insn >> 1) & 0x1f) + 1; 1097} 1098 1099/* The n operand of extrwi, sets MB = 32 - n. */ 1100 1101static uint64_t 1102insert_erwn (uint64_t insn, 1103 int64_t value, 1104 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1105 const char **errmsg ATTRIBUTE_UNUSED) 1106{ 1107 return insn | ((-value & 0x1f) << 6); 1108} 1109 1110static int64_t 1111extract_erwn (uint64_t insn, 1112 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1113 int *invalid ATTRIBUTE_UNUSED) 1114{ 1115 return (~(insn >> 6) & 0x1f) + 1; 1116} 1117 1118/* The b operand of extrwi, sets SH = b + n. */ 1119 1120static uint64_t 1121insert_erwb (uint64_t insn, 1122 int64_t value, 1123 ppc_cpu_t dialect, 1124 const char **errmsg ATTRIBUTE_UNUSED) 1125{ 1126 int64_t n = extract_erwn (insn, dialect, NULL); 1127 return insn | (((n + value) & 0x1f) << 11); 1128} 1129 1130static int64_t 1131extract_erwb (uint64_t insn, 1132 ppc_cpu_t dialect, 1133 int *invalid ATTRIBUTE_UNUSED) 1134{ 1135 int64_t n = extract_erwn (insn, dialect, NULL); 1136 return ((insn >> 11) - n) & 0x1f; 1137} 1138 1139/* The n and b operands of clrlslwi. */ 1140 1141static uint64_t 1142insert_cslwn (uint64_t insn, 1143 int64_t value, 1144 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1145 const char **errmsg ATTRIBUTE_UNUSED) 1146{ 1147 uint64_t mb = 0x1f << 6; 1148 int64_t b = (insn >> 6) & 0x1f; 1149 return ((insn & ~mb) | ((value & 0x1f) << 11) | (((b - value) & 0x1f) << 6) 1150 | ((~value & 0x1f) << 1)); 1151} 1152 1153static int64_t 1154extract_cslwb (uint64_t insn, 1155 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1156 int *invalid) 1157{ 1158 int64_t sh = (insn >> 11) & 0x1f; 1159 int64_t mb = (insn >> 6) & 0x1f; 1160 int64_t me = (insn >> 1) & 0x1f; 1161 if (sh != 31 - me) 1162 *invalid = 1; 1163 return (mb + sh) & 0x1f; 1164} 1165 1166/* The n and b operands of inslwi. */ 1167 1168static uint64_t 1169insert_ilwb (uint64_t insn, 1170 int64_t value, 1171 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1172 const char **errmsg ATTRIBUTE_UNUSED) 1173{ 1174 uint64_t me = 0x1f << 1; 1175 int64_t n = (insn >> 1) & 0x1f; 1176 return ((insn & ~me) | ((-value & 0x1f) << 11) | ((value & 0x1f) << 6) 1177 | (((value + n - 1) & 0x1f) << 1)); 1178} 1179 1180static int64_t 1181extract_ilwn (uint64_t insn, 1182 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1183 int *invalid) 1184{ 1185 int64_t sh = (insn >> 11) & 0x1f; 1186 int64_t mb = (insn >> 6) & 0x1f; 1187 int64_t me = (insn >> 1) & 0x1f; 1188 if (((sh + mb) & 0x1f) != 0) 1189 *invalid = 1; 1190 return ((me - mb) & 0x1f) + 1; 1191} 1192 1193/* The n and b operands of insrwi. */ 1194 1195static uint64_t 1196insert_irwb (uint64_t insn, 1197 int64_t value, 1198 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1199 const char **errmsg ATTRIBUTE_UNUSED) 1200{ 1201 uint64_t me = 0x1f << 1; 1202 int64_t n = (insn >> 1) & 0x1f; 1203 return ((insn & ~me) | ((-(value + n) & 0x1f) << 11) | ((value & 0x1f) << 6) 1204 | (((value + n - 1) & 0x1f) << 1)); 1205} 1206 1207static int64_t 1208extract_irwn (uint64_t insn, 1209 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1210 int *invalid) 1211{ 1212 int64_t sh = (insn >> 11) & 0x1f; 1213 int64_t mb = (insn >> 6) & 0x1f; 1214 int64_t me = (insn >> 1) & 0x1f; 1215 if (((sh + me + 1) & 0x1f) != 0) 1216 *invalid = 1; 1217 return ((me - mb) & 0x1f) + 1; 1218} 1219 1220/* The MB and ME fields in an M form instruction expressed as a single 1221 operand which is itself a bitmask. The extraction function always 1222 marks it as invalid, since we never want to recognize an 1223 instruction which uses a field of this type. */ 1224 1225static uint64_t 1226insert_mbe (uint64_t insn, 1227 int64_t value, 1228 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1229 const char **errmsg) 1230{ 1231 uint64_t uval, mask; 1232 long mb, me, mx, count, last; 1233 1234 uval = value; 1235 1236 if (uval == 0) 1237 { 1238 *errmsg = _("illegal bitmask"); 1239 return insn; 1240 } 1241 1242 mb = 0; 1243 me = 32; 1244 if ((uval & 1) != 0) 1245 last = 1; 1246 else 1247 last = 0; 1248 count = 0; 1249 1250 /* mb: location of last 0->1 transition */ 1251 /* me: location of last 1->0 transition */ 1252 /* count: # transitions */ 1253 1254 for (mx = 0, mask = (uint64_t) 1 << 31; mx < 32; ++mx, mask >>= 1) 1255 { 1256 if ((uval & mask) && !last) 1257 { 1258 ++count; 1259 mb = mx; 1260 last = 1; 1261 } 1262 else if (!(uval & mask) && last) 1263 { 1264 ++count; 1265 me = mx; 1266 last = 0; 1267 } 1268 } 1269 if (me == 0) 1270 me = 32; 1271 1272 if (count != 2 && (count != 0 || ! last)) 1273 *errmsg = _("illegal bitmask"); 1274 1275 return insn | (mb << 6) | ((me - 1) << 1); 1276} 1277 1278static int64_t 1279extract_mbe (uint64_t insn, 1280 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1281 int *invalid) 1282{ 1283 int64_t ret; 1284 long mb, me; 1285 long i; 1286 1287 *invalid = 1; 1288 1289 mb = (insn >> 6) & 0x1f; 1290 me = (insn >> 1) & 0x1f; 1291 if (mb < me + 1) 1292 { 1293 ret = 0; 1294 for (i = mb; i <= me; i++) 1295 ret |= (uint64_t) 1 << (31 - i); 1296 } 1297 else if (mb == me + 1) 1298 ret = ~0; 1299 else /* (mb > me + 1) */ 1300 { 1301 ret = ~0; 1302 for (i = me + 1; i < mb; i++) 1303 ret &= ~((uint64_t) 1 << (31 - i)); 1304 } 1305 return ret; 1306} 1307 1308/* The MB or ME field in an MD or MDS form instruction. The high bit 1309 is wrapped to the low end. */ 1310 1311static uint64_t 1312insert_mb6 (uint64_t insn, 1313 int64_t value, 1314 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1315 const char **errmsg ATTRIBUTE_UNUSED) 1316{ 1317 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1318} 1319 1320static int64_t 1321extract_mb6 (uint64_t insn, 1322 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1323 int *invalid ATTRIBUTE_UNUSED) 1324{ 1325 return ((insn >> 6) & 0x1f) | (insn & 0x20); 1326} 1327 1328/* The n operand of extrdi, which sets MB field. */ 1329 1330static uint64_t 1331insert_erdn (uint64_t insn, 1332 int64_t value, 1333 ppc_cpu_t dialect, 1334 const char **errmsg) 1335{ 1336 return insert_mb6 (insn, -value, dialect, errmsg); 1337} 1338 1339static int64_t 1340extract_erdn (uint64_t insn, 1341 ppc_cpu_t dialect, 1342 int *invalid) 1343{ 1344 return (~extract_mb6 (insn, dialect, invalid) & 63) + 1; 1345} 1346 1347/* The n operand of extldi, which sets ME field. */ 1348 1349static uint64_t 1350insert_eldn (uint64_t insn, 1351 int64_t value, 1352 ppc_cpu_t dialect, 1353 const char **errmsg) 1354{ 1355 return insert_mb6 (insn, value - 1, dialect, errmsg); 1356} 1357 1358static int64_t 1359extract_eldn (uint64_t insn, 1360 ppc_cpu_t dialect, 1361 int *invalid) 1362{ 1363 return extract_mb6 (insn, dialect, invalid) + 1; 1364} 1365 1366/* The n operand of clrrdi, which set ME field. */ 1367 1368static uint64_t 1369insert_crdn (uint64_t insn, 1370 int64_t value, 1371 ppc_cpu_t dialect, 1372 const char **errmsg) 1373{ 1374 return insert_mb6 (insn, 63 - value, dialect, errmsg); 1375} 1376 1377static int64_t 1378extract_crdn (uint64_t insn, 1379 ppc_cpu_t dialect, 1380 int *invalid) 1381{ 1382 return 63 - extract_mb6 (insn, dialect, invalid); 1383} 1384 1385/* The NB field in an X form instruction. The value 32 is stored as 1386 0. */ 1387 1388static int64_t 1389extract_nb (uint64_t insn, 1390 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1391 int *invalid ATTRIBUTE_UNUSED) 1392{ 1393 int64_t ret; 1394 1395 ret = (insn >> 11) & 0x1f; 1396 if (ret == 0) 1397 ret = 32; 1398 return ret; 1399} 1400 1401/* The NB field in an lswi instruction, which has special value 1402 restrictions. The value 32 is stored as 0. */ 1403 1404static uint64_t 1405insert_nbi (uint64_t insn, 1406 int64_t value, 1407 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1408 const char **errmsg ATTRIBUTE_UNUSED) 1409{ 1410 int64_t rtvalue = (insn >> 21) & 0x1f; 1411 int64_t ravalue = (insn >> 16) & 0x1f; 1412 1413 if (value == 0) 1414 value = 32; 1415 if (rtvalue + (value + 3) / 4 > (rtvalue > ravalue ? ravalue + 32 1416 : ravalue)) 1417 *errmsg = _("address register in load range"); 1418 return insn | ((value & 0x1f) << 11); 1419} 1420 1421/* The NSI field in a D form instruction. This is the same as the SI 1422 field, only negated. The extraction function always marks it as 1423 invalid, since we never want to recognize an instruction which uses 1424 a field of this type. */ 1425 1426static uint64_t 1427insert_nsi (uint64_t insn, 1428 int64_t value, 1429 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1430 const char **errmsg ATTRIBUTE_UNUSED) 1431{ 1432 return insn | (-value & 0xffff); 1433} 1434 1435static int64_t 1436extract_nsi (uint64_t insn, 1437 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1438 int *invalid) 1439{ 1440 *invalid = 1; 1441 return -(((insn & 0xffff) ^ 0x8000) - 0x8000); 1442} 1443 1444/* The 2-bit SC field in a SYNC or PL field in a WAIT instruction. 1445 For WAIT, some PL values are reserved: 1446 * Values 1, 2 and 3 are reserved. */ 1447 1448static uint64_t 1449insert_pl (uint64_t insn, 1450 int64_t value, 1451 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1452 const char **errmsg) 1453{ 1454 /* For WAIT, some PL values are illegal. */ 1455 if (((insn >> 1) & 0x3ff) == 30 1456 && value != 0) 1457 *errmsg = _("illegal PL operand value"); 1458 return insn | ((value & 0x3) << 16); 1459} 1460 1461static int64_t 1462extract_pl (uint64_t insn, 1463 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1464 int *invalid) 1465{ 1466 /* Missing optional operands have a value of zero. */ 1467 if (*invalid < 0) 1468 return 0; 1469 1470 uint64_t value = (insn >> 16) & 0x3; 1471 1472 /* For WAIT, some PL values are illegal. */ 1473 if (((insn >> 1) & 0x3ff) == 30 1474 && value != 0) 1475 *invalid = 1; 1476 return value; 1477} 1478 1479/* The RA field in a D or X form instruction which is an updating 1480 load, which means that the RA field may not be zero and may not 1481 equal the RT field. */ 1482 1483static uint64_t 1484insert_ral (uint64_t insn, 1485 int64_t value, 1486 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1487 const char **errmsg) 1488{ 1489 if (value == 0 1490 || (uint64_t) value == ((insn >> 21) & 0x1f)) 1491 *errmsg = "invalid register operand when updating"; 1492 return insn | ((value & 0x1f) << 16); 1493} 1494 1495static int64_t 1496extract_ral (uint64_t insn, 1497 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1498 int *invalid) 1499{ 1500 int64_t rtvalue = (insn >> 21) & 0x1f; 1501 int64_t ravalue = (insn >> 16) & 0x1f; 1502 1503 if (rtvalue == ravalue || ravalue == 0) 1504 *invalid = 1; 1505 return ravalue; 1506} 1507 1508/* The RA field in an lmw instruction, which has special value 1509 restrictions. */ 1510 1511static uint64_t 1512insert_ram (uint64_t insn, 1513 int64_t value, 1514 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1515 const char **errmsg) 1516{ 1517 if ((uint64_t) value >= ((insn >> 21) & 0x1f)) 1518 *errmsg = _("index register in load range"); 1519 return insn | ((value & 0x1f) << 16); 1520} 1521 1522static int64_t 1523extract_ram (uint64_t insn, 1524 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1525 int *invalid) 1526{ 1527 uint64_t rtvalue = (insn >> 21) & 0x1f; 1528 uint64_t ravalue = (insn >> 16) & 0x1f; 1529 1530 if (ravalue >= rtvalue) 1531 *invalid = 1; 1532 return ravalue; 1533} 1534 1535/* The RA field in the DQ form lq or an lswx instruction, which have special 1536 value restrictions. */ 1537 1538static uint64_t 1539insert_raq (uint64_t insn, 1540 int64_t value, 1541 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1542 const char **errmsg) 1543{ 1544 int64_t rtvalue = (insn >> 21) & 0x1f; 1545 1546 if (value == rtvalue) 1547 *errmsg = _("source and target register operands must be different"); 1548 return insn | ((value & 0x1f) << 16); 1549} 1550 1551static int64_t 1552extract_raq (uint64_t insn, 1553 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1554 int *invalid) 1555{ 1556 /* Missing optional operands have a value of zero. */ 1557 if (*invalid < 0) 1558 return 0; 1559 1560 uint64_t rtvalue = (insn >> 21) & 0x1f; 1561 uint64_t ravalue = (insn >> 16) & 0x1f; 1562 if (ravalue == rtvalue) 1563 *invalid = 1; 1564 return ravalue; 1565} 1566 1567/* The RA field in a D or X form instruction which is an updating 1568 store or an updating floating point load, which means that the RA 1569 field may not be zero. */ 1570 1571static uint64_t 1572insert_ras (uint64_t insn, 1573 int64_t value, 1574 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1575 const char **errmsg) 1576{ 1577 if (value == 0) 1578 *errmsg = _("invalid register operand when updating"); 1579 return insn | ((value & 0x1f) << 16); 1580} 1581 1582static int64_t 1583extract_ras (uint64_t insn, 1584 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1585 int *invalid) 1586{ 1587 uint64_t ravalue = (insn >> 16) & 0x1f; 1588 1589 if (ravalue == 0) 1590 *invalid = 1; 1591 return ravalue; 1592} 1593 1594/* The RS and RB fields in an X form instruction when they must be the same. 1595 This is used for extended mnemonics like mr. The extraction function 1596 enforces that the fields are the same. */ 1597 1598static uint64_t 1599insert_rsb (uint64_t insn, 1600 int64_t value, 1601 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1602 const char **errmsg ATTRIBUTE_UNUSED) 1603{ 1604 value &= 0x1f; 1605 return insn | (value << 21) | (value << 11); 1606} 1607 1608static int64_t 1609extract_rsb (uint64_t insn, 1610 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1611 int *invalid) 1612{ 1613 int64_t rs = (insn >> 21) & 0x1f; 1614 int64_t rb = (insn >> 11) & 0x1f; 1615 1616 if (rs != rb) 1617 *invalid = 1; 1618 return rs; 1619} 1620 1621/* The RB field in an lswx instruction, which has special value 1622 restrictions. */ 1623 1624static uint64_t 1625insert_rbx (uint64_t insn, 1626 int64_t value, 1627 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1628 const char **errmsg) 1629{ 1630 int64_t rtvalue = (insn >> 21) & 0x1f; 1631 1632 if (value == rtvalue) 1633 *errmsg = _("source and target register operands must be different"); 1634 return insn | ((value & 0x1f) << 11); 1635} 1636 1637static int64_t 1638extract_rbx (uint64_t insn, 1639 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1640 int *invalid) 1641{ 1642 uint64_t rtvalue = (insn >> 21) & 0x1f; 1643 uint64_t rbvalue = (insn >> 11) & 0x1f; 1644 1645 if (rbvalue == rtvalue) 1646 *invalid = 1; 1647 return rbvalue; 1648} 1649 1650/* The SCI8 field is made up of SCL and {U,N}I8 fields. */ 1651static uint64_t 1652insert_sci8 (uint64_t insn, 1653 int64_t value, 1654 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1655 const char **errmsg) 1656{ 1657 uint64_t fill_scale = 0; 1658 uint64_t ui8 = value; 1659 1660 if ((ui8 & 0xffffff00) == 0) 1661 ; 1662 else if ((ui8 & 0xffffff00) == 0xffffff00) 1663 fill_scale = 0x400; 1664 else if ((ui8 & 0xffff00ff) == 0) 1665 { 1666 fill_scale = 1 << 8; 1667 ui8 >>= 8; 1668 } 1669 else if ((ui8 & 0xffff00ff) == 0xffff00ff) 1670 { 1671 fill_scale = 0x400 | (1 << 8); 1672 ui8 >>= 8; 1673 } 1674 else if ((ui8 & 0xff00ffff) == 0) 1675 { 1676 fill_scale = 2 << 8; 1677 ui8 >>= 16; 1678 } 1679 else if ((ui8 & 0xff00ffff) == 0xff00ffff) 1680 { 1681 fill_scale = 0x400 | (2 << 8); 1682 ui8 >>= 16; 1683 } 1684 else if ((ui8 & 0x00ffffff) == 0) 1685 { 1686 fill_scale = 3 << 8; 1687 ui8 >>= 24; 1688 } 1689 else if ((ui8 & 0x00ffffff) == 0x00ffffff) 1690 { 1691 fill_scale = 0x400 | (3 << 8); 1692 ui8 >>= 24; 1693 } 1694 else 1695 { 1696 *errmsg = _("illegal immediate value"); 1697 ui8 = 0; 1698 } 1699 1700 return insn | fill_scale | (ui8 & 0xff); 1701} 1702 1703static int64_t 1704extract_sci8 (uint64_t insn, 1705 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1706 int *invalid ATTRIBUTE_UNUSED) 1707{ 1708 int64_t fill = insn & 0x400; 1709 int64_t scale_factor = (insn & 0x300) >> 5; 1710 int64_t value = (insn & 0xff) << scale_factor; 1711 1712 if (fill != 0) 1713 value |= ~((int64_t) 0xff << scale_factor); 1714 return value; 1715} 1716 1717static uint64_t 1718insert_sci8n (uint64_t insn, 1719 int64_t value, 1720 ppc_cpu_t dialect, 1721 const char **errmsg) 1722{ 1723 return insert_sci8 (insn, -value, dialect, errmsg); 1724} 1725 1726static int64_t 1727extract_sci8n (uint64_t insn, 1728 ppc_cpu_t dialect, 1729 int *invalid) 1730{ 1731 return -extract_sci8 (insn, dialect, invalid); 1732} 1733 1734static uint64_t 1735insert_oimm (uint64_t insn, 1736 int64_t value, 1737 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1738 const char **errmsg ATTRIBUTE_UNUSED) 1739{ 1740 return insn | (((value - 1) & 0x1f) << 4); 1741} 1742 1743static int64_t 1744extract_oimm (uint64_t insn, 1745 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1746 int *invalid ATTRIBUTE_UNUSED) 1747{ 1748 return ((insn >> 4) & 0x1f) + 1; 1749} 1750 1751/* The n operand of rotrwi, sets SH = 32 - n. */ 1752 1753static uint64_t 1754insert_rrwn (uint64_t insn, 1755 int64_t value, 1756 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1757 const char **errmsg ATTRIBUTE_UNUSED) 1758{ 1759 return insn | ((-value & 0x1f) << 11); 1760} 1761 1762static int64_t 1763extract_rrwn (uint64_t insn, 1764 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1765 int *invalid ATTRIBUTE_UNUSED) 1766{ 1767 return 31 & -(insn >> 11); 1768} 1769 1770/* The n operand of slwi, sets SH = n and ME = 31 - n. */ 1771 1772static uint64_t 1773insert_slwn (uint64_t insn, 1774 int64_t value, 1775 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1776 const char **errmsg ATTRIBUTE_UNUSED) 1777{ 1778 return insn | ((value & 0x1f) << 11) | ((~value & 0x1f) << 1); 1779} 1780 1781static int64_t 1782extract_slwn (uint64_t insn, 1783 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1784 int *invalid) 1785{ 1786 int64_t sh = (insn >> 11) & 0x1f; 1787 int64_t nme = ~(insn >> 1) & 0x1f; 1788 if (sh != nme) 1789 *invalid = 1; 1790 return sh; 1791} 1792 1793/* The n operand of srwi, sets SH = 32 - n and MB = n. */ 1794 1795static uint64_t 1796insert_srwn (uint64_t insn, 1797 int64_t value, 1798 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1799 const char **errmsg ATTRIBUTE_UNUSED) 1800{ 1801 return insn | ((-value & 0x1f) << 11) | ((value & 0x1f) << 6); 1802} 1803 1804static int64_t 1805extract_srwn (uint64_t insn, 1806 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1807 int *invalid) 1808{ 1809 int64_t nsh = -(insn >> 11) & 0x1f; 1810 int64_t mb = (insn >> 6) & 0x1f; 1811 if (nsh != mb) 1812 *invalid = 1; 1813 return nsh; 1814} 1815 1816/* The SH field in an MD form instruction. This is split. */ 1817 1818static uint64_t 1819insert_sh6 (uint64_t insn, 1820 int64_t value, 1821 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1822 const char **errmsg ATTRIBUTE_UNUSED) 1823{ 1824 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1825} 1826 1827static int64_t 1828extract_sh6 (uint64_t insn, 1829 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1830 int *invalid ATTRIBUTE_UNUSED) 1831{ 1832 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 1833} 1834 1835/* The n operand of rotrdi, which writes to SH field. */ 1836 1837static uint64_t 1838insert_rrdn (uint64_t insn, 1839 int64_t value, 1840 ppc_cpu_t dialect, 1841 const char **errmsg) 1842{ 1843 return insert_sh6 (insn, -value, dialect, errmsg); 1844} 1845 1846static int64_t 1847extract_rrdn (uint64_t insn, 1848 ppc_cpu_t dialect, 1849 int *invalid) 1850{ 1851 return -extract_sh6 (insn, dialect, invalid) & 63; 1852} 1853 1854/* The n operand of sldi, which writes to SH and ME fields. */ 1855 1856static uint64_t 1857insert_sldn (uint64_t insn, 1858 int64_t value, 1859 ppc_cpu_t dialect, 1860 const char **errmsg) 1861{ 1862 insn = insert_sh6 (insn, value, dialect, errmsg); 1863 return insert_crdn (insn, value, dialect, errmsg); 1864} 1865 1866static int64_t 1867extract_sldn (uint64_t insn, 1868 ppc_cpu_t dialect, 1869 int *invalid) 1870{ 1871 int64_t sh = extract_sh6 (insn, dialect, invalid); 1872 int64_t me = extract_crdn (insn, dialect, invalid); 1873 if (me != sh) 1874 *invalid = 1; 1875 return sh; 1876} 1877 1878/* The n operand of srdi, which writes to SH and MB fields. */ 1879 1880static uint64_t 1881insert_srdn (uint64_t insn, 1882 int64_t value, 1883 ppc_cpu_t dialect, 1884 const char **errmsg) 1885{ 1886 insn = insert_rrdn (insn, value, dialect, errmsg); 1887 return insert_mb6 (insn, value, dialect, errmsg); 1888} 1889 1890static int64_t 1891extract_srdn (uint64_t insn, 1892 ppc_cpu_t dialect, 1893 int *invalid) 1894{ 1895 int64_t sh = extract_rrdn (insn, dialect, invalid); 1896 int64_t mb = extract_mb6 (insn, dialect, invalid); 1897 if (mb != sh) 1898 *invalid = 1; 1899 return sh; 1900} 1901 1902/* The b operand of extrdi, which sets SH field. */ 1903 1904static uint64_t 1905insert_erdb (uint64_t insn, 1906 int64_t value, 1907 ppc_cpu_t dialect, 1908 const char **errmsg) 1909{ 1910 int64_t n = extract_erdn (insn, dialect, NULL); 1911 return insert_sh6 (insn, value + n, dialect, errmsg); 1912} 1913 1914static int64_t 1915extract_erdb (uint64_t insn, 1916 ppc_cpu_t dialect, 1917 int *invalid) 1918{ 1919 int64_t sh = extract_sh6 (insn, dialect, invalid); 1920 int64_t n = extract_erdn (insn, dialect, invalid); 1921 return (sh - n) & 63; 1922} 1923 1924/* The b and n operands of clrlsldi. */ 1925 1926static uint64_t 1927insert_csldn (uint64_t insn, 1928 int64_t value, 1929 ppc_cpu_t dialect, 1930 const char **errmsg) 1931{ 1932 uint64_t mb6 = 0x3f << 5; 1933 int64_t b = extract_mb6 (insn, dialect, NULL); 1934 insn = insert_mb6 (insn & ~mb6, b - value, dialect, errmsg); 1935 return insert_sh6 (insn, value, dialect, errmsg); 1936} 1937 1938static int64_t 1939extract_csldb (uint64_t insn, 1940 ppc_cpu_t dialect, 1941 int *invalid) 1942{ 1943 int64_t sh = extract_sh6 (insn, dialect, invalid); 1944 int64_t mb = extract_mb6 (insn, dialect, invalid); 1945 return (mb + sh) & 63; 1946} 1947 1948/* The b and n operands of insrdi. */ 1949 1950static uint64_t 1951insert_irdb (uint64_t insn, 1952 int64_t value, 1953 ppc_cpu_t dialect, 1954 const char **errmsg) 1955{ 1956 uint64_t sh6 = (0x1f << 11) | 2; 1957 int64_t n = extract_sh6 (insn, dialect, NULL); 1958 insn = insert_sh6 (insn & ~sh6, -(value + n), dialect, errmsg); 1959 return insert_mb6 (insn, value, dialect, errmsg); 1960} 1961 1962static int64_t 1963extract_irdn (uint64_t insn, 1964 ppc_cpu_t dialect, 1965 int *invalid) 1966{ 1967 int64_t sh = extract_sh6 (insn, dialect, invalid); 1968 int64_t mb = extract_mb6 (insn, dialect, invalid); 1969 return (~(mb + sh) & 63) + 1; 1970} 1971 1972/* The SPR field in an XFX form instruction. This is flipped--the 1973 lower 5 bits are stored in the upper 5 and vice- versa. */ 1974 1975static uint64_t 1976insert_spr (uint64_t insn, 1977 int64_t value, 1978 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1979 const char **errmsg ATTRIBUTE_UNUSED) 1980{ 1981 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1982} 1983 1984static int64_t 1985extract_spr (uint64_t insn, 1986 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 1987 int *invalid ATTRIBUTE_UNUSED) 1988{ 1989 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1990} 1991 1992/* Some dialects have 8 [DI]BAT registers instead of the standard 4. */ 1993#define ALLOW8_BAT (PPC_OPCODE_750) 1994 1995static uint64_t 1996insert_sprbat (uint64_t insn, 1997 int64_t value, 1998 ppc_cpu_t dialect, 1999 const char **errmsg) 2000{ 2001 if ((uint64_t) value > 7 2002 || ((uint64_t) value > 3 && (dialect & ALLOW8_BAT) == 0)) 2003 *errmsg = _("invalid bat number"); 2004 2005 /* If this is [di]bat4..7 then use spr 560..575, otherwise 528..543. */ 2006 if ((uint64_t) value > 3) 2007 value = ((value & 3) << 6) | 1; 2008 else 2009 value = value << 6; 2010 2011 return insn | (value << 11); 2012} 2013 2014static int64_t 2015extract_sprbat (uint64_t insn, 2016 ppc_cpu_t dialect, 2017 int *invalid) 2018{ 2019 uint64_t val = (insn >> 17) & 0x3; 2020 2021 val = val + ((insn >> 9) & 0x4); 2022 if (val > 3 && (dialect & ALLOW8_BAT) == 0) 2023 *invalid = 1; 2024 return val; 2025} 2026 2027/* Some dialects have 8 SPRG registers instead of the standard 4. */ 2028#define ALLOW8_SPRG (PPC_OPCODE_BOOKE | PPC_OPCODE_405) 2029 2030static uint64_t 2031insert_sprg (uint64_t insn, 2032 int64_t value, 2033 ppc_cpu_t dialect, 2034 const char **errmsg) 2035{ 2036 if ((uint64_t) value > 7 2037 || ((uint64_t) value > 3 && (dialect & ALLOW8_SPRG) == 0)) 2038 *errmsg = _("invalid sprg number"); 2039 2040 /* If this is mfsprg4..7 then use spr 260..263 which can be read in 2041 user mode. Anything else must use spr 272..279. */ 2042 if ((uint64_t) value <= 3 || (insn & 0x100) != 0) 2043 value |= 0x10; 2044 2045 return insn | ((value & 0x17) << 16); 2046} 2047 2048static int64_t 2049extract_sprg (uint64_t insn, 2050 ppc_cpu_t dialect, 2051 int *invalid) 2052{ 2053 uint64_t val = (insn >> 16) & 0x1f; 2054 2055 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 2056 If not BOOKE, 405 or VLE, then both use only 272..275. */ 2057 if ((val - 0x10 > 3 && (dialect & ALLOW8_SPRG) == 0) 2058 || (val - 0x10 > 7 && (insn & 0x100) != 0) 2059 || val <= 3 2060 || (val & 8) != 0) 2061 *invalid = 1; 2062 return val & 7; 2063} 2064 2065/* The TBR field in an XFX instruction. This is just like SPR, but it 2066 is optional. */ 2067 2068static uint64_t 2069insert_tbr (uint64_t insn, 2070 int64_t value, 2071 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2072 const char **errmsg) 2073{ 2074 if (value != 268 && value != 269) 2075 *errmsg = _("invalid tbr number"); 2076 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 2077} 2078 2079static int64_t 2080extract_tbr (uint64_t insn, 2081 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2082 int *invalid) 2083{ 2084 /* Missing optional operands have a value of 268. */ 2085 if (*invalid < 0) 2086 return 268; 2087 2088 int64_t ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 2089 if (ret != 268 && ret != 269) 2090 *invalid = 1; 2091 return ret; 2092} 2093 2094/* The XT and XS fields in an XX1 or XX3 form instruction. This is split. */ 2095 2096static uint64_t 2097insert_xt6 (uint64_t insn, 2098 int64_t value, 2099 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2100 const char **errmsg ATTRIBUTE_UNUSED) 2101{ 2102 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 5); 2103} 2104 2105static int64_t 2106extract_xt6 (uint64_t insn, 2107 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2108 int *invalid ATTRIBUTE_UNUSED) 2109{ 2110 return ((insn << 5) & 0x20) | ((insn >> 21) & 0x1f); 2111} 2112 2113/* The XT and XS fields in an DQ form VSX instruction. This is split. */ 2114static uint64_t 2115insert_xtq6 (uint64_t insn, 2116 int64_t value, 2117 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2118 const char **errmsg ATTRIBUTE_UNUSED) 2119{ 2120 return insn | ((value & 0x1f) << 21) | ((value & 0x20) >> 2); 2121} 2122 2123static int64_t 2124extract_xtq6 (uint64_t insn, 2125 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2126 int *invalid ATTRIBUTE_UNUSED) 2127{ 2128 return ((insn << 2) & 0x20) | ((insn >> 21) & 0x1f); 2129} 2130 2131/* The XA field in an XX3 form instruction. This is split. */ 2132 2133static uint64_t 2134insert_xa6 (uint64_t insn, 2135 int64_t value, 2136 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2137 const char **errmsg ATTRIBUTE_UNUSED) 2138{ 2139 return insn | ((value & 0x1f) << 16) | ((value & 0x20) >> 3); 2140} 2141 2142static int64_t 2143extract_xa6 (uint64_t insn, 2144 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2145 int *invalid ATTRIBUTE_UNUSED) 2146{ 2147 return ((insn << 3) & 0x20) | ((insn >> 16) & 0x1f); 2148} 2149 2150/* The XA field in an MMA XX3 form instruction. This is split 2151 and must not overlap with the ACC operand. */ 2152 2153static uint64_t 2154insert_xa6a (uint64_t insn, 2155 int64_t value, 2156 ppc_cpu_t dialect, 2157 const char **errmsg) 2158{ 2159 int64_t acc = (insn >> 23) & 0x7; 2160 if ((value >> 2) == acc) 2161 *errmsg = _("VSR overlaps ACC operand"); 2162 return insert_xa6 (insn, value, dialect, errmsg); 2163} 2164 2165static int64_t 2166extract_xa6a (uint64_t insn, 2167 ppc_cpu_t dialect, 2168 int *invalid) 2169{ 2170 int64_t acc = (insn >> 23) & 0x7; 2171 int64_t value = extract_xa6 (insn, dialect, invalid); 2172 if ((value >> 2) == acc) 2173 *invalid = 1; 2174 return value; 2175} 2176 2177/* The XB field in an XX3 form instruction. This is split. */ 2178 2179static uint64_t 2180insert_xb6 (uint64_t insn, 2181 int64_t value, 2182 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2183 const char **errmsg ATTRIBUTE_UNUSED) 2184{ 2185 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 2186} 2187 2188static int64_t 2189extract_xb6 (uint64_t insn, 2190 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2191 int *invalid ATTRIBUTE_UNUSED) 2192{ 2193 return ((insn << 4) & 0x20) | ((insn >> 11) & 0x1f); 2194} 2195 2196/* The XB field in an MMA XX3 form instruction. This is split 2197 and must not overlap with the ACC operand. */ 2198 2199static uint64_t 2200insert_xb6a (uint64_t insn, 2201 int64_t value, 2202 ppc_cpu_t dialect, 2203 const char **errmsg) 2204{ 2205 int64_t acc = (insn >> 23) & 0x7; 2206 if ((value >> 2) == acc) 2207 *errmsg = _("VSR overlaps ACC operand"); 2208 return insert_xb6 (insn, value, dialect, errmsg); 2209} 2210 2211static int64_t 2212extract_xb6a (uint64_t insn, 2213 ppc_cpu_t dialect, 2214 int *invalid) 2215{ 2216 int64_t acc = (insn >> 23) & 0x7; 2217 int64_t value = extract_xb6 (insn, dialect, invalid); 2218 if ((value >> 2) == acc) 2219 *invalid = 1; 2220 return value; 2221} 2222 2223/* The XA and XB fields in an XX3 form instruction when they must be the same. 2224 This is used for extended mnemonics like xvmovdp. The extraction function 2225 enforces that the fields are the same. */ 2226 2227static uint64_t 2228insert_xab6 (uint64_t insn, 2229 int64_t value, 2230 ppc_cpu_t dialect, 2231 const char **errmsg) 2232{ 2233 return insert_xa6 (insn, value, dialect, errmsg) 2234 | insert_xb6 (insn, value, dialect, errmsg); 2235} 2236 2237static int64_t 2238extract_xab6 (uint64_t insn, 2239 ppc_cpu_t dialect, 2240 int *invalid) 2241{ 2242 int64_t xa6 = extract_xa6 (insn, dialect, invalid); 2243 int64_t xb6 = extract_xb6 (insn, dialect, invalid); 2244 2245 if (xa6 != xb6) 2246 *invalid = 1; 2247 return xa6; 2248} 2249 2250/* The XC field in an XX4 form instruction. This is split. */ 2251 2252static uint64_t 2253insert_xc6 (uint64_t insn, 2254 int64_t value, 2255 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2256 const char **errmsg ATTRIBUTE_UNUSED) 2257{ 2258 return insn | ((value & 0x1f) << 6) | ((value & 0x20) >> 2); 2259} 2260 2261static int64_t 2262extract_xc6 (uint64_t insn, 2263 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2264 int *invalid ATTRIBUTE_UNUSED) 2265{ 2266 return ((insn << 2) & 0x20) | ((insn >> 6) & 0x1f); 2267} 2268 2269/* The split XTp field in a vector paired insn. */ 2270 2271static uint64_t 2272insert_xtp (uint64_t insn, 2273 int64_t value, 2274 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2275 const char **errmsg ATTRIBUTE_UNUSED) 2276{ 2277 return insn | ((value & 0x1e) << 21) | ((value & 0x20) << (21 - 5)); 2278} 2279 2280static int64_t 2281extract_xtp (uint64_t insn, 2282 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2283 int *invalid ATTRIBUTE_UNUSED) 2284{ 2285 return ((insn >> (21 - 5)) & 0x20) | ((insn >> 21) & 0x1e); 2286} 2287 2288/* The split XT field in a vector splat insn. */ 2289 2290static uint64_t 2291insert_xts (uint64_t insn, 2292 int64_t value, 2293 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2294 const char **errmsg ATTRIBUTE_UNUSED) 2295{ 2296 return insn | ((value & 0x1f) << 21) | ((value & 0x20) << (16 - 5)); 2297} 2298 2299static int64_t 2300extract_xts (uint64_t insn, 2301 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2302 int *invalid ATTRIBUTE_UNUSED) 2303{ 2304 return ((insn >> (16 - 5)) & 0x20) | ((insn >> 21) & 0x1f); 2305} 2306 2307static uint64_t 2308insert_dm (uint64_t insn, 2309 int64_t value, 2310 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2311 const char **errmsg) 2312{ 2313 if (value != 0 && value != 1) 2314 *errmsg = _("invalid constant"); 2315 return insn | (((value) ? 3 : 0) << 8); 2316} 2317 2318static int64_t 2319extract_dm (uint64_t insn, 2320 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2321 int *invalid) 2322{ 2323 int64_t value = (insn >> 8) & 3; 2324 if (value != 0 && value != 3) 2325 *invalid = 1; 2326 return (value) ? 1 : 0; 2327} 2328 2329/* The VLESIMM field in an I16A form instruction. This is split. */ 2330 2331static uint64_t 2332insert_vlesi (uint64_t insn, 2333 int64_t value, 2334 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2335 const char **errmsg ATTRIBUTE_UNUSED) 2336{ 2337 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 2338} 2339 2340static int64_t 2341extract_vlesi (uint64_t insn, 2342 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2343 int *invalid ATTRIBUTE_UNUSED) 2344{ 2345 int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); 2346 value = (value ^ 0x8000) - 0x8000; 2347 return value; 2348} 2349 2350static uint64_t 2351insert_vlensi (uint64_t insn, 2352 int64_t value, 2353 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2354 const char **errmsg ATTRIBUTE_UNUSED) 2355{ 2356 value = -value; 2357 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 2358} 2359static int64_t 2360extract_vlensi (uint64_t insn, 2361 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2362 int *invalid) 2363{ 2364 int64_t value = ((insn >> 10) & 0xf800) | (insn & 0x7ff); 2365 value = (value ^ 0x8000) - 0x8000; 2366 /* Don't use for disassembly. */ 2367 *invalid = 1; 2368 return -value; 2369} 2370 2371/* The VLEUIMM field in an I16A form instruction. This is split. */ 2372 2373static uint64_t 2374insert_vleui (uint64_t insn, 2375 int64_t value, 2376 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2377 const char **errmsg ATTRIBUTE_UNUSED) 2378{ 2379 return insn | ((value & 0xf800) << 10) | (value & 0x7ff); 2380} 2381 2382static int64_t 2383extract_vleui (uint64_t insn, 2384 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2385 int *invalid ATTRIBUTE_UNUSED) 2386{ 2387 return ((insn >> 10) & 0xf800) | (insn & 0x7ff); 2388} 2389 2390/* The VLEUIMML field in an I16L form instruction. This is split. */ 2391 2392static uint64_t 2393insert_vleil (uint64_t insn, 2394 int64_t value, 2395 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2396 const char **errmsg ATTRIBUTE_UNUSED) 2397{ 2398 return insn | ((value & 0xf800) << 5) | (value & 0x7ff); 2399} 2400 2401static int64_t 2402extract_vleil (uint64_t insn, 2403 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2404 int *invalid ATTRIBUTE_UNUSED) 2405{ 2406 return ((insn >> 5) & 0xf800) | (insn & 0x7ff); 2407} 2408 2409static uint64_t 2410insert_evuimm1_ex0 (uint64_t insn, 2411 int64_t value, 2412 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2413 const char **errmsg) 2414{ 2415 if (value <= 0 || value > 0x1f) 2416 *errmsg = _("UIMM = 00000 is illegal"); 2417 return insn | ((value & 0x1f) << 11); 2418} 2419 2420static int64_t 2421extract_evuimm1_ex0 (uint64_t insn, 2422 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2423 int *invalid) 2424{ 2425 int64_t value = ((insn >> 11) & 0x1f); 2426 if (value == 0) 2427 *invalid = 1; 2428 2429 return value; 2430} 2431 2432static uint64_t 2433insert_evuimm2_ex0 (uint64_t insn, 2434 int64_t value, 2435 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2436 const char **errmsg) 2437{ 2438 if (value <= 0 || value > 0x3e) 2439 *errmsg = _("UIMM = 00000 is illegal"); 2440 return insn | ((value & 0x3e) << 10); 2441} 2442 2443static int64_t 2444extract_evuimm2_ex0 (uint64_t insn, 2445 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2446 int *invalid) 2447{ 2448 int64_t value = ((insn >> 10) & 0x3e); 2449 if (value == 0) 2450 *invalid = 1; 2451 2452 return value; 2453} 2454 2455static uint64_t 2456insert_evuimm4_ex0 (uint64_t insn, 2457 int64_t value, 2458 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2459 const char **errmsg) 2460{ 2461 if (value <= 0 || value > 0x7c) 2462 *errmsg = _("UIMM = 00000 is illegal"); 2463 return insn | ((value & 0x7c) << 9); 2464} 2465 2466static int64_t 2467extract_evuimm4_ex0 (uint64_t insn, 2468 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2469 int *invalid) 2470{ 2471 int64_t value = ((insn >> 9) & 0x7c); 2472 if (value == 0) 2473 *invalid = 1; 2474 2475 return value; 2476} 2477 2478static uint64_t 2479insert_evuimm8_ex0 (uint64_t insn, 2480 int64_t value, 2481 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2482 const char **errmsg) 2483{ 2484 if (value <= 0 || value > 0xf8) 2485 *errmsg = _("UIMM = 00000 is illegal"); 2486 return insn | ((value & 0xf8) << 8); 2487} 2488 2489static int64_t 2490extract_evuimm8_ex0 (uint64_t insn, 2491 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2492 int *invalid) 2493{ 2494 int64_t value = ((insn >> 8) & 0xf8); 2495 if (value == 0) 2496 *invalid = 1; 2497 2498 return value; 2499} 2500 2501static uint64_t 2502insert_evuimm_lt8 (uint64_t insn, 2503 int64_t value, 2504 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2505 const char **errmsg) 2506{ 2507 if (value < 0 || value > 7) 2508 *errmsg = _("UIMM values >7 are illegal"); 2509 return insn | ((value & 0x7) << 11); 2510} 2511 2512static int64_t 2513extract_evuimm_lt8 (uint64_t insn, 2514 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2515 int *invalid) 2516{ 2517 int64_t value = ((insn >> 11) & 0x1f); 2518 if (value > 7) 2519 *invalid = 1; 2520 2521 return value; 2522} 2523 2524static uint64_t 2525insert_evuimm_lt16 (uint64_t insn, 2526 int64_t value, 2527 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2528 const char **errmsg) 2529{ 2530 if (value < 0 || value > 15) 2531 *errmsg = _("UIMM values >15 are illegal"); 2532 return insn | ((value & 0xf) << 11); 2533} 2534 2535static int64_t 2536extract_evuimm_lt16 (uint64_t insn, 2537 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2538 int *invalid) 2539{ 2540 int64_t value = ((insn >> 11) & 0x1f); 2541 if (value > 15) 2542 *invalid = 1; 2543 2544 return value; 2545} 2546 2547static uint64_t 2548insert_rD_rS_even (uint64_t insn, 2549 int64_t value, 2550 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2551 const char **errmsg) 2552{ 2553 if ((value & 0x1) != 0) 2554 *errmsg = _("GPR odd is illegal"); 2555 return insn | ((value & 0x1e) << 21); 2556} 2557 2558static int64_t 2559extract_rD_rS_even (uint64_t insn, 2560 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2561 int *invalid) 2562{ 2563 int64_t value = ((insn >> 21) & 0x1f); 2564 if ((value & 0x1) != 0) 2565 *invalid = 1; 2566 2567 return value; 2568} 2569 2570static uint64_t 2571insert_off_lsp (uint64_t insn, 2572 int64_t value, 2573 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2574 const char **errmsg) 2575{ 2576 if (value <= 0 || value > 0x3) 2577 *errmsg = _("invalid offset"); 2578 return insn | (value & 0x3); 2579} 2580 2581static int64_t 2582extract_off_lsp (uint64_t insn, 2583 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2584 int *invalid) 2585{ 2586 int64_t value = (insn & 0x3); 2587 if (value == 0) 2588 *invalid = 1; 2589 2590 return value; 2591} 2592 2593static uint64_t 2594insert_off_spe2 (uint64_t insn, 2595 int64_t value, 2596 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2597 const char **errmsg) 2598{ 2599 if (value <= 0 || value > 0x7) 2600 *errmsg = _("invalid offset"); 2601 return insn | (value & 0x7); 2602} 2603 2604static int64_t 2605extract_off_spe2 (uint64_t insn, 2606 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2607 int *invalid) 2608{ 2609 int64_t value = (insn & 0x7); 2610 if (value == 0) 2611 *invalid = 1; 2612 2613 return value; 2614} 2615 2616static uint64_t 2617insert_Ddd (uint64_t insn, 2618 int64_t value, 2619 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2620 const char **errmsg) 2621{ 2622 if (value < 0 || value > 0x7) 2623 *errmsg = _("invalid Ddd value"); 2624 return insn | ((value & 0x3) << 11) | ((value & 0x4) >> 2); 2625} 2626 2627static int64_t 2628extract_Ddd (uint64_t insn, 2629 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2630 int *invalid ATTRIBUTE_UNUSED) 2631{ 2632 return ((insn >> 11) & 0x3) | ((insn << 2) & 0x4); 2633} 2634 2635static uint64_t 2636insert_sxl (uint64_t insn, 2637 int64_t value, 2638 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2639 const char **errmsg ATTRIBUTE_UNUSED) 2640{ 2641 return insn | ((value & 0x1) << 11); 2642} 2643 2644static int64_t 2645extract_sxl (uint64_t insn, 2646 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2647 int *invalid) 2648{ 2649 /* Missing optional operands have a value of one. */ 2650 if (*invalid < 0) 2651 return 1; 2652 return (insn >> 11) & 0x1; 2653} 2654 2655/* The list of embedded processors that use the embedded operand ordering 2656 for the 3 operand dcbt and dcbtst instructions. */ 2657#define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \ 2658 | PPC_OPCODE_A2) 2659 2660/* ISA 2.03 and later specify extended mnemonics dcbtct, dcbtds, and 2661 dcbtstct, dcbtstds with a note saying these should be used in new 2662 programs rather than the base mnemonics "so that it can be coded 2663 with TH as the last operand for all categories". For that reason 2664 the extended mnemonics are enabled in the assembler for the 2665 embedded processors, but not for the disassembler so as to display 2666 the embedded dcbt or dcbtst expected form with TH first for 2667 embedded programmers. */ 2668 2669static uint64_t 2670insert_thct (uint64_t insn, 2671 int64_t value, 2672 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2673 const char **errmsg) 2674{ 2675 if ((uint64_t) value > 7) 2676 *errmsg = _("invalid TH value"); 2677 return insn | ((value & 7) << 21); 2678} 2679 2680static int64_t 2681extract_thct (uint64_t insn, 2682 ppc_cpu_t dialect, 2683 int *invalid) 2684{ 2685 /* Missing optional operands have a value of 0. */ 2686 if (*invalid < 0) 2687 return 0; 2688 2689 int64_t value = (insn >> 21) & 0x1f; 2690 if (value > 7 || (dialect & DCBT_EO) != 0) 2691 *invalid = 1; 2692 2693 return value; 2694} 2695 2696static uint64_t 2697insert_thds (uint64_t insn, 2698 int64_t value, 2699 ppc_cpu_t dialect ATTRIBUTE_UNUSED, 2700 const char **errmsg) 2701{ 2702 if (value < 8 || value > 15) 2703 *errmsg = _("invalid TH value"); 2704 return insn | ((value & 0x1f) << 21); 2705} 2706 2707static int64_t 2708extract_thds (uint64_t insn, 2709 ppc_cpu_t dialect, 2710 int *invalid) 2711{ 2712 /* Missing optional operands have a value of 8. */ 2713 if (*invalid < 0) 2714 return 8; 2715 2716 int64_t value = (insn >> 21) & 0x1f; 2717 if (value < 8 || value > 15 || (dialect & DCBT_EO) != 0) 2718 *invalid = 1; 2719 2720 return value; 2721} 2722 2723/* The operands table. 2724 2725 The fields are bitm, shift, insert, extract, flags. 2726 2727 We used to put parens around the various additions, like the one 2728 for BA just below. However, that caused trouble with feeble 2729 compilers with a limit on depth of a parenthesized expression, like 2730 (reportedly) the compiler in Microsoft Developer Studio 5. So we 2731 omit the parens, since the macros are never used in a context where 2732 the addition will be ambiguous. */ 2733 2734const struct powerpc_operand powerpc_operands[] = 2735{ 2736 /* The zero index is used to indicate the end of the list of 2737 operands. */ 2738#define UNUSED 0 2739 { 0, 0, NULL, NULL, 0 }, 2740 2741 /* The BA field in an XL form instruction. */ 2742#define BA UNUSED + 1 2743 /* The BI field in a B form or XL form instruction. */ 2744#define BI BA 2745#define BI_MASK (0x1f << 16) 2746 { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, 2747 2748 /* The BT, BA and BB fields in a XL form instruction when they must all 2749 be the same. */ 2750#define BTAB BA + 1 2751 { 0x1f, 21, insert_btab, extract_btab, PPC_OPERAND_CR_BIT }, 2752 2753 /* The BB field in an XL form instruction. */ 2754#define BB BTAB + 1 2755#define BB_MASK (0x1f << 11) 2756 { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR_BIT }, 2757 2758 /* The BA and BB fields in a XL form instruction when they must be 2759 the same. */ 2760#define BAB BB + 1 2761 { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_CR_BIT }, 2762 2763 /* The VRA and VRB fields in a VX form instruction when they must be the same. 2764 This is used for extended mnemonics like vmr. */ 2765#define VAB BAB + 1 2766 { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_VR }, 2767 2768 /* The RA and RB fields in a VX form instruction when they must be the same. 2769 This is used for extended mnemonics like evmr. */ 2770#define RAB VAB + 1 2771 { 0x1f, 16, insert_bab, extract_bab, PPC_OPERAND_GPR }, 2772 2773#define BC RAB + 1 2774 { 0x1f, 6, NULL, NULL, PPC_OPERAND_CR_BIT }, 2775 2776 /* The BD field in a B form instruction. The lower two bits are 2777 forced to zero. */ 2778#define BD BC + 1 2779 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 2780 2781 /* The BD field in a B form instruction when absolute addressing is 2782 used. */ 2783#define BDA BD + 1 2784 { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 2785 2786 /* The BD field in a B form instruction when the - modifier is used. 2787 This sets the y bit of the BO field appropriately. */ 2788#define BDM BDA + 1 2789 { 0xfffc, 0, insert_bdm, extract_bdm, 2790 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 2791 2792 /* The BD field in a B form instruction when the - modifier is used 2793 and absolute address is used. */ 2794#define BDMA BDM + 1 2795 { 0xfffc, 0, insert_bdm, extract_bdm, 2796 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 2797 2798 /* The BD field in a B form instruction when the + modifier is used. 2799 This sets the y bit of the BO field appropriately. */ 2800#define BDP BDMA + 1 2801 { 0xfffc, 0, insert_bdp, extract_bdp, 2802 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 2803 2804 /* The BD field in a B form instruction when the + modifier is used 2805 and absolute addressing is used. */ 2806#define BDPA BDP + 1 2807 { 0xfffc, 0, insert_bdp, extract_bdp, 2808 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 2809 2810 /* The BF field in an X or XL form instruction. */ 2811#define BF BDPA + 1 2812 /* The CRFD field in an X form instruction. */ 2813#define CRFD BF 2814 /* The CRD field in an XL form instruction. */ 2815#define CRD BF 2816 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG }, 2817 2818 /* The BF field in an X or XL form instruction. */ 2819#define BFF BF + 1 2820 { 0x7, 23, NULL, NULL, 0 }, 2821 2822 /* The ACC field in a VSX ACC 8LS:D-form instruction. */ 2823#define ACC BFF + 1 2824 { 0x7, 23, NULL, NULL, PPC_OPERAND_ACC }, 2825 2826 /* An optional BF field. This is used for comparison instructions, 2827 in which an omitted BF field is taken as zero. */ 2828#define OBF ACC + 1 2829 { 0x7, 23, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 2830 2831 /* The BFA field in an X or XL form instruction. */ 2832#define BFA OBF + 1 2833 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG }, 2834 2835 /* The BO field in a B form instruction. Certain values are 2836 illegal. */ 2837#define BO BFA + 1 2838#define BO_MASK (0x1f << 21) 2839 { 0x1f, 21, insert_bo, extract_bo, 0 }, 2840 2841 /* The BO field in a B form instruction when the - modifier is used. */ 2842#define BOM BO + 1 2843 { 0x1f, 21, insert_bom, extract_bom, 0 }, 2844 2845 /* The BO field in a B form instruction when the + modifier is used. */ 2846#define BOP BOM + 1 2847 { 0x1f, 21, insert_bop, extract_bop, 0 }, 2848 2849 /* The RM field in an X form instruction. */ 2850#define RM BOP + 1 2851#define DD RM 2852 { 0x3, 11, NULL, NULL, 0 }, 2853 2854#define BH RM + 1 2855 { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2856 2857 /* The BT field in an X or XL form instruction. */ 2858#define BT BH + 1 2859 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT }, 2860 2861 /* The BT field in a mtfsb0 or mtfsb1 instruction. */ 2862#define BTF BT + 1 2863 { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR_BIT | PPC_OPERAND_CR_REG }, 2864 2865 /* The BI16 field in a BD8 form instruction. */ 2866#define BI16 BTF + 1 2867 { 0x3, 8, NULL, NULL, PPC_OPERAND_CR_BIT }, 2868 2869 /* The BI32 field in a BD15 form instruction. */ 2870#define BI32 BI16 + 1 2871 { 0xf, 16, NULL, NULL, PPC_OPERAND_CR_BIT }, 2872 2873 /* The BO32 field in a BD15 form instruction. */ 2874#define BO32 BI32 + 1 2875 { 0x3, 20, NULL, NULL, 0 }, 2876 2877 /* The B8 field in a BD8 form instruction. */ 2878#define B8 BO32 + 1 2879 { 0x1fe, -1, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 2880 2881 /* The B15 field in a BD15 form instruction. The lowest bit is 2882 forced to zero. */ 2883#define B15 B8 + 1 2884 { 0xfffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 2885 2886 /* The B24 field in a BD24 form instruction. The lowest bit is 2887 forced to zero. */ 2888#define B24 B15 + 1 2889 { 0x1fffffe, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 2890 2891 /* The condition register number portion of the BI field in a B form 2892 or XL form instruction. This is used for the extended 2893 conditional branch mnemonics, which set the lower two bits of the 2894 BI field. This field is optional. */ 2895#define CR B24 + 1 2896 { 0x7, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 2897 2898 /* The CRB field in an X form instruction. */ 2899#define CRB CR + 1 2900 /* The MB field in an M form instruction. */ 2901#define MB CRB 2902#define MB_MASK (0x1f << 6) 2903 { 0x1f, 6, NULL, NULL, 0 }, 2904 2905 /* The CRD32 field in an XL form instruction. */ 2906#define CRD32 CRB + 1 2907 { 0x3, 21, NULL, NULL, PPC_OPERAND_CR_REG }, 2908 2909 /* The CRFS field in an X form instruction. */ 2910#define CRFS CRD32 + 1 2911 { 0x7, 0, NULL, NULL, PPC_OPERAND_CR_REG }, 2912 2913#define CRS CRFS + 1 2914 { 0x3, 18, NULL, NULL, PPC_OPERAND_CR_REG | PPC_OPERAND_OPTIONAL }, 2915 2916 /* The CT field in an X form instruction. */ 2917#define CT CRS + 1 2918 /* The MO field in an mbar instruction. */ 2919#define MO CT 2920 { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 2921 2922 /* The TH field in dcbtct. */ 2923#define THCT CT + 1 2924 { 0x1f, 21, insert_thct, extract_thct, PPC_OPERAND_OPTIONAL }, 2925 2926 /* The TH field in dcbtds. */ 2927#define THDS THCT + 1 2928 { 0x1f, 21, insert_thds, extract_thds, PPC_OPERAND_OPTIONAL }, 2929 2930 /* The D field in a D form instruction. This is a displacement off 2931 a register, and implies that the next operand is a register in 2932 parentheses. */ 2933#define D THDS + 1 2934 { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 2935 2936 /* The D8 field in a D form instruction. This is a displacement off 2937 a register, and implies that the next operand is a register in 2938 parentheses. */ 2939#define D8 D + 1 2940 { 0xff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 2941 2942 /* The DCMX field in an X form instruction. */ 2943#define DCMX D8 + 1 2944 { 0x7f, 16, NULL, NULL, 0 }, 2945 2946 /* The split DCMX field in an X form instruction. */ 2947#define DCMXS DCMX + 1 2948 { 0x7f, PPC_OPSHIFT_INV, insert_dcmxs, extract_dcmxs, 0 }, 2949 2950 /* The DQ field in a DQ form instruction. This is like D, but the 2951 lower four bits are forced to zero. */ 2952#define DQ DCMXS + 1 2953 { 0xfff0, 0, NULL, NULL, 2954 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 2955 2956 /* The DS field in a DS form instruction. This is like D, but the 2957 lower two bits are forced to zero. */ 2958#define DS DQ + 1 2959 { 0xfffc, 0, NULL, NULL, 2960 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 2961 2962 /* The D field in an 8-byte D form prefix instruction. This is a displacement 2963 off a register, and implies that the next operand is a register in 2964 parentheses. */ 2965#define D34 DS + 1 2966 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34, 2967 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 2968 2969 /* The SI field in an 8-byte D form prefix instruction. */ 2970#define SI34 D34 + 1 2971 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_d34, extract_d34, PPC_OPERAND_SIGNED }, 2972 2973 /* The NSI field in an 8-byte D form prefix instruction. This is the 2974 same as the SI34 field, only negated. */ 2975#define NSI34 SI34 + 1 2976 { UINT64_C(0x3ffffffff), PPC_OPSHIFT_INV, insert_nsi34, extract_nsi34, 2977 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 2978 2979 /* The IMM32 field in a vector splat immediate prefix instruction. */ 2980#define IMM32 NSI34 + 1 2981 { 0xffffffff, PPC_OPSHIFT_INV, insert_imm32, extract_imm32, 0}, 2982 2983 /* The UIM field in a vector permute extended prefix instruction. */ 2984#define UIM3 IMM32 + 1 2985 { 0x7, 32, NULL, NULL, 0}, 2986 2987 /* The UIM field in a vector eval prefix instruction. */ 2988#define UIM8 UIM3 + 1 2989 { 0xff, 32, NULL, NULL, 0}, 2990 2991 /* The IX field in xxsplti32dx. */ 2992#define IX UIM8 + 1 2993 { 0x1, 17, NULL, NULL, 0 }, 2994 2995 /* The PMSK field in GER rank 8 prefix instructions. */ 2996#define PMSK8 IX + 1 2997 { 0xff, 40, NULL, NULL, 0 }, 2998 2999 /* The PMSK field in GER rank 4 prefix instructions. */ 3000#define PMSK4 PMSK8 + 1 3001 { 0xf, 44, NULL, NULL, 0 }, 3002 3003 /* The PMSK field in GER rank 2 prefix instructions. */ 3004#define PMSK2 PMSK4 + 1 3005 { 0x3, 46, NULL, NULL, 0 }, 3006 3007 /* The XMSK field in GER prefix instructions. */ 3008#define XMSK PMSK2 + 1 3009 { 0xf, 36, NULL, NULL, 0 }, 3010 3011 /* The YMSK field in GER prefix instructions. */ 3012#define YMSK XMSK + 1 3013 { 0xf, 32, NULL, NULL, 0 }, 3014 3015 /* The YMSK field in 64-bit GER prefix instructions. */ 3016#define YMSK2 YMSK + 1 3017 { 0x3, 34, NULL, NULL, 0 }, 3018 3019 /* The DUIS or BHRBE fields in a XFX form instruction, 10 bits 3020 unsigned imediate */ 3021#define DUIS YMSK2 + 1 3022#define BHRBE DUIS 3023 { 0x3ff, 11, NULL, NULL, 0 }, 3024 3025 /* The split DW field in a X form instruction. */ 3026#define DW DUIS + 1 3027 { -1, PPC_OPSHIFT_INV, insert_dw, extract_dw, 3028 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED}, 3029 3030 /* The split D field in a DX form instruction. */ 3031#define DXD DW + 1 3032 { 0xffff, PPC_OPSHIFT_INV, insert_dxd, extract_dxd, 3033 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, 3034 3035 /* The split ND field in a DX form instruction. 3036 This is the same as the DX field, only negated. */ 3037#define NDXD DXD + 1 3038 { 0xffff, PPC_OPSHIFT_INV, insert_dxdn, extract_dxdn, 3039 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT}, 3040 3041 /* The E field in a wrteei instruction. */ 3042 /* And the W bit in the pair singles instructions. */ 3043 /* And the ST field in a VX form instruction. */ 3044#define E NDXD + 1 3045#define PSW E 3046#define ST E 3047 { 0x1, 15, NULL, NULL, 0 }, 3048 3049 /* The FL1 field in a POWER SC form instruction. */ 3050#define FL1 E + 1 3051 /* The U field in an X form instruction. */ 3052#define U FL1 3053 { 0xf, 12, NULL, NULL, 0 }, 3054 3055 /* The FL2 field in a POWER SC form instruction. */ 3056#define FL2 FL1 + 1 3057 { 0x7, 2, NULL, NULL, 0 }, 3058 3059 /* The FLM field in an XFL form instruction. */ 3060#define FLM FL2 + 1 3061 { 0xff, 17, NULL, NULL, 0 }, 3062 3063 /* The FRA field in an X or A form instruction. */ 3064#define FRA FLM + 1 3065#define FRA_MASK (0x1f << 16) 3066 { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR }, 3067 3068 /* The FRAp field of DFP instructions. */ 3069#define FRAp FRA + 1 3070 { 0x1e, 16, NULL, NULL, PPC_OPERAND_FPR }, 3071 3072 /* The FRB field in an X or A form instruction. */ 3073#define FRB FRAp + 1 3074#define FRB_MASK (0x1f << 11) 3075 { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR }, 3076 3077 /* The FRBp field of DFP instructions. */ 3078#define FRBp FRB + 1 3079 { 0x1e, 11, NULL, NULL, PPC_OPERAND_FPR }, 3080 3081 /* The FRC field in an A form instruction. */ 3082#define FRC FRBp + 1 3083#define FRC_MASK (0x1f << 6) 3084 { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR }, 3085 3086 /* The FRS field in an X form instruction or the FRT field in a D, X 3087 or A form instruction. */ 3088#define FRS FRC + 1 3089#define FRT FRS 3090 { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR }, 3091 3092 /* The FRSp field of stfdp or the FRTp field of lfdp and DFP 3093 instructions. */ 3094#define FRSp FRS + 1 3095#define FRTp FRSp 3096 { 0x1e, 21, NULL, NULL, PPC_OPERAND_FPR }, 3097 3098 /* The FXM field in an XFX instruction. */ 3099#define FXM FRSp + 1 3100 { 0xff, 12, insert_fxm, extract_fxm, 0 }, 3101 3102 /* Power4 version for mfcr. */ 3103#define FXM4 FXM + 1 3104 { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, 3105 3106 /* The IMM20 field in an LI instruction. */ 3107#define IMM20 FXM4 + 1 3108 { 0xfffff, PPC_OPSHIFT_INV, insert_li20, extract_li20, PPC_OPERAND_SIGNED}, 3109 3110 /* The L field in a D or X form instruction. */ 3111#define L IMM20 + 1 3112 { 0x1, 21, NULL, NULL, 0 }, 3113 3114 /* The optional L field in tlbie and tlbiel instructions. */ 3115#define LOPT L + 1 3116 /* The R field in a HTM X form instruction. */ 3117#define HTM_R LOPT 3118 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 3119 3120 /* The optional L field in the paste. instruction. This is similar to LOPT 3121 above, but with a default value of 1. */ 3122#define L1OPT LOPT + 1 3123 { 0x1, 21, insert_l1opt, extract_l1opt, PPC_OPERAND_OPTIONAL }, 3124 3125 /* The optional (for 32-bit) L field in cmp[l][i] instructions. */ 3126#define L32OPT L1OPT + 1 3127 { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 }, 3128 3129 /* The 2-bit L or WC field in an X (sync, dcbf or wait) form instruction. */ 3130#define L2OPT L32OPT + 1 3131#define LS L2OPT 3132#define WC L2OPT 3133 { 0x3, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL }, 3134 3135 /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */ 3136#define SVC_LEV L2OPT + 1 3137 { 0x7f, 5, NULL, NULL, 0 }, 3138 3139 /* The LEV field in an SC form instruction. */ 3140#define LEV SVC_LEV + 1 3141 { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, 3142 3143 /* The LI field in an I form instruction. The lower two bits are 3144 forced to zero. */ 3145#define LI LEV + 1 3146 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 3147 3148 /* The LI field in an I form instruction when used as an absolute 3149 address. */ 3150#define LIA LI + 1 3151 { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 3152 3153 /* The 3-bit L field in a sync or dcbf instruction. */ 3154#define LS3 LIA + 1 3155#define L3OPT LS3 3156 { 0x7, 21, insert_ls, extract_ls, PPC_OPERAND_OPTIONAL }, 3157 3158 /* The ME field in an M form instruction. */ 3159#define ME LS3 + 1 3160#define ME_MASK (0x1f << 1) 3161 { 0x1f, 1, NULL, NULL, 0 }, 3162 3163#define CRWn ME + 1 3164 { 0x1f, 1, insert_crwn, extract_crwn, 0 }, 3165 3166#define ELWn CRWn + 1 3167 { 0x1f, 1, insert_elwn, extract_elwn, PPC_OPERAND_PLUS1 }, 3168 3169#define ERWn ELWn + 1 3170 { 0x1f, 6, insert_erwn, extract_erwn, 0 }, 3171 3172#define ERWb ERWn + 1 3173 { 0x1f, 11, insert_erwb, extract_erwb, 0 }, 3174 3175#define CSLWb ERWb + 1 3176 { 0x1f, 6, NULL, extract_cslwb, 0 }, 3177 3178#define CSLWn CSLWb + 1 3179 { 0x1f, 11, insert_cslwn, NULL, 0 }, 3180 3181#define ILWn CSLWn + 1 3182 { 0x1f, 1, NULL, extract_ilwn, PPC_OPERAND_PLUS1 }, 3183 3184#define ILWb ILWn + 1 3185 { 0x1f, 6, insert_ilwb, NULL, 0 }, 3186 3187#define IRWn ILWb + 1 3188 { 0x1f, 1, NULL, extract_irwn, PPC_OPERAND_PLUS1 }, 3189 3190#define IRWb IRWn + 1 3191 { 0x1f, 6, insert_irwb, NULL, 0 }, 3192 3193 /* The MB and ME fields in an M form instruction expressed a single 3194 operand which is a bitmask indicating which bits to select. This 3195 is a two operand form using PPC_OPERAND_NEXT. See the 3196 description in opcode/ppc.h for what this means. */ 3197#define MBE IRWb + 1 3198 { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 3199 { -1, 0, insert_mbe, extract_mbe, 0 }, 3200 3201 /* The MB or ME field in an MD or MDS form instruction. The high 3202 bit is wrapped to the low end. */ 3203#define MB6 MBE + 2 3204#define ME6 MB6 3205#define MB6_MASK (0x3f << 5) 3206 { 0x3f, 5, insert_mb6, extract_mb6, 0 }, 3207 3208#define ELDn MB6 + 1 3209 { 0x3f, 5, insert_eldn, extract_eldn, PPC_OPERAND_PLUS1 }, 3210 3211#define ERDn ELDn + 1 3212 { 0x3f, 5, insert_erdn, extract_erdn, 0 }, 3213 3214#define CRDn ERDn + 1 3215 { 0x3f, 5, insert_crdn, extract_crdn, 0 }, 3216 3217 /* The NB field in an X form instruction. The value 32 is stored as 3218 0. */ 3219#define NB CRDn + 1 3220 { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 }, 3221 3222 /* The NBI field in an lswi instruction, which has special value 3223 restrictions. The value 32 is stored as 0. */ 3224#define NBI NB + 1 3225 { 0x1f, 11, insert_nbi, extract_nb, PPC_OPERAND_PLUS1 }, 3226 3227 /* The NSI field in a D form instruction. This is the same as the 3228 SI field, only negated. */ 3229#define NSI NBI + 1 3230 { 0xffff, 0, insert_nsi, extract_nsi, 3231 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 3232 3233 /* The NSI field in a D form instruction when we accept a wide range 3234 of positive values. */ 3235#define NSISIGNOPT NSI + 1 3236 { 0xffff, 0, insert_nsi, extract_nsi, 3237 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 3238 3239 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 3240#define RA NSISIGNOPT + 1 3241#define RA_MASK (0x1f << 16) 3242 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR }, 3243 3244 /* As above, but 0 in the RA field means zero, not r0. */ 3245#define RA0 RA + 1 3246 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 3247 3248 /* Similar to above, but optional. */ 3249#define PRA0 RA0 + 1 3250 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 | PPC_OPERAND_OPTIONAL }, 3251 3252 /* The RA field in the DQ form lq or an lswx instruction, which have 3253 special value restrictions. */ 3254#define RAQ PRA0 + 1 3255#define RAX RAQ 3256 { 0x1f, 16, insert_raq, extract_raq, PPC_OPERAND_GPR_0 }, 3257 3258 /* Similar to above, but optional. */ 3259#define PRAQ RAQ + 1 3260 { 0x1f, 16, insert_raq, extract_raq, 3261 PPC_OPERAND_GPR_0 | PPC_OPERAND_OPTIONAL }, 3262 3263 /* The R field in an 8-byte D, DS, DQ or X form prefix instruction. */ 3264#define PCREL PRAQ + 1 3265#define PCREL_MASK (1ULL << 52) 3266 { 0x1, 52, insert_pcrel, extract_pcrel, PPC_OPERAND_OPTIONAL }, 3267 3268#define PCREL0 PCREL + 1 3269 { 0x1, 52, insert_pcrel, extract_pcrel0, PPC_OPERAND_OPTIONAL }, 3270 3271 /* The RA field in a D or X form instruction which is an updating 3272 load, which means that the RA field may not be zero and may not 3273 equal the RT field. */ 3274#define RAL PCREL0 + 1 3275 { 0x1f, 16, insert_ral, extract_ral, PPC_OPERAND_GPR_0 }, 3276 3277 /* The RA field in an lmw instruction, which has special value 3278 restrictions. */ 3279#define RAM RAL + 1 3280 { 0x1f, 16, insert_ram, extract_ram, PPC_OPERAND_GPR_0 }, 3281 3282 /* The RA field in a D or X form instruction which is an updating 3283 store or an updating floating point load, which means that the RA 3284 field may not be zero. */ 3285#define RAS RAM + 1 3286 { 0x1f, 16, insert_ras, extract_ras, PPC_OPERAND_GPR_0 }, 3287 3288 /* The RA field of the tlbwe, dccci and iccci instructions, 3289 which are optional. */ 3290#define RAOPT RAS + 1 3291 { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 3292 3293 /* The RB field in an X, XO, M, or MDS form instruction. */ 3294#define RB RAOPT + 1 3295#define RB_MASK (0x1f << 11) 3296 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR }, 3297 3298 /* The RS and RB fields in an X form instruction when they must be the same. 3299 This is used for extended mnemonics like mr. */ 3300#define RSB RB + 1 3301 { 0x1f, 11, insert_rsb, extract_rsb, PPC_OPERAND_GPR }, 3302 3303 /* The RB field in an lswx instruction, which has special value 3304 restrictions. */ 3305#define RBX RSB + 1 3306 { 0x1f, 11, insert_rbx, extract_rbx, PPC_OPERAND_GPR }, 3307 3308 /* The RB field of the dccci and iccci instructions, which are optional. */ 3309#define RBOPT RBX + 1 3310 { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 3311 3312 /* The RC register field in an maddld, maddhd or maddhdu instruction. */ 3313#define RC RBOPT + 1 3314 { 0x1f, 6, NULL, NULL, PPC_OPERAND_GPR }, 3315 3316 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 3317 instruction or the RT field in a D, DS, X, XFX or XO form 3318 instruction. */ 3319#define RS RC + 1 3320#define RT RS 3321#define RT_MASK (0x1f << 21) 3322#define RD RS 3323 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR }, 3324 3325#define RD_EVEN RS + 1 3326#define RS_EVEN RD_EVEN 3327 { 0x1f, 21, insert_rD_rS_even, extract_rD_rS_even, PPC_OPERAND_GPR }, 3328 3329 /* The RS and RT fields of the DS form stq and DQ form lq instructions, 3330 which have special value restrictions. */ 3331#define RSQ RS_EVEN + 1 3332#define RTQ RSQ 3333#define Q_MASK (1 << 21) 3334 { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR }, 3335 3336 /* The RS field of the tlbwe instruction, which is optional. */ 3337#define RSO RSQ + 1 3338#define RTO RSO 3339 { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 3340 3341 /* The RX field of the SE_RR form instruction. */ 3342#define RX RSO + 1 3343 { 0x1f, PPC_OPSHIFT_INV, insert_rx, extract_rx, PPC_OPERAND_GPR }, 3344 3345 /* The ARX field of the SE_RR form instruction. */ 3346#define ARX RX + 1 3347 { 0x1f, PPC_OPSHIFT_INV, insert_arx, extract_arx, PPC_OPERAND_GPR }, 3348 3349 /* The RY field of the SE_RR form instruction. */ 3350#define RY ARX + 1 3351#define RZ RY 3352 { 0x1f, PPC_OPSHIFT_INV, insert_ry, extract_ry, PPC_OPERAND_GPR }, 3353 3354 /* The ARY field of the SE_RR form instruction. */ 3355#define ARY RY + 1 3356 { 0x1f, PPC_OPSHIFT_INV, insert_ary, extract_ary, PPC_OPERAND_GPR }, 3357 3358 /* The SCLSCI8 field in a D form instruction. */ 3359#define SCLSCI8 ARY + 1 3360 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8, extract_sci8, 0 }, 3361 3362 /* The SCLSCI8N field in a D form instruction. This is the same as the 3363 SCLSCI8 field, only negated. */ 3364#define SCLSCI8N SCLSCI8 + 1 3365 { 0xffffffff, PPC_OPSHIFT_INV, insert_sci8n, extract_sci8n, 3366 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 3367 3368 /* The SD field of the SD4 form instruction. */ 3369#define SE_SD SCLSCI8N + 1 3370 { 0xf, 8, NULL, NULL, PPC_OPERAND_PARENS }, 3371 3372 /* The SD field of the SD4 form instruction, for halfword. */ 3373#define SE_SDH SE_SD + 1 3374 { 0x1e, 7, NULL, NULL, PPC_OPERAND_PARENS }, 3375 3376 /* The SD field of the SD4 form instruction, for word. */ 3377#define SE_SDW SE_SDH + 1 3378 { 0x3c, 6, NULL, NULL, PPC_OPERAND_PARENS }, 3379 3380 /* The SH field in an X or M form instruction. */ 3381#define SH SE_SDW + 1 3382#define SH_MASK (0x1f << 11) 3383 /* The other UIMM field in a EVX form instruction. */ 3384#define EVUIMM SH 3385 /* The FC field in an atomic X form instruction. */ 3386#define FC SH 3387#define UIM5 SH 3388 { 0x1f, 11, NULL, NULL, 0 }, 3389 3390#define RRWn SH + 1 3391 { 0x1f, 11, insert_rrwn, extract_rrwn, 0 }, 3392 3393#define SLWn RRWn + 1 3394 { 0x1f, 11, insert_slwn, extract_slwn, 0 }, 3395 3396#define SRWn SLWn + 1 3397 { 0x1f, 11, insert_srwn, extract_srwn, 0 }, 3398 3399#define EVUIMM_LT8 SRWn + 1 3400 { 0x1f, 11, insert_evuimm_lt8, extract_evuimm_lt8, 0 }, 3401 3402#define EVUIMM_LT16 EVUIMM_LT8 + 1 3403 { 0x1f, 11, insert_evuimm_lt16, extract_evuimm_lt16, 0 }, 3404 3405 /* The SI field in a HTM X form instruction. */ 3406#define HTM_SI EVUIMM_LT16 + 1 3407 { 0x1f, 11, NULL, NULL, PPC_OPERAND_SIGNED }, 3408 3409 /* The SH field in an MD form instruction. This is split. */ 3410#define SH6 HTM_SI + 1 3411#define SH6_MASK ((0x1f << 11) | (1 << 1)) 3412 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_sh6, 0 }, 3413 3414#define RRDn SH6 + 1 3415 { 0x3f, PPC_OPSHIFT_INV, insert_rrdn, extract_rrdn, 0 }, 3416 3417#define SLDn RRDn + 1 3418 { 0x3f, PPC_OPSHIFT_INV, insert_sldn, extract_sldn, 0 }, 3419 3420#define SRDn SLDn + 1 3421 { 0x3f, PPC_OPSHIFT_INV, insert_srdn, extract_srdn, 0 }, 3422 3423#define ERDb SRDn + 1 3424 { 0x3f, PPC_OPSHIFT_INV, insert_erdb, extract_erdb, 0 }, 3425 3426#define CSLDn ERDb + 1 3427 { 0x3f, PPC_OPSHIFT_SH6, insert_csldn, extract_sh6, 0 }, 3428 3429#define CSLDb CSLDn + 1 3430 { 0x3f, 5, insert_mb6, extract_csldb, 0 }, 3431 3432#define IRDn CSLDb + 1 3433 { 0x3f, PPC_OPSHIFT_INV, insert_sh6, extract_irdn, PPC_OPERAND_PLUS1 }, 3434 3435#define IRDb IRDn + 1 3436 { 0x3f, 5, insert_irdb, extract_mb6, 0 }, 3437 3438 /* The SH field of some variants of the tlbre and tlbwe 3439 instructions, and the ELEV field of the e_sc instruction. */ 3440#define SHO IRDb + 1 3441#define ELEV SHO 3442 { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 3443 3444 /* The SI field in a D form instruction. */ 3445#define SI SHO + 1 3446 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 3447 3448 /* The SI field in a D form instruction when we accept a wide range 3449 of positive values. */ 3450#define SISIGNOPT SI + 1 3451 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 3452 3453 /* The SI8 field in a D form instruction. */ 3454#define SI8 SISIGNOPT + 1 3455 { 0xff, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 3456 3457 /* The SPR field in an XFX form instruction. This is flipped--the 3458 lower 5 bits are stored in the upper 5 and vice- versa. */ 3459#define SPR SI8 + 1 3460#define PMR SPR 3461#define TMR SPR 3462#define SPR_MASK (0x3ff << 11) 3463 { 0x3ff, 11, insert_spr, extract_spr, PPC_OPERAND_SPR }, 3464 3465 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 3466#define SPRBAT SPR + 1 3467#define SPRBAT_MASK (0xc1 << 11) 3468 { 0x7, PPC_OPSHIFT_INV, insert_sprbat, extract_sprbat, PPC_OPERAND_SPR }, 3469 3470 /* The GQR index number in an XFX form m[ft]gqr instruction. */ 3471#define SPRGQR SPRBAT + 1 3472#define SPRGQR_MASK (0x7 << 16) 3473 { 0x7, 16, NULL, NULL, PPC_OPERAND_GQR }, 3474 3475 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 3476#define SPRG SPRGQR + 1 3477 { 0x1f, 16, insert_sprg, extract_sprg, PPC_OPERAND_SPR }, 3478 3479 /* The SR field in an X form instruction. */ 3480#define SR SPRG + 1 3481 /* The 4-bit UIMM field in a VX form instruction. */ 3482#define UIMM4 SR 3483 { 0xf, 16, NULL, NULL, 0 }, 3484 3485 /* The STRM field in an X AltiVec form instruction. */ 3486#define STRM SR + 1 3487 /* The T field in a tlbilx form instruction. */ 3488#define T STRM 3489 /* The L field in wclr instructions. */ 3490#define L2 STRM 3491 { 0x3, 21, NULL, NULL, 0 }, 3492 3493 /* The ESYNC field in an X (sync) form instruction. */ 3494#define ESYNC STRM + 1 3495 { 0xf, 16, insert_esync, extract_esync, PPC_OPERAND_OPTIONAL }, 3496 3497 /* The SV field in a POWER SC form instruction. */ 3498#define SV ESYNC + 1 3499 { 0x3fff, 2, NULL, NULL, 0 }, 3500 3501 /* The TBR field in an XFX form instruction. This is like the SPR 3502 field, but it is optional. */ 3503#define TBR SV + 1 3504 { 0x3ff, 11, insert_tbr, extract_tbr, 3505 PPC_OPERAND_SPR | PPC_OPERAND_OPTIONAL }, 3506 3507 /* The TO field in a D or X form instruction. */ 3508#define TO TBR + 1 3509#define DUI TO 3510#define TO_MASK (0x1f << 21) 3511 { 0x1f, 21, NULL, NULL, 0 }, 3512 3513 /* The UI field in a D form instruction. */ 3514#define UI TO + 1 3515 { 0xffff, 0, NULL, NULL, 0 }, 3516 3517#define UISIGNOPT UI + 1 3518 { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNOPT }, 3519 3520 /* The IMM field in an SE_IM5 instruction. */ 3521#define UI5 UISIGNOPT + 1 3522 { 0x1f, 4, NULL, NULL, 0 }, 3523 3524 /* The OIMM field in an SE_OIM5 instruction. */ 3525#define OIMM5 UI5 + 1 3526 { 0x1f, 4, insert_oimm, extract_oimm, PPC_OPERAND_PLUS1 }, 3527 3528 /* The UI7 field in an SE_LI instruction. */ 3529#define UI7 OIMM5 + 1 3530 { 0x7f, 4, NULL, NULL, 0 }, 3531 3532 /* The VA field in a VA, VX or VXR form instruction. */ 3533#define VA UI7 + 1 3534 { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR }, 3535 3536 /* The VB field in a VA, VX or VXR form instruction. */ 3537#define VB VA + 1 3538 { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR }, 3539 3540 /* The VC field in a VA form instruction. */ 3541#define VC VB + 1 3542 { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR }, 3543 3544 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 3545#define VD VC + 1 3546#define VS VD 3547 { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR }, 3548 3549 /* The SIMM field in a VX form instruction, and TE in Z form. */ 3550#define SIMM VD + 1 3551#define TE SIMM 3552 { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 3553 3554 /* The UIMM field in a VX form instruction. */ 3555#define UIMM SIMM + 1 3556#define DCTL UIMM 3557 { 0x1f, 16, NULL, NULL, 0 }, 3558 3559 /* The 3-bit UIMM field in a VX form instruction. */ 3560#define UIMM3 UIMM + 1 3561 { 0x7, 16, NULL, NULL, 0 }, 3562 3563 /* The 6-bit UIM field in a X form instruction. */ 3564#define UIM6 UIMM3 + 1 3565 { 0x3f, 16, NULL, NULL, 0 }, 3566 3567 /* The SIX field in a VX form instruction. */ 3568#define SIX UIM6 + 1 3569#define MMMM SIX 3570 { 0xf, 11, NULL, NULL, 0 }, 3571 3572 /* The PS field in a VX form instruction. */ 3573#define PS SIX + 1 3574 { 0x1, 9, NULL, NULL, 0 }, 3575 3576 /* The SH field in a vector shift double by bit immediate instruction. */ 3577#define SH3 PS + 1 3578 { 0x7, 6, NULL, NULL, 0 }, 3579 3580 /* The SHB field in a VA form instruction. */ 3581#define SHB SH3 + 1 3582 { 0xf, 6, NULL, NULL, 0 }, 3583 3584 /* The other UIMM field in a half word EVX form instruction. */ 3585#define EVUIMM_1 SHB + 1 3586 { 0x1f, 11, NULL, NULL, PPC_OPERAND_PARENS }, 3587 3588#define EVUIMM_1_EX0 EVUIMM_1 + 1 3589 { 0x1f, 11, insert_evuimm1_ex0, extract_evuimm1_ex0, PPC_OPERAND_PARENS }, 3590 3591#define EVUIMM_2 EVUIMM_1_EX0 + 1 3592 { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS }, 3593 3594#define EVUIMM_2_EX0 EVUIMM_2 + 1 3595 { 0x3e, 10, insert_evuimm2_ex0, extract_evuimm2_ex0, PPC_OPERAND_PARENS }, 3596 3597 /* The other UIMM field in a word EVX form instruction. */ 3598#define EVUIMM_4 EVUIMM_2_EX0 + 1 3599 { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS }, 3600 3601#define EVUIMM_4_EX0 EVUIMM_4 + 1 3602 { 0x7c, 9, insert_evuimm4_ex0, extract_evuimm4_ex0, PPC_OPERAND_PARENS }, 3603 3604 /* The other UIMM field in a double EVX form instruction. */ 3605#define EVUIMM_8 EVUIMM_4_EX0 + 1 3606 { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS }, 3607 3608#define EVUIMM_8_EX0 EVUIMM_8 + 1 3609 { 0xf8, 8, insert_evuimm8_ex0, extract_evuimm8_ex0, PPC_OPERAND_PARENS }, 3610 3611 /* The WS or DRM field in an X form instruction. */ 3612#define WS EVUIMM_8_EX0 + 1 3613#define DRM WS 3614 /* The NNN field in a VX form instruction for SPE2 */ 3615#define NNN WS 3616 { 0x7, 11, NULL, NULL, 0 }, 3617 3618 /* PowerPC paired singles extensions. */ 3619 /* W bit in the pair singles instructions for x type instructions. */ 3620#define PSWM WS + 1 3621 /* The BO16 field in a BD8 form instruction. */ 3622#define BO16 PSWM 3623 { 0x1, 10, 0, 0, 0 }, 3624 3625 /* IDX bits for quantization in the pair singles instructions. */ 3626#define PSQ PSWM + 1 3627 { 0x7, 12, 0, 0, PPC_OPERAND_GQR }, 3628 3629 /* IDX bits for quantization in the pair singles x-type instructions. */ 3630#define PSQM PSQ + 1 3631 { 0x7, 7, 0, 0, PPC_OPERAND_GQR }, 3632 3633 /* Smaller D field for quantization in the pair singles instructions. */ 3634#define PSD PSQM + 1 3635 { 0xfff, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 3636 3637 /* The L field in an mtmsrd or A form instruction or R or W in an 3638 X form. */ 3639#define A_L PSD + 1 3640#define W A_L 3641#define X_R A_L 3642 { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 3643 3644 /* The RMC or CY field in a Z23 form instruction. */ 3645#define RMC A_L + 1 3646#define CY RMC 3647 { 0x3, 9, NULL, NULL, 0 }, 3648 3649#define R RMC + 1 3650#define MP R 3651 { 0x1, 16, NULL, NULL, 0 }, 3652 3653#define RIC R + 1 3654 { 0x3, 18, NULL, NULL, PPC_OPERAND_OPTIONAL }, 3655 3656#define PRS RIC + 1 3657 { 0x1, 17, NULL, NULL, PPC_OPERAND_OPTIONAL }, 3658 3659#define SP PRS + 1 3660 { 0x3, 19, NULL, NULL, 0 }, 3661 3662#define S SP + 1 3663 { 0x1, 20, NULL, NULL, 0 }, 3664 3665 /* The S field in a XL form instruction. */ 3666#define SXL S + 1 3667 { 0x1, 11, insert_sxl, extract_sxl, PPC_OPERAND_OPTIONAL }, 3668 3669 /* SH field starting at bit position 16. */ 3670#define SH16 SXL + 1 3671 /* The DCM and DGM fields in a Z form instruction. */ 3672#define DCM SH16 3673#define DGM DCM 3674 { 0x3f, 10, NULL, NULL, 0 }, 3675 3676 /* The EH field in larx instruction. */ 3677#define EH SH16 + 1 3678 { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, 3679 3680 /* The L field in an mtfsf or XFL form instruction. */ 3681 /* The A field in a HTM X form instruction. */ 3682#define XFL_L EH + 1 3683#define HTM_A XFL_L 3684 { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL}, 3685 3686 /* Xilinx APU related masks and macros */ 3687#define FCRT XFL_L + 1 3688#define FCRT_MASK (0x1f << 21) 3689 { 0x1f, 21, 0, 0, PPC_OPERAND_FCR }, 3690 3691 /* Xilinx FSL related masks and macros */ 3692#define FSL FCRT + 1 3693#define FSL_MASK (0x1f << 11) 3694 { 0x1f, 11, 0, 0, PPC_OPERAND_FSL }, 3695 3696 /* Xilinx UDI related masks and macros */ 3697#define URT FSL + 1 3698 { 0x1f, 21, 0, 0, PPC_OPERAND_UDI }, 3699 3700#define URA URT + 1 3701 { 0x1f, 16, 0, 0, PPC_OPERAND_UDI }, 3702 3703#define URB URA + 1 3704 { 0x1f, 11, 0, 0, PPC_OPERAND_UDI }, 3705 3706#define URC URB + 1 3707 { 0x1f, 6, 0, 0, PPC_OPERAND_UDI }, 3708 3709 /* The VLESIMM field in a D form instruction. */ 3710#define VLESIMM URC + 1 3711 { 0xffff, PPC_OPSHIFT_INV, insert_vlesi, extract_vlesi, 3712 PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 3713 3714 /* The VLENSIMM field in a D form instruction. */ 3715#define VLENSIMM VLESIMM + 1 3716 { 0xffff, PPC_OPSHIFT_INV, insert_vlensi, extract_vlensi, 3717 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 3718 3719 /* The VLEUIMM field in a D form instruction. */ 3720#define VLEUIMM VLENSIMM + 1 3721 { 0xffff, PPC_OPSHIFT_INV, insert_vleui, extract_vleui, 0 }, 3722 3723 /* The VLEUIMML field in a D form instruction. */ 3724#define VLEUIMML VLEUIMM + 1 3725 { 0xffff, PPC_OPSHIFT_INV, insert_vleil, extract_vleil, 0 }, 3726 3727 /* The XT and XS fields in an XX1 or XX3 form instruction. This is 3728 split. */ 3729#define XS6 VLEUIMML + 1 3730#define XT6 XS6 3731 { 0x3f, PPC_OPSHIFT_INV, insert_xt6, extract_xt6, PPC_OPERAND_VSR }, 3732 3733 /* The XT and XS fields in an DQ form VSX instruction. This is split. */ 3734#define XSQ6 XT6 + 1 3735#define XTQ6 XSQ6 3736 { 0x3f, PPC_OPSHIFT_INV, insert_xtq6, extract_xtq6, PPC_OPERAND_VSR }, 3737 3738 /* The split XTp field in a vector paired instruction. */ 3739#define XTP XSQ6 + 1 3740 { 0x3e, PPC_OPSHIFT_INV, insert_xtp, extract_xtp, PPC_OPERAND_VSR }, 3741 3742#define XTS XTP + 1 3743 { 0x3f, PPC_OPSHIFT_INV, insert_xts, extract_xts, PPC_OPERAND_VSR }, 3744 3745 /* The XT field in a plxv instruction. Runs into the OP field. */ 3746#define XTOP XTS + 1 3747 { 0x3f, 21, NULL, NULL, PPC_OPERAND_VSR }, 3748 3749 /* The XA field in an XX3 form instruction. This is split. */ 3750#define XA6 XTOP + 1 3751 { 0x3f, PPC_OPSHIFT_INV, insert_xa6, extract_xa6, PPC_OPERAND_VSR }, 3752 3753 /* The XA field in an MMA XX3 form instruction. This is split and 3754 must not overlap with the ACC operand. */ 3755#define XA6a XA6 + 1 3756 { 0x3f, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR }, 3757 3758 /* The XAp field in an MMA XX3 form instruction. This is split. 3759 This is like XA6a, but must be even. */ 3760#define XA6ap XA6a + 1 3761 { 0x3e, PPC_OPSHIFT_INV, insert_xa6a, extract_xa6a, PPC_OPERAND_VSR }, 3762 3763 /* The XB field in an XX2 or XX3 form instruction. This is split. */ 3764#define XB6 XA6ap + 1 3765 { 0x3f, PPC_OPSHIFT_INV, insert_xb6, extract_xb6, PPC_OPERAND_VSR }, 3766 3767 /* The XB field in an XX3 form instruction. This is split and 3768 must not overlap with the ACC operand. */ 3769#define XB6a XB6 + 1 3770 { 0x3f, PPC_OPSHIFT_INV, insert_xb6a, extract_xb6a, PPC_OPERAND_VSR }, 3771 3772 /* The XA and XB fields in an XX3 form instruction when they must be the same. 3773 This is used in extended mnemonics like xvmovdp. This is split. */ 3774#define XAB6 XB6a + 1 3775 { 0x3f, PPC_OPSHIFT_INV, insert_xab6, extract_xab6, PPC_OPERAND_VSR }, 3776 3777 /* The XC field in an XX4 form instruction. This is split. */ 3778#define XC6 XAB6 + 1 3779 { 0x3f, PPC_OPSHIFT_INV, insert_xc6, extract_xc6, PPC_OPERAND_VSR }, 3780 3781 /* The DM or SHW field in an XX3 form instruction. */ 3782#define DM XC6 + 1 3783#define SHW DM 3784 { 0x3, 8, NULL, NULL, 0 }, 3785 3786 /* The DM field in an extended mnemonic XX3 form instruction. */ 3787#define DMEX DM + 1 3788 { 0x3, 8, insert_dm, extract_dm, 0 }, 3789 3790 /* The UIM field in an XX2 form instruction. */ 3791#define UIM DMEX + 1 3792 /* The 2-bit UIMM field in a VX form instruction. */ 3793#define UIMM2 UIM 3794 /* The 2-bit L field in a darn instruction. */ 3795#define LRAND UIM 3796 { 0x3, 16, NULL, NULL, 0 }, 3797 3798#define ERAT_T UIM + 1 3799 { 0x7, 21, NULL, NULL, 0 }, 3800 3801#define IH ERAT_T + 1 3802 { 0x7, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 3803 3804 /* The 2-bit SC or PL field in an X form instruction. */ 3805#define SC2 IH + 1 3806#define PL SC2 3807 { 0x3, 16, insert_pl, extract_pl, PPC_OPERAND_OPTIONAL }, 3808 3809 /* The 8-bit IMM8 field in a XX1 form instruction. */ 3810#define IMM8 SC2 + 1 3811 { 0xff, 11, NULL, NULL, PPC_OPERAND_SIGNOPT }, 3812 3813#define VX_OFF IMM8 + 1 3814 { 0x3, 0, insert_off_lsp, extract_off_lsp, 0 }, 3815 3816#define VX_OFF_SPE2 VX_OFF + 1 3817 { 0x7, 0, insert_off_spe2, extract_off_spe2, 0 }, 3818 3819#define BBB VX_OFF_SPE2 + 1 3820 { 0x7, 13, NULL, NULL, 0 }, 3821 3822#define DDD BBB + 1 3823#define VX_MASK_DDD (VX_MASK & ~0x1) 3824 { 0x7, PPC_OPSHIFT_INV, insert_Ddd, extract_Ddd, 0 }, 3825 3826#define HH DDD + 1 3827 { 0x3, 13, NULL, NULL, 0 }, 3828}; 3829 3830const unsigned int num_powerpc_operands = (sizeof (powerpc_operands) 3831 / sizeof (powerpc_operands[0])); 3832 3833/* Macros used to form opcodes. */ 3834 3835/* The main opcode. */ 3836#define OP(x) ((((uint64_t)(x)) & 0x3f) << 26) 3837#define OP_MASK OP (0x3f) 3838 3839/* The prefix opcode. */ 3840#define PREFIX_OP (1ULL << 58) 3841 3842/* The 2-bit prefix form. */ 3843#define PREFIX_FORM(x) ((x & 3ULL) << 56) 3844 3845#define SUFFIX_MASK ((1ULL << 32) - 1) 3846#define PREFIX_MASK (SUFFIX_MASK << 32) 3847 3848/* Prefix insn, eight byte load/store form 8LS. */ 3849#define P8LS (PREFIX_OP | PREFIX_FORM (0)) 3850 3851/* Prefix insn, eight byte register to register form 8RR. */ 3852#define P8RR (PREFIX_OP | PREFIX_FORM (1)) 3853 3854/* Prefix insn, modified load/store form MLS. */ 3855#define PMLS (PREFIX_OP | PREFIX_FORM (2)) 3856 3857/* Prefix insn, modified register to register form MRR. */ 3858#define PMRR (PREFIX_OP | PREFIX_FORM (3)) 3859 3860/* Prefix insn, modified masked immediate register to register form MMIRR. */ 3861#define PMMIRR (PREFIX_OP | PREFIX_FORM (3) | (9ULL << 52)) 3862 3863/* An 8-byte D form prefix instruction. */ 3864#define P_D_MASK (((-1ULL << 50) & ~PCREL_MASK) | OP_MASK) 3865 3866/* The same as P_D_MASK, but with the RA and PCREL fields specified. */ 3867#define P_DRAPCREL_MASK (P_D_MASK | PCREL_MASK | RA_MASK) 3868 3869/* Mask for prefix X form instructions. */ 3870#define P_X_MASK (PREFIX_MASK | X_MASK) 3871#define P_XX1_MASK (PREFIX_MASK | XX1_MASK) 3872 3873/* Mask for prefix vector permute insns. */ 3874#define P_XX4_MASK (PREFIX_MASK | XX4_MASK) 3875#define P_UXX4_MASK (P_XX4_MASK & ~(7ULL << 32)) 3876#define P_U8XX4_MASK (P_XX4_MASK & ~(0xffULL << 32)) 3877 3878/* MMIRR:XX3-form 8-byte outer product instructions. */ 3879#define P_GER_MASK ((-1ULL << 40) | XX3ACC_MASK) 3880#define P_GER2_MASK (P_GER_MASK & ~(3ULL << 46)) 3881#define P_GER4_MASK (P_GER_MASK & ~(15ULL << 44)) 3882#define P_GER8_MASK (P_GER_MASK & ~(255ULL << 40)) 3883#define P_GER64_MASK (P_GER_MASK | (3ULL << 32)) 3884 3885/* Vector splat immediate op. */ 3886#define VSOP(op, xop) (OP (op) | (xop << 17)) 3887#define P_VS_MASK ((-1ULL << 48) | VSOP (0x3f, 0xf)) 3888#define P_VSI_MASK ((-1ULL << 48) | VSOP (0x3f, 0xe)) 3889 3890/* The main opcode combined with a trap code in the TO field of a D 3891 form instruction. Used for extended mnemonics for the trap 3892 instructions. */ 3893#define OPTO(x,to) (OP (x) | ((((uint64_t)(to)) & 0x1f) << 21)) 3894#define OPTO_MASK (OP_MASK | TO_MASK) 3895 3896/* The main opcode combined with a comparison size bit in the L field 3897 of a D form or X form instruction. Used for extended mnemonics for 3898 the comparison instructions. */ 3899#define OPL(x,l) (OP (x) | ((((uint64_t)(l)) & 1) << 21)) 3900#define OPL_MASK OPL (0x3f,1) 3901 3902/* The main opcode combined with an update code in D form instruction. 3903 Used for extended mnemonics for VLE memory instructions. */ 3904#define OPVUP(x,vup) (OP (x) | ((((uint64_t)(vup)) & 0xff) << 8)) 3905#define OPVUP_MASK OPVUP (0x3f, 0xff) 3906 3907/* The main opcode combined with an update code and the RT fields 3908 specified in D form instruction. Used for VLE volatile context 3909 save/restore instructions. */ 3910#define OPVUPRT(x,vup,rt) \ 3911 (OPVUP (x, vup) \ 3912 | ((((uint64_t)(rt)) & 0x1f) << 21)) 3913#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f) 3914 3915/* An A form instruction. */ 3916#define A(op, xop, rc) \ 3917 (OP (op) \ 3918 | ((((uint64_t)(xop)) & 0x1f) << 1) \ 3919 | (((uint64_t)(rc)) & 1)) 3920#define A_MASK A (0x3f, 0x1f, 1) 3921 3922/* An A_MASK with the FRB field fixed. */ 3923#define AFRB_MASK (A_MASK | FRB_MASK) 3924 3925/* An A_MASK with the FRC field fixed. */ 3926#define AFRC_MASK (A_MASK | FRC_MASK) 3927 3928/* An A_MASK with the FRA and FRC fields fixed. */ 3929#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 3930 3931/* An AFRAFRC_MASK, but with L bit clear. */ 3932#define AFRALFRC_MASK (AFRAFRC_MASK & ~((uint64_t) 1 << 16)) 3933 3934/* A B form instruction. */ 3935#define B(op, aa, lk) \ 3936 (OP (op) \ 3937 | ((((uint64_t)(aa)) & 1) << 1) \ 3938 | ((lk) & 1)) 3939#define B_MASK B (0x3f, 1, 1) 3940 3941/* A BD8 form instruction. This is a 16-bit instruction. */ 3942#define BD8(op, aa, lk) \ 3943 (((((uint64_t)(op)) & 0x3f) << 10) \ 3944 | (((aa) & 1) << 9) \ 3945 | (((lk) & 1) << 8)) 3946#define BD8_MASK BD8 (0x3f, 1, 1) 3947 3948/* Another BD8 form instruction. This is a 16-bit instruction. */ 3949#define BD8IO(op) ((((uint64_t)(op)) & 0x1f) << 11) 3950#define BD8IO_MASK BD8IO (0x1f) 3951 3952/* A BD8 form instruction for simplified mnemonics. */ 3953#define EBD8IO(op, bo, bi) (BD8IO ((op)) | ((bo) << 10) | ((bi) << 8)) 3954/* A mask that excludes BO32 and BI32. */ 3955#define EBD8IO1_MASK 0xf800 3956/* A mask that includes BO32 and excludes BI32. */ 3957#define EBD8IO2_MASK 0xfc00 3958/* A mask that include BO32 AND BI32. */ 3959#define EBD8IO3_MASK 0xff00 3960 3961/* A BD15 form instruction. */ 3962#define BD15(op, aa, lk) \ 3963 (OP (op) \ 3964 | ((((uint64_t)(aa)) & 0xf) << 22) \ 3965 | ((lk) & 1)) 3966#define BD15_MASK BD15 (0x3f, 0xf, 1) 3967 3968/* A BD15 form instruction for extended conditional branch mnemonics. */ 3969#define EBD15(op, aa, bo, lk) \ 3970 (((op) & 0x3fu) << 26) \ 3971 | (((aa) & 0xf) << 22) \ 3972 | (((bo) & 0x3) << 20) \ 3973 | ((lk) & 1) 3974#define EBD15_MASK 0xfff00001 3975 3976/* A BD15 form instruction for extended conditional branch mnemonics 3977 with BI. */ 3978#define EBD15BI(op, aa, bo, bi, lk) \ 3979 ((((op) & 0x3fu) << 26) \ 3980 | (((aa) & 0xf) << 22) \ 3981 | (((bo) & 0x3) << 20) \ 3982 | (((bi) & 0x3) << 16) \ 3983 | ((lk) & 1)) 3984 3985#define EBD15BI_MASK 0xfff30001 3986 3987/* A BD24 form instruction. */ 3988#define BD24(op, aa, lk) \ 3989 (OP (op) \ 3990 | ((((uint64_t)(aa)) & 1) << 25) \ 3991 | ((lk) & 1)) 3992#define BD24_MASK BD24 (0x3f, 1, 1) 3993 3994/* A B form instruction setting the BO field. */ 3995#define BBO(op, bo, aa, lk) \ 3996 (B ((op), (aa), (lk)) \ 3997 | ((((uint64_t)(bo)) & 0x1f) << 21)) 3998#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 3999 4000/* A BBO_MASK with the y bit of the BO field removed. This permits 4001 matching a conditional branch regardless of the setting of the y 4002 bit. Similarly for the 'at' bits used for power4 branch hints. */ 4003#define Y_MASK (((uint64_t) 1) << 21) 4004#define AT1_MASK (((uint64_t) 3) << 21) 4005#define AT2_MASK (((uint64_t) 9) << 21) 4006#define BBOY_MASK (BBO_MASK &~ Y_MASK) 4007#define BBOAT_MASK (BBO_MASK &~ AT1_MASK) 4008 4009/* A B form instruction setting the BO field and the condition bits of 4010 the BI field. */ 4011#define BBOCB(op, bo, cb, aa, lk) \ 4012 (BBO ((op), (bo), (aa), (lk)) | ((((uint64_t)(cb)) & 0x3) << 16)) 4013#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) 4014 4015/* A BBOCB_MASK with the y bit of the BO field removed. */ 4016#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) 4017#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) 4018#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) 4019 4020/* A BBOYCB_MASK in which the BI field is fixed. */ 4021#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 4022#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 4023 4024/* A VLE C form instruction. */ 4025#define C_LK(x, lk) (((((uint64_t)(x)) & 0x7fff) << 1) | ((lk) & 1)) 4026#define C_LK_MASK C_LK(0x7fff, 1) 4027#define C(x) ((((uint64_t)(x)) & 0xffff)) 4028#define C_MASK C(0xffff) 4029 4030/* An Context form instruction. */ 4031#define CTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7)) 4032#define CTX_MASK CTX(0x3f, 0x7) 4033 4034/* An User Context form instruction. */ 4035#define UCTX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) 4036#define UCTX_MASK UCTX(0x3f, 0x1f) 4037 4038/* The main opcode mask with the RA field clear. */ 4039#define DRA_MASK (OP_MASK | RA_MASK) 4040 4041/* A DQ form VSX instruction. */ 4042#define DQX(op, xop) (OP (op) | ((xop) & 0x7)) 4043#define DQX_MASK DQX (0x3f, 7) 4044 4045/* A DQ form VSX vector paired instruction. */ 4046#define DQXP(op, xop) (OP (op) | ((xop) & 0xf)) 4047#define DQXP_MASK DQXP (0x3f, 0xf) 4048 4049/* A DS form instruction. */ 4050#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 4051#define DS_MASK DSO (0x3f, 3) 4052 4053/* An DX form instruction. */ 4054#define DX(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) 4055#define DX_MASK DX (0x3f, 0x1f) 4056/* An DX form instruction with the D bits specified. */ 4057#define NODX_MASK (DX_MASK | 0x1fffc1) 4058 4059/* An EVSEL form instruction. */ 4060#define EVSEL(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xff) << 3) 4061#define EVSEL_MASK EVSEL(0x3f, 0xff) 4062 4063/* An IA16 form instruction. */ 4064#define IA16(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) 4065#define IA16_MASK IA16(0x3f, 0x1f) 4066 4067/* An I16A form instruction. */ 4068#define I16A(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) 4069#define I16A_MASK I16A(0x3f, 0x1f) 4070 4071/* An I16L form instruction. */ 4072#define I16L(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f) << 11) 4073#define I16L_MASK I16L(0x3f, 0x1f) 4074 4075/* An IM7 form instruction. */ 4076#define IM7(op) ((((uint64_t)(op)) & 0x1f) << 11) 4077#define IM7_MASK IM7(0x1f) 4078 4079/* An M form instruction. */ 4080#define M(op, rc) (OP (op) | ((rc) & 1)) 4081#define M_MASK M (0x3f, 1) 4082 4083/* An LI20 form instruction. */ 4084#define LI20(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1) << 15) 4085#define LI20_MASK LI20(0x3f, 0x1) 4086 4087/* An M form instruction with the ME field specified. */ 4088#define MME(op, me, rc) \ 4089 (M ((op), (rc)) \ 4090 | ((((uint64_t)(me)) & 0x1f) << 1)) 4091 4092/* An M_MASK with the MB field fixed. */ 4093#define MMB_MASK (M_MASK | MB_MASK) 4094 4095/* An M_MASK with the ME field fixed. */ 4096#define MME_MASK (M_MASK | ME_MASK) 4097 4098/* An M_MASK with the MB and ME fields fixed. */ 4099#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) 4100 4101/* An M_MASK with the SH and ME fields fixed. */ 4102#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) 4103 4104/* An M_MASK with the SH and MB fields fixed. */ 4105#define MSHMB_MASK (M_MASK | SH_MASK | MB_MASK) 4106 4107/* An MD form instruction. */ 4108#define MD(op, xop, rc) \ 4109 (OP (op) \ 4110 | ((((uint64_t)(xop)) & 0x7) << 2) \ 4111 | ((rc) & 1)) 4112#define MD_MASK MD (0x3f, 0x7, 1) 4113 4114/* An MD_MASK with the MB field fixed. */ 4115#define MDMB_MASK (MD_MASK | MB6_MASK) 4116 4117/* An MD_MASK with the SH field fixed. */ 4118#define MDSH_MASK (MD_MASK | SH6_MASK) 4119 4120/* An MDS form instruction. */ 4121#define MDS(op, xop, rc) \ 4122 (OP (op) \ 4123 | ((((uint64_t)(xop)) & 0xf) << 1) \ 4124 | ((rc) & 1)) 4125#define MDS_MASK MDS (0x3f, 0xf, 1) 4126 4127/* An MDS_MASK with the MB field fixed. */ 4128#define MDSMB_MASK (MDS_MASK | MB6_MASK) 4129 4130/* An SC form instruction. */ 4131#define SC(op, sa, lk) \ 4132 (OP (op) \ 4133 | ((((uint64_t)(sa)) & 1) << 1) \ 4134 | ((lk) & 1)) 4135#define SC_MASK \ 4136 (OP_MASK \ 4137 | (((uint64_t) 0x3ff) << 16) \ 4138 | (((uint64_t) 1) << 1) \ 4139 | 1) 4140 4141/* An SCI8 form instruction. */ 4142#define SCI8(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 11)) 4143#define SCI8_MASK SCI8(0x3f, 0x1f) 4144 4145/* An SCI8 form instruction. */ 4146#define SCI8BF(op, fop, xop) \ 4147 (OP (op) \ 4148 | ((((uint64_t)(xop)) & 0x1f) << 11) \ 4149 | (((fop) & 7) << 23)) 4150#define SCI8BF_MASK SCI8BF(0x3f, 7, 0x1f) 4151 4152/* An SD4 form instruction. This is a 16-bit instruction. */ 4153#define SD4(op) ((((uint64_t)(op)) & 0xf) << 12) 4154#define SD4_MASK SD4(0xf) 4155 4156/* An SE_IM5 form instruction. This is a 16-bit instruction. */ 4157#define SE_IM5(op, xop) \ 4158 (((((uint64_t)(op)) & 0x3f) << 10) \ 4159 | (((xop) & 0x1) << 9)) 4160#define SE_IM5_MASK SE_IM5(0x3f, 1) 4161 4162/* An SE_R form instruction. This is a 16-bit instruction. */ 4163#define SE_R(op, xop) \ 4164 (((((uint64_t)(op)) & 0x3f) << 10) \ 4165 | (((xop) & 0x3f) << 4)) 4166#define SE_R_MASK SE_R(0x3f, 0x3f) 4167 4168/* An SE_RR form instruction. This is a 16-bit instruction. */ 4169#define SE_RR(op, xop) \ 4170 (((((uint64_t)(op)) & 0x3f) << 10) \ 4171 | (((xop) & 0x3) << 8)) 4172#define SE_RR_MASK SE_RR(0x3f, 3) 4173 4174/* A VX form instruction. */ 4175#define VX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) 4176 4177/* The mask for an VX form instruction. */ 4178#define VX_MASK VX(0x3f, 0x7ff) 4179 4180/* A VX LSP form instruction. */ 4181#define VX_LSP(op, xop) (OP (op) | (((uint64_t)(xop)) & 0xffff)) 4182 4183/* The mask for an VX LSP form instruction. */ 4184#define VX_LSP_MASK VX_LSP(0x3f, 0xffff) 4185#define VX_LSP_OFF_MASK VX_LSP(0x3f, 0x7fc) 4186 4187/* Additional format of VX SPE2 form instruction. */ 4188#define VX_RA_CONST(op, xop, bits11_15) \ 4189 (OP (op) \ 4190 | (((uint64_t)(bits11_15) & 0x1f) << 16) \ 4191 | (((uint64_t)(xop)) & 0x7ff)) 4192#define VX_RA_CONST_MASK VX_RA_CONST(0x3f, 0x7ff, 0x1f) 4193 4194#define VX_RB_CONST(op, xop, bits16_20) \ 4195 (OP (op) \ 4196 | (((uint64_t)(bits16_20) & 0x1f) << 11) \ 4197 | (((uint64_t)(xop)) & 0x7ff)) 4198#define VX_RB_CONST_MASK VX_RB_CONST(0x3f, 0x7ff, 0x1f) 4199 4200#define VX_OFF_SPE2_MASK VX(0x3f, 0x7f8) 4201 4202#define VX_SPE_CRFD(op, xop, bits9_10) \ 4203 (OP (op) \ 4204 | (((uint64_t)(bits9_10) & 0x3) << 21) \ 4205 | (((uint64_t)(xop)) & 0x7ff)) 4206#define VX_SPE_CRFD_MASK VX_SPE_CRFD(0x3f, 0x7ff, 0x3) 4207 4208#define VX_SPE2_CLR(op, xop, bit16) \ 4209 (OP (op) \ 4210 | (((uint64_t)(bit16) & 0x1) << 15) \ 4211 | (((uint64_t)(xop)) & 0x7ff)) 4212#define VX_SPE2_CLR_MASK VX_SPE2_CLR(0x3f, 0x7ff, 0x1) 4213 4214#define VX_SPE2_SPLATB(op, xop, bits19_20) \ 4215 (OP (op) \ 4216 | (((uint64_t)(bits19_20) & 0x3) << 11) \ 4217 | (((uint64_t)(xop)) & 0x7ff)) 4218#define VX_SPE2_SPLATB_MASK VX_SPE2_SPLATB(0x3f, 0x7ff, 0x3) 4219 4220#define VX_SPE2_OCTET(op, xop, bits16_17) \ 4221 (OP (op) \ 4222 | (((uint64_t)(bits16_17) & 0x3) << 14) \ 4223 | (((uint64_t)(xop)) & 0x7ff)) 4224#define VX_SPE2_OCTET_MASK VX_SPE2_OCTET(0x3f, 0x7ff, 0x7) 4225 4226#define VX_SPE2_DDHH(op, xop, bit16) \ 4227 (OP (op) \ 4228 | (((uint64_t)(bit16) & 0x1) << 15) \ 4229 | (((uint64_t)(xop)) & 0x7ff)) 4230#define VX_SPE2_DDHH_MASK VX_SPE2_DDHH(0x3f, 0x7ff, 0x1) 4231 4232#define VX_SPE2_HH(op, xop, bit16, bits19_20) \ 4233 (OP (op) \ 4234 | (((uint64_t)(bit16) & 0x1) << 15) \ 4235 | (((uint64_t)(bits19_20) & 0x3) << 11) \ 4236 | (((uint64_t)(xop)) & 0x7ff)) 4237#define VX_SPE2_HH_MASK VX_SPE2_HH(0x3f, 0x7ff, 0x1, 0x3) 4238 4239#define VX_SPE2_EVMAR(op, xop) \ 4240 (OP (op) \ 4241 | ((uint64_t)(0x1) << 11) \ 4242 | (((uint64_t)(xop)) & 0x7ff)) 4243#define VX_SPE2_EVMAR_MASK \ 4244 (VX_SPE2_EVMAR(0x3f, 0x7ff) \ 4245 | ((uint64_t)(0x1) << 11)) 4246 4247/* A VX_MASK with the VA field fixed. */ 4248#define VXVA_MASK (VX_MASK | (0x1f << 16)) 4249 4250/* A VX_MASK with the VB field fixed. */ 4251#define VXVB_MASK (VX_MASK | (0x1f << 11)) 4252 4253/* A VX_MASK with the VA and VB fields fixed. */ 4254#define VXVAVB_MASK (VX_MASK | (0x1f << 16) | (0x1f << 11)) 4255 4256/* A VX_MASK with the VD and VA fields fixed. */ 4257#define VXVDVA_MASK (VX_MASK | (0x1f << 21) | (0x1f << 16)) 4258 4259/* A VX_MASK with a UIMM4 field. */ 4260#define VXUIMM4_MASK (VX_MASK | (0x1 << 20)) 4261 4262/* A VX_MASK with a UIMM3 field. */ 4263#define VXUIMM3_MASK (VX_MASK | (0x3 << 19)) 4264 4265/* A VX_MASK with a UIMM2 field. */ 4266#define VXUIMM2_MASK (VX_MASK | (0x7 << 18)) 4267 4268/* A VX_MASK with a PS field. */ 4269#define VXPS_MASK (VX_MASK & ~(0x1 << 9)) 4270 4271/* A VX_MASK with the VA field fixed with a PS field. */ 4272#define VXVAPS_MASK (VXVA_MASK & ~(0x1 << 9)) 4273 4274/* A VX_MASK with the VA field fixed with a MP field. */ 4275#define VXVAM_MASK (VXVA_MASK & ~(0x1 << 16)) 4276 4277/* A VX_MASK for instructions using a BF field. */ 4278#define VXBF_MASK (VX_MASK | (3 << 21)) 4279 4280/* A VX_MASK for instructions with an RC field. */ 4281#define VXRC_MASK (VX_MASK & ~(0x1f << 6)) 4282 4283/* A VX_MASK for instructions with a SH field. */ 4284#define VXSH_MASK (VX_MASK & ~(0x7 << 6)) 4285 4286/* A VA form instruction. */ 4287#define VXA(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x03f)) 4288 4289/* The mask for an VA form instruction. */ 4290#define VXA_MASK VXA(0x3f, 0x3f) 4291 4292/* A VXA_MASK with a SHB field. */ 4293#define VXASHB_MASK (VXA_MASK | (1 << 10)) 4294 4295/* A VXR form instruction. */ 4296#define VXR(op, xop, rc) \ 4297 (OP (op) \ 4298 | (((uint64_t)(rc) & 1) << 10) \ 4299 | (((uint64_t)(xop)) & 0x3ff)) 4300 4301/* The mask for a VXR form instruction. */ 4302#define VXR_MASK VXR(0x3f, 0x3ff, 1) 4303 4304/* A VX form instruction with a VA tertiary opcode. */ 4305#define VXVA(op, xop, vaop) (VX(op,xop) | (((vaop) & 0x1f) << 16)) 4306 4307#define VXASH(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1f) << 1)) 4308#define VXASH_MASK VXASH (0x3f, 0x1f) 4309 4310/* An X form instruction. */ 4311#define X(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) 4312 4313/* A X form instruction for Quad-Precision FP Instructions. */ 4314#define XVA(op, xop, vaop) (X(op,xop) | (((vaop) & 0x1f) << 16)) 4315 4316/* An EX form instruction. */ 4317#define EX(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x7ff)) 4318 4319/* The mask for an EX form instruction. */ 4320#define EX_MASK EX (0x3f, 0x7ff) 4321 4322/* An XX2 form instruction. */ 4323#define XX2(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 2)) 4324 4325/* A XX2 form instruction with the VA bits specified. */ 4326#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16)) 4327 4328/* An XX3 form instruction. */ 4329#define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3)) 4330 4331/* An XX3 form instruction with the RC bit specified. */ 4332#define XX3RC(op, xop, rc) \ 4333 (OP (op) \ 4334 | (((uint64_t)(rc) & 1) << 10) \ 4335 | ((((uint64_t)(xop)) & 0x7f) << 3)) 4336 4337/* An XX4 form instruction. */ 4338#define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4)) 4339 4340/* A Z form instruction. */ 4341#define Z(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x1ff) << 1)) 4342 4343/* An X form instruction with the RC bit specified. */ 4344#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 4345 4346/* A X form instruction for Quad-Precision FP Instructions with RC bit. */ 4347#define XVARC(op, xop, vaop, rc) (XVA ((op), (xop), (vaop)) | ((rc) & 1)) 4348 4349/* An X form instruction with the RA bits specified as two ops. */ 4350#define XMMF(op, xop, mop0, mop1) \ 4351 (X ((op), (xop)) \ 4352 | ((mop0) & 3) << 19 \ 4353 | ((mop1) & 7) << 16) 4354 4355/* A Z form instruction with the RC bit specified. */ 4356#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) 4357 4358/* The mask for an X form instruction. */ 4359#define X_MASK XRC (0x3f, 0x3ff, 1) 4360 4361/* The mask for an X form instruction with the BF bits specified. */ 4362#define XBF_MASK (X_MASK | (3 << 21)) 4363 4364/* An X form instruction without the RC field specified. */ 4365#define XRC_MASK XRC (0x3f, 0x3ff, 0) 4366 4367/* An X form wait instruction with everything filled in except the WC 4368 field. */ 4369#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) 4370 4371/* An X form wait instruction with everything filled in except the WC 4372 and PL fields. */ 4373#define XWCPL_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | (3 << 18) | RB_MASK) 4374 4375/* The mask for an XX1 form instruction. */ 4376#define XX1_MASK X (0x3f, 0x3ff) 4377 4378/* An XX1_MASK with the RB field fixed. */ 4379#define XX1RB_MASK (XX1_MASK | RB_MASK) 4380 4381/* The mask for an XX2 form instruction. */ 4382#define XX2_MASK (XX2 (0x3f, 0x1ff) | (0x1f << 16)) 4383 4384/* The mask for an XX2 form instruction with the UIM bits specified. */ 4385#define XX2UIM_MASK (XX2 (0x3f, 0x1ff) | (7 << 18)) 4386 4387/* The mask for an XX2 form instruction with the 4 UIM bits specified. */ 4388#define XX2UIM4_MASK (XX2 (0x3f, 0x1ff) | (1 << 20)) 4389 4390/* The mask for an XX2 form instruction with the BF bits specified. */ 4391#define XX2BF_MASK (XX2_MASK | (3 << 21) | (1)) 4392 4393/* The mask for an XX2 form instruction with the BF and DCMX bits 4394 specified. */ 4395#define XX2BFD_MASK (XX2 (0x3f, 0x1ff) | 1) 4396 4397/* The mask for an XX2 form instruction with a split DCMX bits 4398 specified. */ 4399#define XX2DCMXS_MASK XX2 (0x3f, 0x1ee) 4400 4401/* The mask for an XX3 form instruction. */ 4402#define XX3_MASK XX3 (0x3f, 0xff) 4403 4404/* The mask for an XX3 form instruction with the BF bits specified. */ 4405#define XX3BF_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) 4406 4407/* An X_MASK with an accumulator register and the RA and RB fields fixed. */ 4408#define XACC_MASK (X_MASK | RA_MASK | RB_MASK | (3 << 21)) 4409 4410/* The mask for an XX3 form instruction with an accumulator register. */ 4411#define XX3ACC_MASK (XX3 (0x3f, 0xff) | (3 << 21) | (1)) 4412 4413/* The mask for an XX3 form instruction with the DM or SHW bits 4414 specified. */ 4415#define XX3DM_MASK (XX3 (0x3f, 0x1f) | (1 << 10)) 4416#define XX3SHW_MASK XX3DM_MASK 4417 4418/* The mask for an XX4 form instruction. */ 4419#define XX4_MASK XX4 (0x3f, 0x3) 4420 4421/* An X form wait instruction with everything filled in except the WC 4422 field. */ 4423#define XWC_MASK (XRC (0x3f, 0x3ff, 1) | (7 << 23) | RA_MASK | RB_MASK) 4424 4425/* The mask for an XMMF form instruction. */ 4426#define XMMF_MASK (XMMF (0x3f, 0x3ff, 3, 7) | (1)) 4427 4428/* The mask for a Z form instruction. */ 4429#define Z_MASK ZRC (0x3f, 0x1ff, 1) 4430#define Z2_MASK ZRC (0x3f, 0xff, 1) 4431 4432/* An X_MASK with the RA/VA field fixed. */ 4433#define XRA_MASK (X_MASK | RA_MASK) 4434#define XVA_MASK XRA_MASK 4435 4436/* An XRA_MASK with the A_L/W field clear. */ 4437#define XWRA_MASK (XRA_MASK & ~((uint64_t) 1 << 16)) 4438#define XRLA_MASK XWRA_MASK 4439 4440/* An X_MASK with the RB field fixed. */ 4441#define XRB_MASK (X_MASK | RB_MASK) 4442 4443/* An X_MASK with the RT field fixed. */ 4444#define XRT_MASK (X_MASK | RT_MASK) 4445 4446/* An XRT_MASK mask with the 2 L bits clear. */ 4447#define XLRT_MASK (XRT_MASK & ~((uint64_t) 0x3 << 21)) 4448 4449/* An XRT_MASK mask with the 3 L bits clear. */ 4450#define XL3RT_MASK (XRT_MASK & ~((uint64_t) 0x7 << 21)) 4451 4452/* An X_MASK with the RA and RB fields fixed. */ 4453#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 4454 4455/* An XBF_MASK with the RA and RB fields fixed. */ 4456#define XBFRARB_MASK (XBF_MASK | RA_MASK | RB_MASK) 4457 4458/* An XRARB_MASK, but with the L bit clear. */ 4459#define XRLARB_MASK (XRARB_MASK & ~((uint64_t) 1 << 16)) 4460 4461/* An XRARB_MASK, but with the L bits in a darn instruction clear. */ 4462#define XLRAND_MASK (XRARB_MASK & ~((uint64_t) 3 << 16)) 4463 4464/* An X_MASK with the RT and RA fields fixed. */ 4465#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 4466 4467/* An X_MASK with the RT and RB fields fixed. */ 4468#define XRTRB_MASK (X_MASK | RT_MASK | RB_MASK) 4469 4470/* An XRTRA_MASK, but with L bit clear. */ 4471#define XRTLRA_MASK (XRTRA_MASK & ~((uint64_t) 1 << 21)) 4472 4473/* An X_MASK with the RT, RA and RB fields fixed. */ 4474#define XRTRARB_MASK (X_MASK | RT_MASK | RA_MASK | RB_MASK) 4475 4476/* An XRTRARB_MASK, but with L bit clear. */ 4477#define XRTLRARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 21)) 4478 4479/* An XRTRARB_MASK, but with A bit clear. */ 4480#define XRTARARB_MASK (XRTRARB_MASK & ~((uint64_t) 1 << 25)) 4481 4482/* An XRTRARB_MASK, but with BF bits clear. */ 4483#define XRTBFRARB_MASK (XRTRARB_MASK & ~((uint64_t) 7 << 23)) 4484 4485/* An X form instruction with the L bit specified. */ 4486#define XOPL(op, xop, l) \ 4487 (X ((op), (xop)) \ 4488 | ((((uint64_t)(l)) & 1) << 21)) 4489 4490/* An X form instruction with the 2 L bits specified. */ 4491#define XOPL2(op, xop, l) \ 4492 (X ((op), (xop)) \ 4493 | ((((uint64_t)(l)) & 3) << 21)) 4494 4495/* An X form instruction with the 3 L bits specified. */ 4496#define XOPL3(op, xop, l) \ 4497 (X ((op), (xop)) \ 4498 | ((((uint64_t)(l)) & 7) << 21)) 4499 4500/* An X form instruction with the WC and PL bits specified. */ 4501#define XWCPL(op, xop, wc, pl) \ 4502 (XOPL3 ((op), (xop), (wc)) \ 4503 | ((((uint64_t)(pl)) & 3) << 16)) 4504 4505/* An X form instruction with the L bit and RC bit specified. */ 4506#define XRCL(op, xop, l, rc) \ 4507 (XRC ((op), (xop), (rc)) \ 4508 | ((((uint64_t)(l)) & 1) << 21)) 4509 4510/* An X form instruction with RT fields specified */ 4511#define XRT(op, xop, rt) \ 4512 (X ((op), (xop)) \ 4513 | ((((uint64_t)(rt)) & 0x1f) << 21)) 4514 4515/* An X form instruction with RT and RA fields specified */ 4516#define XRTRA(op, xop, rt, ra) \ 4517 (X ((op), (xop)) \ 4518 | ((((uint64_t)(rt)) & 0x1f) << 21) \ 4519 | ((((uint64_t)(ra)) & 0x1f) << 16)) 4520 4521/* The mask for an X form comparison instruction. */ 4522#define XCMP_MASK (X_MASK | (((uint64_t)1) << 22)) 4523 4524/* The mask for an X form comparison instruction with the L field 4525 fixed. */ 4526#define XCMPL_MASK (XCMP_MASK | (((uint64_t)1) << 21)) 4527 4528/* An X form trap instruction with the TO field specified. */ 4529#define XTO(op, xop, to) \ 4530 (X ((op), (xop)) \ 4531 | ((((uint64_t)(to)) & 0x1f) << 21)) 4532#define XTO_MASK (X_MASK | TO_MASK) 4533 4534/* An X form tlb instruction with the SH field specified. */ 4535#define XTLB(op, xop, sh) \ 4536 (X ((op), (xop)) \ 4537 | ((((uint64_t)(sh)) & 0x1f) << 11)) 4538#define XTLB_MASK (X_MASK | SH_MASK) 4539 4540/* An X form sync instruction. */ 4541#define XSYNC(op, xop, l) \ 4542 (X ((op), (xop)) \ 4543 | ((((uint64_t)(l)) & 3) << 21)) 4544 4545/* An X form sync instruction with everything filled in except the LS 4546 field. */ 4547#define XSYNC_MASK (0xff9fffff) 4548 4549/* An X form sync instruction with everything filled in except the L 4550 and E fields. */ 4551#define XSYNCLE_MASK (0xff90ffff) 4552 4553/* An X form sync instruction. */ 4554#define XSYNCLS(op, xop, l, s) \ 4555 (X ((op), (xop)) \ 4556 | ((((uint64_t)(l)) & 7) << 21) \ 4557 | ((((uint64_t)(s)) & 3) << 16)) 4558 4559/* An X form sync instruction with everything filled in except the 4560 L and SC fields. */ 4561#define XSYNCLS_MASK (0xff1cffff) 4562 4563/* An X_MASK, but with the EH bit clear. */ 4564#define XEH_MASK (X_MASK & ~((uint64_t )1)) 4565 4566/* An X form AltiVec dss instruction. */ 4567#define XDSS(op, xop, a) (X ((op), (xop)) | ((((uint64_t)(a)) & 1) << 25)) 4568#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 4569 4570/* An XFL form instruction. */ 4571#define XFL(op, xop, rc) \ 4572 (OP (op) \ 4573 | ((((uint64_t)(xop)) & 0x3ff) << 1) \ 4574 | (((uint64_t)(rc)) & 1)) 4575#define XFL_MASK XFL (0x3f, 0x3ff, 1) 4576 4577/* An X form isel instruction. */ 4578#define XISEL(op, xop, cr) (OP (op) | ((xop) << 1) | ((cr) << 6)) 4579#define XISEL_MASK XISEL(0x3f, 0x1f, 0) 4580 4581/* An XL form instruction with the LK field set to 0. */ 4582#define XL(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3ff) << 1)) 4583 4584/* An XL form instruction which uses the LK field. */ 4585#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) 4586 4587/* The mask for an XL form instruction. */ 4588#define XL_MASK XLLK (0x3f, 0x3ff, 1) 4589 4590/* An XL_MASK with the RT, RA and RB fields fixed, but S bit clear. */ 4591#define XLS_MASK ((XL_MASK | RT_MASK | RA_MASK | RB_MASK) & ~(1 << 11)) 4592 4593/* An XL form instruction which explicitly sets the BO field. */ 4594#define XLO(op, bo, xop, lk) \ 4595 (XLLK ((op), (xop), (lk)) | ((((uint64_t)(bo)) & 0x1f) << 21)) 4596#define XLO_MASK (XL_MASK | BO_MASK) 4597 4598/* An XL form instruction which sets the BO field and the condition 4599 bits of the BI field. */ 4600#define XLOCB(op, bo, cb, xop, lk) \ 4601 (XLO ((op), (bo), (xop), (lk)) | ((((uint64_t)(cb)) & 3) << 16)) 4602 4603/* An XL_MASK with the BB field fixed. */ 4604#define XLBB_MASK (XL_MASK | BB_MASK) 4605 4606/* A mask for branch instructions using the BH field. */ 4607#define XLBH_MASK (XL_MASK | (BB_MASK & ~(3 << 11))) 4608 4609/* An XLBH_MASK with the BO field fixed. */ 4610#define XLBOBB_MASK (XLBH_MASK | BO_MASK) 4611 4612/* An XLBH_MASK with the BO and BI fields fixed. */ 4613#define XLBOBIBB_MASK (XLBOBB_MASK | BI_MASK) 4614 4615/* An XLBH_MASK with the BO and condition bits of the BI fields fixed. */ 4616#define XLBOCBBB_MASK (XLBOBB_MASK | (3 << 16)) 4617 4618/* An X form mbar instruction with MO field. */ 4619#define XMBAR(op, xop, mo) \ 4620 (X ((op), (xop)) \ 4621 | ((((uint64_t)(mo)) & 1) << 21)) 4622 4623/* An XO form instruction. */ 4624#define XO(op, xop, oe, rc) \ 4625 (OP (op) \ 4626 | ((((uint64_t)(xop)) & 0x1ff) << 1) \ 4627 | ((((uint64_t)(oe)) & 1) << 10) \ 4628 | (((unsigned long)(rc)) & 1)) 4629#define XO_MASK XO (0x3f, 0x1ff, 1, 1) 4630 4631/* An XO_MASK with the RB field fixed. */ 4632#define XORB_MASK (XO_MASK | RB_MASK) 4633 4634/* An XOPS form instruction for paired singles. */ 4635#define XOPS(op, xop, rc) \ 4636 (OP (op) \ 4637 | ((((uint64_t)(xop)) & 0x3ff) << 1) \ 4638 | (((uint64_t)(rc)) & 1)) 4639#define XOPS_MASK XOPS (0x3f, 0x3ff, 1) 4640 4641 4642/* An XS form instruction. */ 4643#define XS(op, xop, rc) \ 4644 (OP (op) \ 4645 | ((((uint64_t)(xop)) & 0x1ff) << 2) \ 4646 | (((uint64_t)(rc)) & 1)) 4647#define XS_MASK XS (0x3f, 0x1ff, 1) 4648 4649/* A mask for the FXM version of an XFX form instruction. */ 4650#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) 4651 4652/* An XFX form instruction with the FXM field filled in. */ 4653#define XFXM(op, xop, fxm, p4) \ 4654 (X ((op), (xop)) \ 4655 | ((((uint64_t)(fxm)) & 0xff) << 12) \ 4656 | ((uint64_t)(p4) << 20)) 4657 4658/* An XFX form instruction with the SPR field filled in. */ 4659#define XSPR(op, xop, spr) \ 4660 (X ((op), (xop)) \ 4661 | ((((uint64_t)(spr)) & 0x1f) << 16) \ 4662 | ((((uint64_t)(spr)) & 0x3e0) << 6)) 4663#define XSPR_MASK (X_MASK | SPR_MASK) 4664 4665/* An XFX form instruction with the SPR field filled in except for the 4666 SPRBAT field. */ 4667#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) 4668 4669/* An XFX form instruction with the SPR field filled in except for the 4670 SPRGQR field. */ 4671#define XSPRGQR_MASK (XSPR_MASK &~ SPRGQR_MASK) 4672 4673/* An XFX form instruction with the SPR field filled in except for the 4674 SPRG field. */ 4675#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16)) 4676 4677/* An X form instruction with everything filled in except the E field. */ 4678#define XE_MASK (0xffff7fff) 4679 4680/* An X form user context instruction. */ 4681#define XUC(op, xop) (OP (op) | (((uint64_t)(xop)) & 0x1f)) 4682#define XUC_MASK XUC(0x3f, 0x1f) 4683 4684/* An XW form instruction. */ 4685#define XW(op, xop, rc) \ 4686 (OP (op) \ 4687 | ((((uint64_t)(xop)) & 0x3f) << 1) \ 4688 | ((rc) & 1)) 4689/* The mask for a G form instruction. rc not supported at present. */ 4690#define XW_MASK XW (0x3f, 0x3f, 0) 4691 4692/* An APU form instruction. */ 4693#define APU(op, xop, rc) \ 4694 (OP (op) \ 4695 | (((uint64_t)(xop)) & 0x3ff) << 1 \ 4696 | ((rc) & 1)) 4697 4698/* The mask for an APU form instruction. */ 4699#define APU_MASK APU (0x3f, 0x3ff, 1) 4700#define APU_RT_MASK (APU_MASK | RT_MASK) 4701#define APU_RA_MASK (APU_MASK | RA_MASK) 4702 4703/* The BO encodings used in extended conditional branch mnemonics. */ 4704#define BODNZF (0x0) 4705#define BODNZFP (0x1) 4706#define BODZF (0x2) 4707#define BODZFP (0x3) 4708#define BODNZT (0x8) 4709#define BODNZTP (0x9) 4710#define BODZT (0xa) 4711#define BODZTP (0xb) 4712 4713#define BOF (0x4) 4714#define BOFP (0x5) 4715#define BOFM4 (0x6) 4716#define BOFP4 (0x7) 4717#define BOT (0xc) 4718#define BOTP (0xd) 4719#define BOTM4 (0xe) 4720#define BOTP4 (0xf) 4721 4722#define BODNZ (0x10) 4723#define BODNZP (0x11) 4724#define BODZ (0x12) 4725#define BODZP (0x13) 4726#define BODNZM4 (0x18) 4727#define BODNZP4 (0x19) 4728#define BODZM4 (0x1a) 4729#define BODZP4 (0x1b) 4730 4731#define BOU (0x14) 4732 4733/* The BO16 encodings used in extended VLE conditional branch mnemonics. */ 4734#define BO16F (0x0) 4735#define BO16T (0x1) 4736 4737/* The BO32 encodings used in extended VLE conditional branch mnemonics. */ 4738#define BO32F (0x0) 4739#define BO32T (0x1) 4740#define BO32DNZ (0x2) 4741#define BO32DZ (0x3) 4742 4743/* The BI condition bit encodings used in extended conditional branch 4744 mnemonics. */ 4745#define CBLT (0) 4746#define CBGT (1) 4747#define CBEQ (2) 4748#define CBSO (3) 4749 4750/* The TO encodings used in extended trap mnemonics. */ 4751#define TOLGT (0x1) 4752#define TOLLT (0x2) 4753#define TOEQ (0x4) 4754#define TOLGE (0x5) 4755#define TOLNL (0x5) 4756#define TOLLE (0x6) 4757#define TOLNG (0x6) 4758#define TOGT (0x8) 4759#define TOGE (0xc) 4760#define TONL (0xc) 4761#define TOLT (0x10) 4762#define TOLE (0x14) 4763#define TONG (0x14) 4764#define TONE (0x18) 4765#define TOU (0x1f) 4766 4767/* Smaller names for the flags so each entry in the opcodes table will 4768 fit on a single line. */ 4769#undef PPC 4770#define PPC PPC_OPCODE_PPC 4771#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 4772#define POWER4 PPC_OPCODE_POWER4 4773#define POWER5 PPC_OPCODE_POWER5 4774#define POWER6 PPC_OPCODE_POWER6 4775#define POWER7 PPC_OPCODE_POWER7 4776#define POWER8 PPC_OPCODE_POWER8 4777#define POWER9 PPC_OPCODE_POWER9 4778#define POWER10 PPC_OPCODE_POWER10 4779#define CELL PPC_OPCODE_CELL 4780#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_64_BRIDGE 4781#define NON32 (PPC_OPCODE_64 | PPC_OPCODE_POWER4 \ 4782 | PPC_OPCODE_EFS | PPC_OPCODE_E500MC | PPC_OPCODE_TITAN) 4783#define PPC403 PPC_OPCODE_403 4784#define PPC405 PPC_OPCODE_405 4785#define PPC440 PPC_OPCODE_440 4786#define PPC464 PPC440 4787#define PPC476 PPC_OPCODE_476 4788#define PPC750 PPC_OPCODE_750 4789#define GEKKO PPC_OPCODE_750 4790#define BROADWAY PPC_OPCODE_750 4791#define PPC7450 PPC_OPCODE_7450 4792#define PPC860 PPC_OPCODE_860 4793#define PPCPS PPC_OPCODE_PPCPS 4794#define PPCVEC PPC_OPCODE_ALTIVEC 4795#define PPCVEC2 (PPC_OPCODE_POWER8 | PPC_OPCODE_E6500) 4796#define PPCVEC3 PPC_OPCODE_POWER9 4797#define PPCVSX PPC_OPCODE_VSX 4798#define PPCVSX2 PPC_OPCODE_POWER8 4799#define PPCVSX3 PPC_OPCODE_POWER9 4800#define PPCVSX4 PPC_OPCODE_POWER10 4801#define POWER PPC_OPCODE_POWER 4802#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 4803#define PWR2COM PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_COMMON 4804#define PPCPWR2 (PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 \ 4805 | PPC_OPCODE_COMMON) 4806#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 4807#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 4808#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 4809#define MFDEC1 PPC_OPCODE_POWER 4810#define MFDEC2 (PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE \ 4811 | PPC_OPCODE_TITAN) 4812#define BOOKE PPC_OPCODE_BOOKE 4813#define NO371 PPC_OPCODE_BOOKE | PPC_OPCODE_PPCPS | PPC_OPCODE_EFS 4814#define PPCE300 PPC_OPCODE_E300 4815#define PPCSPE PPC_OPCODE_SPE 4816#define PPCSPE2 PPC_OPCODE_SPE2 4817#define PPCISEL PPC_OPCODE_ISEL 4818#define PPCEFS PPC_OPCODE_EFS 4819#define PPCEFS2 PPC_OPCODE_EFS2 4820#define PPCBRLK PPC_OPCODE_BRLOCK 4821#define PPCPMR PPC_OPCODE_PMR 4822#define PPCTMR PPC_OPCODE_TMR 4823#define PPCCHLK PPC_OPCODE_CACHELCK 4824#define PPCRFMCI PPC_OPCODE_RFMCI 4825#define E500MC PPC_OPCODE_E500MC 4826#define PPCA2 PPC_OPCODE_A2 4827#define TITAN PPC_OPCODE_TITAN 4828#define MULHW PPC_OPCODE_405 | PPC_OPCODE_440 | PPC_OPCODE_476 | TITAN 4829#define E500 PPC_OPCODE_E500 4830#define E6500 PPC_OPCODE_E6500 4831#define PPCVLE PPC_OPCODE_VLE 4832#define PPCHTM PPC_OPCODE_POWER8 4833#define E200Z4 PPC_OPCODE_E200Z4 4834#define PPCLSP PPC_OPCODE_LSP 4835/* Used to mark extended mnemonic in deprecated field so that -Mraw 4836 won't use this variant in disassembly. */ 4837#define EXT PPC_OPCODE_RAW 4838 4839/* The opcode table. 4840 4841 The format of the opcode table is: 4842 4843 NAME OPCODE MASK FLAGS ANTI {OPERANDS} 4844 4845 NAME is the name of the instruction. 4846 OPCODE is the instruction opcode. 4847 MASK is the opcode mask; this is used to tell the disassembler 4848 which bits in the actual opcode must match OPCODE. 4849 FLAGS are flags indicating which processors support the instruction. 4850 ANTI indicates which processors don't support the instruction. 4851 OPERANDS is the list of operands. 4852 4853 The disassembler reads the table in order and prints the first 4854 instruction which matches, so this table is sorted to put more 4855 specific instructions before more general instructions. 4856 4857 This table must be sorted by major opcode. Please try to keep it 4858 vaguely sorted within major opcode too, except of course where 4859 constrained otherwise by disassembler operation. */ 4860 4861const struct powerpc_opcode powerpc_opcodes[] = { 4862{"attn", X(0,256), X_MASK, POWER4|PPCA2, PPC476|PPCVLE, {0}}, 4863{"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4864{"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4865{"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4866{"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4867{"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4868{"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4869{"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4870{"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4871{"tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4872{"tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4873{"tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4874{"tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4875{"tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4876{"tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4877{"tdui", OPTO(2,TOU), OPTO_MASK, PPC64, PPCVLE|EXT, {RA, SI}}, 4878{"tdi", OP(2), OP_MASK, PPC64, PPCVLE, {TO, RA, SI}}, 4879 4880{"twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4881{"tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4882{"twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4883{"tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4884{"tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4885{"teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4886{"twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4887{"tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4888{"twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4889{"tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4890{"twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4891{"tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4892{"twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4893{"tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4894{"twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4895{"tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4896{"twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4897{"tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4898{"twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4899{"tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4900{"twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4901{"tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4902{"twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4903{"tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4904{"twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4905{"tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4906{"twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4907{"tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4908{"twui", OPTO(3,TOU), OPTO_MASK, PPCCOM, PPCVLE|EXT, {RA, SI}}, 4909{"tui", OPTO(3,TOU), OPTO_MASK, PWRCOM, PPCVLE|EXT, {RA, SI}}, 4910{"twi", OP(3), OP_MASK, PPCCOM, PPCVLE, {TO, RA, SI}}, 4911{"ti", OP(3), OP_MASK, PWRCOM, PPCVLE, {TO, RA, SI}}, 4912 4913{"ps_cmpu0", X (4, 0), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 4914{"vaddubm", VX (4, 0), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4915{"vmul10cuq", VX (4, 1), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, 4916{"vmaxub", VX (4, 2), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4917{"vrlb", VX (4, 4), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4918{"vrlq", VX (4, 5), VX_MASK, POWER10, 0, {VD, VA, VB}}, 4919{"vcmpequb", VXR(4, 6,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 4920{"vcmpneb", VXR(4, 7,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 4921{"vmuloub", VX (4, 8), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4922{"vaddfp", VX (4, 10), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4923{"vdivuq", VX (4, 11), VX_MASK, POWER10, 0, {VD, VA, VB}}, 4924{"psq_lx", XW (4, 6,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, 4925{"vmrghb", VX (4, 12), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4926{"vstribl", VXVA(4,13,0), VXVA_MASK, POWER10, 0, {VD, VB}}, 4927{"vstribr", VXVA(4,13,1), VXVA_MASK, POWER10, 0, {VD, VB}}, 4928{"vstrihl", VXVA(4,13,2), VXVA_MASK, POWER10, 0, {VD, VB}}, 4929{"vstrihr", VXVA(4,13,3), VXVA_MASK, POWER10, 0, {VD, VB}}, 4930{"psq_stx", XW (4, 7,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, 4931{"vpkuhum", VX (4, 14), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 4932{"vinsbvlx", VX (4, 15), VX_MASK, POWER10, 0, {VD, RA, VB}}, 4933{"mulhhwu", XRC(4, 8,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 4934{"mulhhwu.", XRC(4, 8,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 4935{"mtvsrbmi", DX (4,10), DX_MASK, POWER10, 0, {VD, DXD}}, 4936{"ps_sum0", A (4, 10,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4937{"ps_sum0.", A (4, 10,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4938{"vsldbi", VX (4, 22), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}}, 4939{"ps_sum1", A (4, 11,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4940{"ps_sum1.", A (4, 11,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4941{"vextdubvlx", VX (4, 24), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, 4942{"ps_muls0", A (4, 12,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 4943{"machhwu", XO (4, 12,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4944{"vextdubvrx", VX (4, 25), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, 4945{"ps_muls0.", A (4, 12,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 4946{"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 4947{"vextduhvlx", VX (4, 26), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, 4948{"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 4949{"vextduhvrx", VX (4, 27), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, 4950{"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 4951{"vextduwvlx", VX (4, 28), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, 4952{"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4953{"vextduwvrx", VX (4, 29), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, 4954{"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4955{"vextddvlx", VX (4, 30), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, 4956{"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4957{"vextddvrx", VX (4, 31), VXRC_MASK, POWER10, 0, {VD, VA, VB, RC}}, 4958{"ps_madds1.", A (4, 15,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4959{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4960{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4961{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4962{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, 4963{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4964{"vmsumcud", VXA(4, 23), VXA_MASK, POWER10, 0, {VD, VA, VB, VC}}, 4965{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4966{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4967{"vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4968{"vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4969{"vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4970{"ps_sub", A (4, 20,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4971{"vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4972{"ps_sub.", A (4, 20,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4973{"vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4974{"ps_add", A (4, 21,0), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4975{"vsel", VXA(4, 42), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4976{"ps_add.", A (4, 21,1), AFRC_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 4977{"vperm", VXA(4, 43), VXA_MASK, PPCVEC, 0, {VD, VA, VB, VC}}, 4978{"vsldoi", VXA(4, 44), VXASHB_MASK, PPCVEC, 0, {VD, VA, VB, SHB}}, 4979{"vpermxor", VXA(4, 45), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 4980{"ps_sel", A (4, 23,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4981{"vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, 4982{"ps_sel.", A (4, 23,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4983{"vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, 0, {VD, VA, VC, VB}}, 4984{"ps_res", A (4, 24,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 4985{"maddhd", VXA(4, 48), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 4986{"ps_res.", A (4, 24,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 4987{"maddhdu", VXA(4, 49), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 4988{"ps_mul", A (4, 25,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 4989{"ps_mul.", A (4, 25,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}}, 4990{"maddld", VXA(4, 51), VXA_MASK, POWER9, 0, {RT, RA, RB, RC}}, 4991{"ps_rsqrte", A (4, 26,0), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 4992{"ps_rsqrte.", A (4, 26,1), AFRAFRC_MASK, PPCPS, 0, {FRT, FRB}}, 4993{"ps_msub", A (4, 28,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4994{"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4995{"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4996{"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4997{"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}}, 4998{"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 4999{"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 5000{"ps_nmsub.", A (4, 30,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 5001{"vaddecuq", VXA(4, 61), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 5002{"ps_nmadd", A (4, 31,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 5003{"vsubeuqm", VXA(4, 62), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 5004{"ps_nmadd.", A (4, 31,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}}, 5005{"vsubecuq", VXA(4, 63), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}}, 5006{"ps_cmpo0", X (4, 32), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 5007{"vadduhm", VX (4, 64), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5008{"vmul10ecuq", VX (4, 65), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5009{"vmaxuh", VX (4, 66), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5010{"vrlh", VX (4, 68), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5011{"vrlqmi", VX (4, 69), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5012{"vcmpequh", VXR(4, 70,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5013{"vcmpneh", VXR(4, 71,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5014{"vmulouh", VX (4, 72), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5015{"vsubfp", VX (4, 74), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5016{"psq_lux", XW (4, 38,0), XW_MASK, PPCPS, 0, {FRT,RA,RB,PSWM,PSQM}}, 5017{"vmrghh", VX (4, 76), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5018{"psq_stux", XW (4, 39,0), XW_MASK, PPCPS, 0, {FRS,RA,RB,PSWM,PSQM}}, 5019{"vpkuwum", VX (4, 78), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5020{"vinshvlx", VX (4, 79), VX_MASK, POWER10, 0, {VD, RA, VB}}, 5021{"ps_neg", XRC(4, 40,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5022{"mulhhw", XRC(4, 40,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 5023{"ps_neg.", XRC(4, 40,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5024{"mulhhw.", XRC(4, 40,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 5025{"machhw", XO (4, 44,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5026{"machhw.", XO (4, 44,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5027{"nmachhw", XO (4, 46,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5028{"nmachhw.", XO (4, 46,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5029{"ps_cmpu1", X (4, 64), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 5030{"vadduwm", VX (4, 128), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5031{"vmaxuw", VX (4, 130), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5032{"vrlw", VX (4, 132), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5033{"vrlwmi", VX (4, 133), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5034{"vcmpequw", VXR(4, 134,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5035{"vcmpnew", VXR(4, 135,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5036{"vmulouw", VX (4, 136), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5037{"vmuluwm", VX (4, 137), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5038{"vdivuw", VX (4, 139), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5039{"vmrghw", VX (4, 140), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5040{"vpkuhus", VX (4, 142), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5041{"vinswvlx", VX (4, 143), VX_MASK, POWER10, 0, {VD, RA, VB}}, 5042{"ps_mr", XRC(4, 72,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5043{"ps_mr.", XRC(4, 72,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5044{"machhwsu", XO (4, 76,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5045{"machhwsu.", XO (4, 76,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5046{"ps_cmpo1", X (4, 96), XBF_MASK, PPCPS, 0, {BF, FRA, FRB}}, 5047{"vaddudm", VX (4, 192), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5048{"vmaxud", VX (4, 194), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5049{"vrld", VX (4, 196), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5050{"vrldmi", VX (4, 197), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5051{"vcmpeqfp", VXR(4, 198,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5052{"vcmpequd", VXR(4, 199,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5053{"vmuloud", VX (4, 200), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5054{"vdivud", VX (4, 203), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5055{"vpkuwus", VX (4, 206), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5056{"vinsw", VX (4, 207), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}}, 5057{"machhws", XO (4, 108,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5058{"machhws.", XO (4, 108,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5059{"nmachhws", XO (4, 110,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5060{"nmachhws.", XO (4, 110,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5061{"vadduqm", VX (4, 256), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5062{"vcmpuq", VX (4, 257), VXBF_MASK, POWER10, 0, {BF, VA, VB}}, 5063{"vmaxsb", VX (4, 258), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5064{"vslb", VX (4, 260), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5065{"vslq", VX (4, 261), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5066{"vcmpnezb", VXR(4, 263,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5067{"vmulosb", VX (4, 264), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5068{"vrefp", VX (4, 266), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5069{"vdivsq", VX (4, 267), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5070{"vmrglb", VX (4, 268), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5071{"vpkshus", VX (4, 270), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5072{"vinsbvrx", VX (4, 271), VX_MASK, POWER10, 0, {VD, RA, VB}}, 5073{"ps_nabs", XRC(4, 136,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5074{"mulchwu", XRC(4, 136,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 5075{"ps_nabs.", XRC(4, 136,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5076{"mulchwu.", XRC(4, 136,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 5077{"macchwu", XO (4, 140,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5078{"macchwu.", XO (4, 140,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5079{"vaddcuq", VX (4, 320), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5080{"vcmpsq", VX (4, 321), VXBF_MASK, POWER10, 0, {BF, VA, VB}}, 5081{"vmaxsh", VX (4, 322), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5082{"vslh", VX (4, 324), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5083{"vrlqnm", VX (4, 325), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5084{"vcmpnezh", VXR(4, 327,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5085{"vmulosh", VX (4, 328), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5086{"vrsqrtefp", VX (4, 330), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5087{"vmrglh", VX (4, 332), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5088{"vpkswus", VX (4, 334), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5089{"vinshvrx", VX (4, 335), VX_MASK, POWER10, 0, {VD, RA, VB}}, 5090{"mulchw", XRC(4, 168,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 5091{"mulchw.", XRC(4, 168,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 5092{"macchw", XO (4, 172,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5093{"macchw.", XO (4, 172,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5094{"nmacchw", XO (4, 174,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5095{"nmacchw.", XO (4, 174,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5096{"vaddcuw", VX (4, 384), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5097{"vmaxsw", VX (4, 386), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5098{"vslw", VX (4, 388), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5099{"vrlwnm", VX (4, 389), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5100{"vcmpnezw", VXR(4, 391,0), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5101{"vmulosw", VX (4, 392), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5102{"vexptefp", VX (4, 394), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5103{"vdivsw", VX (4, 395), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5104{"vmrglw", VX (4, 396), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5105{"vclrlb", VX (4, 397), VX_MASK, POWER10, 0, {VD, VA, RB}}, 5106{"vpkshss", VX (4, 398), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5107{"vinswvrx", VX (4, 399), VX_MASK, POWER10, 0, {VD, RA, VB}}, 5108{"macchwsu", XO (4, 204,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5109{"macchwsu.", XO (4, 204,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5110{"vmaxsd", VX (4, 450), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5111{"vsl", VX (4, 452), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5112{"vrldnm", VX (4, 453), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5113{"vcmpgefp", VXR(4, 454,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5114{"vcmpequq", VXR(4, 455,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, 5115{"vmulosd", VX (4, 456), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5116{"vmulld", VX (4, 457), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5117{"vlogefp", VX (4, 458), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5118{"vdivsd", VX (4, 459), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5119{"vclrrb", VX (4, 461), VX_MASK, POWER10, 0, {VD, VA, RB}}, 5120{"vpkswss", VX (4, 462), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5121{"vinsd", VX (4, 463), VXUIMM4_MASK, POWER10, 0, {VD, RB, UIMM4}}, 5122{"macchws", XO (4, 236,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5123{"macchws.", XO (4, 236,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5124{"nmacchws", XO (4, 238,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5125{"nmacchws.", XO (4, 238,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5126{"evaddw", VX (4, 512), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5127{"vaddubs", VX (4, 512), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5128{"vmul10uq", VX (4, 513), VXVB_MASK, PPCVEC3, 0, {VD, VA}}, 5129{"evaddiw", VX (4, 514), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, 5130{"vminub", VX (4, 514), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5131{"evsubfw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5132{"evsubw", VX (4, 516), VX_MASK, PPCSPE, 0, {RS, RB, RA}}, 5133{"vsrb", VX (4, 516), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5134{"vsrq", VX (4, 517), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5135{"evsubifw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, UIMM, RB}}, 5136{"evsubiw", VX (4, 518), VX_MASK, PPCSPE, 0, {RS, RB, UIMM}}, 5137{"vcmpgtub", VXR(4, 518,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5138{"evabs", VX (4, 520), VX_MASK, PPCSPE, 0, {RS, RA}}, 5139{"vmuleub", VX (4, 520), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5140{"evneg", VX (4, 521), VX_MASK, PPCSPE, 0, {RS, RA}}, 5141{"evextsb", VX (4, 522), VX_MASK, PPCSPE, 0, {RS, RA}}, 5142{"vrfin", VX (4, 522), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5143{"vdiveuq", VX (4, 523), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5144{"evextsh", VX (4, 523), VX_MASK, PPCSPE, 0, {RS, RA}}, 5145{"evrndw", VX (4, 524), VX_MASK, PPCSPE, 0, {RS, RA}}, 5146{"vspltb", VX (4, 524), VXUIMM4_MASK, PPCVEC, 0, {VD, VB, UIMM4}}, 5147{"vextractub", VX (4, 525), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 5148{"evcntlzw", VX (4, 525), VX_MASK, PPCSPE, 0, {RS, RA}}, 5149{"evcntlsw", VX (4, 526), VX_MASK, PPCSPE, 0, {RS, RA}}, 5150{"vupkhsb", VX (4, 526), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5151{"vinsblx", VX (4, 527), VX_MASK, POWER10, 0, {VD, RA, RB}}, 5152{"brinc", VX (4, 527), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5153{"ps_abs", XRC(4, 264,0), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5154{"ps_abs.", XRC(4, 264,1), XRA_MASK, PPCPS, 0, {FRT, FRB}}, 5155{"evand", VX (4, 529), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5156{"evandc", VX (4, 530), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5157{"vsrdbi", VX (4, 534), VXSH_MASK, POWER10, 0, {VD, VA, VB, SH3}}, 5158{"evxor", VX (4, 534), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5159{"evmr", VX (4, 535), VX_MASK, PPCSPE, EXT, {RS, RAB}}, 5160{"evor", VX (4, 535), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5161{"evnot", VX (4, 536), VX_MASK, PPCSPE, EXT, {RS, RAB}}, 5162{"evnor", VX (4, 536), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5163{"get", APU(4, 268,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 5164{"eveqv", VX (4, 537), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5165{"evorc", VX (4, 539), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5166{"evnand", VX (4, 542), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5167{"evsrwu", VX (4, 544), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5168{"evsrws", VX (4, 545), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5169{"evsrwiu", VX (4, 546), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 5170{"evsrwis", VX (4, 547), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 5171{"evslw", VX (4, 548), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5172{"evslwi", VX (4, 550), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 5173{"evrlw", VX (4, 552), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5174{"evsplati", VX (4, 553), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 5175{"evrlwi", VX (4, 554), VX_MASK, PPCSPE, 0, {RS, RA, EVUIMM}}, 5176{"evsplatfi", VX (4, 555), VX_MASK, PPCSPE, 0, {RS, SIMM}}, 5177{"evmergehi", VX (4, 556), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5178{"evmergelo", VX (4, 557), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5179{"evmergehilo", VX (4, 558), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5180{"evmergelohi", VX (4, 559), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5181{"evcmpgtu", VX (4, 560), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5182{"evcmpgts", VX (4, 561), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5183{"evcmpltu", VX (4, 562), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5184{"evcmplts", VX (4, 563), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5185{"evcmpeq", VX (4, 564), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5186{"cget", APU(4, 284,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 5187{"vadduhs", VX (4, 576), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5188{"vmul10euq", VX (4, 577), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5189{"vminuh", VX (4, 578), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5190{"vsrh", VX (4, 580), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5191{"vcmpgtuh", VXR(4, 582,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5192{"vmuleuh", VX (4, 584), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5193{"vrfiz", VX (4, 586), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5194{"vsplth", VX (4, 588), VXUIMM3_MASK, PPCVEC, 0, {VD, VB, UIMM3}}, 5195{"vextractuh", VX (4, 589), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 5196{"vupkhsh", VX (4, 590), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5197{"vinshlx", VX (4, 591), VX_MASK, POWER10, 0, {VD, RA, RB}}, 5198{"nget", APU(4, 300,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 5199{"evsel", EVSEL(4,79), EVSEL_MASK, PPCSPE, 0, {RS, RA, RB, CRFS}}, 5200{"ncget", APU(4, 316,0), APU_RA_MASK, PPC405, 0, {RT, FSL}}, 5201{"evfsadd", VX (4, 640), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5202{"vadduws", VX (4, 640), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5203{"evfssub", VX (4, 641), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5204{"evfsmadd", VX (4, 642), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5205{"vminuw", VX (4, 642), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5206{"evfsmsub", VX (4, 643), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5207{"evfsabs", VX (4, 644), VX_MASK, PPCSPE, 0, {RS, RA}}, 5208{"vsrw", VX (4, 644), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5209{"evfsnabs", VX (4, 645), VX_MASK, PPCSPE, 0, {RS, RA}}, 5210{"evfsneg", VX (4, 646), VX_MASK, PPCSPE, 0, {RS, RA}}, 5211{"vcmpgtuw", VXR(4, 646,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5212{"vcmpgtuq", VXR(4, 647,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, 5213{"evfssqrt", VX_RB_CONST(4, 647, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, 5214{"vmuleuw", VX (4, 648), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5215{"evfsmul", VX (4, 648), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5216{"vmulhuw", VX (4, 649), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5217{"evfsdiv", VX (4, 649), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5218{"evfsnmadd", VX (4, 650), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5219{"vrfip", VX (4, 650), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5220{"vdiveuw", VX (4, 651), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5221{"evfsnmsub", VX (4, 651), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5222{"evfscmpgt", VX (4, 652), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5223{"vspltw", VX (4, 652), VXUIMM2_MASK, PPCVEC, 0, {VD, VB, UIMM2}}, 5224{"vextractuw", VX (4, 653), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 5225{"evfscmplt", VX (4, 653), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5226{"evfscmpeq", VX (4, 654), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5227{"vupklsb", VX (4, 654), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5228{"vinswlx", VX (4, 655), VX_MASK, POWER10, 0, {VD, RA, RB}}, 5229{"evfscfui", VX (4, 656), VX_MASK, PPCSPE, 0, {RS, RB}}, 5230{"evfscfh", VX_RA_CONST(4, 657, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 5231{"evfscfsi", VX (4, 657), VX_MASK, PPCSPE, 0, {RS, RB}}, 5232{"evfscfuf", VX (4, 658), VX_MASK, PPCSPE, 0, {RS, RB}}, 5233{"evfscfsf", VX (4, 659), VX_MASK, PPCSPE, 0, {RS, RB}}, 5234{"evfsctui", VX (4, 660), VX_MASK, PPCSPE, 0, {RS, RB}}, 5235{"evfscth", VX_RA_CONST(4, 661, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 5236{"evfsctsi", VX (4, 661), VX_MASK, PPCSPE, 0, {RS, RB}}, 5237{"evfsctuf", VX (4, 662), VX_MASK, PPCSPE, 0, {RS, RB}}, 5238{"evfsctsf", VX (4, 663), VX_MASK, PPCSPE, 0, {RS, RB}}, 5239{"evfsctuiz", VX (4, 664), VX_MASK, PPCSPE, 0, {RS, RB}}, 5240{"put", APU(4, 332,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 5241{"evfsctsiz", VX (4, 666), VX_MASK, PPCSPE, 0, {RS, RB}}, 5242{"evfststgt", VX (4, 668), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5243{"evfststlt", VX (4, 669), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5244{"evfststeq", VX (4, 670), VX_MASK, PPCSPE, 0, {CRFD, RA, RB}}, 5245{"evfsmax", VX (4, 672), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5246{"evfsmin", VX (4, 673), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5247{"evfsaddsub", VX (4, 674), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5248{"evfssubadd", VX (4, 675), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5249{"evfssum", VX (4, 676), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5250{"evfsdiff", VX (4, 677), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5251{"evfssumdiff", VX (4, 678), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5252{"evfsdiffsum", VX (4, 679), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5253{"evfsaddx", VX (4, 680), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5254{"evfssubx", VX (4, 681), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5255{"evfsaddsubx", VX (4, 682), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5256{"evfssubaddx", VX (4, 683), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5257{"evfsmulx", VX (4, 684), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5258{"evfsmule", VX (4, 686), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5259{"evfsmulo", VX (4, 687), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5260{"efsmax", VX (4, 688), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5261{"efsmin", VX (4, 689), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5262{"efdmax", VX (4, 696), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5263{"cput", APU(4, 348,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 5264{"efdmin", VX (4, 697), VX_MASK, PPCEFS2, 0, {RD, RA, RB}}, 5265{"efsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5266{"evsadd", VX (4, 704), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5267{"efssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5268{"evssub", VX (4, 705), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5269{"efsmadd", VX (4, 706), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, 5270{"vminud", VX (4, 706), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5271{"efsmsub", VX (4, 707), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, 5272{"efsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, 5273{"evsabs", VX (4, 708), VX_MASK, PPCEFS, 0, {RS, RA}}, 5274{"vsr", VX (4, 708), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5275{"efsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, 5276{"evsnabs", VX (4, 709), VX_MASK, PPCEFS, 0, {RS, RA}}, 5277{"efsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, 5278{"evsneg", VX (4, 710), VX_MASK, PPCEFS, 0, {RS, RA}}, 5279{"vcmpgtfp", VXR(4, 710,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5280{"efssqrt", VX_RB_CONST(4, 711, 0), VX_RB_CONST_MASK,PPCEFS2, 0, {RD, RA}}, 5281{"vcmpgtud", VXR(4, 711,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5282{"vmuleud", VX (4, 712), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5283{"efsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5284{"evsmul", VX (4, 712), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5285{"vmulhud", VX (4, 713), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5286{"efsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5287{"evsdiv", VX (4, 713), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5288{"efsnmadd", VX (4, 714), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, 5289{"vrfim", VX (4, 714), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5290{"vdiveud", VX (4, 715), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5291{"efsnmsub", VX (4, 715), VX_MASK, PPCEFS2, 0, {RS, RA, RB}}, 5292{"efscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5293{"evscmpgt", VX (4, 716), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5294{"vextractd", VX (4, 717), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 5295{"efscmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5296{"evsgmplt", VX (4, 717), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5297{"efscmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5298{"evsgmpeq", VX (4, 718), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5299{"vupklsh", VX (4, 718), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5300{"vinsdlx", VX (4, 719), VX_MASK, POWER10, 0, {VD, RA, RB}}, 5301{"efscfd", VX (4, 719), VX_MASK, PPCEFS, 0, {RS, RB}}, 5302{"efscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, 5303{"evscfui", VX (4, 720), VX_MASK, PPCEFS, 0, {RS, RB}}, 5304{"efscfh", VX_RA_CONST(4, 721, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 5305{"efscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, 5306{"evscfsi", VX (4, 721), VX_MASK, PPCEFS, 0, {RS, RB}}, 5307{"efscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, 5308{"evscfuf", VX (4, 722), VX_MASK, PPCEFS, 0, {RS, RB}}, 5309{"efscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, 5310{"evscfsf", VX (4, 723), VX_MASK, PPCEFS, 0, {RS, RB}}, 5311{"efsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, 5312{"evsctui", VX (4, 724), VX_MASK, PPCEFS, 0, {RS, RB}}, 5313{"efscth", VX_RA_CONST(4, 725, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 5314{"efsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, 5315{"evsctsi", VX (4, 725), VX_MASK, PPCEFS, 0, {RS, RB}}, 5316{"efsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, 5317{"evsctuf", VX (4, 726), VX_MASK, PPCEFS, 0, {RS, RB}}, 5318{"efsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, 5319{"evsctsf", VX (4, 727), VX_MASK, PPCEFS, 0, {RS, RB}}, 5320{"efsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, 5321{"evsctuiz", VX (4, 728), VX_MASK, PPCEFS, 0, {RS, RB}}, 5322{"nput", APU(4, 364,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 5323{"efsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, 5324{"evsctsiz", VX (4, 730), VX_MASK, PPCEFS, 0, {RS, RB}}, 5325{"efststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5326{"evststgt", VX (4, 732), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5327{"efststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5328{"evststlt", VX (4, 733), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5329{"efststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5330{"evststeq", VX (4, 734), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5331{"efdadd", VX (4, 736), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5332{"efdsub", VX (4, 737), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5333{"efdmadd", VX (4, 738), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, 5334{"efdcfuid", VX (4, 738), VX_MASK, E500|E500MC,0, {RS, RB}}, 5335{"efdmsub", VX (4, 739), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, 5336{"efdcfsid", VX (4, 739), VX_MASK, E500|E500MC,0, {RS, RB}}, 5337{"efdabs", VX (4, 740), VX_MASK, PPCEFS, 0, {RS, RA}}, 5338{"efdnabs", VX (4, 741), VX_MASK, PPCEFS, 0, {RS, RA}}, 5339{"efdneg", VX (4, 742), VX_MASK, PPCEFS, 0, {RS, RA}}, 5340{"efdsqrt", VX_RB_CONST(4, 743, 0), VX_RB_CONST_MASK, PPCEFS2, 0, {RD, RA}}, 5341{"efdmul", VX (4, 744), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5342{"efddiv", VX (4, 745), VX_MASK, PPCEFS, 0, {RS, RA, RB}}, 5343{"efdnmadd", VX (4, 746), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, 5344{"efdctuidz", VX (4, 746), VX_MASK, E500|E500MC,0, {RS, RB}}, 5345{"efdnmsub", VX (4, 747), VX_MASK, PPCEFS2, E500|E500MC, {RD, RA, RB}}, 5346{"efdctsidz", VX (4, 747), VX_MASK, E500|E500MC,0, {RS, RB}}, 5347{"efdcmpgt", VX (4, 748), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5348{"efdcmplt", VX (4, 749), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5349{"efdcmpeq", VX (4, 750), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5350{"efdcfs", VX (4, 751), VX_MASK, PPCEFS, 0, {RS, RB}}, 5351{"efdcfui", VX_RA_CONST(4, 752, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, 5352{"efdcfuid", VX_RA_CONST(4, 752, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, 5353{"efdcfsi", VX_RA_CONST(4, 753, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, 5354{"efdcfsid", VX_RA_CONST(4, 753, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, 5355{"efdcfh", VX_RA_CONST(4, 753, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 5356{"efdcfuf", VX (4, 754), VX_MASK, PPCEFS, 0, {RS, RB}}, 5357{"efdcfsf", VX (4, 755), VX_MASK, PPCEFS, 0, {RS, RB}}, 5358{"efdctui", VX (4, 756), VX_MASK, PPCEFS, 0, {RS, RB}}, 5359{"efdcth", VX_RA_CONST(4, 757, 4), VX_RA_CONST_MASK, PPCEFS2, 0, {RD, RB}}, 5360{"efdctsi", VX (4, 757), VX_MASK, PPCEFS, 0, {RS, RB}}, 5361{"efdctuf", VX (4, 758), VX_MASK, PPCEFS, 0, {RS, RB}}, 5362{"efdctsf", VX (4, 759), VX_MASK, PPCEFS, 0, {RS, RB}}, 5363{"efdctuiz", VX_RA_CONST(4, 760, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, 5364{"efdctuidz", VX_RA_CONST(4, 760, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, 5365{"ncput", APU(4, 380,0), APU_RT_MASK, PPC405, 0, {RA, FSL}}, 5366{"efdctsiz", VX_RA_CONST(4, 762, 0), VX_RA_CONST_MASK, PPCEFS, 0, {RS, RB}}, 5367{"efdctsidz", VX_RA_CONST(4, 762, 1), VX_RA_CONST_MASK, PPCEFS, E500|E500MC, {RS, RB}}, 5368{"efdtstgt", VX (4, 764), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5369{"efdtstlt", VX (4, 765), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5370{"efdtsteq", VX (4, 766), VX_MASK, PPCEFS, 0, {CRFD, RA, RB}}, 5371{"evlddx", VX (4, 768), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5372{"vaddsbs", VX (4, 768), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5373{"evldd", VX (4, 769), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 5374{"evldwx", VX (4, 770), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5375{"vminsb", VX (4, 770), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5376{"evldw", VX (4, 771), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 5377{"evldhx", VX (4, 772), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5378{"vsrab", VX (4, 772), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5379{"vsraq", VX (4, 773), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5380{"evldh", VX (4, 773), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 5381{"vcmpgtsb", VXR(4, 774,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5382{"evlhhesplatx",VX (4, 776), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5383{"vmulesb", VX (4, 776), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5384{"evlhhesplat", VX (4, 777), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 5385{"vcfux", VX (4, 778), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 5386{"vcuxwfp", VX (4, 778), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}}, 5387{"vdivesq", VX (4, 779), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5388{"evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5389{"vspltisb", VX (4, 780), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 5390{"vinsertb", VX (4, 781), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 5391{"evlhhousplat",VX (4, 781), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 5392{"evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5393{"vpkpx", VX (4, 782), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5394{"vinsbrx", VX (4, 783), VX_MASK, POWER10, 0, {VD, RA, RB}}, 5395{"evlhhossplat",VX (4, 783), VX_MASK, PPCSPE, 0, {RS, EVUIMM_2, RA}}, 5396{"mullhwu", XRC(4, 392,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 5397{"evlwhex", VX (4, 784), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5398{"mullhwu.", XRC(4, 392,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 5399{"evlwhe", VX (4, 785), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 5400{"evlwhoux", VX (4, 788), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5401{"evlwhou", VX (4, 789), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 5402{"evlwhosx", VX (4, 790), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5403{"evlwhos", VX (4, 791), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 5404{"maclhwu", XO (4, 396,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 5405{"evlwwsplatx", VX (4, 792), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5406{"maclhwu.", XO (4, 396,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 5407{"evlwwsplat", VX (4, 793), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 5408{"evlwhsplatx", VX (4, 796), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5409{"evlwhsplat", VX (4, 797), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 5410{"evstddx", VX (4, 800), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5411{"evstdd", VX (4, 801), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 5412{"evstdwx", VX (4, 802), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5413{"evstdw", VX (4, 803), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 5414{"evstdhx", VX (4, 804), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5415{"evstdh", VX (4, 805), VX_MASK, PPCSPE, 0, {RS, EVUIMM_8, RA}}, 5416{"evstwhex", VX (4, 816), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5417{"evstwhe", VX (4, 817), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 5418{"evstwhox", VX (4, 820), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5419{"evstwho", VX (4, 821), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 5420{"evstwwex", VX (4, 824), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5421{"evstwwe", VX (4, 825), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 5422{"evstwwox", VX (4, 828), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5423{"evstwwo", VX (4, 829), VX_MASK, PPCSPE, 0, {RS, EVUIMM_4, RA}}, 5424{"vaddshs", VX (4, 832), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5425{"bcdcpsgn.", VX (4, 833), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5426{"vminsh", VX (4, 834), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5427{"vsrah", VX (4, 836), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5428{"vcmpgtsh", VXR(4, 838,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5429{"vmulesh", VX (4, 840), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5430{"vcfsx", VX (4, 842), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 5431{"vcsxwfp", VX (4, 842), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}}, 5432{"vspltish", VX (4, 844), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 5433{"vinserth", VX (4, 845), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 5434{"vupkhpx", VX (4, 846), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5435{"vinshrx", VX (4, 847), VX_MASK, POWER10, 0, {VD, RA, RB}}, 5436{"mullhw", XRC(4, 424,0), X_MASK, MULHW, 0, {RT, RA, RB}}, 5437{"mullhw.", XRC(4, 424,1), X_MASK, MULHW, 0, {RT, RA, RB}}, 5438{"maclhw", XO (4, 428,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 5439{"maclhw.", XO (4, 428,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 5440{"nmaclhw", XO (4, 430,0,0),XO_MASK, MULHW, 0, {RT, RA, RB}}, 5441{"nmaclhw.", XO (4, 430,0,1),XO_MASK, MULHW, 0, {RT, RA, RB}}, 5442{"vaddsws", VX (4, 896), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5443{"vminsw", VX (4, 898), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5444{"vsraw", VX (4, 900), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5445{"vcmpgtsw", VXR(4, 902,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5446{"vcmpgtsq", VXR(4, 903,0), VXR_MASK, POWER10, 0, {VD, VA, VB}}, 5447{"vmulesw", VX (4, 904), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5448{"vmulhsw", VX (4, 905), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5449{"vctuxs", VX (4, 906), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 5450{"vcfpuxws", VX (4, 906), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}}, 5451{"vdivesw", VX (4, 907), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5452{"vspltisw", VX (4, 908), VXVB_MASK, PPCVEC, 0, {VD, SIMM}}, 5453{"vinsertw", VX (4, 909), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 5454{"vinswrx", VX (4, 911), VX_MASK, POWER10, 0, {VD, RA, RB}}, 5455{"maclhwsu", XO (4, 460,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5456{"maclhwsu.", XO (4, 460,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5457{"vminsd", VX (4, 962), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5458{"vsrad", VX (4, 964), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5459{"vcmpbfp", VXR(4, 966,0), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5460{"vcmpgtsd", VXR(4, 967,0), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5461{"vmulesd", VX (4, 968), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5462{"vmulhsd", VX (4, 969), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5463{"vctsxs", VX (4, 970), VX_MASK, PPCVEC, 0, {VD, VB, UIMM}}, 5464{"vcfpsxws", VX (4, 970), VX_MASK, PPCVEC, EXT, {VD, VB, UIMM}}, 5465{"vdivesd", VX (4, 971), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5466{"vinsertd", VX (4, 973), VXUIMM4_MASK, PPCVEC3, 0, {VD, VB, UIMM4}}, 5467{"vupklpx", VX (4, 974), VXVA_MASK, PPCVEC, 0, {VD, VB}}, 5468{"vinsdrx", VX (4, 975), VX_MASK, POWER10, 0, {VD, RA, RB}}, 5469{"maclhws", XO (4, 492,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5470{"maclhws.", XO (4, 492,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5471{"nmaclhws", XO (4, 494,0,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5472{"nmaclhws.", XO (4, 494,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5473{"vsububm", VX (4,1024), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5474{"bcdadd.", VX (4,1025), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, 5475{"vavgub", VX (4,1026), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5476{"vabsdub", VX (4,1027), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5477{"evmhessf", VX (4,1027), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5478{"vand", VX (4,1028), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5479{"vcmpequb.", VXR(4, 6,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5480{"vcmpneb.", VXR(4, 7,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5481{"udi0fcm.", APU(4, 515,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5482{"udi0fcm", APU(4, 515,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5483{"evmhossf", VX (4,1031), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5484{"vpmsumb", VX (4,1032), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5485{"evmheumi", VX (4,1032), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5486{"evmhesmi", VX (4,1033), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5487{"vmaxfp", VX (4,1034), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5488{"evmhesmf", VX (4,1035), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5489{"evmhoumi", VX (4,1036), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5490{"vslo", VX (4,1036), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5491{"vstribl.", VXVA(4,1037,0), VXVA_MASK, POWER10, 0, {VD, VB}}, 5492{"vstribr.", VXVA(4,1037,1), VXVA_MASK, POWER10, 0, {VD, VB}}, 5493{"vstrihl.", VXVA(4,1037,2), VXVA_MASK, POWER10, 0, {VD, VB}}, 5494{"vstrihr.", VXVA(4,1037,3), VXVA_MASK, POWER10, 0, {VD, VB}}, 5495{"evmhosmi", VX (4,1037), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5496{"evmhosmf", VX (4,1039), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5497{"machhwuo", XO (4, 12,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5498{"machhwuo.", XO (4, 12,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5499{"ps_merge00", XOPS(4,528,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 5500{"ps_merge00.", XOPS(4,528,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 5501{"evmhessfa", VX (4,1059), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5502{"evmhossfa", VX (4,1063), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5503{"evmheumia", VX (4,1064), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5504{"evmhesmia", VX (4,1065), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5505{"evmhesmfa", VX (4,1067), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5506{"evmhoumia", VX (4,1068), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5507{"evmhosmia", VX (4,1069), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5508{"evmhosmfa", VX (4,1071), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5509{"vsubuhm", VX (4,1088), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5510{"bcdsub.", VX (4,1089), VXPS_MASK, PPCVEC2, 0, {VD, VA, VB, PS}}, 5511{"vavguh", VX (4,1090), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5512{"evmwlssf", VX (4,1091), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5513{"vabsduh", VX (4,1091), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5514{"vandc", VX (4,1092), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5515{"vcmpequh.", VXR(4, 70,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5516{"udi1fcm.", APU(4, 547,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5517{"udi1fcm", APU(4, 547,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5518{"vcmpneh.", VXR(4, 71,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5519{"evmwhssf", VX (4,1095), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5520{"vpmsumh", VX (4,1096), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5521{"evmwlumi", VX (4,1096), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5522{"vminfp", VX (4,1098), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5523{"evmwlsmf", VX (4,1099), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5524{"evmwhumi", VX (4,1100), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5525{"vsro", VX (4,1100), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5526{"evmwhsmi", VX (4,1101), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5527{"vpkudum", VX (4,1102), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5528{"evmwhsmf", VX (4,1103), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5529{"evmwssf", VX (4,1107), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5530{"machhwo", XO (4, 44,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5531{"evmwumi", VX (4,1112), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5532{"machhwo.", XO (4, 44,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5533{"evmwsmi", VX (4,1113), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5534{"evmwsmf", VX (4,1115), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5535{"nmachhwo", XO (4, 46,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5536{"nmachhwo.", XO (4, 46,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5537{"ps_merge01", XOPS(4,560,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 5538{"ps_merge01.", XOPS(4,560,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 5539{"evmwlssfa", VX (4,1123), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5540{"evmwhssfa", VX (4,1127), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5541{"evmwlumia", VX (4,1128), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5542{"evmwlsmfa", VX (4,1131), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5543{"evmwhumia", VX (4,1132), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5544{"evmwhsmia", VX (4,1133), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5545{"evmwhsmfa", VX (4,1135), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5546{"evmwssfa", VX (4,1139), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5547{"evmwumia", VX (4,1144), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5548{"evmwsmia", VX (4,1145), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5549{"evmwsmfa", VX (4,1147), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5550{"vsubuwm", VX (4,1152), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5551{"bcdus.", VX (4,1153), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5552{"vavguw", VX (4,1154), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5553{"vabsduw", VX (4,1155), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5554{"vmr", VX (4,1156), VX_MASK, PPCVEC, EXT, {VD, VAB}}, 5555{"vor", VX (4,1156), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5556{"vcmpnew.", VXR(4, 135,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5557{"vpmsumw", VX (4,1160), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5558{"vcmpequw.", VXR(4, 134,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5559{"udi2fcm.", APU(4, 579,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5560{"udi2fcm", APU(4, 579,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5561{"machhwsuo", XO (4, 76,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5562{"machhwsuo.", XO (4, 76,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5563{"ps_merge10", XOPS(4,592,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 5564{"ps_merge10.", XOPS(4,592,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 5565{"vsubudm", VX (4,1216), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5566{"evaddusiaaw", VX (4,1216), VX_MASK, PPCSPE, 0, {RS, RA}}, 5567{"bcds.", VX (4,1217), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 5568{"evaddssiaaw", VX (4,1217), VX_MASK, PPCSPE, 0, {RS, RA}}, 5569{"evsubfusiaaw",VX (4,1218), VX_MASK, PPCSPE, 0, {RS, RA}}, 5570{"evsubfssiaaw",VX (4,1219), VX_MASK, PPCSPE, 0, {RS, RA}}, 5571{"evmra", VX (4,1220), VX_MASK, PPCSPE, 0, {RS, RA}}, 5572{"vxor", VX (4,1220), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5573{"evdivws", VX (4,1222), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5574{"vcmpeqfp.", VXR(4, 198,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5575{"udi3fcm.", APU(4, 611,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5576{"vcmpequd.", VXR(4, 199,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5577{"udi3fcm", APU(4, 611,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5578{"evdivwu", VX (4,1223), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5579{"vpmsumd", VX (4,1224), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5580{"evaddumiaaw", VX (4,1224), VX_MASK, PPCSPE, 0, {RS, RA}}, 5581{"evaddsmiaaw", VX (4,1225), VX_MASK, PPCSPE, 0, {RS, RA}}, 5582{"evsubfumiaaw",VX (4,1226), VX_MASK, PPCSPE, 0, {RS, RA}}, 5583{"evsubfsmiaaw",VX (4,1227), VX_MASK, PPCSPE, 0, {RS, RA}}, 5584{"vgnb", VX (4,1228), VX_MASK, POWER10, 0, {RT, VB, UIMM3}}, 5585{"vpkudus", VX (4,1230), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5586{"machhwso", XO (4, 108,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5587{"machhwso.", XO (4, 108,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5588{"nmachhwso", XO (4, 110,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5589{"nmachhwso.", XO (4, 110,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5590{"ps_merge11", XOPS(4,624,0), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 5591{"ps_merge11.", XOPS(4,624,1), XOPS_MASK, PPCPS, 0, {FRT, FRA, FRB}}, 5592{"vsubuqm", VX (4,1280), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5593{"evmheusiaaw", VX (4,1280), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5594{"bcdtrunc.", VX (4,1281), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 5595{"evmhessiaaw", VX (4,1281), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5596{"vavgsb", VX (4,1282), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5597{"evmhessfaaw", VX (4,1283), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5598{"evmhousiaaw", VX (4,1284), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5599{"vnot", VX (4,1284), VX_MASK, PPCVEC, EXT, {VD, VAB}}, 5600{"vnor", VX (4,1284), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5601{"evmhossiaaw", VX (4,1285), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5602{"udi4fcm.", APU(4, 643,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5603{"udi4fcm", APU(4, 643,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5604{"vcmpnezb.", VXR(4, 263,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5605{"evmhossfaaw", VX (4,1287), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5606{"evmheumiaaw", VX (4,1288), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5607{"vcipher", VX (4,1288), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5608{"vcipherlast", VX (4,1289), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5609{"evmhesmiaaw", VX (4,1289), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5610{"evmhesmfaaw", VX (4,1291), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5611{"vgbbd", VX (4,1292), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5612{"evmhoumiaaw", VX (4,1292), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5613{"evmhosmiaaw", VX (4,1293), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5614{"evmhosmfaaw", VX (4,1295), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5615{"macchwuo", XO (4, 140,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5616{"macchwuo.", XO (4, 140,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5617{"evmhegumiaa", VX (4,1320), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5618{"evmhegsmiaa", VX (4,1321), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5619{"evmhegsmfaa", VX (4,1323), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5620{"evmhogumiaa", VX (4,1324), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5621{"evmhogsmiaa", VX (4,1325), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5622{"evmhogsmfaa", VX (4,1327), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5623{"vsubcuq", VX (4,1344), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5624{"evmwlusiaaw", VX (4,1344), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5625{"bcdutrunc.", VX (4,1345), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5626{"evmwlssiaaw", VX (4,1345), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5627{"vavgsh", VX (4,1346), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5628{"evmwlssfaaw", VX (4,1347), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5629{"evmwhusiaa", VX (4,1348), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5630{"vorc", VX (4,1348), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5631{"evmwhssmaa", VX (4,1349), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5632{"udi5fcm.", APU(4, 675,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5633{"udi5fcm", APU(4, 675,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5634{"vcmpnezh.", VXR(4, 327,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5635{"evmwhssfaa", VX (4,1351), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5636{"vncipher", VX (4,1352), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5637{"evmwlumiaaw", VX (4,1352), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5638{"vncipherlast",VX (4,1353), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5639{"evmwlsmiaaw", VX (4,1353), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5640{"evmwlsmfaaw", VX (4,1355), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5641{"evmwhumiaa", VX (4,1356), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5642{"vbpermq", VX (4,1356), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5643{"vcfuged", VX (4,1357), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5644{"evmwhsmiaa", VX (4,1357), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5645{"vpksdus", VX (4,1358), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5646{"evmwhsmfaa", VX (4,1359), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5647{"evmwssfaa", VX (4,1363), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5648{"macchwo", XO (4, 172,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5649{"evmwumiaa", VX (4,1368), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5650{"macchwo.", XO (4, 172,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5651{"evmwsmiaa", VX (4,1369), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5652{"evmwsmfaa", VX (4,1371), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5653{"nmacchwo", XO (4, 174,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5654{"nmacchwo.", XO (4, 174,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5655{"evmwhgumiaa", VX (4,1380), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5656{"evmwhgsmiaa", VX (4,1381), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5657{"evmwhgssfaa", VX (4,1383), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5658{"evmwhgsmfaa", VX (4,1391), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5659{"evmheusianw", VX (4,1408), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5660{"vsubcuw", VX (4,1408), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5661{"evmhessianw", VX (4,1409), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5662{"bcdctsq.", VXVA(4,1409,0), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5663{"bcdcfsq.", VXVA(4,1409,2), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 5664{"bcdctz.", VXVA(4,1409,4), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 5665{"bcdctn.", VXVA(4,1409,5), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5666{"bcdcfz.", VXVA(4,1409,6), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 5667{"bcdcfn.", VXVA(4,1409,7), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 5668{"bcdsetsgn.", VXVA(4,1409,31), VXVAPS_MASK, PPCVEC3, 0, {VD, VB, PS}}, 5669{"vavgsw", VX (4,1410), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5670{"evmhessfanw", VX (4,1411), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5671{"vnand", VX (4,1412), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5672{"evmhousianw", VX (4,1412), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5673{"evmhossianw", VX (4,1413), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5674{"udi6fcm.", APU(4, 707,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5675{"udi6fcm", APU(4, 707,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5676{"vcmpnezw.", VXR(4, 391,1), VXR_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5677{"evmhossfanw", VX (4,1415), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5678{"evmheumianw", VX (4,1416), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5679{"evmhesmianw", VX (4,1417), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5680{"evmhesmfanw", VX (4,1419), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5681{"evmhoumianw", VX (4,1420), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5682{"vpextd", VX (4,1421), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5683{"evmhosmianw", VX (4,1421), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5684{"evmhosmfanw", VX (4,1423), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5685{"macchwsuo", XO (4, 204,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5686{"macchwsuo.", XO (4, 204,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5687{"evmhegumian", VX (4,1448), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5688{"evmhegsmian", VX (4,1449), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5689{"evmhegsmfan", VX (4,1451), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5690{"evmhogumian", VX (4,1452), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5691{"evmhogsmian", VX (4,1453), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5692{"evmhogsmfan", VX (4,1455), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5693{"evmwlusianw", VX (4,1472), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5694{"bcdsr.", VX (4,1473), VXPS_MASK, PPCVEC3, 0, {VD, VA, VB, PS}}, 5695{"evmwlssianw", VX (4,1473), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5696{"evmwlssfanw", VX (4,1475), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5697{"evmwhusian", VX (4,1476), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5698{"vsld", VX (4,1476), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5699{"evmwhssian", VX (4,1477), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5700{"vcmpgefp.", VXR(4, 454,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5701{"udi7fcm.", APU(4, 739,0), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5702{"udi7fcm", APU(4, 739,1), APU_MASK, PPC405|PPC440, 0, {URT, URA, URB}}, 5703{"vcmpequq.", VXR(4, 455,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, 5704{"evmwhssfan", VX (4,1479), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5705{"vsbox", VX (4,1480), VXVB_MASK, PPCVEC2, 0, {VD, VA}}, 5706{"evmwlumianw", VX (4,1480), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5707{"evmwlsmianw", VX (4,1481), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5708{"evmwlsmfanw", VX (4,1483), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5709{"evmwhumian", VX (4,1484), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5710{"vbpermd", VX (4,1484), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5711{"vpdepd", VX (4,1485), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5712{"evmwhsmian", VX (4,1485), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5713{"vpksdss", VX (4,1486), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5714{"evmwhsmfan", VX (4,1487), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5715{"evmwssfan", VX (4,1491), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5716{"macchwso", XO (4, 236,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5717{"evmwumian", VX (4,1496), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5718{"macchwso.", XO (4, 236,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5719{"evmwsmian", VX (4,1497), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5720{"evmwsmfan", VX (4,1499), VX_MASK, PPCSPE, 0, {RS, RA, RB}}, 5721{"evmwhgumian", VX (4,1508), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5722{"evmwhgsmian", VX (4,1509), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5723{"evmwhgssfan", VX (4,1511), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5724{"evmwhgsmfan", VX (4,1519), VX_MASK, PPCSPE, 0, {RD, RA, RB}}, 5725{"nmacchwso", XO (4, 238,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5726{"nmacchwso.", XO (4, 238,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5727{"vsububs", VX (4,1536), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5728{"vclzlsbb", VXVA(4,1538,0), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, 5729{"vctzlsbb", VXVA(4,1538,1), VXVA_MASK, PPCVEC3, 0, {RT, VB}}, 5730{"vnegw", VXVA(4,1538,6), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5731{"vnegd", VXVA(4,1538,7), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5732{"vprtybw", VXVA(4,1538,8), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5733{"vprtybd", VXVA(4,1538,9), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5734{"vprtybq", VXVA(4,1538,10), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5735{"vextsb2w", VXVA(4,1538,16), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5736{"vextsh2w", VXVA(4,1538,17), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5737{"vextsb2d", VXVA(4,1538,24), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5738{"vextsh2d", VXVA(4,1538,25), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5739{"vextsw2d", VXVA(4,1538,26), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5740{"vextsd2q", VXVA(4,1538,27), VXVA_MASK, POWER10, 0, {VD, VB}}, 5741{"vctzb", VXVA(4,1538,28), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5742{"vctzh", VXVA(4,1538,29), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5743{"vctzw", VXVA(4,1538,30), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5744{"vctzd", VXVA(4,1538,31), VXVA_MASK, PPCVEC3, 0, {VD, VB}}, 5745{"mfvscr", VX (4,1540), VXVAVB_MASK, PPCVEC, 0, {VD}}, 5746{"vcmpgtub.", VXR(4, 518,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5747{"udi8fcm.", APU(4, 771,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5748{"udi8fcm", APU(4, 771,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5749{"vsum4ubs", VX (4,1544), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5750{"vmoduq", VX (4,1547), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5751{"vextublx", VX (4,1549), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 5752{"vsubuhs", VX (4,1600), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5753 5754{"vexpandbm", VXVA(4,1602,0), VXVA_MASK, POWER10, 0, {VD, VB}}, 5755{"vexpandhm", VXVA(4,1602,1), VXVA_MASK, POWER10, 0, {VD, VB}}, 5756{"vexpandwm", VXVA(4,1602,2), VXVA_MASK, POWER10, 0, {VD, VB}}, 5757{"vexpanddm", VXVA(4,1602,3), VXVA_MASK, POWER10, 0, {VD, VB}}, 5758{"vexpandqm", VXVA(4,1602,4), VXVA_MASK, POWER10, 0, {VD, VB}}, 5759{"vextractbm", VXVA(4,1602,8), VXVA_MASK, POWER10, 0, {RT, VB}}, 5760{"vextracthm", VXVA(4,1602,9), VXVA_MASK, POWER10, 0, {RT, VB}}, 5761{"vextractwm", VXVA(4,1602,10), VXVA_MASK, POWER10, 0, {RT, VB}}, 5762{"vextractdm", VXVA(4,1602,11), VXVA_MASK, POWER10, 0, {RT, VB}}, 5763{"vextractqm", VXVA(4,1602,12), VXVA_MASK, POWER10, 0, {RT, VB}}, 5764{"mtvsrbm", VXVA(4,1602,16), VXVA_MASK, POWER10, 0, {VD, RB}}, 5765{"mtvsrhm", VXVA(4,1602,17), VXVA_MASK, POWER10, 0, {VD, RB}}, 5766{"mtvsrwm", VXVA(4,1602,18), VXVA_MASK, POWER10, 0, {VD, RB}}, 5767{"mtvsrdm", VXVA(4,1602,19), VXVA_MASK, POWER10, 0, {VD, RB}}, 5768{"mtvsrqm", VXVA(4,1602,20), VXVA_MASK, POWER10, 0, {VD, RB}}, 5769{"vcntmbb", VXVA(4,1602,24), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, 5770{"vcntmbh", VXVA(4,1602,26), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, 5771{"vcntmbw", VXVA(4,1602,28), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, 5772{"vcntmbd", VXVA(4,1602,30), VXVAM_MASK, POWER10, 0, {RT, VB, MP}}, 5773 5774{"mtvscr", VX (4,1604), VXVDVA_MASK, PPCVEC, 0, {VB}}, 5775{"vcmpgtuh.", VXR(4, 582,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5776{"vsum4shs", VX (4,1608), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5777{"udi9fcm.", APU(4, 804,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5778{"udi9fcm", APU(4, 804,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5779{"vextuhlx", VX (4,1613), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 5780{"vupkhsw", VX (4,1614), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5781{"vsubuws", VX (4,1664), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5782{"vshasigmaw", VX (4,1666), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, 5783{"veqv", VX (4,1668), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5784{"vcmpgtuw.", VXR(4, 646,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5785{"udi10fcm.", APU(4, 835,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5786{"vcmpgtuq.", VXR(4, 647,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, 5787{"udi10fcm", APU(4, 835,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5788{"vsum2sws", VX (4,1672), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5789{"vmoduw", VX (4,1675), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5790{"vmrgow", VX (4,1676), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5791{"vextuwlx", VX (4,1677), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 5792{"vshasigmad", VX (4,1730), VX_MASK, PPCVEC2, 0, {VD, VA, ST, SIX}}, 5793{"vsrd", VX (4,1732), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5794{"vcmpgtfp.", VXR(4, 710,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5795{"udi11fcm.", APU(4, 867,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5796{"vcmpgtud.", VXR(4, 711,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5797{"udi11fcm", APU(4, 867,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5798{"vmodud", VX (4,1739), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5799{"vupklsw", VX (4,1742), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5800{"vsubsbs", VX (4,1792), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5801{"vclzb", VX (4,1794), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5802{"vpopcntb", VX (4,1795), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5803{"vsrv", VX (4,1796), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5804{"vcmpgtsb.", VXR(4, 774,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5805{"udi12fcm.", APU(4, 899,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5806{"udi12fcm", APU(4, 899,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5807{"vsum4sbs", VX (4,1800), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5808{"vmodsq", VX (4,1803), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5809{"vextubrx", VX (4,1805), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 5810{"maclhwuo", XO (4, 396,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5811{"maclhwuo.", XO (4, 396,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5812{"vsubshs", VX (4,1856), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5813{"vclzh", VX (4,1858), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5814{"vpopcnth", VX (4,1859), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5815{"vslv", VX (4,1860), VX_MASK, PPCVEC3, 0, {VD, VA, VB}}, 5816{"vcmpgtsh.", VXR(4, 838,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5817{"vextuhrx", VX (4,1869), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 5818{"udi13fcm.", APU(4, 931,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5819{"udi13fcm", APU(4, 931,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5820{"maclhwo", XO (4, 428,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5821{"maclhwo.", XO (4, 428,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5822{"nmaclhwo", XO (4, 430,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5823{"nmaclhwo.", XO (4, 430,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5824{"vsubsws", VX (4,1920), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5825{"vclzw", VX (4,1922), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5826{"vpopcntw", VX (4,1923), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5827{"vclzdm", VX (4,1924), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5828{"vcmpgtsw.", VXR(4, 902,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5829{"udi14fcm.", APU(4, 963,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5830{"vcmpgtsq.", VXR(4, 903,1), VXR_MASK, POWER10, 0, {VD, VA, VB}}, 5831{"udi14fcm", APU(4, 963,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5832{"vsumsws", VX (4,1928), VX_MASK, PPCVEC, 0, {VD, VA, VB}}, 5833{"vmodsw", VX (4,1931), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5834{"vmrgew", VX (4,1932), VX_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5835{"vextuwrx", VX (4,1933), VX_MASK, PPCVEC3, 0, {RT, RA, VB}}, 5836{"maclhwsuo", XO (4, 460,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5837{"maclhwsuo.", XO (4, 460,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5838{"vclzd", VX (4,1986), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5839{"vpopcntd", VX (4,1987), VXVA_MASK, PPCVEC2, 0, {VD, VB}}, 5840{"vctzdm", VX (4,1988), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5841{"vcmpbfp.", VXR(4, 966,1), VXR_MASK, PPCVEC, 0, {VD, VA, VB}}, 5842{"udi15fcm.", APU(4, 995,0), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5843{"vcmpgtsd.", VXR(4, 967,1), VXR_MASK, PPCVEC2, 0, {VD, VA, VB}}, 5844{"udi15fcm", APU(4, 995,1), APU_MASK, PPC440, 0, {URT, URA, URB}}, 5845{"vmodsd", VX (4,1995), VX_MASK, POWER10, 0, {VD, VA, VB}}, 5846{"maclhwso", XO (4, 492,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5847{"maclhwso.", XO (4, 492,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5848{"nmaclhwso", XO (4, 494,1,0), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5849{"nmaclhwso.", XO (4, 494,1,1), XO_MASK, MULHW, 0, {RT, RA, RB}}, 5850{"dcbz_l", X (4,1014), XRT_MASK, PPCPS, 0, {RA, RB}}, 5851 5852{"lxvp", DQXP(6,0), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}}, 5853{"stxvp", DQXP(6,1), DQXP_MASK, POWER10, PPCVLE, {XTP, DQ, RA0}}, 5854 5855{"mulli", OP(7), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 5856{"muli", OP(7), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 5857 5858{"subfic", OP(8), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 5859{"sfi", OP(8), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 5860 5861{"dozi", OP(9), OP_MASK, M601, PPCVLE, {RT, RA, SI}}, 5862 5863{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE|EXT, {OBF, RA, UISIGNOPT}}, 5864{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE|EXT, {OBF, RA, UISIGNOPT}}, 5865{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}}, 5866{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}}, 5867 5868{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE|EXT, {OBF, RA, SI}}, 5869{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE|EXT, {OBF, RA, SI}}, 5870{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}}, 5871{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}}, 5872 5873{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 5874{"ai", OP(12), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 5875{"subic", OP(12), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, RA, NSI}}, 5876 5877{"addic.", OP(13), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}}, 5878{"ai.", OP(13), OP_MASK, PWRCOM, PPCVLE, {RT, RA, SI}}, 5879{"subic.", OP(13), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, RA, NSI}}, 5880 5881{"li", OP(14), DRA_MASK, PPCCOM, PPCVLE|EXT, {RT, SI}}, 5882{"lil", OP(14), DRA_MASK, PWRCOM, PPCVLE|EXT, {RT, SI}}, 5883{"addi", OP(14), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SI}}, 5884{"cal", OP(14), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 5885{"subi", OP(14), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, RA0, NSI}}, 5886{"la", OP(14), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, D, RA0}}, 5887 5888{"lis", OP(15), DRA_MASK, PPCCOM, PPCVLE|EXT, {RT, SISIGNOPT}}, 5889{"liu", OP(15), DRA_MASK, PWRCOM, PPCVLE|EXT, {RT, SISIGNOPT}}, 5890{"addis", OP(15), OP_MASK, PPCCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, 5891{"cau", OP(15), OP_MASK, PWRCOM, PPCVLE, {RT, RA0, SISIGNOPT}}, 5892{"subis", OP(15), OP_MASK, PPCCOM, PPCVLE|EXT, {RT, RA0, NSISIGNOPT}}, 5893 5894{"bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDM}}, 5895{"bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDP}}, 5896{"bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BD}}, 5897{"bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, PPCVLE|EXT, {BD}}, 5898{"bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDM}}, 5899{"bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDP}}, 5900{"bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BD}}, 5901{"bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, PPCVLE|EXT, {BD}}, 5902{"bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDMA}}, 5903{"bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDPA}}, 5904{"bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDA}}, 5905{"bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, PPCVLE|EXT, {BDA}}, 5906{"bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDMA}}, 5907{"bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDPA}}, 5908{"bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDA}}, 5909{"bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, PPCVLE|EXT, {BDA}}, 5910{"bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDM}}, 5911{"bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDP}}, 5912{"bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, PPCVLE|EXT, {BD}}, 5913{"bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDM}}, 5914{"bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDP}}, 5915{"bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, PPCVLE|EXT, {BD}}, 5916{"bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDMA}}, 5917{"bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDPA}}, 5918{"bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, PPCVLE|EXT, {BDA}}, 5919{"bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDMA}}, 5920{"bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, PPCVLE|EXT, {BDPA}}, 5921{"bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, PPCVLE|EXT, {BDA}}, 5922 5923{"bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5924{"bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5925{"bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5926{"bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5927{"bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5928{"bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5929{"bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5930{"bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5931{"bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5932{"bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5933{"bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5934{"bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5935{"bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5936{"bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5937{"bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5938{"bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5939{"bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5940{"bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5941{"bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5942{"bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5943{"bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5944{"bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5945{"bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5946{"bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5947{"ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5948{"ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5949{"ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5950{"bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5951{"bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5952{"bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5953{"blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5954{"blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5955{"blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5956{"bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5957{"bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5958{"bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5959{"blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5960{"blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5961{"blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5962{"bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5963{"bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5964{"bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5965{"blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5966{"blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5967{"blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5968{"bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5969{"bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5970{"bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5971{"bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5972{"bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5973{"bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5974{"bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5975{"bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5976{"bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5977{"bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5978{"bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5979{"bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5980{"bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5981{"bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5982{"bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5983{"bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5984{"bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5985{"bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5986{"bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5987{"bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5988{"bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BD}}, 5989{"bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5990{"bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5991{"bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 5992{"bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 5993{"bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 5994{"bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BD}}, 5995{"bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5996{"bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 5997{"bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 5998{"bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 5999{"bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6000{"bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDA}}, 6001{"bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6002{"bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6003{"bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 6004{"bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6005{"bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6006{"bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDA}}, 6007 6008{"blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6009{"blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6010{"blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 6011{"bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6012{"bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6013{"bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 6014{"blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6015{"blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6016{"blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 6017{"bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6018{"bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6019{"bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 6020{"bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6021{"bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6022{"bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 6023{"bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6024{"bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6025{"bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 6026{"bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6027{"bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6028{"bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 6029{"bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6030{"bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6031{"bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 6032{"beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6033{"beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6034{"beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 6035{"beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6036{"beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6037{"beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 6038{"beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6039{"beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6040{"beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 6041{"beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6042{"beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6043{"beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 6044{"bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6045{"bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6046{"bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 6047{"bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6048{"bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6049{"bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BD}}, 6050{"bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6051{"bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6052{"bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BD}}, 6053{"bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDM}}, 6054{"bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDP}}, 6055{"bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BD}}, 6056{"bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6057{"bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6058{"bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 6059{"buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6060{"buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6061{"buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDA}}, 6062{"bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6063{"bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6064{"bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, PPCVLE|EXT, {CR, BDA}}, 6065{"bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDMA}}, 6066{"bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDPA}}, 6067{"bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, PPCVLE|EXT, {CR, BDA}}, 6068 6069{"bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}}, 6070{"bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}}, 6071{"bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6072{"bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}}, 6073{"bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}}, 6074{"bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6075{"bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}}, 6076{"bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}}, 6077{"bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6078{"bdnzfla-", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}}, 6079{"bdnzfla+", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}}, 6080{"bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6081{"bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}}, 6082{"bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}}, 6083{"bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6084{"bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}}, 6085{"bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}}, 6086{"bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6087{"bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}}, 6088{"bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}}, 6089{"bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6090{"bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}}, 6091{"bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}}, 6092{"bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6093 6094{"bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDM}}, 6095{"bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDP}}, 6096{"bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6097{"bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BD}}, 6098{"bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDM}}, 6099{"bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDP}}, 6100{"bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6101{"bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BD}}, 6102{"bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDMA}}, 6103{"bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDPA}}, 6104{"bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6105{"bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BDA}}, 6106{"bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDMA}}, 6107{"bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDPA}}, 6108{"bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6109{"bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BDA}}, 6110 6111{"bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}}, 6112{"bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}}, 6113{"bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6114{"bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}}, 6115{"bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}}, 6116{"bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6117{"bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}}, 6118{"bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}}, 6119{"bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6120{"bdnztla-", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}}, 6121{"bdnztla+", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}}, 6122{"bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6123{"bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}}, 6124{"bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}}, 6125{"bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6126{"bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDM}}, 6127{"bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDP}}, 6128{"bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6129{"bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}}, 6130{"bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}}, 6131{"bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6132{"bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDMA}}, 6133{"bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BDPA}}, 6134{"bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6135 6136{"bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDM}}, 6137{"bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDP}}, 6138{"bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6139{"bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BD}}, 6140{"btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDM}}, 6141{"btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDP}}, 6142{"btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BD}}, 6143{"bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BD}}, 6144{"bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDMA}}, 6145{"bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDPA}}, 6146{"bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6147{"bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BDA}}, 6148{"btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDMA}}, 6149{"btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDPA}}, 6150{"btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, PPCVLE|EXT, {BI, BDA}}, 6151{"bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, PPCVLE|EXT, {BI, BDA}}, 6152 6153{"bc-", B(16,0,0), B_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BDM}}, 6154{"bc+", B(16,0,0), B_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BDP}}, 6155{"bc", B(16,0,0), B_MASK, COM, PPCVLE, {BO, BI, BD}}, 6156{"bcl-", B(16,0,1), B_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BDM}}, 6157{"bcl+", B(16,0,1), B_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BDP}}, 6158{"bcl", B(16,0,1), B_MASK, COM, PPCVLE, {BO, BI, BD}}, 6159{"bca-", B(16,1,0), B_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BDMA}}, 6160{"bca+", B(16,1,0), B_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BDPA}}, 6161{"bca", B(16,1,0), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, 6162{"bcla-", B(16,1,1), B_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BDMA}}, 6163{"bcla+", B(16,1,1), B_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BDPA}}, 6164{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}}, 6165 6166{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, 6167{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}}, 6168{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}}, 6169{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}}, 6170{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}}, 6171{"svcla", SC(17,1,1), SC_MASK, POWER, PPCVLE, {SV}}, 6172 6173{"b", B(18,0,0), B_MASK, COM, PPCVLE, {LI}}, 6174{"bl", B(18,0,1), B_MASK, COM, PPCVLE, {LI}}, 6175{"ba", B(18,1,0), B_MASK, COM, PPCVLE, {LIA}}, 6176{"bla", B(18,1,1), B_MASK, COM, PPCVLE, {LIA}}, 6177 6178{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, 6179 6180{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE|EXT, {RT}}, 6181{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}}, 6182{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE|EXT, {RT, NDXD}}, 6183 6184{"bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, 6185{"bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, 6186{"bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}}, 6187{"bdnzlrl-", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, 6188{"bdnzlrl+", XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, 6189{"bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}}, 6190{"bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, 6191{"bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, 6192{"bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}}, 6193{"bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, 6194{"bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BH}}, 6195{"bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}}, 6196{"blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}}, 6197{"br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, PPCVLE|EXT, {BH}}, 6198{"blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, PPCVLE|EXT, {BH}}, 6199{"brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, PPCVLE|EXT, {BH}}, 6200{"bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}}, 6201{"bdnzlrl-", XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}}, 6202{"bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}}, 6203{"bdnzlrl+", XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}}, 6204{"bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}}, 6205{"bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}}, 6206{"bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}}, 6207{"bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, ISA_V2, PPCVLE|EXT, {BH}}, 6208 6209{"bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6210{"bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6211{"bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6212{"bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6213{"bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6214{"bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6215{"bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6216{"bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6217{"bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6218{"bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6219{"bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6220{"bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6221{"bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6222{"bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6223{"bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6224{"bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6225{"blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6226{"blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6227{"blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6228{"bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6229{"bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6230{"bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6231{"bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6232{"bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6233{"blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6234{"blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6235{"blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6236{"blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6237{"bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6238{"bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6239{"bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6240{"bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6241{"bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6242{"bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6243{"bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6244{"bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6245{"bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6246{"bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6247{"bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6248{"bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6249{"bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6250{"bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6251{"bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6252{"bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6253{"bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6254{"bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6255{"bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6256{"bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6257{"bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6258{"bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6259{"bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6260{"bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6261{"bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6262{"bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6263{"bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6264{"bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6265{"bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6266{"bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6267{"blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6268{"bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6269{"blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6270{"bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6271{"bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6272{"bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6273{"bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6274{"bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6275{"bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6276{"bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6277{"bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6278{"bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6279{"bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6280{"bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6281{"blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6282{"bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6283{"blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6284{"bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6285{"bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6286{"bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6287{"bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6288{"bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6289{"bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6290{"bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6291{"bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6292{"bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6293{"bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6294{"bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6295{"bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6296{"bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6297{"bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6298{"bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6299{"bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6300{"bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6301{"bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6302{"bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6303{"bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6304{"bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6305{"bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6306{"bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6307{"beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6308{"beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6309{"beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6310{"beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6311{"beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6312{"beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6313{"beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6314{"beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6315{"bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6316{"bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6317{"bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6318{"bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6319{"bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6320{"bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6321{"bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6322{"bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6323{"bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6324{"bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6325{"bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, PPCVLE|EXT, {CR, BH}}, 6326{"bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6327{"bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6328{"bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6329{"bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6330{"bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6331{"bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6332{"bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6333{"beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6334{"beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6335{"bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6336{"bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6337{"bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6338{"bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6339{"bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6340{"bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6341{"bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6342{"bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6343{"beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6344{"beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6345{"bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6346{"bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6347{"bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6348{"bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6349 6350{"bdnzflr-", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6351{"bdnzflr+", XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6352{"bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6353{"bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6354{"bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6355{"bdnzflrl", XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6356{"bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6357{"bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6358{"bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6359{"bdzflrl-", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6360{"bdzflrl+", XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6361{"bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6362{"bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6363{"bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6364{"bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6365{"bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, PPCVLE|EXT, {BI, BH}}, 6366{"bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6367{"bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6368{"bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6369{"bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, PPCVLE|EXT, {BI, BH}}, 6370{"bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6371{"bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6372{"bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6373{"bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6374{"bdnztlr-", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6375{"bdnztlr+", XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6376{"bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6377{"bdnztlrl-", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6378{"bdnztlrl+", XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6379{"bdnztlrl", XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6380{"bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6381{"bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6382{"bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6383{"bdztlrl-", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6384{"bdztlrl+", XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6385{"bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6386{"btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6387{"btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6388{"btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6389{"bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, PPCVLE|EXT, {BI, BH}}, 6390{"btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6391{"btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6392{"btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6393{"bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, PPCVLE|EXT, {BI, BH}}, 6394{"btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6395{"btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6396{"btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6397{"btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6398 6399{"bclr-", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BH}}, 6400{"bclr+", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BH}}, 6401{"bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 6402{"bcr", XLLK(19,16,0), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, 6403{"bclrl-", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BH}}, 6404{"bclrl+", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BH}}, 6405{"bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 6406{"bcrl", XLLK(19,16,1), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, 6407 6408{"rfid", XL(19,18), 0xffffffff, PPC64, PPCVLE, {0}}, 6409 6410{"crnot", XL(19,33), XL_MASK, PPCCOM, PPCVLE|EXT, {BT, BAB}}, 6411{"crnor", XL(19,33), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 6412 6413{"rfmci", X(19,38), 0xffffffff, PPCRFMCI|PPCA2|PPC476, PPCVLE, {0}}, 6414{"rfdi", XL(19,39), 0xffffffff, E500MC, PPCVLE, {0}}, 6415{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}}, 6416{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}}, 6417 6418{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}}, 6419{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}}, 6420 6421{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}}, 6422 6423{"crandc", XL(19,129), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 6424 6425{"rfebb", XL(19,146), XLS_MASK, POWER8, PPCVLE, {SXL}}, 6426 6427{"isync", XL(19,150), 0xffffffff, PPCCOM, PPCVLE, {0}}, 6428{"ics", XL(19,150), 0xffffffff, PWRCOM, PPCVLE, {0}}, 6429 6430{"crclr", XL(19,193), XL_MASK, PPCCOM, PPCVLE|EXT, {BTAB}}, 6431{"crxor", XL(19,193), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 6432 6433{"dnh", X(19,198), X_MASK, E500MC, PPCVLE, {DUI, DUIS}}, 6434 6435{"crnand", XL(19,225), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 6436 6437{"crand", XL(19,257), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 6438 6439{"hrfid", XL(19,274), 0xffffffff, POWER5|CELL, PPC476|PPCVLE, {0}}, 6440 6441{"crset", XL(19,289), XL_MASK, PPCCOM, PPCVLE|EXT, {BTAB}}, 6442{"creqv", XL(19,289), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 6443 6444{"urfid", XL(19,306), 0xffffffff, POWER9, PPCVLE, {0}}, 6445{"stop", XL(19,370), 0xffffffff, POWER9, PPCVLE, {0}}, 6446 6447{"doze", XL(19,402), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 6448 6449{"crorc", XL(19,417), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 6450 6451{"nap", XL(19,434), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 6452 6453{"crmove", XL(19,449), XL_MASK, PPCCOM, PPCVLE|EXT, {BT, BAB}}, 6454{"cror", XL(19,449), XL_MASK, COM, PPCVLE, {BT, BA, BB}}, 6455 6456{"sleep", XL(19,466), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 6457{"rvwinkle", XL(19,498), 0xffffffff, POWER6, POWER9|PPCVLE, {0}}, 6458 6459{"bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, PPCVLE|EXT, {BH}}, 6460{"bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, PPCVLE|EXT, {BH}}, 6461{"bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6462{"bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6463{"bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6464{"bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6465{"bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6466{"bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6467{"bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6468{"bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6469{"bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6470{"bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6471{"bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6472{"bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6473{"blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6474{"blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6475{"blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6476{"bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6477{"bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6478{"bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6479{"blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6480{"blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6481{"blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6482{"bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6483{"bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6484{"bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6485{"bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6486{"bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6487{"bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6488{"bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6489{"bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6490{"bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6491{"bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6492{"bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6493{"bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6494{"bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6495{"bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6496{"bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6497{"bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6498{"bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6499{"bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6500{"bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6501{"bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6502{"bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6503{"bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6504{"bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6505{"bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6506{"bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6507{"blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6508{"bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6509{"blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6510{"bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6511{"bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6512{"bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6513{"bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6514{"bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6515{"bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6516{"bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6517{"bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6518{"bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6519{"bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6520{"bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6521{"blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6522{"bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6523{"blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6524{"bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6525{"bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6526{"bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6527{"bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6528{"bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6529{"bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6530{"bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6531{"bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6532{"bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6533{"bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6534{"bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6535{"bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6536{"bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6537{"bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6538{"bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6539{"bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6540{"bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6541{"bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6542{"bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6543{"beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6544{"beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6545{"beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6546{"beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6547{"beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6548{"beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6549{"bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6550{"bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6551{"bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6552{"bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6553{"bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6554{"bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6555{"bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6556{"bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6557{"bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6558{"bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6559{"bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {CR, BH}}, 6560{"bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, PPCVLE|EXT, {CR, BH}}, 6561{"bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6562{"bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6563{"bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6564{"bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6565{"beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6566{"beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6567{"bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6568{"bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6569{"bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6570{"bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6571{"bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6572{"bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6573{"bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6574{"bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6575{"beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6576{"beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6577{"bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6578{"bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6579{"bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6580{"bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, ISA_V2, PPCVLE|EXT, {CR, BH}}, 6581 6582{"bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6583{"bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6584{"bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6585{"bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6586{"bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6587{"bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6588{"bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6589{"bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6590{"bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6591{"bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6592{"btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6593{"btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6594{"btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6595{"btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6596{"btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, ISA_V2|PPCVLE|EXT, {BI, BH}}, 6597{"btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, PPCVLE|EXT, {BI, BH}}, 6598{"btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6599{"btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6600{"btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6601{"btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, ISA_V2, PPCVLE|EXT, {BI, BH}}, 6602 6603{"bcctr-", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BH}}, 6604{"bcctr+", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BH}}, 6605{"bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 6606{"bcc", XLLK(19,528,0), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, 6607{"bcctrl-", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOM, BI, BH}}, 6608{"bcctrl+", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE|EXT, {BOP, BI, BH}}, 6609{"bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, PPCVLE, {BO, BI, BH}}, 6610{"bccl", XLLK(19,528,1), XLBH_MASK, PWRCOM, PPCVLE, {BO, BI, BH}}, 6611 6612{"bdnztar", XLO(19,BODNZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6613{"bdnztarl", XLO(19,BODNZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6614{"bdztar", XLO(19,BODZ,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6615{"bdztarl", XLO(19,BODZ,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6616{"btar", XLO(19,BOU,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6617{"btarl", XLO(19,BOU,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6618{"bdnztar-", XLO(19,BODNZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6619{"bdnztarl-", XLO(19,BODNZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6620{"bdnztar+", XLO(19,BODNZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6621{"bdnztarl+", XLO(19,BODNZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6622{"bdztar-", XLO(19,BODZM4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6623{"bdztarl-", XLO(19,BODZM4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6624{"bdztar+", XLO(19,BODZP4,560,0), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6625{"bdztarl+", XLO(19,BODZP4,560,1), XLBOBIBB_MASK, POWER8, PPCVLE|EXT, {BH}}, 6626 6627{"bgetar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6628{"bnltar", XLOCB(19,BOF,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6629{"bgetarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6630{"bnltarl", XLOCB(19,BOF,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6631{"bletar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6632{"bngtar", XLOCB(19,BOF,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6633{"bletarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6634{"bngtarl", XLOCB(19,BOF,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6635{"bnetar", XLOCB(19,BOF,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6636{"bnetarl", XLOCB(19,BOF,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6637{"bnstar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6638{"bnutar", XLOCB(19,BOF,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6639{"bnstarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6640{"bnutarl", XLOCB(19,BOF,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6641{"bgetar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6642{"bnltar-", XLOCB(19,BOFM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6643{"bgetarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6644{"bnltarl-",XLOCB(19,BOFM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6645{"bletar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6646{"bngtar-", XLOCB(19,BOFM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6647{"bletarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6648{"bngtarl-",XLOCB(19,BOFM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6649{"bnetar-", XLOCB(19,BOFM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6650{"bnetarl-",XLOCB(19,BOFM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6651{"bnstar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6652{"bnutar-", XLOCB(19,BOFM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6653{"bnstarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6654{"bnutarl-",XLOCB(19,BOFM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6655{"bgetar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6656{"bnltar+", XLOCB(19,BOFP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6657{"bgetarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6658{"bnltarl+",XLOCB(19,BOFP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6659{"bletar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6660{"bngtar+", XLOCB(19,BOFP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6661{"bletarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6662{"bngtarl+",XLOCB(19,BOFP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6663{"bnetar+", XLOCB(19,BOFP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6664{"bnetarl+",XLOCB(19,BOFP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6665{"bnstar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6666{"bnutar+", XLOCB(19,BOFP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6667{"bnstarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6668{"bnutarl+",XLOCB(19,BOFP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6669{"blttar", XLOCB(19,BOT,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6670{"blttarl", XLOCB(19,BOT,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6671{"bgttar", XLOCB(19,BOT,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6672{"bgttarl", XLOCB(19,BOT,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6673{"beqtar", XLOCB(19,BOT,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6674{"beqtarl", XLOCB(19,BOT,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6675{"bsotar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6676{"buntar", XLOCB(19,BOT,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6677{"bsotarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6678{"buntarl", XLOCB(19,BOT,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6679{"blttar-", XLOCB(19,BOTM4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6680{"blttarl-",XLOCB(19,BOTM4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6681{"bgttar-", XLOCB(19,BOTM4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6682{"bgttarl-",XLOCB(19,BOTM4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6683{"beqtar-", XLOCB(19,BOTM4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6684{"beqtarl-",XLOCB(19,BOTM4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6685{"bsotar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6686{"buntar-", XLOCB(19,BOTM4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6687{"bsotarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6688{"buntarl-",XLOCB(19,BOTM4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6689{"blttar+", XLOCB(19,BOTP4,CBLT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6690{"blttarl+",XLOCB(19,BOTP4,CBLT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6691{"bgttar+", XLOCB(19,BOTP4,CBGT,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6692{"bgttarl+",XLOCB(19,BOTP4,CBGT,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6693{"beqtar+", XLOCB(19,BOTP4,CBEQ,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6694{"beqtarl+",XLOCB(19,BOTP4,CBEQ,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6695{"bsotar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6696{"buntar+", XLOCB(19,BOTP4,CBSO,560,0), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6697{"bsotarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6698{"buntarl+",XLOCB(19,BOTP4,CBSO,560,1), XLBOCBBB_MASK, POWER8, PPCVLE|EXT, {CR, BH}}, 6699 6700{"bdnzftar", XLO(19,BODNZF,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6701{"bdnzftarl", XLO(19,BODNZF,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6702{"bdzftar", XLO(19,BODZF,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6703{"bdzftarl", XLO(19,BODZF,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6704 6705{"bftar", XLO(19,BOF,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6706{"bftarl", XLO(19,BOF,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6707{"bftar-", XLO(19,BOFM4,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6708{"bftarl-", XLO(19,BOFM4,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6709{"bftar+", XLO(19,BOFP4,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6710{"bftarl+", XLO(19,BOFP4,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6711 6712{"bdnzttar", XLO(19,BODNZT,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6713{"bdnzttarl", XLO(19,BODNZT,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6714{"bdzttar", XLO(19,BODZT,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6715{"bdzttarl", XLO(19,BODZT,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6716 6717{"bttar", XLO(19,BOT,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6718{"bttarl", XLO(19,BOT,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6719{"bttar-", XLO(19,BOTM4,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6720{"bttarl-", XLO(19,BOTM4,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6721{"bttar+", XLO(19,BOTP4,560,0), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6722{"bttarl+", XLO(19,BOTP4,560,1), XLBOBB_MASK, POWER8, PPCVLE|EXT, {BI, BH}}, 6723 6724{"bctar-", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE|EXT, {BOM, BI, BH}}, 6725{"bctar+", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE|EXT, {BOP, BI, BH}}, 6726{"bctar", XLLK(19,560,0), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, 6727{"bctarl-", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE|EXT, {BOM, BI, BH}}, 6728{"bctarl+", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE|EXT, {BOP, BI, BH}}, 6729{"bctarl", XLLK(19,560,1), XLBH_MASK, POWER8, PPCVLE, {BO, BI, BH}}, 6730 6731{"rlwimi", M(20,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 6732{"inslwi", M(20,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ILWn, ILWb}}, 6733{"insrwi", M(20,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, IRWn, IRWb}}, 6734{"rlimi", M(20,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 6735 6736{"rlwimi.", M(20,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 6737{"inslwi.", M(20,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ILWn, ILWb}}, 6738{"insrwi.", M(20,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, IRWn, IRWb}}, 6739{"rlimi.", M(20,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 6740 6741{"rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SH}}, 6742{"rotrwi", MME(21,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RRWn}}, 6743{"clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, MB}}, 6744{"clrrwi", M(21,0), MSHMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CRWn}}, 6745{"slwi", M(21,0), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SLWn}}, 6746{"srwi", MME(21,31,0), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SRWn}}, 6747{"rlwinm", M(21,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 6748{"extlwi", M(21,0), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ELWn, SH}}, 6749{"extrwi", MME(21,31,0), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ERWn, ERWb}}, 6750{"clrlslwi", M(21,0), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CSLWb, CSLWn}}, 6751{"sli", M(21,0), MMB_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SLWn}}, 6752{"sri", MME(21,31,0), MME_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SRWn}}, 6753{"rlinm", M(21,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 6754{"rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SH}}, 6755{"rotrwi.", MME(21,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RRWn}}, 6756{"clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, MB}}, 6757{"clrrwi.", M(21,1), MSHMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CRWn}}, 6758{"slwi.", M(21,1), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SLWn}}, 6759{"srwi.", MME(21,31,1), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, SRWn}}, 6760{"rlwinm.", M(21,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 6761{"extlwi.", M(21,1), MMB_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ELWn, SH}}, 6762{"extrwi.", MME(21,31,1), MME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, ERWn, ERWb}}, 6763{"clrlslwi.", M(21,1), M_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, CSLWb, CSLWn}}, 6764{"sli.", M(21,1), MMB_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SLWn}}, 6765{"sri.", MME(21,31,1), MME_MASK, PWRCOM, PPCVLE|EXT, {RA, RS, SRWn}}, 6766{"rlinm.", M(21,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, SH, MBE, ME}}, 6767 6768{"rlmi", M(22,0), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, 6769{"rlmi.", M(22,1), M_MASK, M601, PPCVLE, {RA, RS, RB, MBE, ME}}, 6770 6771{"rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}}, 6772{"rlwnm", M(23,0), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 6773{"rlnm", M(23,0), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 6774{"rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, PPCVLE|EXT, {RA, RS, RB}}, 6775{"rlwnm.", M(23,1), M_MASK, PPCCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 6776{"rlnm.", M(23,1), M_MASK, PWRCOM, PPCVLE, {RA, RS, RB, MBE, ME}}, 6777 6778{"nop", OP(24), 0xffffffff, PPCCOM, PPCVLE|EXT, {0}}, 6779{"exser", 0x63ff0000, 0xffffffff, POWER9, PPCVLE|EXT, {0}}, 6780{"ori", OP(24), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 6781{"oril", OP(24), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 6782 6783{"oris", OP(25), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 6784{"oriu", OP(25), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 6785 6786{"xnop", OP(26), 0xffffffff, PPCCOM, PPCVLE|EXT, {0}}, 6787{"xori", OP(26), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 6788{"xoril", OP(26), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 6789 6790{"xoris", OP(27), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 6791{"xoriu", OP(27), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 6792 6793{"andi.", OP(28), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 6794{"andil.", OP(28), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 6795 6796{"andis.", OP(29), OP_MASK, PPCCOM, PPCVLE, {RA, RS, UI}}, 6797{"andiu.", OP(29), OP_MASK, PWRCOM, PPCVLE, {RA, RS, UI}}, 6798 6799{"rotldi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}}, 6800{"rotrdi", MD(30,0,0), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}}, 6801{"clrldi", MD(30,0,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}}, 6802{"srdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}}, 6803{"rldicl", MD(30,0,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 6804{"extrdi", MD(30,0,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}}, 6805{"rotldi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, SH6}}, 6806{"rotrdi.", MD(30,0,1), MDMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RRDn}}, 6807{"clrldi.", MD(30,0,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, MB6}}, 6808{"srdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SRDn}}, 6809{"rldicl.", MD(30,0,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 6810{"extrdi.", MD(30,0,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, ERDn, ERDb}}, 6811 6812{"clrrdi", MD(30,1,0), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}}, 6813{"sldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}}, 6814{"rldicr", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, 6815{"extldi", MD(30,1,0), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}}, 6816{"clrrdi.", MD(30,1,1), MDSH_MASK, PPC64, PPCVLE|EXT, {RA, RS, CRDn}}, 6817{"sldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, SLDn}}, 6818{"rldicr.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, ME6}}, 6819{"extldi.", MD(30,1,1), MD_MASK, PPC64, PPCVLE, {RA, RS, ELDn, SH6}}, 6820 6821{"rldic", MD(30,2,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 6822{"clrlsldi", MD(30,2,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}}, 6823{"rldic.", MD(30,2,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 6824{"clrlsldi.", MD(30,2,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, CSLDb, CSLDn}}, 6825 6826{"rldimi", MD(30,3,0), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 6827{"insrdi", MD(30,3,0), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}}, 6828{"rldimi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE, {RA, RS, SH6, MB6}}, 6829{"insrdi.", MD(30,3,1), MD_MASK, PPC64, PPCVLE|EXT, {RA, RS, IRDn, IRDb}}, 6830 6831{"rotld", MDS(30,8,0), MDSMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RB}}, 6832{"rldcl", MDS(30,8,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, 6833{"rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, PPCVLE|EXT, {RA, RS, RB}}, 6834{"rldcl.", MDS(30,8,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, MB6}}, 6835 6836{"rldcr", MDS(30,9,0), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, 6837{"rldcr.", MDS(30,9,1), MDS_MASK, PPC64, PPCVLE, {RA, RS, RB, ME6}}, 6838 6839{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, EXT, {OBF, RA, RB}}, 6840{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, EXT, {OBF, RA, RB}}, 6841{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, 6842{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, 6843 6844{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6845{"tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6846{"twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6847{"tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6848{"tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6849{"teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6850{"twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6851{"tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6852{"twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6853{"tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6854{"twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6855{"tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6856{"twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6857{"tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6858{"twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6859{"tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6860{"twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6861{"tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6862{"twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6863{"tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6864{"twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6865{"tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6866{"twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6867{"tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6868{"twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6869{"tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6870{"twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6871{"tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6872{"trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, EXT, {0}}, 6873{"twu", XTO(31,4,TOU), XTO_MASK, PPCCOM, EXT, {RA, RB}}, 6874{"tu", XTO(31,4,TOU), XTO_MASK, PWRCOM, EXT, {RA, RB}}, 6875{"tw", X(31,4), X_MASK, PPCCOM, 0, {TO, RA, RB}}, 6876{"t", X(31,4), X_MASK, PWRCOM, 0, {TO, RA, RB}}, 6877 6878{"lvsl", X(31,6), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 6879{"lvebx", X(31,7), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 6880{"lbfcmx", APU(31,7,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6881 6882{"subfc", XO(31,8,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6883{"sf", XO(31,8,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6884{"subc", XO(31,8,0,0), XO_MASK, PPCCOM, EXT, {RT, RB, RA}}, 6885{"subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6886{"sf.", XO(31,8,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6887{"subc.", XO(31,8,0,1), XO_MASK, PPCCOM, EXT, {RT, RB, RA}}, 6888 6889{"mulhdu", XO(31,9,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6890{"mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 6891 6892{"addc", XO(31,10,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6893{"a", XO(31,10,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6894{"addc.", XO(31,10,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 6895{"a.", XO(31,10,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 6896 6897{"mulhwu", XO(31,11,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6898{"mulhwu.", XO(31,11,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6899 6900{"lxsiwzx", X(31,12), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 6901 6902{"lxvrbx", X(31,13), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, 6903 6904{"isellt", XISEL(31,15,0), X_MASK, PPCISEL, EXT, {RT, RA0, RB}}, 6905{"iselgt", XISEL(31,15,1), X_MASK, PPCISEL, EXT, {RT, RA0, RB}}, 6906{"iseleq", XISEL(31,15,2), X_MASK, PPCISEL, EXT, {RT, RA0, RB}}, 6907{"isel", XISEL(31,15,0), XISEL_MASK, PPCISEL|TITAN, 0, {RT, RA0, RB, BC}}, 6908 6909{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC|PPCA2, 0, {0}}, 6910{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC|PPCA2, 0, {0}}, 6911{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 6912{"tlbilx", X(31,18), X_MASK, E500MC|PPCA2, 0, {T, RA0, RB}}, 6913 6914{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, COM, 0, {RT, FXM4}}, 6915{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, 0, {RT, FXM}}, 6916 6917{"lwarx", X(31,20), XEH_MASK, PPC, 0, {RT, RA0, RB, EH}}, 6918 6919{"ldx", X(31,21), X_MASK, PPC64, 0, {RT, RA0, RB}}, 6920 6921{"icbt", X(31,22), X_MASK, POWER5|BOOKE|PPCE300, 0, {CT, RA0, RB}}, 6922 6923{"lwzx", X(31,23), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, 6924{"lx", X(31,23), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 6925 6926{"slw", XRC(31,24,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6927{"sl", XRC(31,24,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6928{"slw.", XRC(31,24,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 6929{"sl.", XRC(31,24,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 6930 6931{"cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, 6932{"cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, 6933{"cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, 6934{"cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, 6935 6936{"sld", XRC(31,27,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 6937{"sld.", XRC(31,27,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 6938 6939{"and", XRC(31,28,0), X_MASK, COM, 0, {RA, RS, RB}}, 6940{"and.", XRC(31,28,1), X_MASK, COM, 0, {RA, RS, RB}}, 6941 6942{"maskg", XRC(31,29,0), X_MASK, M601, PPCA2, {RA, RS, RB}}, 6943{"maskg.", XRC(31,29,1), X_MASK, M601, PPCA2, {RA, RS, RB}}, 6944 6945{"ldepx", X(31,29), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 6946 6947{"waitasec", X(31,30), XRTRARB_MASK, POWER8, POWER9, {0}}, 6948{"waitrsv", XWCPL(31,30,1,0),0xffffffff, POWER10, EXT, {0}}, 6949{"pause_short", XWCPL(31,30,2,0),0xffffffff, POWER10, EXT, {0}}, 6950{"wait", X(31,30), XWCPL_MASK, POWER10, 0, {WC, PL}}, 6951{"wait", X(31,30), XWC_MASK, POWER9, POWER10, {WC}}, 6952 6953{"lwepx", X(31,31), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 6954 6955{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, EXT, {OBF, RA, RB}}, 6956{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, EXT, {OBF, RA, RB}}, 6957{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}}, 6958{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}}, 6959 6960{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 6961{"lvehx", X(31,39), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 6962{"lhfcmx", APU(31,39,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 6963 6964{"lxvrhx", X(31,45), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, 6965 6966{"mviwsplt", X(31,46), X_MASK, E6500, 0, {VD, RA, RB}}, 6967 6968{"lvewx", X(31,71), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 6969 6970{"addg6s", XO(31,74,0,0), XO_MASK, POWER6, 0, {RT, RA, RB}}, 6971 6972{"lxsiwax", X(31,76), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 6973 6974{"lxvrwx", X(31,77), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, 6975 6976{"subf", XO(31,40,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 6977{"sub", XO(31,40,0,0), XO_MASK, PPC, EXT, {RT, RB, RA}}, 6978{"subf.", XO(31,40,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 6979{"sub.", XO(31,40,0,1), XO_MASK, PPC, EXT, {RT, RB, RA}}, 6980 6981{"mffprd", X(31,51), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}}, 6982{"mfvrd", X(31,51)|1, XX1RB_MASK|1, PPCVSX2, EXT, {RA, VS}}, 6983{"mfvsrd", X(31,51), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, 6984{"eratilx", X(31,51), X_MASK, PPCA2, 0, {ERAT_T, RA, RB}}, 6985 6986{"lbarx", X(31,52), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, 6987 6988{"ldux", X(31,53), X_MASK, PPC64, 0, {RT, RAL, RB}}, 6989 6990{"dcbst", X(31,54), XRT_MASK, PPC, 0, {RA0, RB}}, 6991 6992{"lwzux", X(31,55), X_MASK, PPCCOM, 0, {RT, RAL, RB}}, 6993{"lux", X(31,55), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 6994 6995{"cntlzd", XRC(31,58,0), XRB_MASK, PPC64, 0, {RA, RS}}, 6996{"cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, 0, {RA, RS}}, 6997 6998{"cntlzdm", X(31,59), X_MASK, POWER10, 0, {RA, RS, RB}}, 6999 7000{"andc", XRC(31,60,0), X_MASK, COM, 0, {RA, RS, RB}}, 7001{"andc.", XRC(31,60,1), X_MASK, COM, 0, {RA, RS, RB}}, 7002 7003{"waitrsv", X(31,62)|(1<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}}, 7004{"waitimpl", X(31,62)|(2<<21), 0xffffffff, E500MC|PPCA2, EXT, {0}}, 7005{"wait", X(31,62), XWC_MASK, E500MC|PPCA2, 0, {WC}}, 7006 7007{"dcbstep", XRT(31,63,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 7008 7009{"tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, EXT, {RA, RB}}, 7010{"tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, EXT, {RA, RB}}, 7011{"tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, EXT, {RA, RB}}, 7012{"tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, EXT, {RA, RB}}, 7013{"tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, EXT, {RA, RB}}, 7014{"tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, EXT, {RA, RB}}, 7015{"tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, EXT, {RA, RB}}, 7016{"tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, EXT, {RA, RB}}, 7017{"tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, EXT, {RA, RB}}, 7018{"tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, EXT, {RA, RB}}, 7019{"tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, EXT, {RA, RB}}, 7020{"tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, EXT, {RA, RB}}, 7021{"tdng", XTO(31,68,TONG), XTO_MASK, PPC64, EXT, {RA, RB}}, 7022{"tdne", XTO(31,68,TONE), XTO_MASK, PPC64, EXT, {RA, RB}}, 7023{"tdu", XTO(31,68,TOU), XTO_MASK, PPC64, EXT, {RA, RB}}, 7024{"td", X(31,68), X_MASK, PPC64, 0, {TO, RA, RB}}, 7025 7026{"lwfcmx", APU(31,71,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 7027{"mulhd", XO(31,73,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 7028{"mulhd.", XO(31,73,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 7029 7030{"mulhw", XO(31,75,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 7031{"mulhw.", XO(31,75,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 7032 7033{"msgsndu", XRTRA(31,78,0,0), XRTRA_MASK, POWER9, 0, {RB}}, 7034{"dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, 7035{"dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA, RS, RB}}, 7036 7037{"mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, 0, {SR, RS}}, 7038 7039{"mfmsr", X(31,83), XRARB_MASK, COM, 0, {RT}}, 7040 7041{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}}, 7042 7043{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476|EXT, {RA0, RB}}, 7044{"dcbflp", XOPL2(31,86,3), XRT_MASK, POWER9, PPC476|EXT, {RA0, RB}}, 7045{"dcbfps", XOPL3(31,86,4), XRT_MASK, POWER10, PPC476|EXT, {RA0, RB}}, 7046{"dcbstps", XOPL3(31,86,6), XRT_MASK, POWER10, PPC476|EXT, {RA0, RB}}, 7047{"dcbf", X(31,86), XL3RT_MASK, POWER10, PPC476, {RA0, RB, L3OPT}}, 7048{"dcbf", X(31,86), XLRT_MASK, PPC, POWER10, {RA0, RB, L2OPT}}, 7049 7050{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}}, 7051 7052{"lbepx", X(31,95), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 7053 7054{"dni", XRC(31,97,1), XRB_MASK, E6500, 0, {DUI, DCTL}}, 7055 7056{"lvx", X(31,103), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 7057{"lqfcmx", APU(31,103,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 7058 7059{"neg", XO(31,104,0,0), XORB_MASK, COM, 0, {RT, RA}}, 7060{"neg.", XO(31,104,0,1), XORB_MASK, COM, 0, {RT, RA}}, 7061 7062{"mul", XO(31,107,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 7063{"mul.", XO(31,107,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 7064 7065{"lxvrdx", X(31,109), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, 7066 7067{"msgclru", XRTRA(31,110,0,0), XRTRA_MASK, POWER9, 0, {RB}}, 7068{"mvidsplt", X(31,110), X_MASK, E6500, 0, {VD, RA, RB}}, 7069 7070{"mtsrdin", X(31,114), XRA_MASK, PPC64, 0, {RS, RB}}, 7071 7072{"mffprwz", X(31,115), XX1RB_MASK|1, PPCVSX2, EXT, {RA, FRS}}, 7073{"mfvrwz", X(31,115)|1, XX1RB_MASK|1, PPCVSX2, EXT, {RA, VS}}, 7074{"mfvsrwz", X(31,115), XX1RB_MASK, PPCVSX2, 0, {RA, XS6}}, 7075 7076{"lharx", X(31,116), XEH_MASK, POWER8|E6500, 0, {RT, RA0, RB, EH}}, 7077 7078{"clf", X(31,118), XTO_MASK, POWER, 0, {RA, RB}}, 7079 7080{"lbzux", X(31,119), X_MASK, COM, 0, {RT, RAL, RB}}, 7081 7082{"popcntb", X(31,122), XRB_MASK, POWER5, 0, {RA, RS}}, 7083 7084{"not", XRC(31,124,0), X_MASK, COM, EXT, {RA, RSB}}, 7085{"nor", XRC(31,124,0), X_MASK, COM, 0, {RA, RS, RB}}, 7086{"not.", XRC(31,124,1), X_MASK, COM, EXT, {RA, RSB}}, 7087{"nor.", XRC(31,124,1), X_MASK, COM, 0, {RA, RS, RB}}, 7088 7089{"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 7090 7091{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}}, 7092 7093{"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}}, 7094 7095{"dcbtstls", X(31,134), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 7096 7097{"stvebx", X(31,135), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 7098{"stbfcmx", APU(31,135,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 7099 7100{"subfe", XO(31,136,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 7101{"sfe", XO(31,136,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 7102{"subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 7103{"sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 7104 7105{"adde", XO(31,138,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 7106{"ae", XO(31,138,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 7107{"adde.", XO(31,138,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 7108{"ae.", XO(31,138,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 7109 7110{"stxsiwx", X(31,140), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, 7111 7112{"stxvrbx", X(31,141), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, 7113 7114{"msgsndp", XRTRA(31,142,0,0), XRTRA_MASK, POWER8, 0, {RB}}, 7115{"dcbtstlse", X(31,142), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, 7116 7117{"mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, EXT, {RS}}, 7118{"mtcrf", XFXM(31,144,0,0), XFXFXM_MASK, COM, 0, {FXM, RS}}, 7119{"mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, 0, {FXM, RS}}, 7120 7121{"mtmsr", X(31,146), XRLARB_MASK, COM, 0, {RS, A_L}}, 7122 7123{"mtsle", X(31,147), XRTLRARB_MASK, POWER8, 0, {L}}, 7124{"eratsx", XRC(31,147,0), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 7125{"eratsx.", XRC(31,147,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 7126 7127{"stdx", X(31,149), X_MASK, PPC64, 0, {RS, RA0, RB}}, 7128 7129{"stwcx.", XRC(31,150,1), X_MASK, PPC, 0, {RS, RA0, RB}}, 7130 7131{"stwx", X(31,151), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, 7132{"stx", X(31,151), X_MASK, PWRCOM, 0, {RS, RA, RB}}, 7133 7134{"slq", XRC(31,152,0), X_MASK, M601, 0, {RA, RS, RB}}, 7135{"slq.", XRC(31,152,1), X_MASK, M601, 0, {RA, RS, RB}}, 7136 7137{"sle", XRC(31,153,0), X_MASK, M601, 0, {RA, RS, RB}}, 7138{"sle.", XRC(31,153,1), X_MASK, M601, 0, {RA, RS, RB}}, 7139 7140{"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}}, 7141 7142{"brw", X(31,155), XRB_MASK, POWER10, 0, {RA, RS}}, 7143{"pdepd", X(31,156), X_MASK, POWER10, 0, {RA, RS, RB}}, 7144 7145{"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 7146 7147{"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 7148 7149{"wrteei", X(31,163), XE_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {E}}, 7150 7151{"dcbtls", X(31,166), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 7152 7153{"stvehx", X(31,167), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 7154{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 7155 7156{"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}}, 7157 7158{"stxvrhx", X(31,173), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, 7159 7160{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}}, 7161{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}}, 7162 7163{"xxmfacc", XVA(31,177,0), XACC_MASK, POWER10, 0, {ACC}}, 7164{"xxmtacc", XVA(31,177,1), XACC_MASK, POWER10, 0, {ACC}}, 7165{"xxsetaccz", XVA(31,177,3), XACC_MASK, POWER10, 0, {ACC}}, 7166 7167{"mtmsrd", X(31,178), XRLARB_MASK, PPC64, 0, {RS, A_L}}, 7168 7169{"mtfprd", X(31,179), XX1RB_MASK|1, PPCVSX2, EXT, {FRT, RA}}, 7170{"mtvrd", X(31,179)|1, XX1RB_MASK|1, PPCVSX2, EXT, {VD, RA}}, 7171{"mtvsrd", X(31,179), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 7172{"eratre", X(31,179), X_MASK, PPCA2, 0, {RT, RA, WS}}, 7173 7174{"stdux", X(31,181), X_MASK, PPC64, 0, {RS, RAS, RB}}, 7175 7176{"stqcx.", XRC(31,182,1), X_MASK|Q_MASK, POWER8, 0, {RSQ, RA0, RB}}, 7177{"wchkall", X(31,182), X_MASK, PPCA2, 0, {OBF}}, 7178 7179{"stwux", X(31,183), X_MASK, PPCCOM, 0, {RS, RAS, RB}}, 7180{"stux", X(31,183), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 7181 7182{"sliq", XRC(31,184,0), X_MASK, M601, 0, {RA, RS, SH}}, 7183{"sliq.", XRC(31,184,1), X_MASK, M601, 0, {RA, RS, SH}}, 7184 7185{"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}}, 7186 7187{"brd", X(31,187), XRB_MASK, POWER10, 0, {RA, RS}}, 7188{"pextd", X(31,188), X_MASK, POWER10, 0, {RA, RS, RB}}, 7189 7190{"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}}, 7191 7192{"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}}, 7193 7194{"stvewx", X(31,199), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 7195{"stwfcmx", APU(31,199,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 7196 7197{"subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 7198{"sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 7199{"subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 7200{"sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 7201 7202{"addze", XO(31,202,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 7203{"aze", XO(31,202,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 7204{"addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 7205{"aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 7206 7207{"stxvrwx", X(31,205), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, 7208 7209{"msgsnd", XRTRA(31,206,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, 7210 7211{"mtsr", X(31,210), XRB_MASK|(1<<20), COM, NON32, {SR, RS}}, 7212 7213{"mtfprwa", X(31,211), XX1RB_MASK|1, PPCVSX2, EXT, {FRT, RA}}, 7214{"mtvrwa", X(31,211)|1, XX1RB_MASK|1, PPCVSX2, EXT, {VD, RA}}, 7215{"mtvsrwa", X(31,211), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 7216{"eratwe", X(31,211), X_MASK, PPCA2, 0, {RS, RA, WS}}, 7217 7218{"ldawx.", XRC(31,212,1), X_MASK, PPCA2, 0, {RT, RA0, RB}}, 7219 7220{"stdcx.", XRC(31,214,1), X_MASK, PPC64, 0, {RS, RA0, RB}}, 7221 7222{"stbx", X(31,215), X_MASK, COM, 0, {RS, RA0, RB}}, 7223 7224{"sllq", XRC(31,216,0), X_MASK, M601, 0, {RA, RS, RB}}, 7225{"sllq.", XRC(31,216,1), X_MASK, M601, 0, {RA, RS, RB}}, 7226 7227{"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}}, 7228{"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}}, 7229 7230{"brh", X(31,219), XRB_MASK, POWER10, 0, {RA, RS}}, 7231{"cfuged", X(31,220), X_MASK, POWER10, 0, {RA, RS, RB}}, 7232 7233{"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 7234 7235{"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}}, 7236 7237{"icblc", X(31,230), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 7238 7239{"stvx", X(31,231), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 7240{"stqfcmx", APU(31,231,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 7241 7242{"subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 7243{"sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 7244{"subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 7245{"sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 7246 7247{"mulld", XO(31,233,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 7248{"mulld.", XO(31,233,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 7249 7250{"addme", XO(31,234,0,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 7251{"ame", XO(31,234,0,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 7252{"addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 7253{"ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 7254 7255{"mullw", XO(31,235,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 7256{"muls", XO(31,235,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 7257{"mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 7258{"muls.", XO(31,235,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 7259 7260{"stxvrdx", X(31,237), XX1_MASK, POWER10, 0, {XT6, RA0, RB}}, 7261 7262{"icblce", X(31,238), X_MASK, PPCCHLK, E500MC|PPCA2, {CT, RA, RB}}, 7263{"msgclr", XRTRA(31,238,0,0), XRTRA_MASK, E500MC|PPCA2|POWER8, 0, {RB}}, 7264{"mtsrin", X(31,242), XRA_MASK, PPC, NON32, {RS, RB}}, 7265{"mtsri", X(31,242), XRA_MASK, POWER, NON32, {RS, RB}}, 7266 7267{"mtfprwz", X(31,243), XX1RB_MASK|1, PPCVSX2, EXT, {FRT, RA}}, 7268{"mtvrwz", X(31,243)|1, XX1RB_MASK|1, PPCVSX2, EXT, {VD, RA}}, 7269{"mtvsrwz", X(31,243), XX1RB_MASK, PPCVSX2, 0, {XT6, RA}}, 7270 7271{"dcbtstt", XRT(31,246,0x10), XRT_MASK, POWER7, EXT, {RA0, RB}}, 7272{"dcbtstct", X(31,246), X_MASK, POWER4, EXT, {RA0, RB, THCT}}, 7273{"dcbtstds", X(31,246), X_MASK, POWER4, EXT, {RA0, RB, THDS}}, 7274{"dcbtst", X(31,246), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, 7275{"dcbtst", X(31,246), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, 7276{"dcbtst", X(31,246), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, 7277 7278{"stbux", X(31,247), X_MASK, COM, 0, {RS, RAS, RB}}, 7279 7280{"slliq", XRC(31,248,0), X_MASK, M601, 0, {RA, RS, SH}}, 7281{"slliq.", XRC(31,248,1), X_MASK, M601, 0, {RA, RS, SH}}, 7282 7283{"bpermd", X(31,252), X_MASK, POWER7|PPCA2, 0, {RA, RS, RB}}, 7284 7285{"dcbtstep", XRT(31,255,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 7286 7287{"mfdcrx", X(31,259), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RS, RA}}, 7288{"mfdcrx.", XRC(31,259,1), X_MASK, PPCA2, 0, {RS, RA}}, 7289 7290{"lvexbx", X(31,261), X_MASK, E6500, 0, {VD, RA0, RB}}, 7291 7292{"icbt", X(31,262), XRT_MASK, PPC403, 0, {RA, RB}}, 7293 7294{"lvepxl", X(31,263), X_MASK, E6500, 0, {VD, RA0, RB}}, 7295{"ldfcmx", APU(31,263,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 7296 7297{"doz", XO(31,264,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 7298{"doz.", XO(31,264,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 7299 7300{"modud", X(31,265), X_MASK, POWER9, 0, {RT, RA, RB}}, 7301 7302{"add", XO(31,266,0,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 7303{"cax", XO(31,266,0,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 7304{"add.", XO(31,266,0,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 7305{"cax.", XO(31,266,0,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 7306 7307{"moduw", X(31,267), X_MASK, POWER9, 0, {RT, RA, RB}}, 7308 7309{"lxvx", X(31,268), XX1_MASK|1<<6, PPCVSX3, 0, {XT6, RA0, RB}}, 7310{"lxvl", X(31,269), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 7311 7312{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}}, 7313 7314{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, 0, {RB, RSO, RIC, PRS, X_R}}, 7315{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}}, 7316 7317{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}}, 7318 7319{"lqarx", X(31,276), XEH_MASK|Q_MASK, POWER8, 0, {RTQ, RAX, RBX, EH}}, 7320 7321{"lscbx", XRC(31,277,0), X_MASK, M601, 0, {RT, RA, RB}}, 7322{"lscbx.", XRC(31,277,1), X_MASK, M601, 0, {RT, RA, RB}}, 7323 7324{"dcbtt", XRT(31,278,0x10), XRT_MASK, POWER7, EXT, {RA0, RB}}, 7325{"dcbna", XRT(31,278,0x11), XRT_MASK, POWER10, EXT, {RA0, RB}}, 7326{"dcbtct", X(31,278), X_MASK, POWER4, EXT, {RA0, RB, THCT}}, 7327{"dcbtds", X(31,278), X_MASK, POWER4, EXT, {RA0, RB, THDS}}, 7328{"dcbt", X(31,278), X_MASK, POWER4, DCBT_EO, {RA0, RB, CT}}, 7329{"dcbt", X(31,278), X_MASK, DCBT_EO, 0, {CT, RA0, RB}}, 7330{"dcbt", X(31,278), X_MASK, PPC, POWER4|DCBT_EO, {RA0, RB}}, 7331 7332{"lhzx", X(31,279), X_MASK, COM, 0, {RT, RA0, RB}}, 7333 7334{"cdtbcd", X(31,282), XRB_MASK, POWER6, 0, {RA, RS}}, 7335 7336{"eqv", XRC(31,284,0), X_MASK, COM, 0, {RA, RS, RB}}, 7337{"eqv.", XRC(31,284,1), X_MASK, COM, 0, {RA, RS, RB}}, 7338 7339{"lhepx", X(31,287), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 7340 7341{"mfdcrux", X(31,291), X_MASK, PPC464|PPC476, 0, {RS, RA}}, 7342 7343{"lvexhx", X(31,293), X_MASK, E6500, 0, {VD, RA0, RB}}, 7344{"lvepx", X(31,295), X_MASK, E6500, 0, {VD, RA0, RB}}, 7345 7346{"lxvll", X(31,301), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 7347 7348{"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}}, 7349 7350{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}}, 7351{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}}, 7352{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}}, 7353{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}}, 7354 7355{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}}, 7356 7357{"eciwx", X(31,310), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, 7358 7359{"lhzux", X(31,311), X_MASK, COM, 0, {RT, RAL, RB}}, 7360 7361{"cbcdtd", X(31,314), XRB_MASK, POWER6, 0, {RA, RS}}, 7362 7363{"xor", XRC(31,316,0), X_MASK, COM, 0, {RA, RS, RB}}, 7364{"xor.", XRC(31,316,1), X_MASK, COM, 0, {RA, RS, RB}}, 7365 7366{"dcbtep", XRT(31,319,0), X_MASK, E500MC|PPCA2, 0, {RT, RA0, RB}}, 7367 7368{"mfexisr", XSPR(31,323, 64), XSPR_MASK, PPC403, 0, {RT}}, 7369{"mfexier", XSPR(31,323, 66), XSPR_MASK, PPC403, 0, {RT}}, 7370{"mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, 0, {RT}}, 7371{"mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, 0, {RT}}, 7372{"mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, 0, {RT}}, 7373{"mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, 0, {RT}}, 7374{"mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, 0, {RT}}, 7375{"mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, 0, {RT}}, 7376{"mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, 0, {RT}}, 7377{"mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, 0, {RT}}, 7378{"mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, 0, {RT}}, 7379{"mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, 0, {RT}}, 7380{"mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, 0, {RT}}, 7381{"mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, 0, {RT}}, 7382{"mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, 0, {RT}}, 7383{"mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, 0, {RT}}, 7384{"mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, 0, {RT}}, 7385{"mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, 0, {RT}}, 7386{"mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, 0, {RT}}, 7387{"mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, 0, {RT}}, 7388{"mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, 0, {RT}}, 7389{"mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, 0, {RT}}, 7390{"mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, 0, {RT}}, 7391{"mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, 0, {RT}}, 7392{"mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, 0, {RT}}, 7393{"mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, 0, {RT}}, 7394{"mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, 0, {RT}}, 7395{"mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, 0, {RT}}, 7396{"mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, 0, {RT}}, 7397{"mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, 0, {RT}}, 7398{"mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, 0, {RT}}, 7399{"mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, 0, {RT}}, 7400{"mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, 0, {RT}}, 7401{"mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, 0, {RT}}, 7402{"mfdcr", X(31,323), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {RT, SPR}}, 7403{"mfdcr.", XRC(31,323,1), X_MASK, PPCA2, 0, {RT, SPR}}, 7404 7405{"lvexwx", X(31,325), X_MASK, E6500, 0, {VD, RA0, RB}}, 7406 7407{"dcread", X(31,326), X_MASK, PPC476|TITAN, 0, {RT, RA0, RB}}, 7408 7409{"div", XO(31,331,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 7410{"div.", XO(31,331,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 7411 7412{"lxvdsx", X(31,332), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 7413 7414{"lxvpx", X(31,333), XX1_MASK, POWER10, 0, {XTP, RA0, RB}}, 7415 7416{"mfpmr", X(31,334), X_MASK, PPCPMR|PPCE300, 0, {RT, PMR}}, 7417{"mftmr", X(31,366), X_MASK, PPCTMR, 0, {RT, TMR}}, 7418 7419{"slbsync", X(31,338), 0xffffffff, POWER9, 0, {0}}, 7420 7421{"mfmq", XSPR(31,339, 0), XSPR_MASK, M601, EXT, {RT}}, 7422{"mfxer", XSPR(31,339, 1), XSPR_MASK, COM, EXT, {RT}}, 7423{"mfudscr", XSPR(31,339, 3), XSPR_MASK, POWER9, EXT, {RS}}, 7424{"mfrtcu", XSPR(31,339, 4), XSPR_MASK, COM, TITAN|EXT, {RT}}, 7425{"mfrtcl", XSPR(31,339, 5), XSPR_MASK, COM, TITAN|EXT, {RT}}, 7426{"mfdec", XSPR(31,339, 6), XSPR_MASK, MFDEC1, EXT, {RT}}, 7427{"mflr", XSPR(31,339, 8), XSPR_MASK, COM, EXT, {RT}}, 7428{"mfctr", XSPR(31,339, 9), XSPR_MASK, COM, EXT, {RT}}, 7429{"mfuamr", XSPR(31,339, 13), XSPR_MASK, POWER9, EXT, {RS}}, 7430{"mfdscr", XSPR(31,339, 17), XSPR_MASK, POWER6, EXT, {RT}}, 7431{"mftid", XSPR(31,339, 17), XSPR_MASK, POWER, EXT, {RT}}, 7432{"mfdsisr", XSPR(31,339, 18), XSPR_MASK, COM, TITAN|EXT, {RT}}, 7433{"mfdar", XSPR(31,339, 19), XSPR_MASK, COM, TITAN|EXT, {RT}}, 7434{"mfdec", XSPR(31,339, 22), XSPR_MASK, MFDEC2, MFDEC1|EXT, {RT}}, 7435{"mfsdr0", XSPR(31,339, 24), XSPR_MASK, POWER, EXT, {RT}}, 7436{"mfsdr1", XSPR(31,339, 25), XSPR_MASK, COM, TITAN|EXT, {RT}}, 7437{"mfsrr0", XSPR(31,339, 26), XSPR_MASK, COM, EXT, {RT}}, 7438{"mfsrr1", XSPR(31,339, 27), XSPR_MASK, COM, EXT, {RT}}, 7439{"mfcfar", XSPR(31,339, 28), XSPR_MASK, POWER6, EXT, {RT}}, 7440{"mfamr", XSPR(31,339, 29), XSPR_MASK, POWER7, EXT, {RS}}, 7441{"mfpidr", XSPR(31,339, 48), XSPR_MASK, POWER10, EXT, {RS}}, 7442{"mfpid", XSPR(31,339, 48), XSPR_MASK, BOOKE, EXT, {RT}}, 7443{"mfcsrr0", XSPR(31,339, 58), XSPR_MASK, BOOKE, EXT, {RT}}, 7444{"mfcsrr1", XSPR(31,339, 59), XSPR_MASK, BOOKE, EXT, {RT}}, 7445{"mfiamr", XSPR(31,339, 61), XSPR_MASK, POWER10, EXT, {RS}}, 7446{"mfdear", XSPR(31,339, 61), XSPR_MASK, BOOKE, EXT, {RT}}, 7447{"mfesr", XSPR(31,339, 62), XSPR_MASK, BOOKE, EXT, {RT}}, 7448{"mfivpr", XSPR(31,339, 63), XSPR_MASK, BOOKE, EXT, {RT}}, 7449{"mfctrl", XSPR(31,339,136), XSPR_MASK, POWER4, EXT, {RT}}, 7450{"mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, EXT, {RT}}, 7451{"mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, EXT, {RT}}, 7452{"mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, EXT, {RT}}, 7453{"mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, EXT, {RT}}, 7454{"mficr", XSPR(31,339,148), XSPR_MASK, PPC860, EXT, {RT}}, 7455{"mfder", XSPR(31,339,149), XSPR_MASK, PPC860, EXT, {RT}}, 7456{"mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, EXT, {RT}}, 7457{"mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, EXT, {RT}}, 7458{"mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, EXT, {RT}}, 7459{"mffscr", XSPR(31,339,153), XSPR_MASK, POWER10, EXT, {RS}}, 7460{"mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, EXT, {RT}}, 7461{"mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, EXT, {RT}}, 7462{"mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, EXT, {RT}}, 7463{"mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, EXT, {RT}}, 7464{"mfuamor", XSPR(31,339,157), XSPR_MASK, POWER7, EXT, {RS}}, 7465{"mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, EXT, {RT}}, 7466{"mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, EXT, {RT}}, 7467{"mfpspb", XSPR(31,339,159), XSPR_MASK, POWER10, EXT, {RS}}, 7468{"mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, EXT, {RT}}, 7469{"mfdpdes", XSPR(31,339,176), XSPR_MASK, POWER10, EXT, {RS}}, 7470{"mfdawr0", XSPR(31,339,180), XSPR_MASK, POWER10, EXT, {RS}}, 7471{"mfdawr1", XSPR(31,339,181), XSPR_MASK, POWER10, EXT, {RS}}, 7472{"mfrpr", XSPR(31,339,186), XSPR_MASK, POWER10, EXT, {RS}}, 7473{"mfciabr", XSPR(31,339,187), XSPR_MASK, POWER10, EXT, {RS}}, 7474{"mfdawrx0", XSPR(31,339,188), XSPR_MASK, POWER10, EXT, {RS}}, 7475{"mfdawrx1", XSPR(31,339,189), XSPR_MASK, POWER10, EXT, {RS}}, 7476{"mfhfscr", XSPR(31,339,190), XSPR_MASK, POWER10, EXT, {RS}}, 7477{"mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, EXT, {RT}}, 7478{"mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, EXT, {RT}}, 7479{"mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, EXT, {RT, SPRG}}, 7480{"mfusprg3", XSPR(31,339,259), XSPR_MASK, POWER10, EXT, {RT}}, 7481{"mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405|BOOKE, EXT, {RT}}, 7482{"mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405|BOOKE, EXT, {RT}}, 7483{"mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405|BOOKE, EXT, {RT}}, 7484{"mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405|BOOKE, EXT, {RT}}, 7485{"mftbu", XSPR(31,339,269), XSPR_MASK, POWER4|BOOKE, EXT, {RT}}, 7486{"mftb", X(31,339), X_MASK, POWER4|BOOKE, EXT, {RT, TBR}}, 7487{"mftbl", XSPR(31,339,268), XSPR_MASK, POWER4|BOOKE, EXT, {RT}}, 7488{"mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, EXT, {RT}}, 7489{"mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, EXT, {RT}}, 7490{"mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, EXT, {RT}}, 7491{"mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, EXT, {RT}}, 7492{"mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, EXT, {RT}}, 7493{"mfear", XSPR(31,339,282), XSPR_MASK, PPC, TITAN|EXT, {RT}}, 7494{"mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, EXT, {RT}}, 7495{"mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, EXT, {RT}}, 7496{"mfhsprg0", XSPR(31,339,304), XSPR_MASK, POWER10, EXT, {RS}}, 7497{"mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, EXT, {RT}}, 7498{"mfhsprg1", XSPR(31,339,305), XSPR_MASK, POWER10, EXT, {RS}}, 7499{"mfhdisr", XSPR(31,339,306), XSPR_MASK, POWER10, EXT, {RS}}, 7500{"mfhdar", XSPR(31,339,307), XSPR_MASK, POWER10, EXT, {RS}}, 7501{"mfspurr", XSPR(31,339,308), XSPR_MASK, POWER10, EXT, {RS}}, 7502{"mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, EXT, {RT}}, 7503{"mfpurr", XSPR(31,339,309), XSPR_MASK, POWER10, EXT, {RS}}, 7504{"mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, EXT, {RT}}, 7505{"mfhdec", XSPR(31,339,310), XSPR_MASK, POWER10, EXT, {RS}}, 7506{"mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, EXT, {RT}}, 7507{"mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, EXT, {RT}}, 7508{"mfhrmor", XSPR(31,339,313), XSPR_MASK, POWER10, EXT, {RS}}, 7509{"mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, EXT, {RT}}, 7510{"mfhsrr0", XSPR(31,339,314), XSPR_MASK, POWER10, EXT, {RS}}, 7511{"mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, EXT, {RT}}, 7512{"mfhsrr1", XSPR(31,339,315), XSPR_MASK, POWER10, EXT, {RS}}, 7513{"mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, EXT, {RT}}, 7514{"mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, EXT, {RT}}, 7515{"mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, EXT, {RT}}, 7516{"mflpcr", XSPR(31,339,318), XSPR_MASK, POWER10, EXT, {RS}}, 7517{"mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, EXT, {RT}}, 7518{"mflpidr", XSPR(31,339,319), XSPR_MASK, POWER10, EXT, {RS}}, 7519{"mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, EXT, {RT}}, 7520{"mfhmer", XSPR(31,339,336), XSPR_MASK, POWER7, EXT, {RS}}, 7521{"mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, EXT, {RT}}, 7522{"mfhmeer", XSPR(31,339,337), XSPR_MASK, POWER7, EXT, {RS}}, 7523{"mfpcr", XSPR(31,339,338), XSPR_MASK, POWER10, EXT, {RS}}, 7524{"mfheir", XSPR(31,339,339), XSPR_MASK, POWER10, EXT, {RS}}, 7525{"mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, EXT, {RT}}, 7526{"mfamor", XSPR(31,339,349), XSPR_MASK, POWER7, EXT, {RS}}, 7527{"mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, EXT, {RT}}, 7528{"mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, EXT, {RT}}, 7529{"mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, EXT, {RT}}, 7530{"mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, EXT, {RT}}, 7531{"mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, EXT, {RT}}, 7532{"mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, EXT, {RT}}, 7533{"mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, EXT, {RT}}, 7534{"mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, EXT, {RT}}, 7535{"mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, EXT, {RT}}, 7536{"mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, EXT, {RT}}, 7537{"mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, EXT, {RT}}, 7538{"mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, EXT, {RT}}, 7539{"mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, EXT, {RT}}, 7540{"mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, EXT, {RT}}, 7541{"mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, EXT, {RT}}, 7542{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, EXT, {RT}}, 7543{"mftir", XSPR(31,339,446), XSPR_MASK, POWER10, EXT, {RS}}, 7544{"mfptcr", XSPR(31,339,464), XSPR_MASK, POWER10, EXT, {RS}}, 7545{"mfusprg0", XSPR(31,339,496), XSPR_MASK, POWER10, EXT, {RS}}, 7546{"mfusprg1", XSPR(31,339,497), XSPR_MASK, POWER10, EXT, {RS}}, 7547{"mfurmor", XSPR(31,339,505), XSPR_MASK, POWER10, EXT, {RS}}, 7548{"mfusrr0", XSPR(31,339,506), XSPR_MASK, POWER10, EXT, {RS}}, 7549{"mfusrr1", XSPR(31,339,507), XSPR_MASK, POWER10, EXT, {RS}}, 7550{"mfsmfctrl", XSPR(31,339,511), XSPR_MASK, POWER10, EXT, {RS}}, 7551{"mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, EXT, {RT}}, 7552{"mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, EXT, {RT}}, 7553{"mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, EXT, {RT}}, 7554{"mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE|E6500, EXT, {RT}}, 7555{"mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE|E6500, EXT, {RT}}, 7556{"mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, EXT, {RT}}, 7557{"mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, EXT, {RT}}, 7558{"mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, TITAN|EXT, {RT, SPRBAT}}, 7559{"mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, TITAN|EXT, {RT, SPRBAT}}, 7560{"mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, TITAN|EXT, {RT, SPRBAT}}, 7561{"mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, TITAN|EXT, {RT, SPRBAT}}, 7562{"mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, EXT, {RT}}, 7563{"mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, EXT, {RT}}, 7564{"mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, EXT, {RT}}, 7565{"mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, EXT, {RT}}, 7566{"mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, EXT, {RT}}, 7567{"mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, EXT, {RT}}, 7568{"mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, EXT, {RT}}, 7569{"mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, EXT, {RT}}, 7570{"mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, EXT, {RT}}, 7571{"mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, TITAN|EXT, {RT}}, 7572{"mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, EXT, {RT}}, 7573{"mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, EXT, {RT}}, 7574{"mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, EXT, {RT}}, 7575{"mfusier2", XSPR(31,339,736), XSPR_MASK, POWER10, EXT, {RT}}, 7576{"mfsier2", XSPR(31,339,736), XSPR_MASK, POWER10, EXT, {RT}}, 7577{"mfusier3", XSPR(31,339,737), XSPR_MASK, POWER10, EXT, {RT}}, 7578{"mfsier3", XSPR(31,339,737), XSPR_MASK, POWER10, EXT, {RT}}, 7579{"mfummcr3", XSPR(31,339,738), XSPR_MASK, POWER10, EXT, {RT}}, 7580{"mfmmcr3", XSPR(31,339,738), XSPR_MASK, POWER10, EXT, {RT}}, 7581{"mfusier", XSPR(31,339,768), XSPR_MASK, POWER10, EXT, {RT}}, 7582{"mfsier", XSPR(31,339,768), XSPR_MASK, POWER10, EXT, {RT}}, 7583{"mfummcr2", XSPR(31,339,769), XSPR_MASK, POWER9, EXT, {RT}}, 7584{"mfmmcr2", XSPR(31,339,769), XSPR_MASK, POWER9, EXT, {RT}}, 7585{"mfummcra", XSPR(31,339,770), XSPR_MASK, POWER9, EXT, {RS}}, 7586{"mfmmcra", XSPR(31,339,770), XSPR_MASK, POWER7, EXT, {RS}}, 7587{"mfupmc1", XSPR(31,339,771), XSPR_MASK, POWER9, EXT, {RT}}, 7588{"mfpmc1", XSPR(31,339,771), XSPR_MASK, POWER7, EXT, {RT}}, 7589{"mfupmc2", XSPR(31,339,772), XSPR_MASK, POWER9, EXT, {RT}}, 7590{"mfpmc2", XSPR(31,339,772), XSPR_MASK, POWER7, EXT, {RT}}, 7591{"mfupmc3", XSPR(31,339,773), XSPR_MASK, POWER9, EXT, {RT}}, 7592{"mfpmc3", XSPR(31,339,773), XSPR_MASK, POWER7, EXT, {RT}}, 7593{"mfupmc4", XSPR(31,339,774), XSPR_MASK, POWER9, EXT, {RT}}, 7594{"mfpmc4", XSPR(31,339,774), XSPR_MASK, POWER7, EXT, {RT}}, 7595{"mfupmc5", XSPR(31,339,775), XSPR_MASK, POWER9, EXT, {RT}}, 7596{"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER7, EXT, {RT}}, 7597{"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, EXT, {RT}}, 7598{"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER7, EXT, {RT}}, 7599{"mfummcr0", XSPR(31,339,779), XSPR_MASK, POWER9, EXT, {RS}}, 7600{"mfmmcr0", XSPR(31,339,779), XSPR_MASK, POWER7, EXT, {RS}}, 7601{"mfusiar", XSPR(31,339,780), XSPR_MASK, POWER9, EXT, {RS}}, 7602{"mfsiar", XSPR(31,339,780), XSPR_MASK, POWER9, EXT, {RS}}, 7603{"mfusdar", XSPR(31,339,781), XSPR_MASK, POWER9, EXT, {RS}}, 7604{"mfsdar", XSPR(31,339,781), XSPR_MASK, POWER9, EXT, {RS}}, 7605{"mfummcr1", XSPR(31,339,782), XSPR_MASK, POWER9, EXT, {RS}}, 7606{"mfmmcr1", XSPR(31,339,782), XSPR_MASK, POWER7, EXT, {RS}}, 7607{"mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, EXT, {RT}}, 7608{"mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, EXT, {RT}}, 7609{"mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, EXT, {RT}}, 7610{"mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, EXT, {RT}}, 7611{"mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, EXT, {RT}}, 7612{"mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, EXT, {RT}}, 7613{"mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, EXT, {RT}}, 7614{"mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, EXT, {RT}}, 7615{"mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, EXT, {RT}}, 7616{"mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, EXT, {RT}}, 7617{"mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, EXT, {RT}}, 7618{"mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, EXT, {RT}}, 7619{"mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, EXT, {RT}}, 7620{"mfbescrs", XSPR(31,339,800), XSPR_MASK, POWER9, EXT, {RS}}, 7621{"mfbescrsu", XSPR(31,339,801), XSPR_MASK, POWER9, EXT, {RS}}, 7622{"mfbescrr", XSPR(31,339,802), XSPR_MASK, POWER9, EXT, {RS}}, 7623{"mfbescrru", XSPR(31,339,803), XSPR_MASK, POWER9, EXT, {RS}}, 7624{"mfebbhr", XSPR(31,339,804), XSPR_MASK, POWER9, EXT, {RS}}, 7625{"mfebbrr", XSPR(31,339,805), XSPR_MASK, POWER9, EXT, {RS}}, 7626{"mfbescr", XSPR(31,339,806), XSPR_MASK, POWER9, EXT, {RS}}, 7627{"mftar", XSPR(31,339,815), XSPR_MASK, POWER9, EXT, {RS}}, 7628{"mfasdr", XSPR(31,339,816), XSPR_MASK, POWER10, EXT, {RS}}, 7629{"mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, EXT, {RT}}, 7630{"mfmi_dbram0", XSPR(31,339,817), XSPR_MASK, PPC860, EXT, {RT}}, 7631{"mfmi_dbram1", XSPR(31,339,818), XSPR_MASK, PPC860, EXT, {RT}}, 7632{"mfpsscr", XSPR(31,339,823), XSPR_MASK, POWER10, EXT, {RS}}, 7633{"mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, EXT, {RT}}, 7634{"mfmd_dbram0", XSPR(31,339,825), XSPR_MASK, PPC860, EXT, {RT}}, 7635{"mfmd_dbram1", XSPR(31,339,826), XSPR_MASK, PPC860, EXT, {RT}}, 7636{"mfic", XSPR(31,339,848), XSPR_MASK, POWER8, EXT, {RS}}, 7637{"mfvtb", XSPR(31,339,849), XSPR_MASK, POWER8, EXT, {RS}}, 7638{"mfhpsscr", XSPR(31,339,855), XSPR_MASK, POWER10, EXT, {RS}}, 7639{"mfivndx", XSPR(31,339,880), XSPR_MASK, TITAN, EXT, {RT}}, 7640{"mfdvndx", XSPR(31,339,881), XSPR_MASK, TITAN, EXT, {RT}}, 7641{"mfivlim", XSPR(31,339,882), XSPR_MASK, TITAN, EXT, {RT}}, 7642{"mfdvlim", XSPR(31,339,883), XSPR_MASK, TITAN, EXT, {RT}}, 7643{"mfclcsr", XSPR(31,339,884), XSPR_MASK, TITAN, EXT, {RT}}, 7644{"mfccr1", XSPR(31,339,888), XSPR_MASK, TITAN, EXT, {RT}}, 7645{"mfppr", XSPR(31,339,896), XSPR_MASK, POWER5, EXT, {RT}}, 7646{"mfppr32", XSPR(31,339,898), XSPR_MASK, POWER5, EXT, {RT}}, 7647{"mfgqr", XSPR(31,339,912), XSPRGQR_MASK, PPCPS, EXT, {RT, SPRGQR}}, 7648{"mfhid2", XSPR(31,339,920), XSPR_MASK, GEKKO, EXT, {RT}}, 7649{"mfwpar", XSPR(31,339,921), XSPR_MASK, GEKKO, EXT, {RT}}, 7650{"mfdmau", XSPR(31,339,922), XSPR_MASK, GEKKO, EXT, {RT}}, 7651{"mfdmal", XSPR(31,339,923), XSPR_MASK, GEKKO, EXT, {RT}}, 7652{"mfrstcfg", XSPR(31,339,923), XSPR_MASK, TITAN, EXT, {RT}}, 7653{"mfdcdbtrl", XSPR(31,339,924), XSPR_MASK, TITAN, EXT, {RT}}, 7654{"mfdcdbtrh", XSPR(31,339,925), XSPR_MASK, TITAN, EXT, {RT}}, 7655{"mficdbtr", XSPR(31,339,927), XSPR_MASK, TITAN, EXT, {RT}}, 7656{"mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, EXT, {RT}}, 7657{"mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, EXT, {RT}}, 7658{"mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, EXT, {RT}}, 7659{"mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, EXT, {RT}}, 7660{"mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, EXT, {RT}}, 7661{"mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, EXT, {RT}}, 7662{"mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, EXT, {RT}}, 7663{"mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, EXT, {RT}}, 7664{"mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, EXT, {RT}}, 7665{"mfmmucr", XSPR(31,339,946), XSPR_MASK, TITAN, EXT, {RT}}, 7666{"mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405|TITAN, EXT, {RT}}, 7667{"mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, EXT, {RT}}, 7668{"mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, EXT, {RT}}, 7669{"mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, EXT, {RT}}, 7670{"mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, EXT, {RT}}, 7671{"mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, EXT, {RT}}, 7672{"mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, EXT, {RT}}, 7673{"mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, EXT, {RT}}, 7674{"mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, EXT, {RT}}, 7675{"mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, EXT, {RT}}, 7676{"mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, EXT, {RT}}, 7677{"mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, EXT, {RT}}, 7678{"mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, EXT, {RT}}, 7679{"mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, EXT, {RT}}, 7680{"mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, EXT, {RT}}, 7681{"mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, EXT, {RT}}, 7682{"mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, EXT, {RT}}, 7683{"mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403|TITAN, EXT, {RT}}, 7684{"mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, EXT, {RT}}, 7685{"mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, EXT, {RT}}, 7686{"mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, EXT, {RT}}, 7687{"mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, EXT, {RT}}, 7688{"mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, EXT, {RT}}, 7689{"mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, EXT, {RT}}, 7690{"mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, EXT, {RT}}, 7691{"mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, EXT, {RT}}, 7692{"mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, EXT, {RT}}, 7693{"mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, EXT, {RT}}, 7694{"mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, EXT, {RT}}, 7695{"mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, EXT, {RT}}, 7696{"mfhid0", XSPR(31,339,1008), XSPR_MASK, GEKKO, EXT, {RT}}, 7697{"mfhid1", XSPR(31,339,1009), XSPR_MASK, GEKKO, EXT, {RT}}, 7698{"mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, EXT, {RT}}, 7699{"mfiabr", XSPR(31,339,1010), XSPR_MASK, GEKKO, EXT, {RT}}, 7700{"mfhid4", XSPR(31,339,1011), XSPR_MASK, BROADWAY, EXT, {RT}}, 7701{"mfdbdr", XSPR(31,339,1011), XSPR_MASK, TITAN, EXT, {RS}}, 7702{"mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, EXT, {RT}}, 7703{"mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, EXT, {RT}}, 7704{"mfdabr", XSPR(31,339,1013), XSPR_MASK, PPC750, EXT, {RT}}, 7705{"mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, EXT, {RT}}, 7706{"mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, EXT, {RT}}, 7707{"mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, EXT, {RT}}, 7708{"mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, EXT, {RT}}, 7709{"mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, EXT, {RT}}, 7710{"mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, EXT, {RT}}, 7711{"mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, EXT, {RT}}, 7712{"mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, EXT, {RT}}, 7713{"mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, EXT, {RT}}, 7714{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, EXT, {RT}}, 7715{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, EXT, {RT}}, 7716{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, EXT, {RT}}, 7717{"mfpir", XSPR(31,339,1023), XSPR_MASK, POWER10, EXT, {RT}}, 7718{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, EXT, {RT}}, 7719{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}}, 7720 7721{"lwax", X(31,341), X_MASK, PPC64, 0, {RT, RA0, RB}}, 7722 7723{"dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 7724{"dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 7725 7726{"lhax", X(31,343), X_MASK, COM, 0, {RT, RA0, RB}}, 7727 7728{"lvxl", X(31,359), X_MASK, PPCVEC, 0, {VD, RA0, RB}}, 7729 7730{"abs", XO(31,360,0,0), XORB_MASK, M601, 0, {RT, RA}}, 7731{"abs.", XO(31,360,0,1), XORB_MASK, M601, 0, {RT, RA}}, 7732 7733{"divs", XO(31,363,0,0), XO_MASK, M601, 0, {RT, RA, RB}}, 7734{"divs.", XO(31,363,0,1), XO_MASK, M601, 0, {RT, RA, RB}}, 7735 7736{"lxvwsx", X(31,364), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 7737 7738{"tlbia", X(31,370), 0xffffffff, PPC, E500|TITAN, {0}}, 7739 7740{"mftbu", XSPR(31,371,269), XSPR_MASK, PPC, NO371|POWER4|EXT, {RT}}, 7741{"mftb", X(31,371), X_MASK, PPC, NO371|POWER4, {RT, TBR}}, 7742{"mftbl", XSPR(31,371,268), XSPR_MASK, PPC, NO371|POWER4|EXT, {RT}}, 7743 7744{"lwaux", X(31,373), X_MASK, PPC64, 0, {RT, RAL, RB}}, 7745 7746{"dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 7747{"dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, 0, {RA, RB, STRM}}, 7748 7749{"lhaux", X(31,375), X_MASK, COM, 0, {RT, RAL, RB}}, 7750 7751{"popcntw", X(31,378), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, 7752 7753{"setbc", X(31,384), XRB_MASK, POWER10, 0, {RT, BI}}, 7754 7755{"mtdcrx", X(31,387), X_MASK, BOOKE|PPCA2|PPC476, TITAN, {RA, RS}}, 7756{"mtdcrx.", XRC(31,387,1), X_MASK, PPCA2, 0, {RA, RS}}, 7757 7758{"stvexbx", X(31,389), X_MASK, E6500, 0, {VS, RA0, RB}}, 7759 7760{"dcblc", X(31,390), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 7761{"stdfcmx", APU(31,391,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 7762 7763{"divdeu", XO(31,393,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 7764{"divdeu.", XO(31,393,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 7765{"divweu", XO(31,395,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 7766{"divweu.", XO(31,395,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 7767 7768{"stxvx", X(31,396), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 7769{"stxvl", X(31,397), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 7770 7771{"dcblce", X(31,398), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, 7772 7773{"slbmte", X(31,402), XRA_MASK, PPC64, 0, {RS, RB}}, 7774 7775{"mtvsrws", X(31,403), XX1RB_MASK, PPCVSX3, 0, {XT6, RA}}, 7776 7777{"pbt.", XRC(31,404,1), X_MASK, POWER8, 0, {RS, RA0, RB}}, 7778 7779{"icswx", XRC(31,406,0), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, 7780{"icswx.", XRC(31,406,1), X_MASK, POWER7|PPCA2, 0, {RS, RA, RB}}, 7781 7782{"sthx", X(31,407), X_MASK, COM, 0, {RS, RA0, RB}}, 7783 7784{"orc", XRC(31,412,0), X_MASK, COM, 0, {RA, RS, RB}}, 7785{"orc.", XRC(31,412,1), X_MASK, COM, 0, {RA, RS, RB}}, 7786 7787{"sthepx", X(31,415), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}}, 7788 7789{"setbcr", X(31,416), XRB_MASK, POWER10, 0, {RT, BI}}, 7790 7791{"mtdcrux", X(31,419), X_MASK, PPC464|PPC476, 0, {RA, RS}}, 7792 7793{"stvexhx", X(31,421), X_MASK, E6500, 0, {VS, RA0, RB}}, 7794 7795{"dcblq.", XRC(31,422,1), X_MASK, E6500, 0, {CT, RA0, RB}}, 7796 7797{"divde", XO(31,425,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 7798{"divde.", XO(31,425,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 7799{"divwe", XO(31,427,0,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 7800{"divwe.", XO(31,427,0,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 7801 7802{"stxvll", X(31,429), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 7803 7804{"clrbhrb", X(31,430), 0xffffffff, POWER8, 0, {0}}, 7805 7806{"slbie", X(31,434), XRTRA_MASK, PPC64, 0, {RB}}, 7807 7808{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 7809 7810{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}}, 7811 7812{"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}}, 7813 7814/* or 1,1,1 */ 7815{"cctpl", 0x7c210b78, 0xffffffff, CELL, EXT, {0}}, 7816/* or 2,2,2 */ 7817{"cctpm", 0x7c421378, 0xffffffff, CELL, EXT, {0}}, 7818/* or 3,3,3 */ 7819{"cctph", 0x7c631b78, 0xffffffff, CELL, EXT, {0}}, 7820/* or 26,26,26 */ 7821{"miso", 0x7f5ad378, 0xffffffff, POWER8|E6500, EXT, {0}}, 7822/* or 27,27,27 */ 7823{"yield", 0x7f7bdb78, 0xffffffff, POWER7, EXT, {0}}, 7824/* or 28,28,28 */ 7825{"mdors", 0x7f9ce378, 0xffffffff, E500MC, EXT, {0}}, 7826{"db8cyc", 0x7f9ce378, 0xffffffff, CELL, EXT, {0}}, 7827/* or 29,29,29 */ 7828{"mdoio", 0x7fbdeb78, 0xffffffff, POWER7, EXT, {0}}, 7829{"db10cyc", 0x7fbdeb78, 0xffffffff, CELL, EXT, {0}}, 7830/* or 30,30,30 */ 7831{"mdoom", 0x7fdef378, 0xffffffff, POWER7, EXT, {0}}, 7832{"db12cyc", 0x7fdef378, 0xffffffff, CELL, EXT, {0}}, 7833/* or 31,31,31 */ 7834{"db16cyc", 0x7ffffb78, 0xffffffff, CELL, EXT, {0}}, 7835 7836{"mr", XRC(31,444,0), X_MASK, COM, EXT, {RA, RSB}}, 7837{"or", XRC(31,444,0), X_MASK, COM, 0, {RA, RS, RB}}, 7838{"mr.", XRC(31,444,1), X_MASK, COM, EXT, {RA, RSB}}, 7839{"or.", XRC(31,444,1), X_MASK, COM, 0, {RA, RS, RB}}, 7840 7841{"setnbc", X(31,448), XRB_MASK, POWER10, 0, {RT, BI}}, 7842 7843{"mtexisr", XSPR(31,451, 64), XSPR_MASK, PPC403, 0, {RS}}, 7844{"mtexier", XSPR(31,451, 66), XSPR_MASK, PPC403, 0, {RS}}, 7845{"mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, 0, {RS}}, 7846{"mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, 0, {RS}}, 7847{"mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, 0, {RS}}, 7848{"mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, 0, {RS}}, 7849{"mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, 0, {RS}}, 7850{"mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, 0, {RS}}, 7851{"mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, 0, {RS}}, 7852{"mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, 0, {RS}}, 7853{"mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, 0, {RS}}, 7854{"mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, 0, {RS}}, 7855{"mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, 0, {RS}}, 7856{"mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, 0, {RS}}, 7857{"mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, 0, {RS}}, 7858{"mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, 0, {RS}}, 7859{"mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, 0, {RS}}, 7860{"mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, 0, {RS}}, 7861{"mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, 0, {RS}}, 7862{"mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, 0, {RS}}, 7863{"mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, 0, {RS}}, 7864{"mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, 0, {RS}}, 7865{"mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, 0, {RS}}, 7866{"mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, 0, {RS}}, 7867{"mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, 0, {RS}}, 7868{"mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, 0, {RS}}, 7869{"mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, 0, {RS}}, 7870{"mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, 0, {RS}}, 7871{"mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, 0, {RS}}, 7872{"mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, 0, {RS}}, 7873{"mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, 0, {RS}}, 7874{"mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, 0, {RS}}, 7875{"mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, 0, {RS}}, 7876{"mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, 0, {RS}}, 7877{"mtdcr", X(31,451), X_MASK, PPC403|BOOKE|PPCA2|PPC476, E500|TITAN, {SPR, RS}}, 7878{"mtdcr.", XRC(31,451,1), X_MASK, PPCA2, 0, {SPR, RS}}, 7879 7880{"stvexwx", X(31,453), X_MASK, E6500, 0, {VS, RA0, RB}}, 7881 7882{"dccci", X(31,454), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, 7883{"dci", X(31,454), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, 7884 7885{"divdu", XO(31,457,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 7886{"divdu.", XO(31,457,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 7887 7888{"divwu", XO(31,459,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 7889{"divwu.", XO(31,459,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 7890 7891{"stxvpx", X(31,461), XX1_MASK, POWER10, 0, {XTP, RA0, RB}}, 7892 7893{"mtpmr", X(31,462), X_MASK, PPCPMR|PPCE300, 0, {PMR, RS}}, 7894{"mttmr", X(31,494), X_MASK, PPCTMR, 0, {TMR, RS}}, 7895 7896{"slbieg", X(31,466), XRA_MASK, POWER9, 0, {RS, RB}}, 7897 7898{"mtmq", XSPR(31,467, 0), XSPR_MASK, M601, EXT, {RS}}, 7899{"mtxer", XSPR(31,467, 1), XSPR_MASK, COM, EXT, {RS}}, 7900{"mtudscr", XSPR(31,467, 3), XSPR_MASK, POWER9, EXT, {RS}}, 7901{"mtlr", XSPR(31,467, 8), XSPR_MASK, COM, EXT, {RS}}, 7902{"mtctr", XSPR(31,467, 9), XSPR_MASK, COM, EXT, {RS}}, 7903{"mtuamr", XSPR(31,467, 13), XSPR_MASK, POWER9, EXT, {RS}}, 7904{"mtdscr", XSPR(31,467, 17), XSPR_MASK, POWER6, EXT, {RS}}, 7905{"mttid", XSPR(31,467, 17), XSPR_MASK, POWER, EXT, {RS}}, 7906{"mtdsisr", XSPR(31,467, 18), XSPR_MASK, COM, TITAN|EXT, {RS}}, 7907{"mtdar", XSPR(31,467, 19), XSPR_MASK, COM, TITAN|EXT, {RS}}, 7908{"mtrtcu", XSPR(31,467, 20), XSPR_MASK, COM, TITAN|EXT, {RS}}, 7909{"mtrtcl", XSPR(31,467, 21), XSPR_MASK, COM, TITAN|EXT, {RS}}, 7910{"mtdec", XSPR(31,467, 22), XSPR_MASK, COM, EXT, {RS}}, 7911{"mtsdr0", XSPR(31,467, 24), XSPR_MASK, POWER, EXT, {RS}}, 7912{"mtsdr1", XSPR(31,467, 25), XSPR_MASK, COM, TITAN|EXT, {RS}}, 7913{"mtsrr0", XSPR(31,467, 26), XSPR_MASK, COM, EXT, {RS}}, 7914{"mtsrr1", XSPR(31,467, 27), XSPR_MASK, COM, EXT, {RS}}, 7915{"mtcfar", XSPR(31,467, 28), XSPR_MASK, POWER6, EXT, {RS}}, 7916{"mtamr", XSPR(31,467, 29), XSPR_MASK, POWER7, EXT, {RS}}, 7917{"mtpidr", XSPR(31,467, 48), XSPR_MASK, POWER10, EXT, {RS}}, 7918{"mtpid", XSPR(31,467, 48), XSPR_MASK, BOOKE, EXT, {RS}}, 7919{"mtdecar", XSPR(31,467, 54), XSPR_MASK, BOOKE, EXT, {RS}}, 7920{"mtcsrr0", XSPR(31,467, 58), XSPR_MASK, BOOKE, EXT, {RS}}, 7921{"mtcsrr1", XSPR(31,467, 59), XSPR_MASK, BOOKE, EXT, {RS}}, 7922{"mtiamr", XSPR(31,467, 61), XSPR_MASK, POWER10, EXT, {RS}}, 7923{"mtdear", XSPR(31,467, 61), XSPR_MASK, BOOKE, EXT, {RS}}, 7924{"mtesr", XSPR(31,467, 62), XSPR_MASK, BOOKE, EXT, {RS}}, 7925{"mtivpr", XSPR(31,467, 63), XSPR_MASK, BOOKE, EXT, {RS}}, 7926{"mttfhar", XSPR(31,467,128), XSPR_MASK, POWER9, EXT, {RS}}, 7927{"mttfiar", XSPR(31,467,129), XSPR_MASK, POWER9, EXT, {RS}}, 7928{"mttexasr", XSPR(31,467,130), XSPR_MASK, POWER9, EXT, {RS}}, 7929{"mttexasru", XSPR(31,467,131), XSPR_MASK, POWER9, EXT, {RS}}, 7930{"mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, EXT, {RS}}, 7931{"mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, EXT, {RS}}, 7932{"mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, EXT, {RS}}, 7933{"mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, EXT, {RS}}, 7934{"mticr", XSPR(31,467,148), XSPR_MASK, PPC860, EXT, {RS}}, 7935{"mtder", XSPR(31,467,149), XSPR_MASK, PPC860, EXT, {RS}}, 7936{"mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, EXT, {RS}}, 7937{"mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, EXT, {RS}}, 7938{"mtctrl", XSPR(31,467,152), XSPR_MASK, POWER4, EXT, {RS}}, 7939{"mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, EXT, {RS}}, 7940{"mtfscr", XSPR(31,467,153), XSPR_MASK, POWER10, EXT, {RS}}, 7941{"mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, EXT, {RS}}, 7942{"mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, EXT, {RS}}, 7943{"mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, EXT, {RS}}, 7944{"mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, EXT, {RS}}, 7945{"mtuamor", XSPR(31,467,157), XSPR_MASK, POWER7, EXT, {RS}}, 7946{"mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, EXT, {RS}}, 7947{"mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, EXT, {RS}}, 7948{"mtpspb", XSPR(31,467,159), XSPR_MASK, POWER10, EXT, {RS}}, 7949{"mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, EXT, {RS}}, 7950{"mtdpdes", XSPR(31,467,176), XSPR_MASK, POWER10, EXT, {RS}}, 7951{"mtdawr0", XSPR(31,467,180), XSPR_MASK, POWER10, EXT, {RS}}, 7952{"mtdawr1", XSPR(31,467,181), XSPR_MASK, POWER10, EXT, {RS}}, 7953{"mtrpr", XSPR(31,467,186), XSPR_MASK, POWER10, EXT, {RS}}, 7954{"mtciabr", XSPR(31,467,187), XSPR_MASK, POWER10, EXT, {RS}}, 7955{"mtdawrx0", XSPR(31,467,188), XSPR_MASK, POWER10, EXT, {RS}}, 7956{"mtdawrx1", XSPR(31,467,189), XSPR_MASK, POWER10, EXT, {RS}}, 7957{"mthfscr", XSPR(31,467,190), XSPR_MASK, POWER10, EXT, {RS}}, 7958{"mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, EXT, {RS}}, 7959{"mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, EXT, {RS}}, 7960{"mtsprg", XSPR(31,467,256), XSPRG_MASK, PPC, EXT, {SPRG, RS}}, 7961{"mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, EXT, {RS}}, 7962{"mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, EXT, {RS}}, 7963{"mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, EXT, {RS}}, 7964{"mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, EXT, {RS}}, 7965{"mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405|BOOKE, EXT, {RS}}, 7966{"mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405|BOOKE, EXT, {RS}}, 7967{"mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405|BOOKE, EXT, {RS}}, 7968{"mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405|BOOKE, EXT, {RS}}, 7969{"mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, EXT, {RS}}, 7970{"mtear", XSPR(31,467,282), XSPR_MASK, PPC, TITAN|EXT, {RS}}, 7971{"mttbl", XSPR(31,467,284), XSPR_MASK, PPC, EXT, {RS}}, 7972{"mttbu", XSPR(31,467,285), XSPR_MASK, PPC, EXT, {RS}}, 7973{"mttbu40", XSPR(31,467,286), XSPR_MASK, POWER10, EXT, {RS}}, 7974{"mthsprg0", XSPR(31,467,304), XSPR_MASK, POWER10, EXT, {RS}}, 7975{"mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, EXT, {RS}}, 7976{"mthsprg1", XSPR(31,467,305), XSPR_MASK, POWER10, EXT, {RS}}, 7977{"mthdisr", XSPR(31,467,306), XSPR_MASK, POWER10, EXT, {RS}}, 7978{"mthdar", XSPR(31,467,307), XSPR_MASK, POWER10, EXT, {RS}}, 7979{"mtspurr", XSPR(31,467,308), XSPR_MASK, POWER10, EXT, {RS}}, 7980{"mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, EXT, {RS}}, 7981{"mtpurr", XSPR(31,467,309), XSPR_MASK, POWER10, EXT, {RS}}, 7982{"mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, EXT, {RS}}, 7983{"mthdec", XSPR(31,467,310), XSPR_MASK, POWER10, EXT, {RS}}, 7984{"mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, EXT, {RS}}, 7985{"mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, EXT, {RS}}, 7986{"mthrmor", XSPR(31,467,313), XSPR_MASK, POWER10, EXT, {RS}}, 7987{"mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, EXT, {RS}}, 7988{"mthsrr0", XSPR(31,467,314), XSPR_MASK, POWER10, EXT, {RS}}, 7989{"mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, EXT, {RS}}, 7990{"mthsrr1", XSPR(31,467,315), XSPR_MASK, POWER10, EXT, {RS}}, 7991{"mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, EXT, {RS}}, 7992{"mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, EXT, {RS}}, 7993{"mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, EXT, {RS}}, 7994{"mtlpcr", XSPR(31,467,318), XSPR_MASK, POWER10, EXT, {RS}}, 7995{"mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, EXT, {RS}}, 7996{"mtlpidr", XSPR(31,467,319), XSPR_MASK, POWER10, EXT, {RS}}, 7997{"mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, EXT, {RS}}, 7998{"mthmer", XSPR(31,467,336), XSPR_MASK, POWER7, EXT, {RS}}, 7999{"mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, EXT, {RS}}, 8000{"mthmeer", XSPR(31,467,337), XSPR_MASK, POWER7, EXT, {RS}}, 8001{"mtpcr", XSPR(31,467,338), XSPR_MASK, POWER10, EXT, {RS}}, 8002{"mtheir", XSPR(31,467,339), XSPR_MASK, POWER10, EXT, {RS}}, 8003{"mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, EXT, {RS}}, 8004{"mtamor", XSPR(31,467,349), XSPR_MASK, POWER7, EXT, {RS}}, 8005{"mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, EXT, {RS}}, 8006{"mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, EXT, {RS}}, 8007{"mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, EXT, {RS}}, 8008{"mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, EXT, {RS}}, 8009{"mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, EXT, {RS}}, 8010{"mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, EXT, {RS}}, 8011{"mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, EXT, {RS}}, 8012{"mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, EXT, {RS}}, 8013{"mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, EXT, {RS}}, 8014{"mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, EXT, {RS}}, 8015{"mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, EXT, {RS}}, 8016{"mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, EXT, {RS}}, 8017{"mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, EXT, {RS}}, 8018{"mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, EXT, {RS}}, 8019{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, EXT, {RS}}, 8020{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, EXT, {RS}}, 8021{"mtptcr", XSPR(31,467,464), XSPR_MASK, POWER10, EXT, {RS}}, 8022{"mtusprg0", XSPR(31,467,496), XSPR_MASK, POWER10, EXT, {RS}}, 8023{"mtusprg1", XSPR(31,467,497), XSPR_MASK, POWER10, EXT, {RS}}, 8024{"mturmor", XSPR(31,467,505), XSPR_MASK, POWER10, EXT, {RS}}, 8025{"mtusrr0", XSPR(31,467,506), XSPR_MASK, POWER10, EXT, {RS}}, 8026{"mtusrr1", XSPR(31,467,507), XSPR_MASK, POWER10, EXT, {RS}}, 8027{"mtsmfctrl", XSPR(31,467,511), XSPR_MASK, POWER10, EXT, {RS}}, 8028{"mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, EXT, {RS}}, 8029{"mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, EXT, {RS}}, 8030{"mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, EXT, {RS}}, 8031{"mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE|E6500, EXT, {RS}}, 8032{"mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE|E6500, EXT, {RS}}, 8033{"mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, EXT, {RS}}, 8034{"mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, EXT, {RS}}, 8035{"mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, TITAN|EXT, {SPRBAT, RS}}, 8036{"mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, TITAN|EXT, {SPRBAT, RS}}, 8037{"mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, TITAN|EXT, {SPRBAT, RS}}, 8038{"mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, TITAN|EXT, {SPRBAT, RS}}, 8039{"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, EXT, {RS}}, 8040{"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, EXT, {RS}}, 8041{"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, EXT, {RS}}, 8042{"mtsier2", XSPR(31,467,752), XSPR_MASK, POWER10, EXT, {RS}}, 8043{"mtsier3", XSPR(31,467,753), XSPR_MASK, POWER10, EXT, {RS}}, 8044{"mtmmcr3", XSPR(31,467,754), XSPR_MASK, POWER10, EXT, {RS}}, 8045{"mtummcr2", XSPR(31,467,769), XSPR_MASK, POWER9, EXT, {RS}}, 8046{"mtmmcr2", XSPR(31,467,769), XSPR_MASK, POWER9, EXT, {RS}}, 8047{"mtummcra", XSPR(31,467,770), XSPR_MASK, POWER9, EXT, {RS}}, 8048{"mtupmc1", XSPR(31,467,771), XSPR_MASK, POWER9, EXT, {RS}}, 8049{"mtupmc2", XSPR(31,467,772), XSPR_MASK, POWER9, EXT, {RS}}, 8050{"mtupmc3", XSPR(31,467,773), XSPR_MASK, POWER9, EXT, {RS}}, 8051{"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, EXT, {RS}}, 8052{"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, EXT, {RS}}, 8053{"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, EXT, {RS}}, 8054{"mtummcr0", XSPR(31,467,779), XSPR_MASK, POWER9, EXT, {RS}}, 8055{"mtsier", XSPR(31,467,784), XSPR_MASK, POWER10, EXT, {RS}}, 8056{"mtmmcra", XSPR(31,467,786), XSPR_MASK, POWER7, EXT, {RS}}, 8057{"mtpmc1", XSPR(31,467,787), XSPR_MASK, POWER7, EXT, {RS}}, 8058{"mtpmc2", XSPR(31,467,788), XSPR_MASK, POWER7, EXT, {RS}}, 8059{"mtpmc3", XSPR(31,467,789), XSPR_MASK, POWER7, EXT, {RS}}, 8060{"mtpmc4", XSPR(31,467,790), XSPR_MASK, POWER7, EXT, {RS}}, 8061{"mtpmc5", XSPR(31,467,791), XSPR_MASK, POWER7, EXT, {RS}}, 8062{"mtpmc6", XSPR(31,467,792), XSPR_MASK, POWER7, EXT, {RS}}, 8063{"mtmmcr0", XSPR(31,467,795), XSPR_MASK, POWER7, EXT, {RS}}, 8064{"mtsiar", XSPR(31,467,796), XSPR_MASK, POWER10, EXT, {RS}}, 8065{"mtsdar", XSPR(31,467,797), XSPR_MASK, POWER10, EXT, {RS}}, 8066{"mtmmcr1", XSPR(31,467,798), XSPR_MASK, POWER7, EXT, {RS}}, 8067{"mtbescrs", XSPR(31,467,800), XSPR_MASK, POWER9, EXT, {RS}}, 8068{"mtbescrsu", XSPR(31,467,801), XSPR_MASK, POWER9, EXT, {RS}}, 8069{"mtbescrr", XSPR(31,467,802), XSPR_MASK, POWER9, EXT, {RS}}, 8070{"mtbescrru", XSPR(31,467,803), XSPR_MASK, POWER9, EXT, {RS}}, 8071{"mtebbhr", XSPR(31,467,804), XSPR_MASK, POWER9, EXT, {RS}}, 8072{"mtebbrr", XSPR(31,467,805), XSPR_MASK, POWER9, EXT, {RS}}, 8073{"mtbescr", XSPR(31,467,806), XSPR_MASK, POWER9, EXT, {RS}}, 8074{"mttar", XSPR(31,467,815), XSPR_MASK, POWER9, EXT, {RS}}, 8075{"mtasdr", XSPR(31,467,816), XSPR_MASK, POWER10, EXT, {RS}}, 8076{"mtpsscr", XSPR(31,467,823), XSPR_MASK, POWER10, EXT, {RS}}, 8077{"mtic", XSPR(31,467,848), XSPR_MASK, POWER8, EXT, {RS}}, 8078{"mtvtb", XSPR(31,467,849), XSPR_MASK, POWER8, EXT, {RS}}, 8079{"mthpsscr", XSPR(31,467,855), XSPR_MASK, POWER10, EXT, {RS}}, 8080{"mtivndx", XSPR(31,467,880), XSPR_MASK, TITAN, EXT, {RS}}, 8081{"mtdvndx", XSPR(31,467,881), XSPR_MASK, TITAN, EXT, {RS}}, 8082{"mtivlim", XSPR(31,467,882), XSPR_MASK, TITAN, EXT, {RS}}, 8083{"mtdvlim", XSPR(31,467,883), XSPR_MASK, TITAN, EXT, {RS}}, 8084{"mtclcsr", XSPR(31,467,884), XSPR_MASK, TITAN, EXT, {RS}}, 8085{"mtccr1", XSPR(31,467,888), XSPR_MASK, TITAN, EXT, {RS}}, 8086{"mtppr", XSPR(31,467,896), XSPR_MASK, POWER5, EXT, {RS}}, 8087{"mtppr32", XSPR(31,467,898), XSPR_MASK, POWER5, EXT, {RS}}, 8088{"mtgqr", XSPR(31,467,912), XSPRGQR_MASK, PPCPS, EXT, {SPRGQR, RS}}, 8089{"mthid2", XSPR(31,467,920), XSPR_MASK, GEKKO, EXT, {RS}}, 8090{"mtwpar", XSPR(31,467,921), XSPR_MASK, GEKKO, EXT, {RS}}, 8091{"mtdmau", XSPR(31,467,922), XSPR_MASK, GEKKO, EXT, {RS}}, 8092{"mtdmal", XSPR(31,467,923), XSPR_MASK, GEKKO, EXT, {RS}}, 8093{"mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, EXT, {RS}}, 8094{"mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, EXT, {RS}}, 8095{"mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, EXT, {RS}}, 8096{"mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, EXT, {RS}}, 8097{"mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, EXT, {RS}}, 8098{"mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, EXT, {RS}}, 8099{"mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, EXT, {RS}}, 8100{"mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, EXT, {RS}}, 8101{"mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, EXT, {RS}}, 8102{"mtrmmucr", XSPR(31,467,946), XSPR_MASK, TITAN, EXT, {RS}}, 8103{"mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405|TITAN, EXT, {RS}}, 8104{"mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, EXT, {RS}}, 8105{"mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, EXT, {RS}}, 8106{"mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, EXT, {RS}}, 8107{"mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, EXT, {RS}}, 8108{"mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, EXT, {RS}}, 8109{"mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, EXT, {RS}}, 8110{"mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, EXT, {RS}}, 8111{"mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, EXT, {RS}}, 8112{"mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, EXT, {RS}}, 8113{"mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, EXT, {RS}}, 8114{"mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, EXT, {RS}}, 8115{"mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, EXT, {RS}}, 8116{"mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, EXT, {RS}}, 8117{"mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, EXT, {RS}}, 8118{"mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, EXT, {RS}}, 8119{"mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, EXT, {RS}}, 8120{"mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, EXT, {RS}}, 8121{"mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, EXT, {RS}}, 8122{"mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, EXT, {RS}}, 8123{"mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, EXT, {RS}}, 8124{"mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, EXT, {RS}}, 8125{"mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, EXT, {RS}}, 8126{"mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, EXT, {RS}}, 8127{"mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, EXT, {RS}}, 8128{"mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, EXT, {RS}}, 8129{"mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, EXT, {RS}}, 8130{"mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, EXT, {RS}}, 8131{"mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, EXT, {RS}}, 8132{"mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, EXT, {RS}}, 8133{"mthid0", XSPR(31,467,1008), XSPR_MASK, GEKKO, EXT, {RS}}, 8134{"mthid1", XSPR(31,467,1009), XSPR_MASK, GEKKO, EXT, {RS}}, 8135{"mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, EXT, {RS}}, 8136{"mtiabr", XSPR(31,467,1010), XSPR_MASK, GEKKO, EXT, {RS}}, 8137{"mthid4", XSPR(31,467,1011), XSPR_MASK, BROADWAY, EXT, {RS}}, 8138{"mtdbdr", XSPR(31,467,1011), XSPR_MASK, TITAN, EXT, {RS}}, 8139{"mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, EXT, {RS}}, 8140{"mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, EXT, {RS}}, 8141{"mtdabr", XSPR(31,467,1013), XSPR_MASK, PPC750, EXT, {RS}}, 8142{"mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, EXT, {RS}}, 8143{"mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, EXT, {RS}}, 8144{"mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, EXT, {RS}}, 8145{"mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, EXT, {RS}}, 8146{"mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, EXT, {RS}}, 8147{"mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, EXT, {RS}}, 8148{"mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, EXT, {RS}}, 8149{"mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, EXT, {RS}}, 8150{"mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, EXT, {RS}}, 8151{"mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, EXT, {RS}}, 8152{"mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, EXT, {RS}}, 8153{"mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, EXT, {RS}}, 8154{"mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, EXT, {RS}}, 8155{"mtspr", X(31,467), X_MASK, COM, 0, {SPR, RS}}, 8156 8157{"dcbi", X(31,470), XRT_MASK, PPC, 0, {RA0, RB}}, 8158 8159{"nand", XRC(31,476,0), X_MASK, COM, 0, {RA, RS, RB}}, 8160{"nand.", XRC(31,476,1), X_MASK, COM, 0, {RA, RS, RB}}, 8161 8162{"setnbcr", X(31,480), XRB_MASK, POWER10, 0, {RT, BI}}, 8163 8164{"dsn", X(31,483), XRT_MASK, E500MC, 0, {RA, RB}}, 8165 8166{"dcread", X(31,486), X_MASK, PPC403|PPC440, PPCA2, {RT, RA0, RB}}, 8167 8168{"icbtls", X(31,486), X_MASK, PPCCHLK|PPC476|TITAN, 0, {CT, RA0, RB}}, 8169 8170{"stvxl", X(31,487), X_MASK, PPCVEC, 0, {VS, RA0, RB}}, 8171 8172{"nabs", XO(31,488,0,0), XORB_MASK, M601, 0, {RT, RA}}, 8173{"nabs.", XO(31,488,0,1), XORB_MASK, M601, 0, {RT, RA}}, 8174 8175{"divd", XO(31,489,0,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 8176{"divd.", XO(31,489,0,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 8177 8178{"divw", XO(31,491,0,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 8179{"divw.", XO(31,491,0,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 8180 8181{"icbtlse", X(31,494), X_MASK, PPCCHLK, E500MC, {CT, RA, RB}}, 8182 8183{"slbia", X(31,498), 0xff1fffff, POWER6, 0, {IH}}, 8184{"slbia", X(31,498), 0xffffffff, PPC64, POWER6, {0}}, 8185 8186{"cli", X(31,502), XRB_MASK, POWER, 0, {RT, RA}}, 8187 8188{"popcntd", X(31,506), XRB_MASK, POWER7|PPCA2, 0, {RA, RS}}, 8189 8190{"cmpb", X(31,508), X_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS, RB}}, 8191 8192{"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}}, 8193 8194{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}}, 8195{"lbdx", X(31,515), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, 8196 8197{"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}}, 8198 8199{"lvlx", X(31,519), X_MASK, CELL, 0, {VD, RA0, RB}}, 8200{"lbfcmux", APU(31,519,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8201 8202{"subfco", XO(31,8,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8203{"sfo", XO(31,8,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8204{"subco", XO(31,8,1,0), XO_MASK, PPCCOM, EXT, {RT, RB, RA}}, 8205{"subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8206{"sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8207{"subco.", XO(31,8,1,1), XO_MASK, PPCCOM, EXT, {RT, RB, RA}}, 8208 8209{"addco", XO(31,10,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8210{"ao", XO(31,10,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8211{"addco.", XO(31,10,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8212{"ao.", XO(31,10,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8213 8214{"lxsspx", X(31,524), XX1_MASK, PPCVSX2, 0, {XT6, RA0, RB}}, 8215 8216{"clcs", X(31,531), XRB_MASK, M601, 0, {RT, RA}}, 8217 8218{"ldbrx", X(31,532), X_MASK, CELL|POWER7|PPCA2, 0, {RT, RA0, RB}}, 8219 8220{"lswx", X(31,533), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, RBX}}, 8221{"lsx", X(31,533), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 8222 8223{"lwbrx", X(31,534), X_MASK, PPCCOM, 0, {RT, RA0, RB}}, 8224{"lbrx", X(31,534), X_MASK, PWRCOM, 0, {RT, RA, RB}}, 8225 8226{"lfsx", X(31,535), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, 8227 8228{"srw", XRC(31,536,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 8229{"sr", XRC(31,536,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 8230{"srw.", XRC(31,536,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 8231{"sr.", XRC(31,536,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 8232 8233{"rrib", XRC(31,537,0), X_MASK, M601, 0, {RA, RS, RB}}, 8234{"rrib.", XRC(31,537,1), X_MASK, M601, 0, {RA, RS, RB}}, 8235 8236{"cnttzw", XRC(31,538,0), XRB_MASK, POWER9, 0, {RA, RS}}, 8237{"cnttzw.", XRC(31,538,1), XRB_MASK, POWER9, 0, {RA, RS}}, 8238 8239{"srd", XRC(31,539,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 8240{"srd.", XRC(31,539,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 8241 8242{"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}}, 8243{"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}}, 8244 8245{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}}, 8246{"lhdx", X(31,547), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, 8247 8248{"lvtrx", X(31,549), X_MASK, E6500, 0, {VD, RA0, RB}}, 8249 8250{"bbelr", X(31,550), X_MASK, PPCBRLK, 0, {0}}, 8251 8252{"lvrx", X(31,551), X_MASK, CELL, 0, {VD, RA0, RB}}, 8253{"lhfcmux", APU(31,551,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8254 8255{"subfo", XO(31,40,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 8256{"subo", XO(31,40,1,0), XO_MASK, PPC, EXT, {RT, RB, RA}}, 8257{"subfo.", XO(31,40,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 8258{"subo.", XO(31,40,1,1), XO_MASK, PPC, EXT, {RT, RB, RA}}, 8259 8260{"tlbsync", X(31,566), 0xffffffff, PPC, 0, {0}}, 8261 8262{"lfsux", X(31,567), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, 8263 8264{"cnttzd", XRC(31,570,0), XRB_MASK, POWER9, 0, {RA, RS}}, 8265{"cnttzd.", XRC(31,570,1), XRB_MASK, POWER9, 0, {RA, RS}}, 8266 8267{"cnttzdm", X(31,571), X_MASK, POWER10, 0, {RA, RS, RB}}, 8268 8269{"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}}, 8270 8271{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}}, 8272{"lwdx", X(31,579), X_MASK, E500MC|E200Z4, 0, {RT, RA, RB}}, 8273 8274{"lvtlx", X(31,581), X_MASK, E6500, 0, {VD, RA0, RB}}, 8275 8276{"lwat", X(31,582), X_MASK, POWER9, 0, {RT, RA0, FC}}, 8277 8278{"lwfcmux", APU(31,583,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8279 8280{"lxsdx", X(31,588), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 8281 8282{"mfsr", X(31,595), XRB_MASK|(1<<20), COM, NON32, {RT, SR}}, 8283 8284{"lswi", X(31,597), X_MASK, PPCCOM, E500|E500MC, {RT, RAX, NBI}}, 8285{"lsi", X(31,597), X_MASK, PWRCOM, 0, {RT, RA0, NB}}, 8286 8287{"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476|EXT, {0}}, 8288{"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500|EXT, {0}}, 8289{"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, EXT, {0}}, 8290{"phwsync", XSYNCLS(31,598,4,0), 0xffffffff, POWER10, EXT, {0}}, 8291{"plwsync", XSYNCLS(31,598,5,0), 0xffffffff, POWER10, EXT, {0}}, 8292{"stncisync", XSYNCLS(31,598,1,1), 0xffffffff, POWER10, EXT, {0}}, 8293{"stcisync", XSYNCLS(31,598,0,2), 0xffffffff, POWER10, EXT, {0}}, 8294{"stsync", XSYNCLS(31,598,0,3), 0xffffffff, POWER10, EXT, {0}}, 8295{"sync", X(31,598), XSYNCLS_MASK, POWER10, BOOKE|PPC476, {LS3, SC2}}, 8296{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}}, 8297{"sync", X(31,598), XSYNC_MASK, PPCCOM, POWER10|BOOKE|PPC476, {LS}}, 8298{"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}}, 8299{"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}}, 8300{"lwsync", X(31,598), 0xffffffff, E500, 0, {0}}, 8301{"dcs", X(31,598), 0xffffffff, PWRCOM, 0, {0}}, 8302 8303{"lfdx", X(31,599), X_MASK, COM, PPCEFS, {FRT, RA0, RB}}, 8304 8305{"mffgpr", XRC(31,607,0), XRA_MASK, POWER6, POWER7, {FRT, RB}}, 8306{"lfdepx", X(31,607), X_MASK, E500MC|PPCA2, 0, {FRT, RA0, RB}}, 8307 8308{"lddx", X(31,611), X_MASK, E500MC, 0, {RT, RA, RB}}, 8309 8310{"lvswx", X(31,613), X_MASK, E6500, 0, {VD, RA0, RB}}, 8311 8312{"ldat", X(31,614), X_MASK, POWER9, 0, {RT, RA0, FC}}, 8313 8314{"lqfcmux", APU(31,615,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8315 8316{"nego", XO(31,104,1,0), XORB_MASK, COM, 0, {RT, RA}}, 8317{"nego.", XO(31,104,1,1), XORB_MASK, COM, 0, {RT, RA}}, 8318 8319{"mulo", XO(31,107,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 8320{"mulo.", XO(31,107,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 8321 8322{"mfsri", X(31,627), X_MASK, M601, 0, {RT, RA, RB}}, 8323 8324{"dclst", X(31,630), XRB_MASK, M601, 0, {RS, RA}}, 8325 8326{"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}}, 8327 8328{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}}, 8329{"stbdx", X(31,643), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, 8330 8331{"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}}, 8332{"stbfcmux", APU(31,647,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8333 8334{"stxsspx", X(31,652), XX1_MASK, PPCVSX2, 0, {XS6, RA0, RB}}, 8335 8336{"tbegin.", XRC(31,654,1), XRTLRARB_MASK, PPCHTM, 0, {HTM_R}}, 8337 8338{"subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8339{"sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8340{"subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8341{"sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8342 8343{"addeo", XO(31,138,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8344{"aeo", XO(31,138,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8345{"addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8346{"aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8347 8348{"hashstp", X(31,658), XRC_MASK, POWER8, 0, {RB, DW, RA0}}, 8349 8350{"mfsrin", X(31,659), XRA_MASK, PPC, NON32, {RT, RB}}, 8351 8352{"stdbrx", X(31,660), X_MASK, CELL|POWER7|PPCA2, 0, {RS, RA0, RB}}, 8353 8354{"stswx", X(31,661), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, RB}}, 8355{"stsx", X(31,661), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 8356 8357{"stwbrx", X(31,662), X_MASK, PPCCOM, 0, {RS, RA0, RB}}, 8358{"stbrx", X(31,662), X_MASK, PWRCOM, 0, {RS, RA0, RB}}, 8359 8360{"stfsx", X(31,663), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, 8361 8362{"srq", XRC(31,664,0), X_MASK, M601, 0, {RA, RS, RB}}, 8363{"srq.", XRC(31,664,1), X_MASK, M601, 0, {RA, RS, RB}}, 8364 8365{"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}}, 8366{"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}}, 8367 8368{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}}, 8369{"sthdx", X(31,675), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, 8370 8371{"stvfrx", X(31,677), X_MASK, E6500, 0, {VS, RA0, RB}}, 8372 8373{"stvrx", X(31,679), X_MASK, CELL, 0, {VS, RA0, RB}}, 8374{"sthfcmux", APU(31,679,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8375 8376{"tendall.", XRC(31,686,1)|(1<<25), XRTRARB_MASK, PPCHTM, 0, {0}}, 8377{"tend.", XRC(31,686,1), XRTARARB_MASK, PPCHTM, 0, {HTM_A}}, 8378 8379{"hashchkp", X(31,690), XRC_MASK, POWER8, 0, {RB, DW, RA0}}, 8380 8381{"stbcx.", XRC(31,694,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, 8382 8383{"stfsux", X(31,695), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, 8384 8385{"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}}, 8386{"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}}, 8387 8388{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}}, 8389{"stwdx", X(31,707), X_MASK, E500MC|E200Z4, 0, {RS, RA, RB}}, 8390 8391{"stvflx", X(31,709), X_MASK, E6500, 0, {VS, RA0, RB}}, 8392 8393{"stwat", X(31,710), X_MASK, POWER9, 0, {RS, RA0, FC}}, 8394 8395{"stwfcmux", APU(31,711,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8396 8397{"stxsdx", X(31,716), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 8398 8399{"tcheck", X(31,718), XRTBFRARB_MASK, PPCHTM, 0, {BF}}, 8400 8401{"subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 8402{"sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 8403{"subfzeo.", XO(31,200,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 8404{"sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 8405 8406{"addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 8407{"azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 8408{"addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 8409{"azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 8410 8411{"hashst", X(31,722), XRC_MASK, POWER8, 0, {RB, DW, RA0}}, 8412 8413{"stswi", X(31,725), X_MASK, PPCCOM, E500|E500MC, {RS, RA0, NB}}, 8414{"stsi", X(31,725), X_MASK, PWRCOM, 0, {RS, RA0, NB}}, 8415 8416{"sthcx.", XRC(31,726,1), X_MASK, POWER8|E6500, 0, {RS, RA0, RB}}, 8417 8418{"stfdx", X(31,727), X_MASK, COM, PPCEFS, {FRS, RA0, RB}}, 8419 8420{"srlq", XRC(31,728,0), X_MASK, M601, 0, {RA, RS, RB}}, 8421{"srlq.", XRC(31,728,1), X_MASK, M601, 0, {RA, RS, RB}}, 8422 8423{"sreq", XRC(31,729,0), X_MASK, M601, 0, {RA, RS, RB}}, 8424{"sreq.", XRC(31,729,1), X_MASK, M601, 0, {RA, RS, RB}}, 8425 8426{"mftgpr", XRC(31,735,0), XRA_MASK, POWER6, POWER7, {RT, FRB}}, 8427{"stfdepx", X(31,735), X_MASK, E500MC|PPCA2, 0, {FRS, RA0, RB}}, 8428 8429{"stddx", X(31,739), X_MASK, E500MC, 0, {RS, RA, RB}}, 8430 8431{"stvswx", X(31,741), X_MASK, E6500, 0, {VS, RA0, RB}}, 8432 8433{"stdat", X(31,742), X_MASK, POWER9, 0, {RS, RA0, FC}}, 8434 8435{"stqfcmux", APU(31,743,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8436 8437{"subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 8438{"sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 8439{"subfmeo.", XO(31,232,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 8440{"sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 8441 8442{"mulldo", XO(31,233,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 8443{"mulldo.", XO(31,233,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 8444 8445{"addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, 0, {RT, RA}}, 8446{"ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, 0, {RT, RA}}, 8447{"addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, 0, {RT, RA}}, 8448{"ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, 0, {RT, RA}}, 8449 8450{"mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8451{"mulso", XO(31,235,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8452{"mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8453{"mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8454 8455{"tsuspend.", XRCL(31,750,0,1), XRTRARB_MASK,PPCHTM, EXT, {0}}, 8456{"tresume.", XRCL(31,750,1,1), XRTRARB_MASK,PPCHTM, EXT, {0}}, 8457{"tsr.", XRC(31,750,1), XRTLRARB_MASK,PPCHTM, 0, {L}}, 8458 8459{"hashchk", X(31,754), XRC_MASK, POWER8, 0, {RB, DW, RA0}}, 8460 8461{"darn", X(31,755), XLRAND_MASK, POWER9, 0, {RT, LRAND}}, 8462 8463{"dcba", X(31,758), XRT_MASK, PPC405|PPC7450|BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, 8464{"dcbal", XOPL(31,758,1), XRT_MASK, E500MC, 0, {RA0, RB}}, 8465 8466{"stfdux", X(31,759), X_MASK, COM, PPCEFS, {FRS, RAS, RB}}, 8467 8468{"srliq", XRC(31,760,0), X_MASK, M601, 0, {RA, RS, SH}}, 8469{"srliq.", XRC(31,760,1), X_MASK, M601, 0, {RA, RS, SH}}, 8470 8471{"lvsm", X(31,773), X_MASK, E6500, 0, {VD, RA0, RB}}, 8472 8473{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}}, 8474 8475{"stvepxl", X(31,775), X_MASK, E6500, 0, {VS, RA0, RB}}, 8476{"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}}, 8477{"ldfcmux", APU(31,775,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8478 8479{"dozo", XO(31,264,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 8480{"dozo.", XO(31,264,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 8481 8482{"addo", XO(31,266,1,0), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8483{"caxo", XO(31,266,1,0), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8484{"addo.", XO(31,266,1,1), XO_MASK, PPCCOM, 0, {RT, RA, RB}}, 8485{"caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, 0, {RT, RA, RB}}, 8486 8487{"modsd", X(31,777), X_MASK, POWER9, 0, {RT, RA, RB}}, 8488{"modsw", X(31,779), X_MASK, POWER9, 0, {RT, RA, RB}}, 8489 8490{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 8491{"lxsibzx", X(31,781), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 8492 8493{"tabortwc.", XRC(31,782,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, 8494 8495{"tlbivax", X(31,786), XRT_MASK, BOOKE|PPCA2|PPC476, 0, {RA0, RB}}, 8496 8497{"lwzcix", X(31,789), X_MASK, POWER6, 0, {RT, RA0, RB}}, 8498 8499{"lhbrx", X(31,790), X_MASK, COM, 0, {RT, RA0, RB}}, 8500 8501{"lfdpx", X(31,791), X_MASK|Q_MASK, POWER6, POWER7, {FRTp, RA0, RB}}, 8502{"lfqx", X(31,791), X_MASK, POWER2, 0, {FRT, RA, RB}}, 8503 8504{"sraw", XRC(31,792,0), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 8505{"sra", XRC(31,792,0), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 8506{"sraw.", XRC(31,792,1), X_MASK, PPCCOM, 0, {RA, RS, RB}}, 8507{"sra.", XRC(31,792,1), X_MASK, PWRCOM, 0, {RA, RS, RB}}, 8508 8509{"srad", XRC(31,794,0), X_MASK, PPC64, 0, {RA, RS, RB}}, 8510{"srad.", XRC(31,794,1), X_MASK, PPC64, 0, {RA, RS, RB}}, 8511 8512{"evlddepx", VX (31, 1598), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, 8513{"lfddx", X(31,803), X_MASK, E500MC, 0, {FRT, RA, RB}}, 8514 8515{"lvtrxl", X(31,805), X_MASK, E6500, 0, {VD, RA0, RB}}, 8516{"stvepx", X(31,807), X_MASK, E6500, 0, {VS, RA0, RB}}, 8517{"lvrxl", X(31,807), X_MASK, CELL, 0, {VD, RA0, RB}}, 8518 8519{"lxvh8x", X(31,812), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 8520{"lxsihzx", X(31,813), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 8521 8522{"tabortdc.", XRC(31,814,1), X_MASK, PPCHTM, 0, {TO, RA, RB}}, 8523 8524{"rac", X(31,818), X_MASK, M601, 0, {RT, RA, RB}}, 8525 8526{"erativax", X(31,819), X_MASK, PPCA2, 0, {RS, RA0, RB}}, 8527 8528{"lhzcix", X(31,821), X_MASK, POWER6, 0, {RT, RA0, RB}}, 8529 8530{"dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, 0, {STRM}}, 8531{"dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, 0, {0}}, 8532 8533{"lfqux", X(31,823), X_MASK, POWER2, 0, {FRT, RA, RB}}, 8534 8535{"srawi", XRC(31,824,0), X_MASK, PPCCOM, 0, {RA, RS, SH}}, 8536{"srai", XRC(31,824,0), X_MASK, PWRCOM, 0, {RA, RS, SH}}, 8537{"srawi.", XRC(31,824,1), X_MASK, PPCCOM, 0, {RA, RS, SH}}, 8538{"srai.", XRC(31,824,1), X_MASK, PWRCOM, 0, {RA, RS, SH}}, 8539 8540{"sradi", XS(31,413,0), XS_MASK, PPC64, 0, {RA, RS, SH6}}, 8541{"sradi.", XS(31,413,1), XS_MASK, PPC64, 0, {RA, RS, SH6}}, 8542 8543{"lvtlxl", X(31,837), X_MASK, E6500, 0, {VD, RA0, RB}}, 8544 8545{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}}, 8546 8547{"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 8548{"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 8549 8550{"lxvd2x", X(31,844), XX1_MASK, PPCVSX, 0, {XT6, RA0, RB}}, 8551{"lxvx", X(31,844), XX1_MASK, POWER8, POWER9|PPCVSX3, {XT6, RA0, RB}}, 8552 8553{"tabortwci.", XRC(31,846,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, 8554 8555{"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}}, 8556 8557{"slbiag", X(31,850), XRLARB_MASK, POWER10, 0, {RS, A_L}}, 8558{"slbiag", X(31,850), XRARB_MASK, POWER9, POWER10, {RS}}, 8559 8560{"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, 8561{"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}}, 8562 8563{"lbzcix", X(31,853), X_MASK, POWER6, 0, {RT, RA0, RB}}, 8564 8565{"eieio", X(31,854), 0xffffffff, PPC, BOOKE|PPCA2|PPC476, {0}}, 8566{"mbar", X(31,854), X_MASK, BOOKE|PPCA2|PPC476, 0, {MO}}, 8567{"eieio", XMBAR(31,854,1),0xffffffff, E500, 0, {0}}, 8568{"eieio", X(31,854), 0xffffffff, PPCA2|PPC476, 0, {0}}, 8569 8570{"lfiwax", X(31,855), X_MASK, POWER6|PPCA2|PPC476, 0, {FRT, RA0, RB}}, 8571 8572{"lvswxl", X(31,869), X_MASK, E6500, 0, {VD, RA0, RB}}, 8573 8574{"abso", XO(31,360,1,0), XORB_MASK, M601, 0, {RT, RA}}, 8575{"abso.", XO(31,360,1,1), XORB_MASK, M601, 0, {RT, RA}}, 8576 8577{"divso", XO(31,363,1,0), XO_MASK, M601, 0, {RT, RA, RB}}, 8578{"divso.", XO(31,363,1,1), XO_MASK, M601, 0, {RT, RA, RB}}, 8579 8580{"lxvb16x", X(31,876), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}}, 8581 8582{"tabortdci.", XRC(31,878,1), X_MASK, PPCHTM, 0, {TO, RA, HTM_SI}}, 8583 8584{"rmieg", X(31,882), XRTRA_MASK, POWER9, 0, {RB}}, 8585 8586{"ldcix", X(31,885), X_MASK, POWER6, 0, {RT, RA0, RB}}, 8587 8588{"msgsync", X(31,886), 0xffffffff, POWER9, 0, {0}}, 8589 8590{"lfiwzx", X(31,887), X_MASK, POWER7|PPCA2, 0, {FRT, RA0, RB}}, 8591 8592{"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}}, 8593{"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}}, 8594 8595{"paste.", XRC(31,902,1), XLRT_MASK, POWER10, 0, {RA0, RB, L1OPT}}, 8596{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, POWER10, {RA0, RB}}, 8597 8598{"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}}, 8599{"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}}, 8600 8601{"divdeuo", XO(31,393,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 8602{"divdeuo.", XO(31,393,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 8603{"divweuo", XO(31,395,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 8604{"divweuo.", XO(31,395,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 8605 8606{"stxvw4x", X(31,908), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 8607{"stxsibx", X(31,909), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 8608 8609{"tabort.", XRC(31,910,1), XRTRB_MASK, PPCHTM, 0, {RA}}, 8610 8611{"tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, 8612{"tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RTO, RA0, RB}}, 8613 8614{"slbmfee", X(31,915), XRLA_MASK, POWER9, 0, {RT, RB, A_L}}, 8615{"slbmfee", X(31,915), XRA_MASK, PPC64, POWER9, {RT, RB}}, 8616 8617{"stwcix", X(31,917), X_MASK, POWER6, 0, {RS, RA0, RB}}, 8618 8619{"sthbrx", X(31,918), X_MASK, COM, 0, {RS, RA0, RB}}, 8620 8621{"stfdpx", X(31,919), X_MASK|Q_MASK, POWER6, POWER7, {FRSp, RA0, RB}}, 8622{"stfqx", X(31,919), X_MASK, POWER2, 0, {FRS, RA0, RB}}, 8623 8624{"sraq", XRC(31,920,0), X_MASK, M601, 0, {RA, RS, RB}}, 8625{"sraq.", XRC(31,920,1), X_MASK, M601, 0, {RA, RS, RB}}, 8626 8627{"srea", XRC(31,921,0), X_MASK, M601, 0, {RA, RS, RB}}, 8628{"srea.", XRC(31,921,1), X_MASK, M601, 0, {RA, RS, RB}}, 8629 8630{"extsh", XRC(31,922,0), XRB_MASK, PPCCOM, 0, {RA, RS}}, 8631{"exts", XRC(31,922,0), XRB_MASK, PWRCOM, 0, {RA, RS}}, 8632{"extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, 0, {RA, RS}}, 8633{"exts.", XRC(31,922,1), XRB_MASK, PWRCOM, 0, {RA, RS}}, 8634 8635{"evstddepx", VX (31, 1854), VX_MASK, PPCSPE, 0, {RT, RA, RB}}, 8636{"stfddx", X(31,931), X_MASK, E500MC, 0, {FRS, RA, RB}}, 8637 8638{"stvfrxl", X(31,933), X_MASK, E6500, 0, {VS, RA0, RB}}, 8639 8640{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, EXT, {RA0, RB}}, 8641{"wclrall", X(31,934), XRARB_MASK, PPCA2, EXT, {L2}}, 8642{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}}, 8643 8644{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}}, 8645 8646{"divdeo", XO(31,425,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 8647{"divdeo.", XO(31,425,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 8648{"divweo", XO(31,427,1,0), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 8649{"divweo.", XO(31,427,1,1), XO_MASK, POWER7|PPCA2, 0, {RT, RA, RB}}, 8650 8651{"stxvh8x", X(31,940), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 8652{"stxsihx", X(31,941), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 8653 8654{"treclaim.", XRC(31,942,1), XRTRB_MASK, PPCHTM, 0, {RA}}, 8655 8656{"tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, PPCA2|EXT, {RT, RA}}, 8657{"tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, PPCA2|EXT, {RT, RA}}, 8658{"tlbre", X(31,946), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, 8659 8660{"sthcix", X(31,949), X_MASK, POWER6, 0, {RS, RA0, RB}}, 8661 8662{"icswepx", XRC(31,950,0), X_MASK, PPCA2, 0, {RS, RA, RB}}, 8663{"icswepx.", XRC(31,950,1), X_MASK, PPCA2, 0, {RS, RA, RB}}, 8664 8665{"stfqux", X(31,951), X_MASK, POWER2, 0, {FRS, RA, RB}}, 8666 8667{"sraiq", XRC(31,952,0), X_MASK, M601, 0, {RA, RS, SH}}, 8668{"sraiq.", XRC(31,952,1), X_MASK, M601, 0, {RA, RS, SH}}, 8669 8670{"extsb", XRC(31,954,0), XRB_MASK, PPC, 0, {RA, RS}}, 8671{"extsb.", XRC(31,954,1), XRB_MASK, PPC, 0, {RA, RS}}, 8672 8673{"stvflxl", X(31,965), X_MASK, E6500, 0, {VS, RA0, RB}}, 8674 8675{"iccci", X(31,966), XRT_MASK, PPC403|PPC440|PPC476|TITAN|PPCA2, 0, {RAOPT, RBOPT}}, 8676{"ici", X(31,966), XRARB_MASK, PPCA2|PPC476, 0, {CT}}, 8677 8678{"divduo", XO(31,457,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 8679{"divduo.", XO(31,457,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 8680 8681{"divwuo", XO(31,459,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 8682{"divwuo.", XO(31,459,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 8683 8684{"stxvd2x", X(31,972), XX1_MASK, PPCVSX, 0, {XS6, RA0, RB}}, 8685{"stxvx", X(31,972), XX1_MASK, POWER8, POWER9|PPCVSX3, {XS6, RA0, RB}}, 8686 8687{"tlbld", X(31,978), XRTRA_MASK, PPC, PPC403|BOOKE|PPCA2|PPC476, {RB}}, 8688{"tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, EXT, {RT, RA}}, 8689{"tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, EXT, {RT, RA}}, 8690{"tlbwe", X(31,978), X_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RSO, RAOPT, SHO}}, 8691 8692{"slbfee.", XRC(31,979,1), XRA_MASK, POWER6, 0, {RT, RB}}, 8693 8694{"stbcix", X(31,981), X_MASK, POWER6, 0, {RS, RA0, RB}}, 8695 8696{"icbi", X(31,982), XRT_MASK, PPC, 0, {RA0, RB}}, 8697 8698{"stfiwx", X(31,983), X_MASK, PPC, PPCEFS, {FRS, RA0, RB}}, 8699 8700{"extsw", XRC(31,986,0), XRB_MASK, PPC64, 0, {RA, RS}}, 8701{"extsw.", XRC(31,986,1), XRB_MASK, PPC64, 0, {RA, RS}}, 8702 8703{"icbiep", XRT(31,991,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 8704 8705{"stvswxl", X(31,997), X_MASK, E6500, 0, {VS, RA0, RB}}, 8706 8707{"icread", X(31,998), XRT_MASK, PPC403|PPC440|PPC476|TITAN, 0, {RA0, RB}}, 8708 8709{"nabso", XO(31,488,1,0), XORB_MASK, M601, 0, {RT, RA}}, 8710{"nabso.", XO(31,488,1,1), XORB_MASK, M601, 0, {RT, RA}}, 8711 8712{"divdo", XO(31,489,1,0), XO_MASK, PPC64, 0, {RT, RA, RB}}, 8713{"divdo.", XO(31,489,1,1), XO_MASK, PPC64, 0, {RT, RA, RB}}, 8714 8715{"divwo", XO(31,491,1,0), XO_MASK, PPC, 0, {RT, RA, RB}}, 8716{"divwo.", XO(31,491,1,1), XO_MASK, PPC, 0, {RT, RA, RB}}, 8717 8718{"stxvb16x", X(31,1004), XX1_MASK, PPCVSX3, 0, {XS6, RA0, RB}}, 8719 8720{"trechkpt.", XRC(31,1006,1), XRTRARB_MASK,PPCHTM, 0, {0}}, 8721 8722{"tlbli", X(31,1010), XRTRA_MASK, PPC, TITAN, {RB}}, 8723 8724{"stdcix", X(31,1013), X_MASK, POWER6, 0, {RS, RA0, RB}}, 8725 8726{"dcbz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, 8727{"dclz", X(31,1014), XRT_MASK, PPC, 0, {RA0, RB}}, 8728{"dcbzl", XOPL(31,1014,1), XRT_MASK, POWER4|E500MC, PPC476, {RA0, RB}}, 8729 8730{"dcbzep", XRT(31,1023,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}}, 8731 8732{"lwz", OP(32), OP_MASK, PPCCOM, PPCVLE, {RT, D, RA0}}, 8733{"l", OP(32), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 8734 8735{"lwzu", OP(33), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAL}}, 8736{"lu", OP(33), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 8737 8738{"lbz", OP(34), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 8739 8740{"lbzu", OP(35), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 8741 8742{"stw", OP(36), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, 8743{"st", OP(36), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 8744 8745{"stwu", OP(37), OP_MASK, PPCCOM, PPCVLE, {RS, D, RAS}}, 8746{"stu", OP(37), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 8747 8748{"stb", OP(38), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, 8749 8750{"stbu", OP(39), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, 8751 8752{"lhz", OP(40), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 8753 8754{"lhzu", OP(41), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 8755 8756{"lha", OP(42), OP_MASK, COM, PPCVLE, {RT, D, RA0}}, 8757 8758{"lhau", OP(43), OP_MASK, COM, PPCVLE, {RT, D, RAL}}, 8759 8760{"sth", OP(44), OP_MASK, COM, PPCVLE, {RS, D, RA0}}, 8761 8762{"sthu", OP(45), OP_MASK, COM, PPCVLE, {RS, D, RAS}}, 8763 8764{"lmw", OP(46), OP_MASK, PPCCOM, PPCVLE, {RT, D, RAM}}, 8765{"lm", OP(46), OP_MASK, PWRCOM, PPCVLE, {RT, D, RA0}}, 8766 8767{"stmw", OP(47), OP_MASK, PPCCOM, PPCVLE, {RS, D, RA0}}, 8768{"stm", OP(47), OP_MASK, PWRCOM, PPCVLE, {RS, D, RA0}}, 8769 8770{"lfs", OP(48), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, 8771 8772{"lfsu", OP(49), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, 8773 8774{"lfd", OP(50), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RA0}}, 8775 8776{"lfdu", OP(51), OP_MASK, COM, PPCEFS|PPCVLE, {FRT, D, RAS}}, 8777 8778{"stfs", OP(52), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, 8779 8780{"stfsu", OP(53), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, 8781 8782{"stfd", OP(54), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RA0}}, 8783 8784{"stfdu", OP(55), OP_MASK, COM, PPCEFS|PPCVLE, {FRS, D, RAS}}, 8785 8786{"lq", OP(56), OP_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RTQ, DQ, RAQ}}, 8787{"psq_l", OP(56), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, 8788{"lfq", OP(56), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, 8789 8790{"lxsd", DSO(57,2), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, 8791{"lxssp", DSO(57,3), DS_MASK, PPCVSX3, PPCVLE, {VD, DS, RA0}}, 8792{"lfdp", OP(57), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRTp, DS, RA0}}, 8793{"psq_lu", OP(57), OP_MASK, PPCPS, PPCVLE, {FRT,PSD,RA,PSW,PSQ}}, 8794{"lfqu", OP(57), OP_MASK, POWER2, PPCVLE, {FRT, D, RA0}}, 8795 8796{"ld", DSO(58,0), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, 8797{"ldu", DSO(58,1), DS_MASK, PPC64, PPCVLE, {RT, DS, RAL}}, 8798{"lwa", DSO(58,2), DS_MASK, PPC64, PPCVLE, {RT, DS, RA0}}, 8799 8800{"dadd", XRC(59,2,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8801{"dadd.", XRC(59,2,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8802 8803{"dqua", ZRC(59,3,0), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, 8804{"dqua.", ZRC(59,3,1), Z2_MASK, POWER6, PPCVLE, {FRT,FRA,FRB,RMC}}, 8805 8806{"xvi8ger4pp", XX3(59,2), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8807{"xvi8ger4", XX3(59,3), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8808 8809{"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 8810{"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 8811 8812{"fsubs", A(59,20,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 8813{"fsubs.", A(59,20,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 8814 8815{"fadds", A(59,21,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 8816{"fadds.", A(59,21,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 8817 8818{"fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, 8819{"fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, TITAN|PPCVLE, {FRT, FRB}}, 8820 8821{"fres", A(59,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 8822{"fres", A(59,24,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 8823{"fres.", A(59,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 8824{"fres.", A(59,24,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 8825 8826{"fmuls", A(59,25,0), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 8827{"fmuls.", A(59,25,1), AFRB_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 8828 8829{"frsqrtes", A(59,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 8830{"frsqrtes", A(59,26,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 8831{"frsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 8832{"frsqrtes.", A(59,26,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 8833 8834{"fmsubs", A(59,28,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 8835{"fmsubs.", A(59,28,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 8836 8837{"fmadds", A(59,29,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 8838{"fmadds.", A(59,29,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 8839 8840{"fnmsubs", A(59,30,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 8841{"fnmsubs.", A(59,30,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 8842 8843{"fnmadds", A(59,31,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 8844{"fnmadds.", A(59,31,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 8845 8846{"dmul", XRC(59,34,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8847{"dmul.", XRC(59,34,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8848 8849{"drrnd", ZRC(59,35,0), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, 8850{"drrnd.", ZRC(59,35,1), Z2_MASK, POWER6, PPCVLE, {FRT, FRA, FRB, RMC}}, 8851 8852{"dscli", ZRC(59,66,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 8853{"dscli.", ZRC(59,66,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 8854 8855{"dquai", ZRC(59,67,0), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, 8856{"dquai.", ZRC(59,67,1), Z2_MASK, POWER6, PPCVLE, {TE, FRT,FRB,RMC}}, 8857 8858{"xvf16ger2pp", XX3(59,18), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8859{"xvf16ger2", XX3(59,19), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8860 8861{"dscri", ZRC(59,98,0), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 8862{"dscri.", ZRC(59,98,1), Z_MASK, POWER6, PPCVLE, {FRT, FRA, SH16}}, 8863 8864{"drintx", ZRC(59,99,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 8865{"drintx.", ZRC(59,99,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 8866 8867{"xvf32gerpp", XX3(59,26), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8868{"xvf32ger", XX3(59,27), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8869 8870{"dcmpo", X(59,130), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 8871 8872{"xvi4ger8pp", XX3(59,34), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8873{"xvi4ger8", XX3(59,35), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8874 8875{"dtstex", X(59,162), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 8876 8877{"xvi16ger2spp",XX3(59,42), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8878{"xvi16ger2s", XX3(59,43), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8879 8880{"dtstdc", Z(59,194), Z_MASK, POWER6, PPCVLE, {BF, FRA, DCM}}, 8881 8882{"xvbf16ger2pp",XX3(59,50), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8883{"xvbf16ger2", XX3(59,51), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8884 8885{"dtstdg", Z(59,226), Z_MASK, POWER6, PPCVLE, {BF, FRA, DGM}}, 8886 8887{"drintn", ZRC(59,227,0), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 8888{"drintn.", ZRC(59,227,1), Z2_MASK, POWER6, PPCVLE, {R, FRT, FRB, RMC}}, 8889 8890{"xvf64gerpp", XX3(59,58), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, 8891{"xvf64ger", XX3(59,59), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, 8892 8893{"dctdp", XRC(59,258,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 8894{"dctdp.", XRC(59,258,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 8895 8896{"dctfix", XRC(59,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 8897{"dctfix.", XRC(59,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 8898 8899{"ddedpd", XRC(59,322,0), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, 8900{"ddedpd.", XRC(59,322,1), X_MASK, POWER6, PPCVLE, {SP, FRT, FRB}}, 8901 8902{"xvi16ger2", XX3(59,75), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8903 8904{"xvf16ger2np", XX3(59,82), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8905 8906{"dxex", XRC(59,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 8907{"dxex.", XRC(59,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 8908 8909{"xvf32gernp", XX3(59,90), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8910 8911{"xvi8ger4spp", XX3(59,99), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8912 8913{"xvi16ger2pp", XX3(59,107), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8914 8915{"xvbf16ger2np",XX3(59,114), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8916 8917{"xvf64gernp", XX3(59,122), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, 8918 8919{"dsub", XRC(59,514,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8920{"dsub.", XRC(59,514,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8921 8922{"ddiv", XRC(59,546,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8923{"ddiv.", XRC(59,546,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8924 8925{"xvf16ger2pn", XX3(59,146), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8926 8927{"xvf32gerpn", XX3(59,154), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8928 8929{"dcmpu", X(59,642), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 8930 8931{"dtstsf", X(59,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRB}}, 8932{"dtstsfi", X(59,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRB}}, 8933 8934{"xvbf16ger2pn",XX3(59,178), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8935 8936{"xvf64gerpn", XX3(59,186), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, 8937 8938{"drsp", XRC(59,770,0), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 8939{"drsp.", XRC(59,770,1), X_MASK, POWER6, PPCVLE, {FRT, FRB}}, 8940 8941{"dcffix", XRC(59,802,0), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 8942{"dcffix.", XRC(59,802,1), X_MASK|FRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 8943 8944{"denbcd", XRC(59,834,0), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, 8945{"denbcd.", XRC(59,834,1), X_MASK, POWER6, PPCVLE, {S, FRT, FRB}}, 8946 8947{"xvf16ger2nn", XX3(59,210), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8948 8949{"fcfids", XRC(59,846,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 8950{"fcfids.", XRC(59,846,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 8951 8952{"diex", XRC(59,866,0), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8953{"diex.", XRC(59,866,1), X_MASK, POWER6, PPCVLE, {FRT, FRA, FRB}}, 8954 8955{"xvf32gernn", XX3(59,218), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8956 8957{"xvbf16ger2nn",XX3(59,242), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, 8958 8959{"fcfidus", XRC(59,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 8960{"fcfidus.", XRC(59,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 8961 8962{"xvf64gernn", XX3(59,250), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6ap, XB6a}}, 8963 8964{"xsaddsp", XX3(60,0), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 8965{"xsmaddasp", XX3(60,1), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 8966{"xxsldwi", XX3(60,2), XX3SHW_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, SHW}}, 8967{"xscmpeqdp", XX3(60,3), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 8968{"xsrsqrtesp", XX2(60,10), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 8969{"xssqrtsp", XX2(60,11), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 8970{"xxsel", XX4(60,3), XX4_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, XC6}}, 8971{"xssubsp", XX3(60,8), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 8972{"xsmaddmsp", XX3(60,9), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 8973{"xxspltd", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6, DMEX}}, 8974{"xxmrghd", XX3(60,10), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XA6, XB6}}, 8975{"xxswapd", XX3(60,10)|(2<<8), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}}, 8976{"xxmrgld", XX3(60,10)|(3<<8), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XA6, XB6}}, 8977{"xxpermdi", XX3(60,10), XX3DM_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, DM}}, 8978{"xscmpgtdp", XX3(60,11), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 8979{"xsresp", XX2(60,26), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 8980{"xsmulsp", XX3(60,16), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 8981{"xsmsubasp", XX3(60,17), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 8982{"xxmrghw", XX3(60,18), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 8983{"xscmpgedp", XX3(60,19), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 8984{"xsdivsp", XX3(60,24), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 8985{"xsmsubmsp", XX3(60,25), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 8986{"xxperm", XX3(60,26), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 8987{"xsadddp", XX3(60,32), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 8988{"xsmaddadp", XX3(60,33), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 8989{"xscmpudp", XX3(60,35), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 8990{"xscvdpuxws", XX2(60,72), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 8991{"xsrdpi", XX2(60,73), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 8992{"xsrsqrtedp", XX2(60,74), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 8993{"xssqrtdp", XX2(60,75), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 8994{"xssubdp", XX3(60,40), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 8995{"xsmaddmdp", XX3(60,41), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 8996{"xscmpodp", XX3(60,43), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 8997{"xscvdpsxws", XX2(60,88), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 8998{"xsrdpiz", XX2(60,89), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 8999{"xsredp", XX2(60,90), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9000{"xsmuldp", XX3(60,48), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9001{"xsmsubadp", XX3(60,49), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9002{"xxmrglw", XX3(60,50), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9003{"xsrdpip", XX2(60,105), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9004{"xstsqrtdp", XX2(60,106), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 9005{"xsrdpic", XX2(60,107), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9006{"xsdivdp", XX3(60,56), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9007{"xsmsubmdp", XX3(60,57), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9008{"xxpermr", XX3(60,58), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 9009{"xscmpexpdp", XX3(60,59), XX3BF_MASK, PPCVSX3, PPCVLE, {BF, XA6, XB6}}, 9010{"xsrdpim", XX2(60,121), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9011{"xstdivdp", XX3(60,61), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 9012{"xvaddsp", XX3(60,64), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9013{"xvmaddasp", XX3(60,65), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9014{"xvcmpeqsp", XX3RC(60,67,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9015{"xvcmpeqsp.", XX3RC(60,67,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9016{"xvcvspuxws", XX2(60,136), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9017{"xvrspi", XX2(60,137), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9018{"xvrsqrtesp", XX2(60,138), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9019{"xvsqrtsp", XX2(60,139), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9020{"xvsubsp", XX3(60,72), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9021{"xvmaddmsp", XX3(60,73), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9022{"xvcmpgtsp", XX3RC(60,75,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9023{"xvcmpgtsp.", XX3RC(60,75,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9024{"xvcvspsxws", XX2(60,152), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9025{"xvrspiz", XX2(60,153), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9026{"xvresp", XX2(60,154), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9027{"xvmulsp", XX3(60,80), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9028{"xvmsubasp", XX3(60,81), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9029{"xxspltw", XX2(60,164), XX2UIM_MASK, PPCVSX, PPCVLE, {XT6, XB6, UIM}}, 9030{"xxextractuw", XX2(60,165), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, 9031{"xvcmpgesp", XX3RC(60,83,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9032{"xvcmpgesp.", XX3RC(60,83,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9033{"xvcvuxwsp", XX2(60,168), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9034{"xvrspip", XX2(60,169), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9035{"xvtsqrtsp", XX2(60,170), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 9036{"xvrspic", XX2(60,171), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9037{"xvdivsp", XX3(60,88), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9038{"xvmsubmsp", XX3(60,89), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9039{"xxspltib", X(60,360), XX1_MASK|3<<19, PPCVSX3, PPCVLE, {XT6, IMM8}}, 9040{"lxvkq", XVA(60,360,31), XVA_MASK&~1, POWER10, PPCVLE, {XT6, UIM5}}, 9041{"xxinsertw", XX2(60,181), XX2UIM4_MASK, PPCVSX3, PPCVLE, {XT6, XB6, UIMM4}}, 9042{"xvcvsxwsp", XX2(60,184), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9043{"xvrspim", XX2(60,185), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9044{"xvtdivsp", XX3(60,93), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 9045{"xvadddp", XX3(60,96), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9046{"xvmaddadp", XX3(60,97), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9047{"xvcmpeqdp", XX3RC(60,99,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9048{"xvcmpeqdp.", XX3RC(60,99,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9049{"xvcvdpuxws", XX2(60,200), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9050{"xvrdpi", XX2(60,201), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9051{"xvrsqrtedp", XX2(60,202), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9052{"xvsqrtdp", XX2(60,203), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9053{"xvsubdp", XX3(60,104), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9054{"xvmaddmdp", XX3(60,105), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9055{"xvcmpgtdp", XX3RC(60,107,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9056{"xvcmpgtdp.", XX3RC(60,107,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9057{"xvcvdpsxws", XX2(60,216), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9058{"xvrdpiz", XX2(60,217), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9059{"xvredp", XX2(60,218), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9060{"xvmuldp", XX3(60,112), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9061{"xvmsubadp", XX3(60,113), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9062{"xvcmpgedp", XX3RC(60,115,0), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9063{"xvcmpgedp.", XX3RC(60,115,1), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9064{"xvcvuxwdp", XX2(60,232), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9065{"xvrdpip", XX2(60,233), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9066{"xvtsqrtdp", XX2(60,234), XX2BF_MASK, PPCVSX, PPCVLE, {BF, XB6}}, 9067{"xvrdpic", XX2(60,235), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9068{"xvdivdp", XX3(60,120), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9069{"xvmsubmdp", XX3(60,121), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9070{"xvcvsxwdp", XX2(60,248), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9071{"xvrdpim", XX2(60,249), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9072{"xvtdivdp", XX3(60,125), XX3BF_MASK, PPCVSX, PPCVLE, {BF, XA6, XB6}}, 9073{"xsmaxcdp", XX3(60,128), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 9074{"xsnmaddasp", XX3(60,129), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 9075{"xxland", XX3(60,130), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9076{"xscvdpsp", XX2(60,265), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9077{"xscvdpspn", XX2(60,267), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 9078{"xsmincdp", XX3(60,136), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 9079{"xsnmaddmsp", XX3(60,137), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 9080{"xxlandc", XX3(60,138), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9081{"xsrsp", XX2(60,281), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 9082{"xsmaxjdp", XX3(60,144), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 9083{"xsnmsubasp", XX3(60,145), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 9084{"xxmr", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}}, 9085{"xxlor", XX3(60,146), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9086{"xscvuxdsp", XX2(60,296), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 9087{"xststdcsp", XX2(60,298), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, 9088{"xsminjdp", XX3(60,152), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 9089{"xsnmsubmsp", XX3(60,153), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 9090{"xxlxor", XX3(60,154), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9091{"xscvsxdsp", XX2(60,312), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 9092{"xsmaxdp", XX3(60,160), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9093{"xsnmaddadp", XX3(60,161), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9094{"xxlnot", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}}, 9095{"xxlnor", XX3(60,162), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9096{"xscvdpuxds", XX2(60,328), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9097{"xscvspdp", XX2(60,329), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9098{"xscvspdpn", XX2(60,331), XX2_MASK, PPCVSX2, PPCVLE, {XT6, XB6}}, 9099{"xsmindp", XX3(60,168), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9100{"xsnmaddmdp", XX3(60,169), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9101{"xxlorc", XX3(60,170), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 9102{"xscvdpsxds", XX2(60,344), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9103{"xsabsdp", XX2(60,345), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9104{"xsxexpdp", XX2VA(60,347,0),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, 9105{"xsxsigdp", XX2VA(60,347,1),XX2_MASK|1, PPCVSX3, PPCVLE, {RT, XB6}}, 9106{"xscvhpdp", XX2VA(60,347,16),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9107{"xscvdphp", XX2VA(60,347,17),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9108{"xscpsgndp", XX3(60,176), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9109{"xsnmsubadp", XX3(60,177), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9110{"xxlnand", XX3(60,178), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 9111{"xscvuxddp", XX2(60,360), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9112{"xsnabsdp", XX2(60,361), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9113{"xststdcdp", XX2(60,362), XX2BFD_MASK, PPCVSX3, PPCVLE, {BF, XB6, DCMX}}, 9114{"xsnmsubmdp", XX3(60,185), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9115{"xxleqv", XX3(60,186), XX3_MASK, PPCVSX2, PPCVLE, {XT6, XA6, XB6}}, 9116{"xscvsxddp", XX2(60,376), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9117{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9118{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9119{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9120{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9121{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9122{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9123{"xvnmaddmsp", XX3(60,201), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9124{"xvcvspsxds", XX2(60,408), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9125{"xvabssp", XX2(60,409), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9126{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}}, 9127{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9128{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9129{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9130{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9131{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, 9132{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 9133{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9134{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9135{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9136{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9137{"xvnmaddadp", XX3(60,225), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9138{"xvcvdpuxds", XX2(60,456), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9139{"xvcvspdp", XX2(60,457), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9140{"xxgenpcvbm", X(60,916), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, 9141{"xxgenpcvhm", X(60,917), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, 9142{"xsiexpdp", X(60,918), XX1_MASK, PPCVSX3, PPCVLE, {XT6, RA, RB}}, 9143{"xvmindp", XX3(60,232), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9144{"xvnmaddmdp", XX3(60,233), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9145{"xvcvdpsxds", XX2(60,472), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9146{"xvabsdp", XX2(60,473), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9147{"xxgenpcvwm", X(60,948), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, 9148{"xxgenpcvdm", X(60,949), XX1_MASK, POWER10, PPCVLE, {XT6, VB, UIMM}}, 9149{"xvxexpdp", XX2VA(60,475,0),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9150{"xvxsigdp", XX2VA(60,475,1),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9151{"xvtlsbb", XX2VA(60,475,2),XX2BF_MASK, POWER10, PPCVLE, {BF, XB6}}, 9152{"xxbrh", XX2VA(60,475,7),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9153{"xvxexpsp", XX2VA(60,475,8),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9154{"xvxsigsp", XX2VA(60,475,9),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9155{"xxbrw", XX2VA(60,475,15),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9156{"xvcvbf16spn", XX2VA(60,475,16),XX2_MASK, PPCVSX4, PPCVLE, {XT6, XB6}}, 9157{"xvcvspbf16", XX2VA(60,475,17),XX2_MASK, PPCVSX4, PPCVLE, {XT6, XB6}}, 9158{"xxbrd", XX2VA(60,475,23),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9159{"xvcvhpsp", XX2VA(60,475,24),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9160{"xvcvsphp", XX2VA(60,475,25),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9161{"xxbrq", XX2VA(60,475,31),XX2_MASK, PPCVSX3, PPCVLE, {XT6, XB6}}, 9162{"xvmovdp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}}, 9163{"xvcpsgndp", XX3(60,240), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9164{"xvnmsubadp", XX3(60,241), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9165{"xvcvuxddp", XX2(60,488), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9166{"xvnabsdp", XX2(60,489), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9167{"xvtstdcdp", XX2(60,490), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}}, 9168{"xviexpdp", XX3(60,248), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}}, 9169{"xvnmsubmdp", XX3(60,249), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}}, 9170{"xvcvsxddp", XX2(60,504), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9171{"xvnegdp", XX2(60,505), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}}, 9172 9173{"psq_st", OP(60), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, 9174{"stfq", OP(60), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, 9175 9176{"lxv", DQX(61,1), DQX_MASK, PPCVSX3, PPCVLE, {XTQ6, DQ, RA0}}, 9177{"stxv", DQX(61,5), DQX_MASK, PPCVSX3, PPCVLE, {XSQ6, DQ, RA0}}, 9178{"stxsd", DSO(61,2), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, 9179{"stxssp", DSO(61,3), DS_MASK, PPCVSX3, PPCVLE, {VS, DS, RA0}}, 9180{"stfdp", OP(61), OP_MASK|Q_MASK, POWER6, POWER7|PPCVLE, {FRSp, DS, RA0}}, 9181{"psq_stu", OP(61), OP_MASK, PPCPS, PPCVLE, {FRS,PSD,RA,PSW,PSQ}}, 9182{"stfqu", OP(61), OP_MASK, POWER2, PPCVLE, {FRS, D, RA}}, 9183 9184{"std", DSO(62,0), DS_MASK, PPC64, PPCVLE, {RS, DS, RA0}}, 9185{"stdu", DSO(62,1), DS_MASK, PPC64, PPCVLE, {RS, DS, RAS}}, 9186{"stq", DSO(62,2), DS_MASK|Q_MASK, POWER4, PPC476|PPCVLE, {RSQ, DS, RA0}}, 9187 9188{"fcmpu", X(63,0), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, 9189 9190{"daddq", XRC(63,2,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 9191{"daddq.", XRC(63,2,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 9192 9193{"dquaq", ZRC(63,3,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, 9194{"dquaq.", ZRC(63,3,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp, RMC}}, 9195 9196{"xsaddqp", XRC(63,4,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9197{"xsaddqpo", XRC(63,4,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9198 9199{"xsrqpi", ZRC(63,5,0), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 9200{"xsrqpix", ZRC(63,5,1), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 9201 9202{"fcpsgn", XRC(63,8,0), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, 9203{"fcpsgn.", XRC(63,8,1), X_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FRT, FRA, FRB}}, 9204 9205{"frsp", XRC(63,12,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9206{"frsp.", XRC(63,12,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9207 9208{"fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 9209{"fcir", XRC(63,14,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 9210{"fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 9211{"fcir.", XRC(63,14,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 9212 9213{"fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 9214{"fcirz", XRC(63,15,0), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 9215{"fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRB}}, 9216{"fcirz.", XRC(63,15,1), XRA_MASK, PWR2COM, PPCVLE, {FRT, FRB}}, 9217 9218{"fdiv", A(63,18,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 9219{"fd", A(63,18,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 9220{"fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 9221{"fd.", A(63,18,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 9222 9223{"fsub", A(63,20,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 9224{"fs", A(63,20,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 9225{"fsub.", A(63,20,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 9226{"fs.", A(63,20,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 9227 9228{"fadd", A(63,21,0), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 9229{"fa", A(63,21,0), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 9230{"fadd.", A(63,21,1), AFRC_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, 9231{"fa.", A(63,21,1), AFRC_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRB}}, 9232 9233{"fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, 9234{"fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, TITAN|PPCVLE, {FRT, FRB}}, 9235 9236{"fsel", A(63,23,0), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9237{"fsel.", A(63,23,1), A_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9238 9239{"fre", A(63,24,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 9240{"fre", A(63,24,0), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 9241{"fre.", A(63,24,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 9242{"fre.", A(63,24,1), AFRALFRC_MASK, POWER5, POWER7|PPCVLE, {FRT, FRB, A_L}}, 9243 9244{"fmul", A(63,25,0), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 9245{"fm", A(63,25,0), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, 9246{"fmul.", A(63,25,1), AFRB_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC}}, 9247{"fm.", A(63,25,1), AFRB_MASK, PWRCOM, PPCVLE|PPCVLE, {FRT, FRA, FRC}}, 9248 9249{"frsqrte", A(63,26,0), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 9250{"frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 9251{"frsqrte.", A(63,26,1), AFRAFRC_MASK, POWER7, PPCVLE, {FRT, FRB}}, 9252{"frsqrte.", A(63,26,1), AFRALFRC_MASK, PPC, POWER7|PPCVLE, {FRT, FRB, A_L}}, 9253 9254{"fmsub", A(63,28,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9255{"fms", A(63,28,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 9256{"fmsub.", A(63,28,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9257{"fms.", A(63,28,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 9258 9259{"fmadd", A(63,29,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9260{"fma", A(63,29,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 9261{"fmadd.", A(63,29,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9262{"fma.", A(63,29,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 9263 9264{"fnmsub", A(63,30,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9265{"fnms", A(63,30,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 9266{"fnmsub.", A(63,30,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9267{"fnms.", A(63,30,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 9268 9269{"fnmadd", A(63,31,0), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9270{"fnma", A(63,31,0), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 9271{"fnmadd.", A(63,31,1), A_MASK, PPCCOM, PPCEFS|PPCVLE, {FRT, FRA, FRC, FRB}}, 9272{"fnma.", A(63,31,1), A_MASK, PWRCOM, PPCVLE, {FRT, FRA, FRC, FRB}}, 9273 9274{"fcmpo", X(63,32), XBF_MASK, COM, PPCEFS|PPCVLE, {BF, FRA, FRB}}, 9275 9276{"dmulq", XRC(63,34,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 9277{"dmulq.", XRC(63,34,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 9278 9279{"drrndq", ZRC(63,35,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, 9280{"drrndq.", ZRC(63,35,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp, RMC}}, 9281 9282{"xsmulqp", XRC(63,36,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9283{"xsmulqpo", XRC(63,36,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9284 9285{"xsrqpxp", Z(63,37), Z2_MASK, PPCVSX3, PPCVLE, {R, VD, VB, RMC}}, 9286 9287{"mtfsb1", XRC(63,38,0), XRARB_MASK, COM, PPCVLE, {BTF}}, 9288{"mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, PPCVLE, {BTF}}, 9289 9290{"fneg", XRC(63,40,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9291{"fneg.", XRC(63,40,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9292 9293{"mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}}, 9294 9295{"dscliq", ZRC(63,66,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 9296{"dscliq.", ZRC(63,66,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 9297 9298{"dquaiq", ZRC(63,67,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, 9299{"dquaiq.", ZRC(63,67,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {TE, FRTp, FRBp, RMC}}, 9300 9301{"xscmpeqqp", X(63,68), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, 9302 9303{"mtfsb0", XRC(63,70,0), XRARB_MASK, COM, PPCVLE, {BTF}}, 9304{"mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, PPCVLE, {BTF}}, 9305 9306{"fmr", XRC(63,72,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9307{"fmr.", XRC(63,72,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9308 9309{"dscriq", ZRC(63,98,0), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 9310{"dscriq.", ZRC(63,98,1), Z_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, SH16}}, 9311 9312{"drintxq", ZRC(63,99,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 9313{"drintxq.", ZRC(63,99,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 9314 9315{"xscpsgnqp", X(63,100), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9316 9317{"ftdiv", X(63,128), XBF_MASK, POWER7, PPCVLE, {BF, FRA, FRB}}, 9318 9319{"dcmpoq", X(63,130), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 9320 9321{"xscmpoqp", X(63,132), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 9322 9323{"mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, 9324{"mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, 9325{"mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), POWER6|PPCA2|PPC476, PPCVLE, {BFF, U, W}}, 9326{"mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, POWER6|PPCA2|PPC476|PPCVLE, {BFF, U}}, 9327 9328{"fnabs", XRC(63,136,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9329{"fnabs.", XRC(63,136,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9330 9331{"fctiwu", XRC(63,142,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 9332{"fctiwu.", XRC(63,142,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 9333{"fctiwuz", XRC(63,143,0), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 9334{"fctiwuz.", XRC(63,143,1), XRA_MASK, POWER7, PPCVLE, {FRT, FRB}}, 9335 9336{"ftsqrt", X(63,160), XBF_MASK|FRA_MASK, POWER7, PPCVLE, {BF, FRB}}, 9337 9338{"dtstexq", X(63,162), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 9339 9340{"xscmpexpqp", X(63,164), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 9341 9342{"dtstdcq", Z(63,194), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DCM}}, 9343 9344{"xscmpgeqp", X(63,196), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, 9345 9346{"dtstdgq", Z(63,226), Z_MASK, POWER6, PPCVLE, {BF, FRAp, DGM}}, 9347 9348{"drintnq", ZRC(63,227,0), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 9349{"drintnq.", ZRC(63,227,1), Z2_MASK|Q_MASK, POWER6, PPCVLE, {R, FRTp, FRBp, RMC}}, 9350 9351{"xscmpgtqp", X(63,228), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, 9352 9353{"dctqpq", XRC(63,258,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 9354{"dctqpq.", XRC(63,258,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 9355 9356{"fabs", XRC(63,264,0), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9357{"fabs.", XRC(63,264,1), XRA_MASK, COM, PPCEFS|PPCVLE, {FRT, FRB}}, 9358 9359{"dctfixq", XRC(63,290,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 9360{"dctfixq.", XRC(63,290,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 9361 9362{"ddedpdq", XRC(63,322,0), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, 9363{"ddedpdq.", XRC(63,322,1), X_MASK|Q_MASK, POWER6, PPCVLE, {SP, FRTp, FRBp}}, 9364 9365{"dxexq", XRC(63,354,0), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 9366{"dxexq.", XRC(63,354,1), X_MASK, POWER6, PPCVLE, {FRT, FRBp}}, 9367 9368{"xsmaddqp", XRC(63,388,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9369{"xsmaddqpo", XRC(63,388,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9370 9371{"frin", XRC(63,392,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 9372{"frin.", XRC(63,392,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 9373 9374{"xsmsubqp", XRC(63,420,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9375{"xsmsubqpo", XRC(63,420,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9376 9377{"friz", XRC(63,424,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 9378{"friz.", XRC(63,424,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 9379 9380{"xsnmaddqp", XRC(63,452,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9381{"xsnmaddqpo", XRC(63,452,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9382 9383{"frip", XRC(63,456,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 9384{"frip.", XRC(63,456,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 9385 9386{"xsnmsubqp", XRC(63,484,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9387{"xsnmsubqpo", XRC(63,484,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9388 9389{"frim", XRC(63,488,0), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 9390{"frim.", XRC(63,488,1), XRA_MASK, POWER5, PPCVLE, {FRT, FRB}}, 9391 9392{"dsubq", XRC(63,514,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 9393{"dsubq.", XRC(63,514,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 9394 9395{"xssubqp", XRC(63,516,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9396{"xssubqpo", XRC(63,516,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9397 9398{"ddivq", XRC(63,546,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 9399{"ddivq.", XRC(63,546,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRAp, FRBp}}, 9400 9401{"xsdivqp", XRC(63,548,0), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9402{"xsdivqpo", XRC(63,548,1), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9403 9404{"mffs", XRC(63,583,0), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, 9405{"mffs.", XRC(63,583,1), XRARB_MASK, COM, PPCEFS|PPCVLE, {FRT}}, 9406 9407{"mffsce", XMMF(63,583,0,1), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, 9408{"mffscdrn", XMMF(63,583,2,4), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, 9409{"mffscdrni", XMMF(63,583,2,5), XMMF_MASK|(3<<14), POWER9, PPCVLE, {FRT, DRM}}, 9410{"mffscrn", XMMF(63,583,2,6), XMMF_MASK, POWER9, PPCVLE, {FRT, FRB}}, 9411{"mffscrni", XMMF(63,583,2,7), XMMF_MASK|(7<<13), POWER9, PPCVLE, {FRT, RM}}, 9412{"mffsl", XMMF(63,583,3,0), XMMF_MASK|RB_MASK, POWER9, PPCVLE, {FRT}}, 9413 9414{"dcmpuq", X(63,642), X_MASK, POWER6, PPCVLE, {BF, FRAp, FRBp}}, 9415 9416{"xscmpuqp", X(63,644), XBF_MASK, PPCVSX3, PPCVLE, {BF, VA, VB}}, 9417 9418{"dtstsfq", X(63,674), X_MASK, POWER6, PPCVLE, {BF, FRA, FRBp}}, 9419{"dtstsfiq", X(63,675), X_MASK|1<<22,POWER9, PPCVLE, {BF, UIM6, FRBp}}, 9420 9421{"xsmaxcqp", X(63,676), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, 9422 9423{"xststdcqp", X(63,708), X_MASK, PPCVSX3, PPCVLE, {BF, VB, DCMX}}, 9424 9425{"mtfsf", XFL(63,711,0), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, 9426{"mtfsf", XFL(63,711,0), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, 9427{"mtfsf.", XFL(63,711,1), XFL_MASK, POWER6|PPCA2|PPC476, PPCVLE, {FLM, FRB, XFL_L, W}}, 9428{"mtfsf.", XFL(63,711,1), XFL_MASK, COM, POWER6|PPCA2|PPC476|PPCEFS|PPCVLE, {FLM, FRB}}, 9429 9430{"xsmincqp", X(63,740), X_MASK, POWER10, PPCVLE, {VD, VA, VB}}, 9431 9432{"drdpq", XRC(63,770,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, 9433{"drdpq.", XRC(63,770,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRBp}}, 9434 9435{"dcffixq", XRC(63,802,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 9436{"dcffixq.", XRC(63,802,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRB}}, 9437 9438{"xsabsqp", XVA(63,804,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9439{"xsxexpqp", XVA(63,804,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9440{"xsnabsqp", XVA(63,804,8), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9441{"xsnegqp", XVA(63,804,16), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9442{"xsxsigqp", XVA(63,804,18), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9443{"xssqrtqp", XVARC(63,804,27,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9444{"xssqrtqpo", XVARC(63,804,27,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9445 9446{"fctid", XRC(63,814,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 9447{"fctid", XRC(63,814,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 9448{"fctid.", XRC(63,814,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 9449{"fctid.", XRC(63,814,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 9450 9451{"fctidz", XRC(63,815,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 9452{"fctidz", XRC(63,815,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 9453{"fctidz.", XRC(63,815,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 9454{"fctidz.", XRC(63,815,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 9455 9456{"denbcdq", XRC(63,834,0), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, 9457{"denbcdq.", XRC(63,834,1), X_MASK|Q_MASK, POWER6, PPCVLE, {S, FRTp, FRBp}}, 9458 9459{"xscvqpuqz", XVA(63,836,0), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, 9460{"xscvqpuwz", XVA(63,836,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9461{"xscvudqp", XVA(63,836,2), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9462{"xscvuqqp", XVA(63,836,3), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, 9463{"xscvqpsqz", XVA(63,836,8), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, 9464{"xscvqpswz", XVA(63,836,9), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9465{"xscvsdqp", XVA(63,836,10), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9466{"xscvsqqp", XVA(63,836,11), XVA_MASK, POWER10, PPCVLE, {VD, VB}}, 9467{"xscvqpudz", XVA(63,836,17), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9468{"xscvqpdp", XVARC(63,836,20,0), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9469{"xscvqpdpo", XVARC(63,836,20,1), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9470{"xscvdpqp", XVA(63,836,22), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9471{"xscvqpsdz", XVA(63,836,25), XVA_MASK, PPCVSX3, PPCVLE, {VD, VB}}, 9472 9473{"fmrgow", X(63,838), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, 9474 9475{"fcfid", XRC(63,846,0), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 9476{"fcfid", XRC(63,846,0), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 9477{"fcfid.", XRC(63,846,1), XRA_MASK, PPC64, PPCVLE, {FRT, FRB}}, 9478{"fcfid.", XRC(63,846,1), XRA_MASK, PPC476, PPCVLE, {FRT, FRB}}, 9479 9480{"diexq", XRC(63,866,0), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, 9481{"diexq.", XRC(63,866,1), X_MASK|Q_MASK, POWER6, PPCVLE, {FRTp, FRA, FRBp}}, 9482 9483{"xsiexpqp", X(63,868), X_MASK, PPCVSX3, PPCVLE, {VD, VA, VB}}, 9484 9485{"fctidu", XRC(63,942,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 9486{"fctidu.", XRC(63,942,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 9487 9488{"fctiduz", XRC(63,943,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 9489{"fctiduz.", XRC(63,943,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 9490 9491{"fmrgew", X(63,966), X_MASK, PPCVSX2, PPCVLE, {FRT, FRA, FRB}}, 9492 9493{"fcfidu", XRC(63,974,0), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 9494{"fcfidu.", XRC(63,974,1), XRA_MASK, POWER7|PPCA2, PPCVLE, {FRT, FRB}}, 9495 9496{"dcffixqq", XVA(63,994,0), XVA_MASK, POWER10, PPCVLE, {FRTp, VB}}, 9497{"dctfixqq", XVA(63,994,1), XVA_MASK, POWER10, PPCVLE, {VD, FRBp}}, 9498}; 9499 9500const unsigned int powerpc_num_opcodes = 9501 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); 9502 9503/* The opcode table for 8-byte prefix instructions. 9504 9505 The format of this opcode table is the same as the main opcode table. */ 9506 9507const struct powerpc_opcode prefix_opcodes[] = { 9508{"pnop", PMRR, PREFIX_MASK, POWER10, 0, {0}}, 9509{"pli", PMLS|OP(14), P_DRAPCREL_MASK, POWER10, EXT, {RT, SI34}}, 9510{"paddi", PMLS|OP(14), P_D_MASK, POWER10, 0, {RT, RA0, SI34, PCREL0}}, 9511{"psubi", PMLS|OP(14), P_D_MASK, POWER10, EXT, {RT, RA0, NSI34, PCREL0}}, 9512{"pla", PMLS|OP(14), P_D_MASK, POWER10, EXT, {RT, D34, PRA0, PCREL}}, 9513{"xxsplti32dx", P8RR|VSOP(32,0), P_VSI_MASK, POWER10, 0, {XTS, IX, IMM32}}, 9514{"xxspltidp", P8RR|VSOP(32,2), P_VS_MASK, POWER10, 0, {XTS, IMM32}}, 9515{"xxspltiw", P8RR|VSOP(32,3), P_VS_MASK, POWER10, 0, {XTS, IMM32}}, 9516{"plwz", PMLS|OP(32), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, 9517{"xxblendvb", P8RR|XX4(33,0), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, 9518{"xxblendvh", P8RR|XX4(33,1), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, 9519{"xxblendvw", P8RR|XX4(33,2), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, 9520{"xxblendvd", P8RR|XX4(33,3), P_XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6}}, 9521{"xxpermx", P8RR|XX4(34,0), P_UXX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM3}}, 9522{"xxeval", P8RR|XX4(34,1), P_U8XX4_MASK, POWER10, 0, {XT6, XA6, XB6, XC6, UIM8}}, 9523{"plbz", PMLS|OP(34), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, 9524{"pstw", PMLS|OP(36), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, 9525{"pstb", PMLS|OP(38), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, 9526{"plhz", PMLS|OP(40), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, 9527{"plwa", P8LS|OP(41), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, 9528{"plxsd", P8LS|OP(42), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}}, 9529{"plha", PMLS|OP(42), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, 9530{"plxssp", P8LS|OP(43), P_D_MASK, POWER10, 0, {VD, D34, PRA0, PCREL}}, 9531{"psth", PMLS|OP(44), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, 9532{"pstxsd", P8LS|OP(46), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}}, 9533{"pstxssp", P8LS|OP(47), P_D_MASK, POWER10, 0, {VS, D34, PRA0, PCREL}}, 9534{"plfs", PMLS|OP(48), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}}, 9535{"plxv", P8LS|OP(50), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}}, 9536{"plfd", PMLS|OP(50), P_D_MASK, POWER10, 0, {FRT, D34, PRA0, PCREL}}, 9537{"pstfs", PMLS|OP(52), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}}, 9538{"pstxv", P8LS|OP(54), P_D_MASK&~OP(1), POWER10, 0, {XTOP, D34, PRA0, PCREL}}, 9539{"pstfd", PMLS|OP(54), P_D_MASK, POWER10, 0, {FRS, D34, PRA0, PCREL}}, 9540{"plq", P8LS|OP(56), P_D_MASK, POWER10, 0, {RTQ, D34, PRAQ, PCREL}}, 9541{"pld", P8LS|OP(57), P_D_MASK, POWER10, 0, {RT, D34, PRA0, PCREL}}, 9542{"plxvp", P8LS|OP(58), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}}, 9543{"pmxvi8ger4pp", PMMIRR|XX3(59,2), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}}, 9544{"pmxvi8ger4", PMMIRR|XX3(59,3), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}}, 9545{"pmxvf16ger2pp", PMMIRR|XX3(59,18), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9546{"pmxvf16ger2", PMMIRR|XX3(59,19), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9547{"pmxvf32gerpp", PMMIRR|XX3(59,26), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, 9548{"pmxvf32ger", PMMIRR|XX3(59,27), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, 9549{"pmxvi4ger8pp", PMMIRR|XX3(59,34), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}}, 9550{"pmxvi4ger8", PMMIRR|XX3(59,35), P_GER8_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK8}}, 9551{"pmxvi16ger2spp",PMMIRR|XX3(59,42), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9552{"pmxvi16ger2s", PMMIRR|XX3(59,43), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9553{"pmxvbf16ger2pp",PMMIRR|XX3(59,50), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9554{"pmxvbf16ger2", PMMIRR|XX3(59,51), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9555{"pmxvf64gerpp", PMMIRR|XX3(59,58), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, 9556{"pmxvf64ger", PMMIRR|XX3(59,59), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, 9557{"pmxvi16ger2", PMMIRR|XX3(59,75), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9558{"pmxvf16ger2np", PMMIRR|XX3(59,82), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9559{"pmxvf32gernp", PMMIRR|XX3(59,90), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, 9560{"pmxvi8ger4spp", PMMIRR|XX3(59,99), P_GER4_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK4}}, 9561{"pmxvi16ger2pp", PMMIRR|XX3(59,107), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9562{"pmxvbf16ger2np",PMMIRR|XX3(59,114), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9563{"pmxvf64gernp", PMMIRR|XX3(59,122), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, 9564{"pmxvf16ger2pn", PMMIRR|XX3(59,146), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9565{"pmxvf32gerpn", PMMIRR|XX3(59,154), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, 9566{"pmxvbf16ger2pn",PMMIRR|XX3(59,178), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9567{"pmxvf64gerpn", PMMIRR|XX3(59,186), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, 9568{"pmxvf16ger2nn", PMMIRR|XX3(59,210), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9569{"pmxvf32gernn", PMMIRR|XX3(59,218), P_GER_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK}}, 9570{"pmxvbf16ger2nn",PMMIRR|XX3(59,242), P_GER2_MASK, POWER10, 0, {ACC, XA6a, XB6a, XMSK, YMSK, PMSK2}}, 9571{"pmxvf64gernn", PMMIRR|XX3(59,250), P_GER64_MASK, POWER10, 0, {ACC, XA6ap, XB6a, XMSK, YMSK2}}, 9572{"pstq", P8LS|OP(60), P_D_MASK, POWER10, 0, {RSQ, D34, PRA0, PCREL}}, 9573{"pstd", P8LS|OP(61), P_D_MASK, POWER10, 0, {RS, D34, PRA0, PCREL}}, 9574{"pstxvp", P8LS|OP(62), P_D_MASK, POWER10, 0, {XTP, D34, PRA0, PCREL}}, 9575}; 9576 9577const unsigned int prefix_num_opcodes = 9578 sizeof (prefix_opcodes) / sizeof (prefix_opcodes[0]); 9579 9580/* The VLE opcode table. 9581 9582 The format of this opcode table is the same as the main opcode table. */ 9583 9584const struct powerpc_opcode vle_opcodes[] = { 9585{"se_illegal", C(0), C_MASK, PPCVLE, 0, {}}, 9586{"se_isync", C(1), C_MASK, PPCVLE, 0, {}}, 9587{"se_sc", C(2), C_MASK, PPCVLE, 0, {}}, 9588{"se_blr", C_LK(2,0), C_LK_MASK, PPCVLE, 0, {}}, 9589{"se_blrl", C_LK(2,1), C_LK_MASK, PPCVLE, 0, {}}, 9590{"se_bctr", C_LK(3,0), C_LK_MASK, PPCVLE, 0, {}}, 9591{"se_bctrl", C_LK(3,1), C_LK_MASK, PPCVLE, 0, {}}, 9592{"se_rfi", C(8), C_MASK, PPCVLE, 0, {}}, 9593{"se_rfci", C(9), C_MASK, PPCVLE, 0, {}}, 9594{"se_rfdi", C(10), C_MASK, PPCVLE, 0, {}}, 9595{"se_rfmci", C(11), C_MASK, PPCRFMCI|PPCVLE, 0, {}}, 9596{"se_rfgi", C(12), C_MASK, PPCVLE, 0, {}}, 9597{"se_not", SE_R(0,2), SE_R_MASK, PPCVLE, 0, {RX}}, 9598{"se_neg", SE_R(0,3), SE_R_MASK, PPCVLE, 0, {RX}}, 9599{"se_mflr", SE_R(0,8), SE_R_MASK, PPCVLE, 0, {RX}}, 9600{"se_mtlr", SE_R(0,9), SE_R_MASK, PPCVLE, 0, {RX}}, 9601{"se_mfctr", SE_R(0,10), SE_R_MASK, PPCVLE, 0, {RX}}, 9602{"se_mtctr", SE_R(0,11), SE_R_MASK, PPCVLE, 0, {RX}}, 9603{"se_extzb", SE_R(0,12), SE_R_MASK, PPCVLE, 0, {RX}}, 9604{"se_extsb", SE_R(0,13), SE_R_MASK, PPCVLE, 0, {RX}}, 9605{"se_extzh", SE_R(0,14), SE_R_MASK, PPCVLE, 0, {RX}}, 9606{"se_extsh", SE_R(0,15), SE_R_MASK, PPCVLE, 0, {RX}}, 9607{"se_mr", SE_RR(0,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 9608{"se_mtar", SE_RR(0,2), SE_RR_MASK, PPCVLE, 0, {ARX, RY}}, 9609{"se_mfar", SE_RR(0,3), SE_RR_MASK, PPCVLE, 0, {RX, ARY}}, 9610{"se_add", SE_RR(1,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 9611{"se_mullw", SE_RR(1,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 9612{"se_sub", SE_RR(1,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 9613{"se_subf", SE_RR(1,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 9614{"se_cmp", SE_RR(3,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 9615{"se_cmpl", SE_RR(3,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 9616{"se_cmph", SE_RR(3,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 9617{"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 9618 9619/* by major opcode */ 9620{"zvaddih", VX(4, 0x200), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, 9621{"zvsubifh", VX(4, 0x201), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, 9622{"zvaddh", VX(4, 0x204), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9623{"zvsubfh", VX(4, 0x205), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9624{"zvaddsubfh", VX(4, 0x206), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9625{"zvsubfaddh", VX(4, 0x207), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9626{"zvaddhx", VX(4, 0x20C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9627{"zvsubfhx", VX(4, 0x20D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9628{"zvaddsubfhx", VX(4, 0x20E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9629{"zvsubfaddhx", VX(4, 0x20F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9630{"zaddwus", VX(4, 0x210), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9631{"zsubfwus", VX(4, 0x211), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9632{"zaddwss", VX(4, 0x212), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9633{"zsubfwss", VX(4, 0x213), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9634{"zvaddhus", VX(4, 0x214), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9635{"zvsubfhus", VX(4, 0x215), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9636{"zvaddhss", VX(4, 0x216), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9637{"zvsubfhss", VX(4, 0x217), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9638{"zvaddsubfhss", VX(4, 0x21A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9639{"zvsubfaddhss", VX(4, 0x21B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9640{"zvaddhxss", VX(4, 0x21C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9641{"zvsubfhxss", VX(4, 0x21D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9642{"zvaddsubfhxss", VX(4, 0x21E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9643{"zvsubfaddhxss", VX(4, 0x21F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9644{"zaddheuw", VX(4, 0x220), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9645{"zsubfheuw", VX(4, 0x221), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9646{"zaddhesw", VX(4, 0x222), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9647{"zsubfhesw", VX(4, 0x223), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9648{"zaddhouw", VX(4, 0x224), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9649{"zsubfhouw", VX(4, 0x225), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9650{"zaddhosw", VX(4, 0x226), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9651{"zsubfhosw", VX(4, 0x227), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9652{"zvmergehih", VX(4, 0x22C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9653{"zvmergeloh", VX(4, 0x22D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9654{"zvmergehiloh", VX(4, 0x22E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9655{"zvmergelohih", VX(4, 0x22F), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9656{"zvcmpgthu", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 9657{"zvcmpgths", VX(4, 0x230), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 9658{"zvcmplthu", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 9659{"zvcmplths", VX(4, 0x231), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 9660{"zvcmpeqh", VX(4, 0x232), VX_MASK, PPCLSP, 0, {CRFD, RA, RB}}, 9661{"zpkswgshfrs", VX(4, 0x238), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9662{"zpkswgswfrs", VX(4, 0x239), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9663{"zvpkshgwshfrs", VX(4, 0x23A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9664{"zvpkswshfrs", VX(4, 0x23B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9665{"zvpkswuhs", VX(4, 0x23C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9666{"zvpkswshs", VX(4, 0x23D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9667{"zvpkuwuhs", VX(4, 0x23E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9668{"zvsplatih", VX_LSP(4, 0x23F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, 9669{"zvsplatfih", VX_LSP(4, 0xA3F), VX_LSP_MASK, PPCLSP, 0, {RD, SIMM}}, 9670{"zcntlsw", VX_LSP(4, 0x2A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9671{"zvcntlzh", VX_LSP(4, 0x323F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9672{"zvcntlsh", VX_LSP(4, 0x3A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9673{"znegws", VX_LSP(4, 0x4A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9674{"zvnegh", VX_LSP(4, 0x523F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9675{"zvneghs", VX_LSP(4, 0x5A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9676{"zvnegho", VX_LSP(4, 0x623F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9677{"zvneghos", VX_LSP(4, 0x6A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9678{"zrndwh", VX_LSP(4, 0x823F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9679{"zrndwhss", VX_LSP(4, 0x8A3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9680{"zvabsh", VX_LSP(4, 0xA23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9681{"zvabshs", VX_LSP(4, 0xAA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9682{"zabsw", VX_LSP(4, 0xB23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9683{"zabsws", VX_LSP(4, 0xBA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9684{"zsatswuw", VX_LSP(4, 0xC23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9685{"zsatuwsw", VX_LSP(4, 0xCA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9686{"zsatswuh", VX_LSP(4, 0xD23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9687{"zsatswsh", VX_LSP(4, 0xDA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9688{"zvsatshuh", VX_LSP(4, 0xE23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9689{"zvsatuhsh", VX_LSP(4, 0xEA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9690{"zsatuwuh", VX_LSP(4, 0xF23F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9691{"zsatuwsh", VX_LSP(4, 0xFA3F), VX_LSP_MASK, PPCLSP, 0, {RD, RA}}, 9692{"zsatsduw", VX(4, 0x260), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9693{"zsatsdsw", VX(4, 0x261), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9694{"zsatuduw", VX(4, 0x262), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9695{"zvselh", VX(4, 0x264), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9696{"zxtrw", VX(4, 0x264), VX_LSP_OFF_MASK, PPCLSP, 0, {RD, RA, RB, VX_OFF}}, 9697{"zbrminc", VX(4, 0x268), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9698{"zcircinc", VX(4, 0x269), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9699{"zdivwsf", VX(4, 0x26B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9700{"zvsrhu", VX(4, 0x270), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9701{"zvsrhs", VX(4, 0x271), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9702{"zvsrhiu", VX(4, 0x272), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 9703{"zvsrhis", VX(4, 0x273), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 9704{"zvslh", VX(4, 0x274), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9705{"zvrlh", VX(4, 0x275), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9706{"zvslhi", VX(4, 0x276), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 9707{"zvrlhi", VX(4, 0x277), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 9708{"zvslhus", VX(4, 0x278), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9709{"zvslhss", VX(4, 0x279), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9710{"zvslhius", VX(4, 0x27A), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 9711{"zvslhiss", VX(4, 0x27B), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM_LT16}}, 9712{"zslwus", VX(4, 0x27C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9713{"zslwss", VX(4, 0x27D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9714{"zslwius", VX(4, 0x27E), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, 9715{"zslwiss", VX(4, 0x27F), VX_MASK, PPCLSP, 0, {RD, RA, EVUIMM}}, 9716{"zaddwgui", VX(4, 0x460), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9717{"zsubfwgui", VX(4, 0x461), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9718{"zaddd", VX(4, 0x462), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9719{"zsubfd", VX(4, 0x463), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9720{"zvaddsubfw", VX(4, 0x464), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9721{"zvsubfaddw", VX(4, 0x465), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9722{"zvaddw", VX(4, 0x466), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9723{"zvsubfw", VX(4, 0x467), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9724{"zaddwgsi", VX(4, 0x468), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9725{"zsubfwgsi", VX(4, 0x469), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9726{"zadddss", VX(4, 0x46A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9727{"zsubfdss", VX(4, 0x46B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9728{"zvaddsubfwss", VX(4, 0x46C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9729{"zvsubfaddwss", VX(4, 0x46D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9730{"zvaddwss", VX(4, 0x46E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9731{"zvsubfwss", VX(4, 0x46F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9732{"zaddwgsf", VX(4, 0x470), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9733{"zsubfwgsf", VX(4, 0x471), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9734{"zadddus", VX(4, 0x472), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9735{"zsubfdus", VX(4, 0x473), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9736{"zvaddwus", VX(4, 0x476), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9737{"zvsubfwus", VX(4, 0x477), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9738{"zvunpkhgwsf", VX_LSP(4, 0x478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 9739{"zvunpkhsf", VX_LSP(4, 0xC78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 9740{"zvunpkhui", VX_LSP(4, 0x1478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 9741{"zvunpkhsi", VX_LSP(4, 0x1C78), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 9742{"zunpkwgsf", VX_LSP(4, 0x2478), VX_LSP_MASK, PPCLSP, 0, {RD_EVEN, RA}}, 9743{"zvdotphgwasmf", VX(4, 0x488), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9744{"zvdotphgwasmfr", VX(4, 0x489), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9745{"zvdotphgwasmfaa", VX(4, 0x48A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9746{"zvdotphgwasmfraa", VX(4, 0x48B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9747{"zvdotphgwasmfan", VX(4, 0x48C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9748{"zvdotphgwasmfran", VX(4, 0x48D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9749{"zvmhulgwsmf", VX(4, 0x490), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9750{"zvmhulgwsmfr", VX(4, 0x491), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9751{"zvmhulgwsmfaa", VX(4, 0x492), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9752{"zvmhulgwsmfraa", VX(4, 0x493), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9753{"zvmhulgwsmfan", VX(4, 0x494), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9754{"zvmhulgwsmfran", VX(4, 0x495), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9755{"zvmhulgwsmfanp", VX(4, 0x496), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9756{"zvmhulgwsmfranp", VX(4, 0x497), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9757{"zmhegwsmf", VX(4, 0x498), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9758{"zmhegwsmfr", VX(4, 0x499), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9759{"zmhegwsmfaa", VX(4, 0x49A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9760{"zmhegwsmfraa", VX(4, 0x49B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9761{"zmhegwsmfan", VX(4, 0x49C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9762{"zmhegwsmfran", VX(4, 0x49D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9763{"zvdotphxgwasmf", VX(4, 0x4A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9764{"zvdotphxgwasmfr", VX(4, 0x4A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9765{"zvdotphxgwasmfaa", VX(4, 0x4AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9766{"zvdotphxgwasmfraa", VX(4, 0x4AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9767{"zvdotphxgwasmfan", VX(4, 0x4AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9768{"zvdotphxgwasmfran", VX(4, 0x4AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9769{"zvmhllgwsmf", VX(4, 0x4B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9770{"zvmhllgwsmfr", VX(4, 0x4B1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9771{"zvmhllgwsmfaa", VX(4, 0x4B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9772{"zvmhllgwsmfraa", VX(4, 0x4B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9773{"zvmhllgwsmfan", VX(4, 0x4B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9774{"zvmhllgwsmfran", VX(4, 0x4B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9775{"zvmhllgwsmfanp", VX(4, 0x4B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9776{"zvmhllgwsmfranp", VX(4, 0x4B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9777{"zmheogwsmf", VX(4, 0x4B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9778{"zmheogwsmfr", VX(4, 0x4B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9779{"zmheogwsmfaa", VX(4, 0x4BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9780{"zmheogwsmfraa", VX(4, 0x4BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9781{"zmheogwsmfan", VX(4, 0x4BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9782{"zmheogwsmfran", VX(4, 0x4BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9783{"zvdotphgwssmf", VX(4, 0x4C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9784{"zvdotphgwssmfr", VX(4, 0x4C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9785{"zvdotphgwssmfaa", VX(4, 0x4CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9786{"zvdotphgwssmfraa", VX(4, 0x4CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9787{"zvdotphgwssmfan", VX(4, 0x4CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9788{"zvdotphgwssmfran", VX(4, 0x4CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9789{"zvmhuugwsmf", VX(4, 0x4D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9790{"zvmhuugwsmfr", VX(4, 0x4D1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9791{"zvmhuugwsmfaa", VX(4, 0x4D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9792{"zvmhuugwsmfraa", VX(4, 0x4D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9793{"zvmhuugwsmfan", VX(4, 0x4D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9794{"zvmhuugwsmfran", VX(4, 0x4D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9795{"zvmhuugwsmfanp", VX(4, 0x4D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9796{"zvmhuugwsmfranp", VX(4, 0x4D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9797{"zmhogwsmf", VX(4, 0x4D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9798{"zmhogwsmfr", VX(4, 0x4D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9799{"zmhogwsmfaa", VX(4, 0x4DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9800{"zmhogwsmfraa", VX(4, 0x4DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9801{"zmhogwsmfan", VX(4, 0x4DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9802{"zmhogwsmfran", VX(4, 0x4DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 9803{"zvmhxlgwsmf", VX(4, 0x4F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9804{"zvmhxlgwsmfr", VX(4, 0x4F1), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9805{"zvmhxlgwsmfaa", VX(4, 0x4F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9806{"zvmhxlgwsmfraa", VX(4, 0x4F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9807{"zvmhxlgwsmfan", VX(4, 0x4F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9808{"zvmhxlgwsmfran", VX(4, 0x4F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9809{"zvmhxlgwsmfanp", VX(4, 0x4F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9810{"zvmhxlgwsmfranp", VX(4, 0x4F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9811{"zmhegui", VX(4, 0x500), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9812{"zvdotphgaui", VX(4, 0x501), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9813{"zmheguiaa", VX(4, 0x502), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9814{"zvdotphgauiaa", VX(4, 0x503), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9815{"zmheguian", VX(4, 0x504), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9816{"zvdotphgauian", VX(4, 0x505), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9817{"zmhegsi", VX(4, 0x508), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9818{"zvdotphgasi", VX(4, 0x509), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9819{"zmhegsiaa", VX(4, 0x50A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9820{"zvdotphgasiaa", VX(4, 0x50B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9821{"zmhegsian", VX(4, 0x50C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9822{"zvdotphgasian", VX(4, 0x50D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9823{"zmhegsui", VX(4, 0x510), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9824{"zvdotphgasui", VX(4, 0x511), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9825{"zmhegsuiaa", VX(4, 0x512), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9826{"zvdotphgasuiaa", VX(4, 0x513), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9827{"zmhegsuian", VX(4, 0x514), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9828{"zvdotphgasuian", VX(4, 0x515), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9829{"zmhegsmf", VX(4, 0x518), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9830{"zvdotphgasmf", VX(4, 0x519), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9831{"zmhegsmfaa", VX(4, 0x51A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9832{"zvdotphgasmfaa", VX(4, 0x51B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9833{"zmhegsmfan", VX(4, 0x51C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9834{"zvdotphgasmfan", VX(4, 0x51D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9835{"zmheogui", VX(4, 0x520), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9836{"zvdotphxgaui", VX(4, 0x521), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9837{"zmheoguiaa", VX(4, 0x522), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9838{"zvdotphxgauiaa", VX(4, 0x523), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9839{"zmheoguian", VX(4, 0x524), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9840{"zvdotphxgauian", VX(4, 0x525), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9841{"zmheogsi", VX(4, 0x528), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9842{"zvdotphxgasi", VX(4, 0x529), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9843{"zmheogsiaa", VX(4, 0x52A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9844{"zvdotphxgasiaa", VX(4, 0x52B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9845{"zmheogsian", VX(4, 0x52C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9846{"zvdotphxgasian", VX(4, 0x52D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9847{"zmheogsui", VX(4, 0x530), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9848{"zvdotphxgasui", VX(4, 0x531), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9849{"zmheogsuiaa", VX(4, 0x532), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9850{"zvdotphxgasuiaa", VX(4, 0x533), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9851{"zmheogsuian", VX(4, 0x534), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9852{"zvdotphxgasuian", VX(4, 0x535), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9853{"zmheogsmf", VX(4, 0x538), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9854{"zvdotphxgasmf", VX(4, 0x539), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9855{"zmheogsmfaa", VX(4, 0x53A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9856{"zvdotphxgasmfaa", VX(4, 0x53B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9857{"zmheogsmfan", VX(4, 0x53C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9858{"zvdotphxgasmfan", VX(4, 0x53D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9859{"zmhogui", VX(4, 0x540), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9860{"zvdotphgsui", VX(4, 0x541), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9861{"zmhoguiaa", VX(4, 0x542), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9862{"zvdotphgsuiaa", VX(4, 0x543), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9863{"zmhoguian", VX(4, 0x544), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9864{"zvdotphgsuian", VX(4, 0x545), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9865{"zmhogsi", VX(4, 0x548), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9866{"zvdotphgssi", VX(4, 0x549), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9867{"zmhogsiaa", VX(4, 0x54A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9868{"zvdotphgssiaa", VX(4, 0x54B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9869{"zmhogsian", VX(4, 0x54C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9870{"zvdotphgssian", VX(4, 0x54D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9871{"zmhogsui", VX(4, 0x550), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9872{"zvdotphgssui", VX(4, 0x551), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9873{"zmhogsuiaa", VX(4, 0x552), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9874{"zvdotphgssuiaa", VX(4, 0x553), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9875{"zmhogsuian", VX(4, 0x554), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9876{"zvdotphgssuian", VX(4, 0x555), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9877{"zmhogsmf", VX(4, 0x558), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9878{"zvdotphgssmf", VX(4, 0x559), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9879{"zmhogsmfaa", VX(4, 0x55A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9880{"zvdotphgssmfaa", VX(4, 0x55B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9881{"zmhogsmfan", VX(4, 0x55C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9882{"zvdotphgssmfan", VX(4, 0x55D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9883{"zmwgui", VX(4, 0x560), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9884{"zmwguiaa", VX(4, 0x562), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9885{"zmwguiaas", VX(4, 0x563), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9886{"zmwguian", VX(4, 0x564), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9887{"zmwguians", VX(4, 0x565), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9888{"zmwgsi", VX(4, 0x568), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9889{"zmwgsiaa", VX(4, 0x56A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9890{"zmwgsiaas", VX(4, 0x56B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9891{"zmwgsian", VX(4, 0x56C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9892{"zmwgsians", VX(4, 0x56D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9893{"zmwgsui", VX(4, 0x570), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9894{"zmwgsuiaa", VX(4, 0x572), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9895{"zmwgsuiaas", VX(4, 0x573), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9896{"zmwgsuian", VX(4, 0x574), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9897{"zmwgsuians", VX(4, 0x575), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9898{"zmwgsmf", VX(4, 0x578), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9899{"zmwgsmfr", VX(4, 0x579), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9900{"zmwgsmfaa", VX(4, 0x57A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9901{"zmwgsmfraa", VX(4, 0x57B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9902{"zmwgsmfan", VX(4, 0x57C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9903{"zmwgsmfran", VX(4, 0x57D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9904{"zvmhului", VX(4, 0x580), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9905{"zvmhuluiaa", VX(4, 0x582), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9906{"zvmhuluiaas", VX(4, 0x583), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9907{"zvmhuluian", VX(4, 0x584), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9908{"zvmhuluians", VX(4, 0x585), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9909{"zvmhuluianp", VX(4, 0x586), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9910{"zvmhuluianps", VX(4, 0x587), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9911{"zvmhulsi", VX(4, 0x588), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9912{"zvmhulsiaa", VX(4, 0x58A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9913{"zvmhulsiaas", VX(4, 0x58B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9914{"zvmhulsian", VX(4, 0x58C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9915{"zvmhulsians", VX(4, 0x58D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9916{"zvmhulsianp", VX(4, 0x58E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9917{"zvmhulsianps", VX(4, 0x58F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9918{"zvmhulsui", VX(4, 0x590), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9919{"zvmhulsuiaa", VX(4, 0x592), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9920{"zvmhulsuiaas", VX(4, 0x593), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9921{"zvmhulsuian", VX(4, 0x594), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9922{"zvmhulsuians", VX(4, 0x595), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9923{"zvmhulsuianp", VX(4, 0x596), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9924{"zvmhulsuianps", VX(4, 0x597), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9925{"zvmhulsf", VX(4, 0x598), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9926{"zvmhulsfr", VX(4, 0x599), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9927{"zvmhulsfaas", VX(4, 0x59A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9928{"zvmhulsfraas", VX(4, 0x59B), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9929{"zvmhulsfans", VX(4, 0x59C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9930{"zvmhulsfrans", VX(4, 0x59D), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9931{"zvmhulsfanps", VX(4, 0x59E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9932{"zvmhulsfranps", VX(4, 0x59F), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9933{"zvmhllui", VX(4, 0x5A0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9934{"zvmhlluiaa", VX(4, 0x5A2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9935{"zvmhlluiaas", VX(4, 0x5A3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9936{"zvmhlluian", VX(4, 0x5A4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9937{"zvmhlluians", VX(4, 0x5A5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9938{"zvmhlluianp", VX(4, 0x5A6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9939{"zvmhlluianps", VX(4, 0x5A7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9940{"zvmhllsi", VX(4, 0x5A8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9941{"zvmhllsiaa", VX(4, 0x5AA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9942{"zvmhllsiaas", VX(4, 0x5AB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9943{"zvmhllsian", VX(4, 0x5AC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9944{"zvmhllsians", VX(4, 0x5AD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9945{"zvmhllsianp", VX(4, 0x5AE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9946{"zvmhllsianps", VX(4, 0x5AF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9947{"zvmhllsui", VX(4, 0x5B0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9948{"zvmhllsuiaa", VX(4, 0x5B2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9949{"zvmhllsuiaas", VX(4, 0x5B3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9950{"zvmhllsuian", VX(4, 0x5B4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9951{"zvmhllsuians", VX(4, 0x5B5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9952{"zvmhllsuianp", VX(4, 0x5B6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9953{"zvmhllsuianps", VX(4, 0x5B7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9954{"zvmhllsf", VX(4, 0x5B8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9955{"zvmhllsfr", VX(4, 0x5B9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9956{"zvmhllsfaas", VX(4, 0x5BA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9957{"zvmhllsfraas", VX(4, 0x5BB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9958{"zvmhllsfans", VX(4, 0x5BC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9959{"zvmhllsfrans", VX(4, 0x5BD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9960{"zvmhllsfanps", VX(4, 0x5BE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9961{"zvmhllsfranps", VX(4, 0x5BF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9962{"zvmhuuui", VX(4, 0x5C0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9963{"zvmhuuuiaa", VX(4, 0x5C2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9964{"zvmhuuuiaas", VX(4, 0x5C3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9965{"zvmhuuuian", VX(4, 0x5C4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9966{"zvmhuuuians", VX(4, 0x5C5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9967{"zvmhuuuianp", VX(4, 0x5C6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9968{"zvmhuuuianps", VX(4, 0x5C7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9969{"zvmhuusi", VX(4, 0x5C8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9970{"zvmhuusiaa", VX(4, 0x5CA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9971{"zvmhuusiaas", VX(4, 0x5CB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9972{"zvmhuusian", VX(4, 0x5CC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9973{"zvmhuusians", VX(4, 0x5CD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9974{"zvmhuusianp", VX(4, 0x5CE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9975{"zvmhuusianps", VX(4, 0x5CF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9976{"zvmhuusui", VX(4, 0x5D0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9977{"zvmhuusuiaa", VX(4, 0x5D2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9978{"zvmhuusuiaas", VX(4, 0x5D3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9979{"zvmhuusuian", VX(4, 0x5D4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9980{"zvmhuusuians", VX(4, 0x5D5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9981{"zvmhuusuianp", VX(4, 0x5D6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9982{"zvmhuusuianps", VX(4, 0x5D7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9983{"zvmhuusf", VX(4, 0x5D8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9984{"zvmhuusfr", VX(4, 0x5D9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9985{"zvmhuusfaas", VX(4, 0x5DA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9986{"zvmhuusfraas", VX(4, 0x5DB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9987{"zvmhuusfans", VX(4, 0x5DC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9988{"zvmhuusfrans", VX(4, 0x5DD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9989{"zvmhuusfanps", VX(4, 0x5DE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9990{"zvmhuusfranps", VX(4, 0x5DF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9991{"zvmhxlui", VX(4, 0x5E0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9992{"zvmhxluiaa", VX(4, 0x5E2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9993{"zvmhxluiaas", VX(4, 0x5E3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9994{"zvmhxluian", VX(4, 0x5E4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9995{"zvmhxluians", VX(4, 0x5E5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9996{"zvmhxluianp", VX(4, 0x5E6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9997{"zvmhxluianps", VX(4, 0x5E7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9998{"zvmhxlsi", VX(4, 0x5E8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 9999{"zvmhxlsiaa", VX(4, 0x5EA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10000{"zvmhxlsiaas", VX(4, 0x5EB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10001{"zvmhxlsian", VX(4, 0x5EC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10002{"zvmhxlsians", VX(4, 0x5ED), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10003{"zvmhxlsianp", VX(4, 0x5EE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10004{"zvmhxlsianps", VX(4, 0x5EF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10005{"zvmhxlsui", VX(4, 0x5F0), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10006{"zvmhxlsuiaa", VX(4, 0x5F2), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10007{"zvmhxlsuiaas", VX(4, 0x5F3), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10008{"zvmhxlsuian", VX(4, 0x5F4), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10009{"zvmhxlsuians", VX(4, 0x5F5), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10010{"zvmhxlsuianp", VX(4, 0x5F6), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10011{"zvmhxlsuianps", VX(4, 0x5F7), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10012{"zvmhxlsf", VX(4, 0x5F8), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10013{"zvmhxlsfr", VX(4, 0x5F9), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10014{"zvmhxlsfaas", VX(4, 0x5FA), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10015{"zvmhxlsfraas", VX(4, 0x5FB), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10016{"zvmhxlsfans", VX(4, 0x5FC), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10017{"zvmhxlsfrans", VX(4, 0x5FD), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10018{"zvmhxlsfanps", VX(4, 0x5FE), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10019{"zvmhxlsfranps", VX(4, 0x5FF), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10020{"zmheui", VX(4, 0x600), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10021{"zmheuiaa", VX(4, 0x602), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10022{"zmheuiaas", VX(4, 0x603), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10023{"zmheuian", VX(4, 0x604), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10024{"zmheuians", VX(4, 0x605), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10025{"zmhesi", VX(4, 0x608), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10026{"zmhesiaa", VX(4, 0x60A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10027{"zmhesiaas", VX(4, 0x60B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10028{"zmhesian", VX(4, 0x60C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10029{"zmhesians", VX(4, 0x60D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10030{"zmhesui", VX(4, 0x610), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10031{"zmhesuiaa", VX(4, 0x612), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10032{"zmhesuiaas", VX(4, 0x613), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10033{"zmhesuian", VX(4, 0x614), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10034{"zmhesuians", VX(4, 0x615), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10035{"zmhesf", VX(4, 0x618), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10036{"zmhesfr", VX(4, 0x619), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10037{"zmhesfaas", VX(4, 0x61A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10038{"zmhesfraas", VX(4, 0x61B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10039{"zmhesfans", VX(4, 0x61C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10040{"zmhesfrans", VX(4, 0x61D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10041{"zmheoui", VX(4, 0x620), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10042{"zmheouiaa", VX(4, 0x622), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10043{"zmheouiaas", VX(4, 0x623), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10044{"zmheouian", VX(4, 0x624), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10045{"zmheouians", VX(4, 0x625), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10046{"zmheosi", VX(4, 0x628), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10047{"zmheosiaa", VX(4, 0x62A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10048{"zmheosiaas", VX(4, 0x62B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10049{"zmheosian", VX(4, 0x62C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10050{"zmheosians", VX(4, 0x62D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10051{"zmheosui", VX(4, 0x630), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10052{"zmheosuiaa", VX(4, 0x632), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10053{"zmheosuiaas", VX(4, 0x633), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10054{"zmheosuian", VX(4, 0x634), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10055{"zmheosuians", VX(4, 0x635), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10056{"zmheosf", VX(4, 0x638), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10057{"zmheosfr", VX(4, 0x639), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10058{"zmheosfaas", VX(4, 0x63A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10059{"zmheosfraas", VX(4, 0x63B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10060{"zmheosfans", VX(4, 0x63C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10061{"zmheosfrans", VX(4, 0x63D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10062{"zmhoui", VX(4, 0x640), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10063{"zmhouiaa", VX(4, 0x642), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10064{"zmhouiaas", VX(4, 0x643), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10065{"zmhouian", VX(4, 0x644), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10066{"zmhouians", VX(4, 0x645), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10067{"zmhosi", VX(4, 0x648), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10068{"zmhosiaa", VX(4, 0x64A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10069{"zmhosiaas", VX(4, 0x64B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10070{"zmhosian", VX(4, 0x64C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10071{"zmhosians", VX(4, 0x64D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10072{"zmhosui", VX(4, 0x650), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10073{"zmhosuiaa", VX(4, 0x652), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10074{"zmhosuiaas", VX(4, 0x653), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10075{"zmhosuian", VX(4, 0x654), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10076{"zmhosuians", VX(4, 0x655), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10077{"zmhosf", VX(4, 0x658), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10078{"zmhosfr", VX(4, 0x659), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10079{"zmhosfaas", VX(4, 0x65A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10080{"zmhosfraas", VX(4, 0x65B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10081{"zmhosfans", VX(4, 0x65C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10082{"zmhosfrans", VX(4, 0x65D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10083{"zvmhuih", VX(4, 0x660), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10084{"zvmhuihs", VX(4, 0x661), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10085{"zvmhuiaah", VX(4, 0x662), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10086{"zvmhuiaahs", VX(4, 0x663), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10087{"zvmhuianh", VX(4, 0x664), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10088{"zvmhuianhs", VX(4, 0x665), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10089{"zvmhsihs", VX(4, 0x669), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10090{"zvmhsiaahs", VX(4, 0x66B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10091{"zvmhsianhs", VX(4, 0x66D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10092{"zvmhsuihs", VX(4, 0x671), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10093{"zvmhsuiaahs", VX(4, 0x673), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10094{"zvmhsuianhs", VX(4, 0x675), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10095{"zvmhsfh", VX(4, 0x678), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10096{"zvmhsfrh", VX(4, 0x679), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10097{"zvmhsfaahs", VX(4, 0x67A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10098{"zvmhsfraahs", VX(4, 0x67B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10099{"zvmhsfanhs", VX(4, 0x67C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10100{"zvmhsfranhs", VX(4, 0x67D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10101{"zvdotphaui", VX(4, 0x680), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10102{"zvdotphauis", VX(4, 0x681), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10103{"zvdotphauiaa", VX(4, 0x682), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10104{"zvdotphauiaas", VX(4, 0x683), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10105{"zvdotphauian", VX(4, 0x684), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10106{"zvdotphauians", VX(4, 0x685), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10107{"zvdotphasi", VX(4, 0x688), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10108{"zvdotphasis", VX(4, 0x689), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10109{"zvdotphasiaa", VX(4, 0x68A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10110{"zvdotphasiaas", VX(4, 0x68B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10111{"zvdotphasian", VX(4, 0x68C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10112{"zvdotphasians", VX(4, 0x68D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10113{"zvdotphasui", VX(4, 0x690), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10114{"zvdotphasuis", VX(4, 0x691), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10115{"zvdotphasuiaa", VX(4, 0x692), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10116{"zvdotphasuiaas", VX(4, 0x693), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10117{"zvdotphasuian", VX(4, 0x694), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10118{"zvdotphasuians", VX(4, 0x695), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10119{"zvdotphasfs", VX(4, 0x698), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10120{"zvdotphasfrs", VX(4, 0x699), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10121{"zvdotphasfaas", VX(4, 0x69A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10122{"zvdotphasfraas", VX(4, 0x69B), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10123{"zvdotphasfans", VX(4, 0x69C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10124{"zvdotphasfrans", VX(4, 0x69D), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10125{"zvdotphxaui", VX(4, 0x6A0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10126{"zvdotphxauis", VX(4, 0x6A1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10127{"zvdotphxauiaa", VX(4, 0x6A2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10128{"zvdotphxauiaas", VX(4, 0x6A3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10129{"zvdotphxauian", VX(4, 0x6A4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10130{"zvdotphxauians", VX(4, 0x6A5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10131{"zvdotphxasi", VX(4, 0x6A8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10132{"zvdotphxasis", VX(4, 0x6A9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10133{"zvdotphxasiaa", VX(4, 0x6AA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10134{"zvdotphxasiaas", VX(4, 0x6AB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10135{"zvdotphxasian", VX(4, 0x6AC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10136{"zvdotphxasians", VX(4, 0x6AD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10137{"zvdotphxasui", VX(4, 0x6B0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10138{"zvdotphxasuis", VX(4, 0x6B1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10139{"zvdotphxasuiaa", VX(4, 0x6B2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10140{"zvdotphxasuiaas", VX(4, 0x6B3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10141{"zvdotphxasuian", VX(4, 0x6B4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10142{"zvdotphxasuians", VX(4, 0x6B5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10143{"zvdotphxasfs", VX(4, 0x6B8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10144{"zvdotphxasfrs", VX(4, 0x6B9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10145{"zvdotphxasfaas", VX(4, 0x6BA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10146{"zvdotphxasfraas", VX(4, 0x6BB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10147{"zvdotphxasfans", VX(4, 0x6BC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10148{"zvdotphxasfrans", VX(4, 0x6BD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10149{"zvdotphsui", VX(4, 0x6C0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10150{"zvdotphsuis", VX(4, 0x6C1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10151{"zvdotphsuiaa", VX(4, 0x6C2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10152{"zvdotphsuiaas", VX(4, 0x6C3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10153{"zvdotphsuian", VX(4, 0x6C4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10154{"zvdotphsuians", VX(4, 0x6C5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10155{"zvdotphssi", VX(4, 0x6C8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10156{"zvdotphssis", VX(4, 0x6C9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10157{"zvdotphssiaa", VX(4, 0x6CA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10158{"zvdotphssiaas", VX(4, 0x6CB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10159{"zvdotphssian", VX(4, 0x6CC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10160{"zvdotphssians", VX(4, 0x6CD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10161{"zvdotphssui", VX(4, 0x6D0), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10162{"zvdotphssuis", VX(4, 0x6D1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10163{"zvdotphssuiaa", VX(4, 0x6D2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10164{"zvdotphssuiaas", VX(4, 0x6D3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10165{"zvdotphssuian", VX(4, 0x6D4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10166{"zvdotphssuians", VX(4, 0x6D5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10167{"zvdotphssfs", VX(4, 0x6D8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10168{"zvdotphssfrs", VX(4, 0x6D9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10169{"zvdotphssfaas", VX(4, 0x6DA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10170{"zvdotphssfraas", VX(4, 0x6DB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10171{"zvdotphssfans", VX(4, 0x6DC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10172{"zvdotphssfrans", VX(4, 0x6DD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10173{"zmwluis", VX(4, 0x6E1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10174{"zmwluiaa", VX(4, 0x6E2), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10175{"zmwluiaas", VX(4, 0x6E3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10176{"zmwluian", VX(4, 0x6E4), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10177{"zmwluians", VX(4, 0x6E5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10178{"zmwlsis", VX(4, 0x6E9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10179{"zmwlsiaas", VX(4, 0x6EB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10180{"zmwlsians", VX(4, 0x6ED), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10181{"zmwlsuis", VX(4, 0x6F1), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10182{"zmwlsuiaas", VX(4, 0x6F3), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10183{"zmwlsuians", VX(4, 0x6F5), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10184{"zmwsf", VX(4, 0x6F8), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10185{"zmwsfr", VX(4, 0x6F9), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10186{"zmwsfaas", VX(4, 0x6FA), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10187{"zmwsfraas", VX(4, 0x6FB), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10188{"zmwsfans", VX(4, 0x6FC), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10189{"zmwsfrans", VX(4, 0x6FD), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10190{"zlddx", VX(4, 0x300), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10191{"zldd", VX(4, 0x301), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, 10192{"zldwx", VX(4, 0x302), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10193{"zldw", VX(4, 0x303), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, 10194{"zldhx", VX(4, 0x304), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10195{"zldh", VX(4, 0x305), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8, RA}}, 10196{"zlwgsfdx", VX(4, 0x308), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10197{"zlwgsfd", VX(4, 0x309), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 10198{"zlwwosdx", VX(4, 0x30A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10199{"zlwwosd", VX(4, 0x30B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 10200{"zlwhsplatwdx", VX(4, 0x30C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10201{"zlwhsplatwd", VX(4, 0x30D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 10202{"zlwhsplatdx", VX(4, 0x30E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10203{"zlwhsplatd", VX(4, 0x30F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 10204{"zlwhgwsfdx", VX(4, 0x310), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10205{"zlwhgwsfd", VX(4, 0x311), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 10206{"zlwhedx", VX(4, 0x312), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10207{"zlwhed", VX(4, 0x313), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 10208{"zlwhosdx", VX(4, 0x314), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10209{"zlwhosd", VX(4, 0x315), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 10210{"zlwhoudx", VX(4, 0x316), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10211{"zlwhoud", VX(4, 0x317), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4, RA}}, 10212{"zlwhx", VX(4, 0x318), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10213{"zlwh", VX(4, 0x319), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, 10214{"zlwwx", VX(4, 0x31A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10215{"zlww", VX(4, 0x31B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4, RA}}, 10216{"zlhgwsfx", VX(4, 0x31C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10217{"zlhgwsf", VX(4, 0x31D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 10218{"zlhhsplatx", VX(4, 0x31E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10219{"zlhhsplat", VX(4, 0x31F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 10220{"zstddx", VX(4, 0x320), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10221{"zstdd", VX(4, 0x321), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, 10222{"zstdwx", VX(4, 0x322), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10223{"zstdw", VX(4, 0x323), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, 10224{"zstdhx", VX(4, 0x324), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10225{"zstdh", VX(4, 0x325), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8, RA}}, 10226{"zstwhedx", VX(4, 0x328), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10227{"zstwhed", VX(4, 0x329), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, 10228{"zstwhodx", VX(4, 0x32A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10229{"zstwhod", VX(4, 0x32B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4, RA}}, 10230{"zlhhex", VX(4, 0x330), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10231{"zlhhe", VX(4, 0x331), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 10232{"zlhhosx", VX(4, 0x332), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10233{"zlhhos", VX(4, 0x333), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 10234{"zlhhoux", VX(4, 0x334), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10235{"zlhhou", VX(4, 0x335), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2, RA}}, 10236{"zsthex", VX(4, 0x338), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 10237{"zsthe", VX(4, 0x339), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, 10238{"zsthox", VX(4, 0x33A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 10239{"zstho", VX(4, 0x33B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2, RA}}, 10240{"zstwhx", VX(4, 0x33C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 10241{"zstwh", VX(4, 0x33D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, 10242{"zstwwx", VX(4, 0x33E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 10243{"zstww", VX(4, 0x33F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4, RA}}, 10244{"zlddmx", VX(4, 0x340), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10245{"zlddu", VX(4, 0x341), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, 10246{"zldwmx", VX(4, 0x342), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10247{"zldwu", VX(4, 0x343), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, 10248{"zldhmx", VX(4, 0x344), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10249{"zldhu", VX(4, 0x345), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_8_EX0, RA}}, 10250{"zlwgsfdmx", VX(4, 0x348), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10251{"zlwgsfdu", VX(4, 0x349), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 10252{"zlwwosdmx", VX(4, 0x34A), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10253{"zlwwosdu", VX(4, 0x34B), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 10254{"zlwhsplatwdmx", VX(4, 0x34C), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10255{"zlwhsplatwdu", VX(4, 0x34D), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 10256{"zlwhsplatdmx", VX(4, 0x34E), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10257{"zlwhsplatdu", VX(4, 0x34F), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 10258{"zlwhgwsfdmx", VX(4, 0x350), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10259{"zlwhgwsfdu", VX(4, 0x351), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 10260{"zlwhedmx", VX(4, 0x352), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10261{"zlwhedu", VX(4, 0x353), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 10262{"zlwhosdmx", VX(4, 0x354), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10263{"zlwhosdu", VX(4, 0x355), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 10264{"zlwhoudmx", VX(4, 0x356), VX_MASK, PPCLSP, 0, {RD_EVEN, RA, RB}}, 10265{"zlwhoudu", VX(4, 0x357), VX_MASK, PPCLSP, 0, {RD_EVEN, EVUIMM_4_EX0, RA}}, 10266{"zlwhmx", VX(4, 0x358), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10267{"zlwhu", VX(4, 0x359), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, 10268{"zlwwmx", VX(4, 0x35A), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10269{"zlwwu", VX(4, 0x35B), VX_MASK, PPCLSP, 0, {RD, EVUIMM_4_EX0, RA}}, 10270{"zlhgwsfmx", VX(4, 0x35C), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10271{"zlhgwsfu", VX(4, 0x35D), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 10272{"zlhhsplatmx", VX(4, 0x35E), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10273{"zlhhsplatu", VX(4, 0x35F), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 10274{"zstddmx", VX(4, 0x360), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10275{"zstddu", VX(4, 0x361), VX_MASK, PPCLSP, 0, {RS, EVUIMM_8_EX0, RA}}, 10276{"zstdwmx", VX(4, 0x362), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10277{"zstdwu", VX(4, 0x363), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, 10278{"zstdhmx", VX(4, 0x364), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10279{"zstdhu", VX(4, 0x365), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_8_EX0, RA}}, 10280{"zstwhedmx", VX(4, 0x368), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10281{"zstwhedu", VX(4, 0x369), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, 10282{"zstwhodmx", VX(4, 0x36A), VX_MASK, PPCLSP, 0, {RS_EVEN, RA, RB}}, 10283{"zstwhodu", VX(4, 0x36B), VX_MASK, PPCLSP, 0, {RS_EVEN, EVUIMM_4_EX0, RA}}, 10284{"zlhhemx", VX(4, 0x370), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10285{"zlhheu", VX(4, 0x371), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 10286{"zlhhosmx", VX(4, 0x372), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10287{"zlhhosu", VX(4, 0x373), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 10288{"zlhhoumx", VX(4, 0x374), VX_MASK, PPCLSP, 0, {RD, RA, RB}}, 10289{"zlhhouu", VX(4, 0x375), VX_MASK, PPCLSP, 0, {RD, EVUIMM_2_EX0, RA}}, 10290{"zsthemx", VX(4, 0x378), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 10291{"zstheu", VX(4, 0x379), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, 10292{"zsthomx", VX(4, 0x37A), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 10293{"zsthou", VX(4, 0x37B), VX_MASK, PPCLSP, 0, {RS, EVUIMM_2_EX0, RA}}, 10294{"zstwhmx", VX(4, 0x37C), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 10295{"zstwhu", VX(4, 0x37D), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, 10296{"zstwwmx", VX(4, 0x37E), VX_MASK, PPCLSP, 0, {RS, RA, RB}}, 10297{"zstwwu", VX(4, 0x37F), VX_MASK, PPCLSP, 0, {RS, EVUIMM_4_EX0, RA}}, 10298 10299{"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 10300{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 10301{"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 10302{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}}, 10303{"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 10304{"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}}, 10305{"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 10306{"e_addic", SCI8(6,18), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 10307{"e_subic", SCI8(6,18), SCI8_MASK, PPCVLE, EXT, {RT, RA, SCLSCI8N}}, 10308{"e_addic.", SCI8(6,19), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 10309{"e_subic.", SCI8(6,19), SCI8_MASK, PPCVLE, EXT, {RT, RA, SCLSCI8N}}, 10310{"e_mulli", SCI8(6,20), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 10311{"e_subfic", SCI8(6,22), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 10312{"e_subfic.", SCI8(6,23), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}}, 10313{"e_andi", SCI8(6,24), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 10314{"e_andi.", SCI8(6,25), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 10315{"e_nop", SCI8(6,26), 0xffffffff, PPCVLE, EXT, {0}}, 10316{"e_ori", SCI8(6,26), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 10317{"e_ori.", SCI8(6,27), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 10318{"e_xori", SCI8(6,28), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 10319{"e_xori.", SCI8(6,29), SCI8_MASK, PPCVLE, 0, {RA, RS, SCLSCI8}}, 10320{"e_lbzu", OPVUP(6,0), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 10321{"e_lhau", OPVUP(6,3), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 10322{"e_lhzu", OPVUP(6,1), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 10323{"e_lmw", OPVUP(6,8), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 10324{"e_lwzu", OPVUP(6,2), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 10325{"e_stbu", OPVUP(6,4), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 10326{"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 10327{"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 10328{"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}}, 10329{"e_lmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10330{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10331{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10332{"e_lmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10333{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10334{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10335{"e_lmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10336{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10337{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10338{"e_lmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10339{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10340{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10341{"e_lmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10342{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10343{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10344{"e_lmvmcsrrw", OPVUPRT(6,16,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10345{"e_stmvmcsrrw", OPVUPRT(6,17,7),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}}, 10346{"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}}, 10347{"e_la", OP(7), OP_MASK, PPCVLE, EXT, {RT, D, RA0}}, 10348{"e_sub16i", OP(7), OP_MASK, PPCVLE, EXT, {RT, RA, NSI}}, 10349 10350{"se_addi", SE_IM5(8,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 10351{"se_cmpli", SE_IM5(8,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 10352{"se_subi", SE_IM5(9,0), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 10353{"se_subi.", SE_IM5(9,1), SE_IM5_MASK, PPCVLE, 0, {RX, OIMM5}}, 10354{"se_cmpi", SE_IM5(10,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10355{"se_bmaski", SE_IM5(11,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10356{"se_andi", SE_IM5(11,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10357 10358{"e_lbz", OP(12), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 10359{"e_stb", OP(13), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 10360{"e_lha", OP(14), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 10361 10362{"se_srw", SE_RR(16,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 10363{"se_sraw", SE_RR(16,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 10364{"se_slw", SE_RR(16,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 10365{"se_nop", SE_RR(17,0), 0xffff, PPCVLE, EXT, {0}}, 10366{"se_or", SE_RR(17,0), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 10367{"se_andc", SE_RR(17,1), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 10368{"se_and", SE_RR(17,2), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 10369{"se_and.", SE_RR(17,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}}, 10370{"se_li", IM7(9), IM7_MASK, PPCVLE, 0, {RX, UI7}}, 10371 10372{"e_lwz", OP(20), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 10373{"e_stw", OP(21), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 10374{"e_lhz", OP(22), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 10375{"e_sth", OP(23), OP_MASK, PPCVLE, 0, {RT, D, RA0}}, 10376 10377{"se_bclri", SE_IM5(24,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10378{"se_bgeni", SE_IM5(24,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10379{"se_bseti", SE_IM5(25,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10380{"se_btsti", SE_IM5(25,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10381{"se_srwi", SE_IM5(26,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10382{"se_srawi", SE_IM5(26,1), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10383{"se_slwi", SE_IM5(27,0), SE_IM5_MASK, PPCVLE, 0, {RX, UI5}}, 10384 10385{"e_lis", I16L(28,28), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 10386{"e_and2is.", I16L(28,29), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 10387{"e_or2is", I16L(28,26), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 10388{"e_and2i.", I16L(28,25), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 10389{"e_or2i", I16L(28,24), I16L_MASK, PPCVLE, 0, {RD, VLEUIMML}}, 10390{"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}}, 10391{"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, 10392{"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}}, 10393{"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 10394{"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}}, 10395{"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, EXT, {RA, VLENSIMM}}, 10396{"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 10397{"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, EXT, {RA, VLENSIMM}}, 10398{"e_add2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}}, 10399{"e_li", LI20(28,0), LI20_MASK, PPCVLE, 0, {RT, IMM20}}, 10400{"e_rlwimi", M(29,0), M_MASK, PPCVLE, 0, {RA, RS, SH, MB, ME}}, 10401{"e_inslwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, ILWn, ILWb}}, 10402{"e_insrwi", M(29,0), M_MASK, PPCVLE, EXT, {RA, RS, IRWn, IRWb}}, 10403{"e_rotlwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, SH}}, 10404{"e_rotrwi", MME(29,31,1), MMBME_MASK, PPCVLE, EXT, {RA, RS, RRWn}}, 10405{"e_clrlwi", MME(29,31,1), MSHME_MASK, PPCVLE, EXT, {RA, RS, MB}}, 10406{"e_clrrwi", M(29,1), MSHMB_MASK, PPCVLE, EXT, {RA, RS, CRWn}}, 10407{"e_rlwinm", M(29,1), M_MASK, PPCVLE, 0, {RA, RS, SH, MBE, ME}}, 10408{"e_extlwi", M(29,1), MMB_MASK, PPCVLE, EXT, {RA, RS, ELWn, SH}}, 10409{"e_extrwi", MME(29,31,1), MME_MASK, PPCVLE, EXT, {RA, RS, ERWn, ERWb}}, 10410{"e_clrlslwi", M(29,1), M_MASK, PPCVLE, EXT, {RA, RS, CSLWb, CSLWn}}, 10411{"e_b", BD24(30,0,0), BD24_MASK, PPCVLE, 0, {B24}}, 10412{"e_bl", BD24(30,0,1), BD24_MASK, PPCVLE, 0, {B24}}, 10413{"e_bdnz", EBD15(30,8,BO32DNZ,0), EBD15_MASK, PPCVLE, EXT, {B15}}, 10414{"e_bdnzl", EBD15(30,8,BO32DNZ,1), EBD15_MASK, PPCVLE, EXT, {B15}}, 10415{"e_bdz", EBD15(30,8,BO32DZ,0), EBD15_MASK, PPCVLE, EXT, {B15}}, 10416{"e_bdzl", EBD15(30,8,BO32DZ,1), EBD15_MASK, PPCVLE, EXT, {B15}}, 10417{"e_bge", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10418{"e_bgel", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10419{"e_bnl", EBD15BI(30,8,BO32F,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10420{"e_bnll", EBD15BI(30,8,BO32F,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10421{"e_blt", EBD15BI(30,8,BO32T,CBLT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10422{"e_bltl", EBD15BI(30,8,BO32T,CBLT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10423{"e_bgt", EBD15BI(30,8,BO32T,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10424{"e_bgtl", EBD15BI(30,8,BO32T,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10425{"e_ble", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10426{"e_blel", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10427{"e_bng", EBD15BI(30,8,BO32F,CBGT,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10428{"e_bngl", EBD15BI(30,8,BO32F,CBGT,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10429{"e_bne", EBD15BI(30,8,BO32F,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10430{"e_bnel", EBD15BI(30,8,BO32F,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10431{"e_beq", EBD15BI(30,8,BO32T,CBEQ,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10432{"e_beql", EBD15BI(30,8,BO32T,CBEQ,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10433{"e_bso", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10434{"e_bsol", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10435{"e_bun", EBD15BI(30,8,BO32T,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10436{"e_bunl", EBD15BI(30,8,BO32T,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10437{"e_bns", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10438{"e_bnsl", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10439{"e_bnu", EBD15BI(30,8,BO32F,CBSO,0), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10440{"e_bnul", EBD15BI(30,8,BO32F,CBSO,1), EBD15BI_MASK, PPCVLE, EXT, {CRS,B15}}, 10441{"e_bc", BD15(30,8,0), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, 10442{"e_bcl", BD15(30,8,1), BD15_MASK, PPCVLE, 0, {BO32, BI32, B15}}, 10443 10444{"e_bf", EBD15(30,8,BO32F,0), EBD15_MASK, PPCVLE, EXT, {BI32,B15}}, 10445{"e_bfl", EBD15(30,8,BO32F,1), EBD15_MASK, PPCVLE, EXT, {BI32,B15}}, 10446{"e_bt", EBD15(30,8,BO32T,0), EBD15_MASK, PPCVLE, EXT, {BI32,B15}}, 10447{"e_btl", EBD15(30,8,BO32T,1), EBD15_MASK, PPCVLE, EXT, {BI32,B15}}, 10448 10449{"e_cmph", X(31,14), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, 10450{"e_sc", X(31,36), XRTRA_MASK, PPCVLE, 0, {ELEV}}, 10451{"e_cmphl", X(31,46), X_MASK, PPCVLE, 0, {CRD, RA, RB}}, 10452{"e_crandc", XL(31,129), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 10453{"e_crnand", XL(31,225), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 10454{"e_crnot", XL(31,33), XL_MASK, PPCVLE, EXT, {BT, BAB}}, 10455{"e_crnor", XL(31,33), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 10456{"e_crclr", XL(31,193), XL_MASK, PPCVLE, EXT, {BTAB}}, 10457{"e_crxor", XL(31,193), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 10458{"e_mcrf", XL(31,16), XL_MASK, PPCVLE, 0, {CRD, CR}}, 10459{"e_slwi", EX(31,112), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 10460{"e_slwi.", EX(31,113), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 10461 10462{"e_crand", XL(31,257), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 10463 10464{"e_rlw", EX(31,560), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, 10465{"e_rlw.", EX(31,561), EX_MASK, PPCVLE, 0, {RA, RS, RB}}, 10466 10467{"e_crset", XL(31,289), XL_MASK, PPCVLE, EXT, {BTAB}}, 10468{"e_creqv", XL(31,289), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 10469 10470{"e_rlwi", EX(31,624), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 10471{"e_rlwi.", EX(31,625), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 10472 10473{"e_crorc", XL(31,417), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 10474 10475{"e_crmove", XL(31,449), XL_MASK, PPCVLE, EXT, {BT, BAB}}, 10476{"e_cror", XL(31,449), XL_MASK, PPCVLE, 0, {BT, BA, BB}}, 10477 10478{"mtmas1", XSPR(31,467,625), XSPR_MASK, PPCVLE, EXT, {RS}}, 10479 10480{"e_srwi", EX(31,1136), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 10481{"e_srwi.", EX(31,1137), EX_MASK, PPCVLE, 0, {RA, RS, SH}}, 10482 10483{"se_lbz", SD4(8), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, 10484 10485{"se_stb", SD4(9), SD4_MASK, PPCVLE, 0, {RZ, SE_SD, RX}}, 10486 10487{"se_lhz", SD4(10), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, 10488 10489{"se_sth", SD4(11), SD4_MASK, PPCVLE, 0, {RZ, SE_SDH, RX}}, 10490 10491{"se_lwz", SD4(12), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, 10492 10493{"se_stw", SD4(13), SD4_MASK, PPCVLE, 0, {RZ, SE_SDW, RX}}, 10494 10495{"se_bge", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10496{"se_bnl", EBD8IO(28,0,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10497{"se_ble", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10498{"se_bng", EBD8IO(28,0,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10499{"se_bne", EBD8IO(28,0,2), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10500{"se_bns", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10501{"se_bnu", EBD8IO(28,0,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10502{"se_bf", EBD8IO(28,0,0), EBD8IO2_MASK, PPCVLE, EXT, {BI16, B8}}, 10503{"se_blt", EBD8IO(28,1,0), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10504{"se_bgt", EBD8IO(28,1,1), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10505{"se_beq", EBD8IO(28,1,2), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10506{"se_bso", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10507{"se_bun", EBD8IO(28,1,3), EBD8IO3_MASK, PPCVLE, EXT, {B8}}, 10508{"se_bt", EBD8IO(28,1,0), EBD8IO2_MASK, PPCVLE, EXT, {BI16, B8}}, 10509{"se_bc", BD8IO(28), BD8IO_MASK, PPCVLE, 0, {BO16, BI16, B8}}, 10510{"se_b", BD8(58,0,0), BD8_MASK, PPCVLE, 0, {B8}}, 10511{"se_bl", BD8(58,0,1), BD8_MASK, PPCVLE, 0, {B8}}, 10512}; 10513 10514const unsigned int vle_num_opcodes = 10515 sizeof (vle_opcodes) / sizeof (vle_opcodes[0]); 10516 10517/* SPE v2 instruction set from SPE2PIM Rev. 2 08/2011 */ 10518const struct powerpc_opcode spe2_opcodes[] = { 10519{"evdotpwcssi", VX (4, 128), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10520{"evdotpwcsmi", VX (4, 129), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10521{"evdotpwcssfr", VX (4, 130), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10522{"evdotpwcssf", VX (4, 131), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10523{"evdotpwgasmf", VX (4, 136), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10524{"evdotpwxgasmf", VX (4, 137), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10525{"evdotpwgasmfr", VX (4, 138), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10526{"evdotpwxgasmfr", VX (4, 139), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10527{"evdotpwgssmf", VX (4, 140), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10528{"evdotpwxgssmf", VX (4, 141), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10529{"evdotpwgssmfr", VX (4, 142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10530{"evdotpwxgssmfr", VX (4, 143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10531{"evdotpwcssiaaw3", VX (4, 144), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10532{"evdotpwcsmiaaw3", VX (4, 145), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10533{"evdotpwcssfraaw3", VX (4, 146), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10534{"evdotpwcssfaaw3", VX (4, 147), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10535{"evdotpwgasmfaa3", VX (4, 152), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10536{"evdotpwxgasmfaa3", VX (4, 153), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10537{"evdotpwgasmfraa3", VX (4, 154), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10538{"evdotpwxgasmfraa3", VX (4, 155), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10539{"evdotpwgssmfaa3", VX (4, 156), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10540{"evdotpwxgssmfaa3", VX (4, 157), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10541{"evdotpwgssmfraa3", VX (4, 158), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10542{"evdotpwxgssmfraa3", VX (4, 159), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10543{"evdotpwcssia", VX (4, 160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10544{"evdotpwcsmia", VX (4, 161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10545{"evdotpwcssfra", VX (4, 162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10546{"evdotpwcssfa", VX (4, 163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10547{"evdotpwgasmfa", VX (4, 168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10548{"evdotpwxgasmfa", VX (4, 169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10549{"evdotpwgasmfra", VX (4, 170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10550{"evdotpwxgasmfra", VX (4, 171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10551{"evdotpwgssmfa", VX (4, 172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10552{"evdotpwxgssmfa", VX (4, 173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10553{"evdotpwgssmfra", VX (4, 174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10554{"evdotpwxgssmfra", VX (4, 175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10555{"evdotpwcssiaaw", VX (4, 176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10556{"evdotpwcsmiaaw", VX (4, 177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10557{"evdotpwcssfraaw", VX (4, 178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10558{"evdotpwcssfaaw", VX (4, 179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10559{"evdotpwgasmfaa", VX (4, 184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10560{"evdotpwxgasmfaa", VX (4, 185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10561{"evdotpwgasmfraa", VX (4, 186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10562{"evdotpwxgasmfraa", VX (4, 187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10563{"evdotpwgssmfaa", VX (4, 188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10564{"evdotpwxgssmfaa", VX (4, 189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10565{"evdotpwgssmfraa", VX (4, 190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10566{"evdotpwxgssmfraa", VX (4, 191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10567{"evdotphihcssi", VX (4, 256), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10568{"evdotplohcssi", VX (4, 257), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10569{"evdotphihcssf", VX (4, 258), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10570{"evdotplohcssf", VX (4, 259), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10571{"evdotphihcsmi", VX (4, 264), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10572{"evdotplohcsmi", VX (4, 265), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10573{"evdotphihcssfr", VX (4, 266), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10574{"evdotplohcssfr", VX (4, 267), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10575{"evdotphihcssiaaw3", VX (4, 272), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10576{"evdotplohcssiaaw3", VX (4, 273), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10577{"evdotphihcssfaaw3", VX (4, 274), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10578{"evdotplohcssfaaw3", VX (4, 275), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10579{"evdotphihcsmiaaw3", VX (4, 280), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10580{"evdotplohcsmiaaw3", VX (4, 281), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10581{"evdotphihcssfraaw3", VX (4, 282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10582{"evdotplohcssfraaw3", VX (4, 283), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10583{"evdotphihcssia", VX (4, 288), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10584{"evdotplohcssia", VX (4, 289), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10585{"evdotphihcssfa", VX (4, 290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10586{"evdotplohcssfa", VX (4, 291), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10587{"evdotphihcsmia", VX (4, 296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10588{"evdotplohcsmia", VX (4, 297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10589{"evdotphihcssfra", VX (4, 298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10590{"evdotplohcssfra", VX (4, 299), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10591{"evdotphihcssiaaw", VX (4, 304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10592{"evdotplohcssiaaw", VX (4, 305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10593{"evdotphihcssfaaw", VX (4, 306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10594{"evdotplohcssfaaw", VX (4, 307), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10595{"evdotphihcsmiaaw", VX (4, 312), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10596{"evdotplohcsmiaaw", VX (4, 313), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10597{"evdotphihcssfraaw", VX (4, 314), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10598{"evdotplohcssfraaw", VX (4, 315), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10599{"evdotphausi", VX (4, 320), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10600{"evdotphassi", VX (4, 321), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10601{"evdotphasusi", VX (4, 322), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10602{"evdotphassf", VX (4, 323), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10603{"evdotphsssf", VX (4, 327), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10604{"evdotphaumi", VX (4, 328), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10605{"evdotphasmi", VX (4, 329), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10606{"evdotphasumi", VX (4, 330), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10607{"evdotphassfr", VX (4, 331), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10608{"evdotphssmi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10609{"evdotphsssi", VX (4, 333), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10610{"evdotphsssfr", VX (4, 335), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10611{"evdotphausiaaw3", VX (4, 336), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10612{"evdotphassiaaw3", VX (4, 337), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10613{"evdotphasusiaaw3", VX (4, 338), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10614{"evdotphassfaaw3", VX (4, 339), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10615{"evdotphsssiaaw3", VX (4, 341), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10616{"evdotphsssfaaw3", VX (4, 343), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10617{"evdotphaumiaaw3", VX (4, 344), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10618{"evdotphasmiaaw3", VX (4, 345), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10619{"evdotphasumiaaw3", VX (4, 346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10620{"evdotphassfraaw3", VX (4, 347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10621{"evdotphssmiaaw3", VX (4, 349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10622{"evdotphsssfraaw3", VX (4, 351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10623{"evdotphausia", VX (4, 352), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10624{"evdotphassia", VX (4, 353), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10625{"evdotphasusia", VX (4, 354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10626{"evdotphassfa", VX (4, 355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10627{"evdotphsssfa", VX (4, 359), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10628{"evdotphaumia", VX (4, 360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10629{"evdotphasmia", VX (4, 361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10630{"evdotphasumia", VX (4, 362), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10631{"evdotphassfra", VX (4, 363), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10632{"evdotphssmia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10633{"evdotphsssia", VX (4, 365), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10634{"evdotphsssfra", VX (4, 367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10635{"evdotphausiaaw", VX (4, 368), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10636{"evdotphassiaaw", VX (4, 369), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10637{"evdotphasusiaaw", VX (4, 370), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10638{"evdotphassfaaw", VX (4, 371), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10639{"evdotphsssiaaw", VX (4, 373), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10640{"evdotphsssfaaw", VX (4, 375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10641{"evdotphaumiaaw", VX (4, 376), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10642{"evdotphasmiaaw", VX (4, 377), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10643{"evdotphasumiaaw", VX (4, 378), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10644{"evdotphassfraaw", VX (4, 379), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10645{"evdotphssmiaaw", VX (4, 381), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10646{"evdotphsssfraaw", VX (4, 383), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10647{"evdotp4hgaumi", VX (4, 384), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10648{"evdotp4hgasmi", VX (4, 385), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10649{"evdotp4hgasumi", VX (4, 386), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10650{"evdotp4hgasmf", VX (4, 387), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10651{"evdotp4hgssmi", VX (4, 388), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10652{"evdotp4hgssmf", VX (4, 389), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10653{"evdotp4hxgasmi", VX (4, 390), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10654{"evdotp4hxgasmf", VX (4, 391), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10655{"evdotpbaumi", VX (4, 392), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10656{"evdotpbasmi", VX (4, 393), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10657{"evdotpbasumi", VX (4, 394), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10658{"evdotp4hxgssmi", VX (4, 398), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10659{"evdotp4hxgssmf", VX (4, 399), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10660{"evdotp4hgaumiaa3", VX (4, 400), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10661{"evdotp4hgasmiaa3", VX (4, 401), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10662{"evdotp4hgasumiaa3", VX (4, 402), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10663{"evdotp4hgasmfaa3", VX (4, 403), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10664{"evdotp4hgssmiaa3", VX (4, 404), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10665{"evdotp4hgssmfaa3", VX (4, 405), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10666{"evdotp4hxgasmiaa3", VX (4, 406), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10667{"evdotp4hxgasmfaa3", VX (4, 407), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10668{"evdotpbaumiaaw3", VX (4, 408), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10669{"evdotpbasmiaaw3", VX (4, 409), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10670{"evdotpbasumiaaw3", VX (4, 410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10671{"evdotp4hxgssmiaa3", VX (4, 414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10672{"evdotp4hxgssmfaa3", VX (4, 415), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10673{"evdotp4hgaumia", VX (4, 416), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10674{"evdotp4hgasmia", VX (4, 417), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10675{"evdotp4hgasumia", VX (4, 418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10676{"evdotp4hgasmfa", VX (4, 419), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10677{"evdotp4hgssmia", VX (4, 420), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10678{"evdotp4hgssmfa", VX (4, 421), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10679{"evdotp4hxgasmia", VX (4, 422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10680{"evdotp4hxgasmfa", VX (4, 423), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10681{"evdotpbaumia", VX (4, 424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10682{"evdotpbasmia", VX (4, 425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10683{"evdotpbasumia", VX (4, 426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10684{"evdotp4hxgssmia", VX (4, 430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10685{"evdotp4hxgssmfa", VX (4, 431), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10686{"evdotp4hgaumiaa", VX (4, 432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10687{"evdotp4hgasmiaa", VX (4, 433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10688{"evdotp4hgasumiaa", VX (4, 434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10689{"evdotp4hgasmfaa", VX (4, 435), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10690{"evdotp4hgssmiaa", VX (4, 436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10691{"evdotp4hgssmfaa", VX (4, 437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10692{"evdotp4hxgasmiaa", VX (4, 438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10693{"evdotp4hxgasmfaa", VX (4, 439), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10694{"evdotpbaumiaaw", VX (4, 440), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10695{"evdotpbasmiaaw", VX (4, 441), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10696{"evdotpbasumiaaw", VX (4, 442), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10697{"evdotp4hxgssmiaa", VX (4, 446), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10698{"evdotp4hxgssmfaa", VX (4, 447), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10699{"evdotpwausi", VX (4, 448), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10700{"evdotpwassi", VX (4, 449), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10701{"evdotpwasusi", VX (4, 450), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10702{"evdotpwaumi", VX (4, 456), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10703{"evdotpwasmi", VX (4, 457), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10704{"evdotpwasumi", VX (4, 458), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10705{"evdotpwssmi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10706{"evdotpwsssi", VX (4, 461), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10707{"evdotpwausiaa3", VX (4, 464), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10708{"evdotpwassiaa3", VX (4, 465), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10709{"evdotpwasusiaa3", VX (4, 466), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10710{"evdotpwsssiaa3", VX (4, 469), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10711{"evdotpwaumiaa3", VX (4, 472), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10712{"evdotpwasmiaa3", VX (4, 473), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10713{"evdotpwasumiaa3", VX (4, 474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10714{"evdotpwssmiaa3", VX (4, 477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10715{"evdotpwausia", VX (4, 480), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10716{"evdotpwassia", VX (4, 481), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10717{"evdotpwasusia", VX (4, 482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10718{"evdotpwaumia", VX (4, 488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10719{"evdotpwasmia", VX (4, 489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10720{"evdotpwasumia", VX (4, 490), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10721{"evdotpwssmia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10722{"evdotpwsssia", VX (4, 493), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10723{"evdotpwausiaa", VX (4, 496), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10724{"evdotpwassiaa", VX (4, 497), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10725{"evdotpwasusiaa", VX (4, 498), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10726{"evdotpwsssiaa", VX (4, 501), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10727{"evdotpwaumiaa", VX (4, 504), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10728{"evdotpwasmiaa", VX (4, 505), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10729{"evdotpwasumiaa", VX (4, 506), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10730{"evdotpwssmiaa", VX (4, 509), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10731{"evaddib", VX (4, 515), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, 10732{"evaddih", VX (4, 513), VX_MASK, PPCSPE2, 0, {RD, RB, UIMM}}, 10733{"evsubifh", VX (4, 517), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, 10734{"evsubifb", VX (4, 519), VX_MASK, PPCSPE2, 0, {RD, UIMM, RB}}, 10735{"evabsb", VX_RB_CONST(4, 520, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10736{"evabsh", VX_RB_CONST(4, 520, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10737{"evabsd", VX_RB_CONST(4, 520, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10738{"evabss", VX_RB_CONST(4, 520, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10739{"evabsbs", VX_RB_CONST(4, 520, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10740{"evabshs", VX_RB_CONST(4, 520, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10741{"evabsds", VX_RB_CONST(4, 520, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10742{"evnegwo", VX_RB_CONST(4, 521, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10743{"evnegb", VX_RB_CONST(4, 521, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10744{"evnegbo", VX_RB_CONST(4, 521, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10745{"evnegh", VX_RB_CONST(4, 521, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10746{"evnegho", VX_RB_CONST(4, 521, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10747{"evnegd", VX_RB_CONST(4, 521, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10748{"evnegs", VX_RB_CONST(4, 521, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10749{"evnegwos", VX_RB_CONST(4, 521, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10750{"evnegbs", VX_RB_CONST(4, 521, 10), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10751{"evnegbos", VX_RB_CONST(4, 521, 11), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10752{"evneghs", VX_RB_CONST(4, 521, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10753{"evneghos", VX_RB_CONST(4, 521, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10754{"evnegds", VX_RB_CONST(4, 521, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10755{"evextzb", VX_RB_CONST(4, 522, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10756{"evextsbh", VX_RB_CONST(4, 522, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10757{"evextsw", VX_RB_CONST(4, 523, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10758{"evrndwh", VX_RB_CONST(4, 524, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10759{"evrndhb", VX_RB_CONST(4, 524, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10760{"evrnddw", VX_RB_CONST(4, 524, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10761{"evrndwhus", VX_RB_CONST(4, 524, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10762{"evrndwhss", VX_RB_CONST(4, 524, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10763{"evrndhbus", VX_RB_CONST(4, 524, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10764{"evrndhbss", VX_RB_CONST(4, 524, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10765{"evrnddwus", VX_RB_CONST(4, 524, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10766{"evrnddwss", VX_RB_CONST(4, 524, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10767{"evrndwnh", VX_RB_CONST(4, 524, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10768{"evrndhnb", VX_RB_CONST(4, 524, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10769{"evrnddnw", VX_RB_CONST(4, 524, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10770{"evrndwnhus", VX_RB_CONST(4, 524, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10771{"evrndwnhss", VX_RB_CONST(4, 524, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10772{"evrndhnbus", VX_RB_CONST(4, 524, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10773{"evrndhnbss", VX_RB_CONST(4, 524, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10774{"evrnddnwus", VX_RB_CONST(4, 524, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10775{"evrnddnwss", VX_RB_CONST(4, 524, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10776{"evcntlzh", VX_RB_CONST(4, 525, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10777{"evcntlsh", VX_RB_CONST(4, 526, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10778{"evpopcntb", VX_RB_CONST(4, 526, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10779{"circinc", VX (4, 528), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10780{"evunpkhibui", VX_RB_CONST(4, 540, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10781{"evunpkhibsi", VX_RB_CONST(4, 540, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10782{"evunpkhihui", VX_RB_CONST(4, 540, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10783{"evunpkhihsi", VX_RB_CONST(4, 540, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10784{"evunpklobui", VX_RB_CONST(4, 540, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10785{"evunpklobsi", VX_RB_CONST(4, 540, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10786{"evunpklohui", VX_RB_CONST(4, 540, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10787{"evunpklohsi", VX_RB_CONST(4, 540, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10788{"evunpklohf", VX_RB_CONST(4, 540, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10789{"evunpkhihf", VX_RB_CONST(4, 540, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10790{"evunpklowgsf", VX_RB_CONST(4, 540, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10791{"evunpkhiwgsf", VX_RB_CONST(4, 540, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10792{"evsatsduw", VX_RB_CONST(4, 540, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10793{"evsatsdsw", VX_RB_CONST(4, 540, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10794{"evsatshub", VX_RB_CONST(4, 540, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10795{"evsatshsb", VX_RB_CONST(4, 540, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10796{"evsatuwuh", VX_RB_CONST(4, 540, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10797{"evsatswsh", VX_RB_CONST(4, 540, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10798{"evsatswuh", VX_RB_CONST(4, 540, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10799{"evsatuhub", VX_RB_CONST(4, 540, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10800{"evsatuduw", VX_RB_CONST(4, 540, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10801{"evsatuwsw", VX_RB_CONST(4, 540, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10802{"evsatshuh", VX_RB_CONST(4, 540, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10803{"evsatuhsh", VX_RB_CONST(4, 540, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10804{"evsatswuw", VX_RB_CONST(4, 540, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10805{"evsatswgsdf", VX_RB_CONST(4, 540, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10806{"evsatsbub", VX_RB_CONST(4, 540, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10807{"evsatubsb", VX_RB_CONST(4, 540, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10808{"evmaxhpuw", VX_RB_CONST(4, 541, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10809{"evmaxhpsw", VX_RB_CONST(4, 541, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10810{"evmaxbpuh", VX_RB_CONST(4, 541, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10811{"evmaxbpsh", VX_RB_CONST(4, 541, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10812{"evmaxwpud", VX_RB_CONST(4, 541, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10813{"evmaxwpsd", VX_RB_CONST(4, 541, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10814{"evminhpuw", VX_RB_CONST(4, 541, 8), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10815{"evminhpsw", VX_RB_CONST(4, 541, 9), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10816{"evminbpuh", VX_RB_CONST(4, 541, 12), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10817{"evminbpsh", VX_RB_CONST(4, 541, 13), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10818{"evminwpud", VX_RB_CONST(4, 541, 14), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10819{"evminwpsd", VX_RB_CONST(4, 541, 15), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 10820{"evmaxmagws", VX (4, 543), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10821{"evsl", VX (4, 549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10822{"evsli", VX (4, 551), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, 10823{"evsplatie", VX_RB_CONST (4, 553, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10824{"evsplatib", VX_RB_CONST (4, 553, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10825{"evsplatibe", VX_RB_CONST (4, 553, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10826{"evsplatih", VX_RB_CONST (4, 553, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10827{"evsplatihe", VX_RB_CONST (4, 553, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10828{"evsplatid", VX_RB_CONST (4, 553, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10829{"evsplatia", VX_RB_CONST (4, 553, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10830{"evsplatiea", VX_RB_CONST (4, 553, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10831{"evsplatiba", VX_RB_CONST (4, 553, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10832{"evsplatibea", VX_RB_CONST (4, 553, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10833{"evsplatiha", VX_RB_CONST (4, 553, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10834{"evsplatihea", VX_RB_CONST (4, 553, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10835{"evsplatida", VX_RB_CONST (4, 553, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10836{"evsplatfio", VX_RB_CONST (4, 555, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10837{"evsplatfib", VX_RB_CONST (4, 555, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10838{"evsplatfibo", VX_RB_CONST (4, 555, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10839{"evsplatfih", VX_RB_CONST (4, 555, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10840{"evsplatfiho", VX_RB_CONST (4, 555, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10841{"evsplatfid", VX_RB_CONST (4, 555, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10842{"evsplatfia", VX_RB_CONST (4, 555, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10843{"evsplatfioa", VX_RB_CONST (4, 555, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10844{"evsplatfiba", VX_RB_CONST (4, 555, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10845{"evsplatfiboa", VX_RB_CONST (4, 555, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10846{"evsplatfiha", VX_RB_CONST (4, 555, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10847{"evsplatfihoa", VX_RB_CONST (4, 555, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10848{"evsplatfida", VX_RB_CONST (4, 555, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, SIMM}}, 10849{"evcmpgtdu", VX_SPE_CRFD (4, 560, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 10850{"evcmpgtds", VX_SPE_CRFD (4, 561, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 10851{"evcmpltdu", VX_SPE_CRFD (4, 562, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 10852{"evcmpltds", VX_SPE_CRFD (4, 563, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 10853{"evcmpeqd", VX_SPE_CRFD (4, 564, 1), VX_SPE_CRFD_MASK, PPCSPE2, 0, {CRFD, RA, RB}}, 10854{"evswapbhilo", VX (4, 568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10855{"evswapblohi", VX (4, 569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10856{"evswaphhilo", VX (4, 570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10857{"evswaphlohi", VX (4, 571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10858{"evswaphe", VX (4, 572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10859{"evswaphhi", VX (4, 573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10860{"evswaphlo", VX (4, 574), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10861{"evswapho", VX (4, 575), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10862{"evinsb", VX (4, 584), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, 10863{"evxtrb", VX (4, 586), VX_MASK_DDD, PPCSPE2, 0, {RD, RA, DDD, BBB}}, 10864{"evsplath", VX_SPE2_HH (4, 588, 0, 0), VX_SPE2_HH_MASK, PPCSPE2, 0, {RD, RA, HH}}, 10865{"evsplatb", VX_SPE2_SPLATB (4, 588, 2), VX_SPE2_SPLATB_MASK, PPCSPE2, 0, {RD, RA, BBB}}, 10866{"evinsh", VX_SPE2_DDHH (4, 589, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, 10867{"evclrbe", VX_SPE2_CLR (4, 590, 0), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, 10868{"evclrbo", VX_SPE2_CLR (4, 590, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, 10869{"evclrh", VX_SPE2_CLR (4, 591, 1), VX_SPE2_CLR_MASK, PPCSPE2, 0, {RD, RA, MMMM}}, 10870{"evxtrh", VX_SPE2_DDHH (4, 591, 0), VX_SPE2_DDHH_MASK, PPCSPE2, 0, {RD, RA, DD, HH}}, 10871{"evselbitm0", VX (4, 592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10872{"evselbitm1", VX (4, 593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10873{"evselbit", VX (4, 594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10874{"evperm", VX (4, 596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10875{"evperm2", VX (4, 597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10876{"evperm3", VX (4, 598), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10877{"evxtrd", VX (4, 600), VX_OFF_SPE2_MASK, PPCSPE2, 0, {RD, RA, RB, VX_OFF_SPE2}}, 10878{"evsrbu", VX (4, 608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10879{"evsrbs", VX (4, 609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10880{"evsrbiu", VX (4, 610), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, 10881{"evsrbis", VX (4, 611), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, 10882{"evslb", VX (4, 612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10883{"evrlb", VX (4, 613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10884{"evslbi", VX (4, 614), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, 10885{"evrlbi", VX (4, 615), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT8}}, 10886{"evsrhu", VX (4, 616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10887{"evsrhs", VX (4, 617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10888{"evsrhiu", VX (4, 618), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, 10889{"evsrhis", VX (4, 619), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, 10890{"evslh", VX (4, 620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10891{"evrlh", VX (4, 621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10892{"evslhi", VX (4, 622), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, 10893{"evrlhi", VX (4, 623), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM_LT16}}, 10894{"evsru", VX (4, 624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10895{"evsrs", VX (4, 625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10896{"evsriu", VX (4, 626), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, 10897{"evsris", VX (4, 627), VX_MASK, PPCSPE2, 0, {RD, RA, EVUIMM}}, 10898{"evlvsl", VX (4, 628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10899{"evlvsr", VX (4, 629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10900{"evsroiu", VX_SPE2_OCTET (4, 631, 0), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, 10901{"evsrois", VX_SPE2_OCTET (4, 631, 1), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, 10902{"evsloi", VX_SPE2_OCTET (4, 631, 2), VX_SPE2_OCTET_MASK, PPCSPE2, 0, {RD, RA, NNN}}, 10903{"evldbx", VX (4, 774), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10904{"evldb", VX (4, 775), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8, RA}}, 10905{"evlhhsplathx", VX (4, 778), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10906{"evlhhsplath", VX (4, 779), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2, RA}}, 10907{"evlwbsplatwx", VX (4, 786), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10908{"evlwbsplatw", VX (4, 787), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 10909{"evlwhsplatwx", VX (4, 794), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10910{"evlwhsplatw", VX (4, 795), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 10911{"evlbbsplatbx", VX (4, 798), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10912{"evlbbsplatb", VX (4, 799), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1, RA}}, 10913{"evstdbx", VX (4, 806), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10914{"evstdb", VX (4, 807), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8, RA}}, 10915{"evlwbex", VX (4, 810), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10916{"evlwbe", VX (4, 811), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 10917{"evlwboux", VX (4, 812), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10918{"evlwbou", VX (4, 813), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 10919{"evlwbosx", VX (4, 814), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10920{"evlwbos", VX (4, 815), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4, RA}}, 10921{"evstwbex", VX (4, 818), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10922{"evstwbe", VX (4, 819), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, 10923{"evstwbox", VX (4, 822), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10924{"evstwbo", VX (4, 823), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, 10925{"evstwbx", VX (4, 826), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10926{"evstwb", VX (4, 827), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4, RA}}, 10927{"evsthbx", VX (4, 830), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10928{"evsthb", VX (4, 831), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2, RA}}, 10929{"evlddmx", VX (4, 832), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10930{"evlddu", VX (4, 833), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, 10931{"evldwmx", VX (4, 834), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10932{"evldwu", VX (4, 835), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, 10933{"evldhmx", VX (4, 836), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10934{"evldhu", VX (4, 837), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, 10935{"evldbmx", VX (4, 838), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10936{"evldbu", VX (4, 839), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_8_EX0, RA}}, 10937{"evlhhesplatmx", VX (4, 840), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10938{"evlhhesplatu", VX (4, 841), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, 10939{"evlhhsplathmx", VX (4, 842), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10940{"evlhhsplathu", VX (4, 843), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, 10941{"evlhhousplatmx", VX (4, 844), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10942{"evlhhousplatu", VX (4, 845), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, 10943{"evlhhossplatmx", VX (4, 846), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10944{"evlhhossplatu", VX (4, 847), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_2_EX0, RA}}, 10945{"evlwhemx", VX (4, 848), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10946{"evlwheu", VX (4, 849), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10947{"evlwbsplatwmx", VX (4, 850), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10948{"evlwbsplatwu", VX (4, 851), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10949{"evlwhoumx", VX (4, 852), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10950{"evlwhouu", VX (4, 853), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10951{"evlwhosmx", VX (4, 854), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10952{"evlwhosu", VX (4, 855), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10953{"evlwwsplatmx", VX (4, 856), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10954{"evlwwsplatu", VX (4, 857), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10955{"evlwhsplatwmx", VX (4, 858), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10956{"evlwhsplatwu", VX (4, 859), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10957{"evlwhsplatmx", VX (4, 860), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10958{"evlwhsplatu", VX (4, 861), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10959{"evlbbsplatbmx", VX (4, 862), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10960{"evlbbsplatbu", VX (4, 863), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_1_EX0, RA}}, 10961{"evstddmx", VX (4, 864), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10962{"evstddu", VX (4, 865), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, 10963{"evstdwmx", VX (4, 866), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10964{"evstdwu", VX (4, 867), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, 10965{"evstdhmx", VX (4, 868), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10966{"evstdhu", VX (4, 869), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, 10967{"evstdbmx", VX (4, 870), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10968{"evstdbu", VX (4, 871), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_8_EX0, RA}}, 10969{"evlwbemx", VX (4, 874), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10970{"evlwbeu", VX (4, 875), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10971{"evlwboumx", VX (4, 876), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10972{"evlwbouu", VX (4, 877), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10973{"evlwbosmx", VX (4, 878), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10974{"evlwbosu", VX (4, 879), VX_MASK, PPCSPE2, 0, {RD, EVUIMM_4_EX0, RA}}, 10975{"evstwhemx", VX (4, 880), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10976{"evstwheu", VX (4, 881), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 10977{"evstwbemx", VX (4, 882), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10978{"evstwbeu", VX (4, 883), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 10979{"evstwhomx", VX (4, 884), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10980{"evstwhou", VX (4, 885), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 10981{"evstwbomx", VX (4, 886), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10982{"evstwbou", VX (4, 887), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 10983{"evstwwemx", VX (4, 888), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10984{"evstwweu", VX (4, 889), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 10985{"evstwbmx", VX (4, 890), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10986{"evstwbu", VX (4, 891), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 10987{"evstwwomx", VX (4, 892), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10988{"evstwwou", VX (4, 893), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_4_EX0, RA}}, 10989{"evsthbmx", VX (4, 894), VX_MASK, PPCSPE2, 0, {RS, RA, RB}}, 10990{"evsthbu", VX (4, 895), VX_MASK, PPCSPE2, 0, {RS, EVUIMM_2_EX0, RA}}, 10991{"evmhusi", VX (4, 1024), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10992{"evmhssi", VX (4, 1025), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10993{"evmhsusi", VX (4, 1026), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10994{"evmhssf", VX (4, 1028), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10995{"evmhumi", VX (4, 1029), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10996{"evmhssfr", VX (4, 1030), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10997{"evmhesumi", VX (4, 1034), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10998{"evmhosumi", VX (4, 1038), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 10999{"evmbeumi", VX (4, 1048), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11000{"evmbesmi", VX (4, 1049), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11001{"evmbesumi", VX (4, 1050), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11002{"evmboumi", VX (4, 1052), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11003{"evmbosmi", VX (4, 1053), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11004{"evmbosumi", VX (4, 1054), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11005{"evmhesumia", VX (4, 1066), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11006{"evmhosumia", VX (4, 1070), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11007{"evmbeumia", VX (4, 1080), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11008{"evmbesmia", VX (4, 1081), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11009{"evmbesumia", VX (4, 1082), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11010{"evmboumia", VX (4, 1084), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11011{"evmbosmia", VX (4, 1085), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11012{"evmbosumia", VX (4, 1086), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11013{"evmwusiw", VX (4, 1088), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11014{"evmwssiw", VX (4, 1089), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11015{"evmwhssfr", VX (4, 1094), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11016{"evmwehgsmfr", VX (4, 1110), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11017{"evmwehgsmf", VX (4, 1111), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11018{"evmwohgsmfr", VX (4, 1118), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11019{"evmwohgsmf", VX (4, 1119), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11020{"evmwhssfra", VX (4, 1126), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11021{"evmwehgsmfra", VX (4, 1142), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11022{"evmwehgsmfa", VX (4, 1143), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11023{"evmwohgsmfra", VX (4, 1150), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11024{"evmwohgsmfa", VX (4, 1151), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11025{"evaddusiaa", VX_RB_CONST(4, 1152, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11026{"evaddssiaa", VX_RB_CONST(4, 1153, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11027{"evsubfusiaa", VX_RB_CONST(4, 1154, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11028{"evsubfssiaa", VX_RB_CONST(4, 1155, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11029{"evaddsmiaa", VX_RB_CONST(4, 1156, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11030{"evsubfsmiaa", VX_RB_CONST(4, 1158, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11031{"evaddh", VX (4, 1160), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11032{"evaddhss", VX (4, 1161), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11033{"evsubfh", VX (4, 1162), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11034{"evsubfhss", VX (4, 1163), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11035{"evaddhx", VX (4, 1164), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11036{"evaddhxss", VX (4, 1165), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11037{"evsubfhx", VX (4, 1166), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11038{"evsubfhxss", VX (4, 1167), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11039{"evaddd", VX (4, 1168), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11040{"evadddss", VX (4, 1169), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11041{"evsubfd", VX (4, 1170), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11042{"evsubfdss", VX (4, 1171), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11043{"evaddb", VX (4, 1172), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11044{"evaddbss", VX (4, 1173), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11045{"evsubfb", VX (4, 1174), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11046{"evsubfbss", VX (4, 1175), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11047{"evaddsubfh", VX (4, 1176), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11048{"evaddsubfhss", VX (4, 1177), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11049{"evsubfaddh", VX (4, 1178), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11050{"evsubfaddhss", VX (4, 1179), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11051{"evaddsubfhx", VX (4, 1180), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11052{"evaddsubfhxss", VX (4, 1181), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11053{"evsubfaddhx", VX (4, 1182), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11054{"evsubfaddhxss", VX (4, 1183), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11055{"evadddus", VX (4, 1184), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11056{"evaddbus", VX (4, 1185), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11057{"evsubfdus", VX (4, 1186), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11058{"evsubfbus", VX (4, 1187), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11059{"evaddwus", VX (4, 1188), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11060{"evaddwxus", VX (4, 1189), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11061{"evsubfwus", VX (4, 1190), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11062{"evsubfwxus", VX (4, 1191), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11063{"evadd2subf2h", VX (4, 1192), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11064{"evadd2subf2hss", VX (4, 1193), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11065{"evsubf2add2h", VX (4, 1194), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11066{"evsubf2add2hss", VX (4, 1195), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11067{"evaddhus", VX (4, 1196), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11068{"evaddhxus", VX (4, 1197), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11069{"evsubfhus", VX (4, 1198), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11070{"evsubfhxus", VX (4, 1199), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11071{"evaddwss", VX (4, 1201), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11072{"evsubfwss", VX (4, 1203), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11073{"evaddwx", VX (4, 1204), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11074{"evaddwxss", VX (4, 1205), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11075{"evsubfwx", VX (4, 1206), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11076{"evsubfwxss", VX (4, 1207), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11077{"evaddsubfw", VX (4, 1208), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11078{"evaddsubfwss", VX (4, 1209), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11079{"evsubfaddw", VX (4, 1210), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11080{"evsubfaddwss", VX (4, 1211), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11081{"evaddsubfwx", VX (4, 1212), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11082{"evaddsubfwxss", VX (4, 1213), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11083{"evsubfaddwx", VX (4, 1214), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11084{"evsubfaddwxss", VX (4, 1215), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11085{"evmar", VX_SPE2_EVMAR (4, 1220), VX_SPE2_EVMAR_MASK, PPCSPE2, 0, {RD}}, 11086{"evsumwu", VX_RB_CONST(4, 1221, 0), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11087{"evsumws", VX_RB_CONST(4, 1221, 1), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11088{"evsum4bu", VX_RB_CONST(4, 1221, 2), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11089{"evsum4bs", VX_RB_CONST(4, 1221, 3), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11090{"evsum2hu", VX_RB_CONST(4, 1221, 4), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11091{"evsum2hs", VX_RB_CONST(4, 1221, 5), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11092{"evdiff2his", VX_RB_CONST(4, 1221, 6), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11093{"evsum2his", VX_RB_CONST(4, 1221, 7), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11094{"evsumwua", VX_RB_CONST(4, 1221, 16), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11095{"evsumwsa", VX_RB_CONST(4, 1221, 17), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11096{"evsum4bua", VX_RB_CONST(4, 1221, 18), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11097{"evsum4bsa", VX_RB_CONST(4, 1221, 19), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11098{"evsum2hua", VX_RB_CONST(4, 1221, 20), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11099{"evsum2hsa", VX_RB_CONST(4, 1221, 21), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11100{"evdiff2hisa", VX_RB_CONST(4, 1221, 22), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11101{"evsum2hisa", VX_RB_CONST(4, 1221, 23), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11102{"evsumwuaa", VX_RB_CONST(4, 1221, 24), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11103{"evsumwsaa", VX_RB_CONST(4, 1221, 25), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11104{"evsum4buaaw", VX_RB_CONST(4, 1221, 26), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11105{"evsum4bsaaw", VX_RB_CONST(4, 1221, 27), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11106{"evsum2huaaw", VX_RB_CONST(4, 1221, 28), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11107{"evsum2hsaaw", VX_RB_CONST(4, 1221, 29), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11108{"evdiff2hisaaw", VX_RB_CONST(4, 1221, 30), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11109{"evsum2hisaaw", VX_RB_CONST(4, 1221, 31), VX_RB_CONST_MASK, PPCSPE2, 0, {RD, RA}}, 11110{"evdivwsf", VX (4, 1228), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11111{"evdivwuf", VX (4, 1229), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11112{"evdivs", VX (4, 1230), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11113{"evdivu", VX (4, 1231), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11114{"evaddwegsi", VX (4, 1232), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11115{"evaddwegsf", VX (4, 1233), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11116{"evsubfwegsi", VX (4, 1234), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11117{"evsubfwegsf", VX (4, 1235), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11118{"evaddwogsi", VX (4, 1236), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11119{"evaddwogsf", VX (4, 1237), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11120{"evsubfwogsi", VX (4, 1238), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11121{"evsubfwogsf", VX (4, 1239), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11122{"evaddhhiuw", VX (4, 1240), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11123{"evaddhhisw", VX (4, 1241), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11124{"evsubfhhiuw", VX (4, 1242), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11125{"evsubfhhisw", VX (4, 1243), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11126{"evaddhlouw", VX (4, 1244), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11127{"evaddhlosw", VX (4, 1245), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11128{"evsubfhlouw", VX (4, 1246), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11129{"evsubfhlosw", VX (4, 1247), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11130{"evmhesusiaaw", VX (4, 1282), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11131{"evmhosusiaaw", VX (4, 1286), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11132{"evmhesumiaaw", VX (4, 1290), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11133{"evmhosumiaaw", VX (4, 1294), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11134{"evmbeusiaah", VX (4, 1296), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11135{"evmbessiaah", VX (4, 1297), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11136{"evmbesusiaah", VX (4, 1298), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11137{"evmbousiaah", VX (4, 1300), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11138{"evmbossiaah", VX (4, 1301), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11139{"evmbosusiaah", VX (4, 1302), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11140{"evmbeumiaah", VX (4, 1304), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11141{"evmbesmiaah", VX (4, 1305), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11142{"evmbesumiaah", VX (4, 1306), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11143{"evmboumiaah", VX (4, 1308), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11144{"evmbosmiaah", VX (4, 1309), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11145{"evmbosumiaah", VX (4, 1310), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11146{"evmwlusiaaw3", VX (4, 1346), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11147{"evmwlssiaaw3", VX (4, 1347), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11148{"evmwhssfraaw3", VX (4, 1348), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11149{"evmwhssfaaw3", VX (4, 1349), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11150{"evmwhssfraaw", VX (4, 1350), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11151{"evmwhssfaaw", VX (4, 1351), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11152{"evmwlumiaaw3", VX (4, 1354), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11153{"evmwlsmiaaw3", VX (4, 1355), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11154{"evmwusiaa", VX (4, 1360), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11155{"evmwssiaa", VX (4, 1361), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11156{"evmwehgsmfraa", VX (4, 1366), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11157{"evmwehgsmfaa", VX (4, 1367), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11158{"evmwohgsmfraa", VX (4, 1374), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11159{"evmwohgsmfaa", VX (4, 1375), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11160{"evmhesusianw", VX (4, 1410), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11161{"evmhosusianw", VX (4, 1414), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11162{"evmhesumianw", VX (4, 1418), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11163{"evmhosumianw", VX (4, 1422), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11164{"evmbeusianh", VX (4, 1424), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11165{"evmbessianh", VX (4, 1425), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11166{"evmbesusianh", VX (4, 1426), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11167{"evmbousianh", VX (4, 1428), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11168{"evmbossianh", VX (4, 1429), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11169{"evmbosusianh", VX (4, 1430), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11170{"evmbeumianh", VX (4, 1432), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11171{"evmbesmianh", VX (4, 1433), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11172{"evmbesumianh", VX (4, 1434), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11173{"evmboumianh", VX (4, 1436), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11174{"evmbosmianh", VX (4, 1437), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11175{"evmbosumianh", VX (4, 1438), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11176{"evmwlusianw3", VX (4, 1474), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11177{"evmwlssianw3", VX (4, 1475), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11178{"evmwhssfranw3", VX (4, 1476), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11179{"evmwhssfanw3", VX (4, 1477), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11180{"evmwhssfranw", VX (4, 1478), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11181{"evmwhssfanw", VX (4, 1479), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11182{"evmwlumianw3", VX (4, 1482), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11183{"evmwlsmianw3", VX (4, 1483), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11184{"evmwusian", VX (4, 1488), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11185{"evmwssian", VX (4, 1489), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11186{"evmwehgsmfran", VX (4, 1494), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11187{"evmwehgsmfan", VX (4, 1495), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11188{"evmwohgsmfran", VX (4, 1502), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11189{"evmwohgsmfan", VX (4, 1503), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11190{"evseteqb", VX (4, 1536), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11191{"evseteqb.", VX (4, 1537), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11192{"evseteqh", VX (4, 1538), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11193{"evseteqh.", VX (4, 1539), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11194{"evseteqw", VX (4, 1540), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11195{"evseteqw.", VX (4, 1541), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11196{"evsetgthu", VX (4, 1544), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11197{"evsetgthu.", VX (4, 1545), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11198{"evsetgths", VX (4, 1546), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11199{"evsetgths.", VX (4, 1547), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11200{"evsetgtwu", VX (4, 1548), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11201{"evsetgtwu.", VX (4, 1549), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11202{"evsetgtws", VX (4, 1550), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11203{"evsetgtws.", VX (4, 1551), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11204{"evsetgtbu", VX (4, 1552), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11205{"evsetgtbu.", VX (4, 1553), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11206{"evsetgtbs", VX (4, 1554), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11207{"evsetgtbs.", VX (4, 1555), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11208{"evsetltbu", VX (4, 1556), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11209{"evsetltbu.", VX (4, 1557), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11210{"evsetltbs", VX (4, 1558), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11211{"evsetltbs.", VX (4, 1559), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11212{"evsetlthu", VX (4, 1560), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11213{"evsetlthu.", VX (4, 1561), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11214{"evsetlths", VX (4, 1562), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11215{"evsetlths.", VX (4, 1563), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11216{"evsetltwu", VX (4, 1564), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11217{"evsetltwu.", VX (4, 1565), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11218{"evsetltws", VX (4, 1566), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11219{"evsetltws.", VX (4, 1567), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11220{"evsaduw", VX (4, 1568), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11221{"evsadsw", VX (4, 1569), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11222{"evsad4ub", VX (4, 1570), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11223{"evsad4sb", VX (4, 1571), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11224{"evsad2uh", VX (4, 1572), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11225{"evsad2sh", VX (4, 1573), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11226{"evsaduwa", VX (4, 1576), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11227{"evsadswa", VX (4, 1577), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11228{"evsad4uba", VX (4, 1578), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11229{"evsad4sba", VX (4, 1579), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11230{"evsad2uha", VX (4, 1580), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11231{"evsad2sha", VX (4, 1581), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11232{"evabsdifuw", VX (4, 1584), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11233{"evabsdifsw", VX (4, 1585), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11234{"evabsdifub", VX (4, 1586), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11235{"evabsdifsb", VX (4, 1587), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11236{"evabsdifuh", VX (4, 1588), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11237{"evabsdifsh", VX (4, 1589), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11238{"evsaduwaa", VX (4, 1592), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11239{"evsadswaa", VX (4, 1593), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11240{"evsad4ubaaw", VX (4, 1594), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11241{"evsad4sbaaw", VX (4, 1595), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11242{"evsad2uhaaw", VX (4, 1596), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11243{"evsad2shaaw", VX (4, 1597), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11244{"evpkshubs", VX (4, 1600), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11245{"evpkshsbs", VX (4, 1601), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11246{"evpkswuhs", VX (4, 1602), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11247{"evpkswshs", VX (4, 1603), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11248{"evpkuhubs", VX (4, 1604), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11249{"evpkuwuhs", VX (4, 1605), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11250{"evpkswshilvs", VX (4, 1606), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11251{"evpkswgshefrs", VX (4, 1607), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11252{"evpkswshfrs", VX (4, 1608), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11253{"evpkswshilvfrs", VX (4, 1609), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11254{"evpksdswfrs", VX (4, 1610), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11255{"evpksdshefrs", VX (4, 1611), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11256{"evpkuduws", VX (4, 1612), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11257{"evpksdsws", VX (4, 1613), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11258{"evpkswgswfrs", VX (4, 1614), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11259{"evilveh", VX (4, 1616), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11260{"evilveoh", VX (4, 1617), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11261{"evilvhih", VX (4, 1618), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11262{"evilvhiloh", VX (4, 1619), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11263{"evilvloh", VX (4, 1620), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11264{"evilvlohih", VX (4, 1621), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11265{"evilvoeh", VX (4, 1622), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11266{"evilvoh", VX (4, 1623), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11267{"evdlveb", VX (4, 1624), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11268{"evdlveh", VX (4, 1625), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11269{"evdlveob", VX (4, 1626), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11270{"evdlveoh", VX (4, 1627), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11271{"evdlvob", VX (4, 1628), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11272{"evdlvoh", VX (4, 1629), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11273{"evdlvoeb", VX (4, 1630), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11274{"evdlvoeh", VX (4, 1631), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11275{"evmaxbu", VX (4, 1632), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11276{"evmaxbs", VX (4, 1633), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11277{"evmaxhu", VX (4, 1634), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11278{"evmaxhs", VX (4, 1635), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11279{"evmaxwu", VX (4, 1636), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11280{"evmaxws", VX (4, 1637), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11281{"evmaxdu", VX (4, 1638), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11282{"evmaxds", VX (4, 1639), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11283{"evminbu", VX (4, 1640), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11284{"evminbs", VX (4, 1641), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11285{"evminhu", VX (4, 1642), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11286{"evminhs", VX (4, 1643), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11287{"evminwu", VX (4, 1644), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11288{"evminws", VX (4, 1645), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11289{"evmindu", VX (4, 1646), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11290{"evminds", VX (4, 1647), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11291{"evavgwu", VX (4, 1648), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11292{"evavgws", VX (4, 1649), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11293{"evavgbu", VX (4, 1650), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11294{"evavgbs", VX (4, 1651), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11295{"evavghu", VX (4, 1652), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11296{"evavghs", VX (4, 1653), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11297{"evavgdu", VX (4, 1654), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11298{"evavgds", VX (4, 1655), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11299{"evavgwur", VX (4, 1656), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11300{"evavgwsr", VX (4, 1657), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11301{"evavgbur", VX (4, 1658), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11302{"evavgbsr", VX (4, 1659), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11303{"evavghur", VX (4, 1660), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11304{"evavghsr", VX (4, 1661), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11305{"evavgdur", VX (4, 1662), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11306{"evavgdsr", VX (4, 1663), VX_MASK, PPCSPE2, 0, {RD, RA, RB}}, 11307}; 11308 11309const unsigned int spe2_num_opcodes = 11310 sizeof (spe2_opcodes) / sizeof (spe2_opcodes[0]); 11311