Searched refs:N_REG_CLASSES (Results 1 - 25 of 139) sorted by relevance

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/netbsd-current/external/gpl3/gcc/dist/gcc/
H A Dira.h48 enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
53 enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
61 enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
67 enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
76 unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
77 unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
80 short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
85 short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
89 int x_ira_class_hard_regs_num[N_REG_CLASSES];
94 int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSE
[all...]
H A Dhard-reg-set.h431 HARD_REG_SET x_reg_class_contents[N_REG_CLASSES];
435 bool x_class_only_fixed_regs[N_REG_CLASSES];
438 unsigned int x_reg_class_size[N_REG_CLASSES];
441 enum reg_class x_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
445 enum reg_class x_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
449 enum reg_class x_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
H A Dira-int.h71 typedef unsigned short move_table[N_REG_CLASSES];
125 int reg_pressure[N_REG_CLASSES];
844 short int x_ira_max_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
848 bool x_ira_reg_allocno_class_p[N_REG_CLASSES];
851 bool x_ira_reg_pressure_class_p[N_REG_CLASSES];
856 short x_ira_non_ordered_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
862 short x_ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
876 HARD_REG_SET x_ira_useful_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
883 enum reg_class x_ira_important_classes[N_REG_CLASSES];
888 int x_ira_important_class_nums[N_REG_CLASSES];
[all...]
H A Dreginfo.cc113 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
173 for (i = 0; i < N_REG_CLASSES; i++)
265 for (i = 0; i < N_REG_CLASSES; i++)
283 for (i = 0; i < N_REG_CLASSES; i++)
285 for (j = 0; j < N_REG_CLASSES; j++)
291 for (k = 0; k < N_REG_CLASSES; k++)
305 for (i = 0; i < N_REG_CLASSES; i++)
307 for (j = 0; j < N_REG_CLASSES; j++)
313 for (k = 0; k < N_REG_CLASSES; k++)
324 for (i = 0; i < N_REG_CLASSES;
[all...]
H A Dira.cc474 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
538 for (i = 0; i < N_REG_CLASSES; i++)
539 for (j = 0; j < N_REG_CLASSES; j++)
542 for (i = 0; i < N_REG_CLASSES; i++)
550 for (j = 0; j < N_REG_CLASSES; j++)
579 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
607 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
608 for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
627 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
793 enum reg_class pressure_classes[N_REG_CLASSES];
[all...]
H A Dregs.h219 char x_contains_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE];
223 char x_contains_allocatable_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE];
/netbsd-current/external/gpl3/gcc.old/dist/gcc/
H A Dira.h48 enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
53 enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
61 enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
67 enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
76 unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
77 unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
80 short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
85 short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
89 int x_ira_class_hard_regs_num[N_REG_CLASSES];
94 int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSE
[all...]
H A Dhard-reg-set.h429 HARD_REG_SET x_reg_class_contents[N_REG_CLASSES];
433 bool x_class_only_fixed_regs[N_REG_CLASSES];
436 unsigned int x_reg_class_size[N_REG_CLASSES];
439 enum reg_class x_reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
443 enum reg_class x_reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
447 enum reg_class x_reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
H A Dira-int.h71 typedef unsigned short move_table[N_REG_CLASSES];
125 int reg_pressure[N_REG_CLASSES];
834 short int x_ira_max_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
838 bool x_ira_reg_allocno_class_p[N_REG_CLASSES];
841 bool x_ira_reg_pressure_class_p[N_REG_CLASSES];
846 short x_ira_non_ordered_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
852 short x_ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
866 HARD_REG_SET x_ira_useful_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
873 enum reg_class x_ira_important_classes[N_REG_CLASSES];
878 int x_ira_important_class_nums[N_REG_CLASSES];
[all...]
H A Dreginfo.c110 static const unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
152 for (i = 0; i < N_REG_CLASSES; i++)
244 for (i = 0; i < N_REG_CLASSES; i++)
262 for (i = 0; i < N_REG_CLASSES; i++)
264 for (j = 0; j < N_REG_CLASSES; j++)
270 for (k = 0; k < N_REG_CLASSES; k++)
284 for (i = 0; i < N_REG_CLASSES; i++)
286 for (j = 0; j < N_REG_CLASSES; j++)
292 for (k = 0; k < N_REG_CLASSES; k++)
303 for (i = 0; i < N_REG_CLASSES;
[all...]
H A Dira.c474 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
538 for (i = 0; i < N_REG_CLASSES; i++)
539 for (j = 0; j < N_REG_CLASSES; j++)
542 for (i = 0; i < N_REG_CLASSES; i++)
550 for (j = 0; j < N_REG_CLASSES; j++)
579 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
607 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
608 for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--)
627 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--)
793 enum reg_class pressure_classes[N_REG_CLASSES];
[all...]
H A Dregs.h216 char x_contains_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE];
220 char x_contains_allocatable_reg_of_mode[N_REG_CLASSES][MAX_MACHINE_MODE];
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/pa/
H A Dpa64-regs.h210 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
220 of length N_REG_CLASSES. Register 0, the "condition code" register,
H A Dpa32-regs.h274 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
284 of length N_REG_CLASSES. Register 0, the "condition code" register,
/netbsd-current/external/gpl3/gcc/dist/gcc/config/pa/
H A Dpa64-regs.h210 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
220 of length N_REG_CLASSES. Register 0, the "condition code" register,
H A Dpa32-regs.h274 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
284 of length N_REG_CLASSES. Register 0, the "condition code" register,
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/moxie/
H A Dmoxie.h150 #define N_REG_CLASSES LIM_REG_CLASSES macro
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/bpf/
H A Dbpf.h183 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
/netbsd-current/external/gpl3/gcc/dist/gcc/config/or1k/
H A Dor1k.h209 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
/netbsd-current/external/gpl3/gcc/dist/gcc/config/moxie/
H A Dmoxie.h150 #define N_REG_CLASSES LIM_REG_CLASSES macro
/netbsd-current/external/gpl3/gcc/dist/gcc/config/bpf/
H A Dbpf.h183 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/spu/
H A Dspu.h187 #define N_REG_CLASSES (int) LIM_REG_CLASSES
182 #define N_REG_CLASSES macro
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/nios2/
H A Dnios2.h197 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/ft32/
H A Dft32.h137 #define N_REG_CLASSES LIM_REG_CLASSES macro
/netbsd-current/external/gpl3/gcc.old/dist/gcc/config/mmix/
H A Dmmix.h392 #define N_REG_CLASSES (int) LIM_REG_CLASSES macro

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