Searched refs:ETH_RSR (Results 1 - 4 of 4) sorted by relevance

/netbsd-current/sys/arch/arm/at91/
H A Dat91emac.c156 u = EMAC_READ(ETH_RSR);
157 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
233 EMAC_READ(ETH_RSR); // get receive status register
239 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt
242 EMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit
249 EMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt
349 u = EMAC_READ(ETH_RSR);
350 EMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
745 u = EMAC_READ(ETH_RSR);
746 EMAC_WRITE(ETH_RSR, (
[all...]
H A Dat91emacreg.h43 #define ETH_RSR 0x20U /* 0x20: Receive Status Register */ macro
/netbsd-current/sys/dev/cadence/
H A Dif_cemac.c205 u = CEMAC_READ(ETH_RSR);
206 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
295 rsr = CEMAC_READ(ETH_RSR); // get receive status register
301 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear interrupt
304 CEMAC_WRITE(ETH_RSR, ETH_RSR_BNA); // clear BNA bit
311 CEMAC_WRITE(ETH_RSR, ETH_RSR_OVR); // clear interrupt
435 u = CEMAC_READ(ETH_RSR);
436 CEMAC_WRITE(ETH_RSR, (u & (ETH_RSR_OVR | ETH_RSR_REC | ETH_RSR_BNA)));
954 u = CEMAC_READ(ETH_RSR);
955 CEMAC_WRITE(ETH_RSR, (
[all...]
H A Dcemacreg.h47 #define ETH_RSR 0x20U /* 0x20: Receive Status Register */ macro

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