Searched refs:CPSR (Results 1 - 25 of 52) sorted by relevance

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/netbsd-current/external/gpl3/gdb.old/dist/gas/testsuite/gas/arm/
H A Darm6.s12 mrs r8, CPSR
15 msr CPSR, r1
H A Dmrs-msr-arm-v6.d8 0+00 <[^>]*> e10f4000 mrs r4, CPSR
9 0+04 <[^>]*> e10f5000 mrs r5, CPSR
H A Dmrs-msr-arm-v7-a.d8 0+00 <[^>]*> e10f4000 mrs r4, CPSR
9 0+04 <[^>]*> e10f5000 mrs r5, CPSR
H A Dmrs-msr-thumb-v6t2.d10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
11 0+04 <[^>]*> f3ef 8500 mrs r5, CPSR
H A Darm6.d8 0+00 <[^>]+> e10f8000 ? mrs r8, CPSR
14 0+18 <[^>]+> e10f8000 ? mrs r8, CPSR
H A Dmrs-msr-thumb-v7-m.d10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
H A Dmrs-msr-thumb-v7e-m.d10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
H A Dthumb-w-good.d9 00000004 <.text\+0x4> f3ef 8000 mrs r0, CPSR
H A Dmsr-imm.s14 @ Write to CPSR flags
15 msr CPSR,#0xc0000004
21 @ Write to CPSR flag combos
H A Dmsr-reg.s13 @ Write to CPSR flags
14 msr CPSR,r9
20 @ Write to CPSR flag combos
H A Darch7.d49 0+0a0 <[^>]*> f3ef 8000 mrs r0, (CPSR|APSR)
/netbsd-current/external/gpl3/gdb/dist/sim/aarch64/
H A Dsim-main.h39 uint32_t CPSR; member in struct:_sim_cpu
H A Dcpustate.c243 /* Retrieve the CPSR register as an int. */
247 return cpu->CPSR;
250 /* Set the CPSR register as an int. */
256 if (cpu->CPSR != new_flags)
258 "CPSR changes from %s to %s",
259 decode_cpsr (cpu->CPSR), decode_cpsr (new_flags));
262 "CPSR stays at %s", decode_cpsr (cpu->CPSR));
265 cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
268 /* Read a specific subset of the CPSR a
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/netbsd-current/external/gpl3/gdb.old/dist/sim/aarch64/
H A Dsim-main.h39 uint32_t CPSR; member in struct:_sim_cpu
H A Dcpustate.c239 /* Retrieve the CPSR register as an int. */
243 return cpu->CPSR;
246 /* Set the CPSR register as an int. */
252 if (cpu->CPSR != new_flags)
254 "CPSR changes from %s to %s",
255 decode_cpsr (cpu->CPSR), decode_cpsr (new_flags));
258 "CPSR stays at %s", decode_cpsr (cpu->CPSR));
261 cpu->CPSR = new_flags & CPSR_ALL_FLAGS;
264 /* Read a specific subset of the CPSR a
[all...]
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h106 MIB.addReg(ARM::CPSR, RegState::Define);
114 MIB.addReg(ARM::CPSR);
142 MIB.addReg(ARM::CPSR);
170 MIB.addReg(ARM::CPSR);
H A DThumb2SizeReduction.cpp74 // 2 - Always set CPSR.
217 // Last instruction to define CPSR in the current block.
219 // Was CPSR last defined by a high latency instruction?
220 // When CPSRDef is null, this refers to CPSR defs in predecessors.
256 if (*Regs == ARM::CPSR)
272 /// the 's' 16-bit instruction partially update CPSR. Abort the
273 /// transformation to avoid adding false dependency on last CPSR setting
277 /// last instruction that defines the CPSR and the current instruction. If there
279 /// before the CPSR setting instruction anyway.
304 if (Reg == 0 || Reg == ARM::CPSR)
[all...]
H A DThumb1InstrInfo.cpp60 if (MBB.computeRegisterLiveness(RegInfo, ARM::CPSR, I)
64 ->addRegisterDead(ARM::CPSR, RegInfo);
145 // In Thumb1 the scheduler may need to schedule a cross-copy between GPRS and CPSR
H A DThumb2ITBlockPass.cpp155 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
H A DARMBaseInstrInfo.cpp497 // For conditional branches, we use addOperand to preserve CPSR flags.
590 // Thumb 1 arithmetic instructions do not set CPSR when executed inside an
594 assert(MCID.OpInfo[1].isOptionalDef() && "CPSR def isn't expected operand");
596 MI.getOperand(1).getReg() != ARM::CPSR) &&
597 "if conversion tried to stop defining used CPSR");
638 bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR);
639 bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR;
642 // Filter out T1 instructions that have a dead CPSR,
659 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
738 if (MO.getReg() != ARM::CPSR)
[all...]
H A DARMFastISel.cpp234 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
245 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
246 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { argument
250 // Look to see if our OptionalDef is defining CPSR or CCR.
253 if (MO.getReg() == ARM::CPSR)
254 *CPSR = true;
277 // CPSR defs that need to be added before the remaining operands. See s_cc_out
290 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
291 bool CPSR local
[all...]
/netbsd-current/sys/arch/dreamcast/dev/microcode/
H A Daica_arm_locore.S45 mrs r0,CPSR /* disable interrupt */
/netbsd-current/external/gpl3/gdb.old/dist/sim/arm/
H A Darmemu.h166 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) macro
168 #define CPSR (ECC | EINT | EMODE) macro
/netbsd-current/external/gpl3/gdb/dist/sim/arm/
H A Darmemu.h166 #define CPSR (ECC | EINT | EMODE | (TFLAG << 5)) macro
168 #define CPSR (ECC | EINT | EMODE) macro
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp191 if (MO.isReg() && MO.getReg() == ARM::CPSR &&
239 {codeview::RegisterId::ARM_CPSR, ARM::CPSR},

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