/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 22 namespace ARM_AM { namespace in namespace:llvm 25 default: return ARM_AM::no_shift; 26 case ISD::SHL: return ARM_AM::lsl; 27 case ISD::SRL: return ARM_AM::lsr; 28 case ISD::SRA: return ARM_AM::asr; 29 case ISD::ROTR: return ARM_AM::ror; 33 //case ARMISD::RRX: return ARM_AM::rrx; 36 } // end namespace ARM_AM
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H A D | ARMLoadStoreOptimizer.cpp | 235 int Offset = isAM3 ? ARM_AM::getAM3Offset(OffField) 236 : ARM_AM::getAM5Offset(OffField) * 4; 237 ARM_AM::AddrOpc Op = isAM3 ? ARM_AM::getAM3Op(OffField) 238 : ARM_AM::getAM5Op(OffField); 240 if (Op == ARM_AM::sub) 254 static int getLoadStoreMultipleOpcode(unsigned Opcode, ARM_AM::AMSubMode Mode) { 261 case ARM_AM::ia: return ARM::LDMIA; 262 case ARM_AM::da: return ARM::LDMDA; 263 case ARM_AM [all...] |
H A D | ARMBaseInstrInfo.cpp | 218 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; 219 unsigned Amt = ARM_AM::getAM2Offset(OffImm); 221 if (ARM_AM::getSOImmVal(Amt) == -1) 232 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm); 233 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt); 252 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; 253 unsigned Amt = ARM_AM [all...] |
H A D | ARMISelDAGToDAG.cpp | 83 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt); 172 return ARM_AM::getSOImmVal(Imm) != -1; 176 return ARM_AM::getSOImmVal(~Imm) != -1; 180 return ARM_AM::getT2SOImmVal(Imm) != -1; 184 return ARM_AM::getT2SOImmVal(~Imm) != -1; 527 ARM_AM::ShiftOpc ShOpcVal, 534 return ShOpcVal == ARM_AM::lsl && 595 ARM_AM::getSORegOpc(ARM_AM::lsl, PowerOfTwo), Loc, MVT::i32); 600 ARM_AM [all...] |
H A D | Thumb2InstrInfo.cpp | 296 ARM_AM::getT2SOImmVal(NumBytes) == -1) { 366 int ImmIsT2SO = ARM_AM::getT2SOImmVal(ThisVal); 386 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt); 388 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 && 564 if (ARM_AM::getT2SOImmVal(Offset) != -1) { 591 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt); 596 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 && 642 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 643 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM [all...] |
H A D | ARMFastISel.cpp | 182 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 425 Imm = ARM_AM::getFP64Imm(Val); 428 Imm = ARM_AM::getFP32Imm(Val); 475 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 476 (ARM_AM::getSOImmVal(Imm) != -1); 1366 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1367 (ARM_AM::getSOImmVal(Imm) != -1); 1623 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1624 (ARM_AM::getSOImmVal(Imm) != -1); 2635 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM [all...] |
H A D | ARMBaseRegisterInfo.cpp | 528 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm()); 529 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub) 536 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm()); 537 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub) 542 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm()); 543 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
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H A D | ARMMCInstLower.cpp | 159 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
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H A D | ARMInstructionSelector.cpp | 820 int FPImmEncoding = ARM_AM::getFP32Imm(FPImmValue); 832 int FPImmEncoding = ARM_AM::getFP64Imm(FPImmValue); 1060 return selectShift(ARM_AM::ShiftOpc::lsr, MIB); 1062 return selectShift(ARM_AM::ShiftOpc::asr, MIB); 1064 return selectShift(ARM_AM::ShiftOpc::lsl, MIB);
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H A D | ARMFrameLowering.cpp | 394 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsr, NrBitsToZero)) 399 .addImm(ARM_AM::getSORegOpc(ARM_AM::lsl, NrBitsToZero)) 1247 MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift));
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H A D | ARMTargetTransformInfo.cpp | 263 (ARM_AM::getSOImmVal(ZImmVal) != -1) || 264 (ARM_AM::getSOImmVal(~ZImmVal) != -1)) 270 (ARM_AM::getT2SOImmVal(ZImmVal) != -1) || 271 (ARM_AM::getT2SOImmVal(~ZImmVal) != -1)) 278 if ((~SImmVal < 256) || ARM_AM::isThumbImmShiftedVal(ZImmVal))
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H A D | ARMExpandPseudoInsts.cpp | 907 if (ARM_AM::isSOImmTwoPartVal(ImmVal)) { // Expand into a movi + orr. 912 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 913 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 919 SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(-ImmVal); 920 SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(-ImmVal); 2301 .addImm(ARM_AM::getSORegOpc( 2302 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)) 2314 .addImm(ARM_AM::getSORegOpc(ARM_AM [all...] |
H A D | ARMISelLowering.cpp | 4534 } else if ((ARM_AM::getShiftOpcForNode(LHS.getOpcode()) != ARM_AM::no_shift) && 4535 (ARM_AM::getShiftOpcForNode(RHS.getOpcode()) == ARM_AM::no_shift)) { 5740 unsigned EncodedVal = ARM_AM::createVMOVModImm(0x6, 0x80); 5763 SDValue AllOnes = DAG.getTargetConstant(ARM_AM::createVMOVModImm(0xe, 0xff), 6786 unsigned EncodedVal = ARM_AM::createVMOVModImm(OpCmode, Imm); 6830 int ImmVal = IsDouble ? ARM_AM::getFP64Imm(FPVal) : ARM_AM::getFP32Imm(FPVal); 7374 if (ARM_AM [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMInstPrinter.cpp | 52 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc, 54 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm)) 58 assert(!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0"); 61 if (ShOpc != ARM_AM::rrx) { 105 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); 116 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); 127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM [all...] |
H A D | ARMAddressingModes.h | 25 /// ARM_AM - ARM Addressing Mode Stuff 26 namespace ARM_AM { namespace in namespace:llvm 47 case ARM_AM::asr: return "asr"; 48 case ARM_AM::lsl: return "lsl"; 49 case ARM_AM::lsr: return "lsr"; 50 case ARM_AM::ror: return "ror"; 51 case ARM_AM::rrx: return "rrx"; 52 case ARM_AM::uxtw: return "uxtw"; 59 case ARM_AM::asr: return 2; 60 case ARM_AM [all...] |
H A D | ARMMCCodeEmitter.cpp | 234 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); 237 case ARM_AM::da: return 0; 238 case ARM_AM::ia: return 1; 239 case ARM_AM::db: return 2; 240 case ARM_AM::ib: return 3; 246 unsigned getShiftOp(ARM_AM::ShiftOpc ShOpc) const { 248 case ARM_AM::no_shift: 249 case ARM_AM::lsl: return 0; 250 case ARM_AM [all...] |
H A D | ARMAsmBackend.cpp | 524 if (ARM_AM::getSOImmVal(Value) == -1) { 529 return ARM_AM::getSOImmVal(Value) | (opc << 21); 799 Value = ARM_AM::getSOImmVal(Value); 806 Value = ARM_AM::getT2SOImmVal(Value);
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/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 459 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType, 852 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg 862 ARM_AM::ShiftOpc ShiftTy; 872 ARM_AM::ShiftOpc ShiftTy; 879 ARM_AM::ShiftOpc ShiftTy; 1123 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue())); 1295 return (ARM_AM::getSOImmVal(Value) != -1 || 1296 ARM_AM::getSOImmVal(-Value) != -1); 1313 return ARM_AM::getT2SOImmVal(Value) != -1; 1321 return ARM_AM [all...] |
/netbsd-current/external/apache2/llvm/dist/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 1482 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1485 Shift = ARM_AM::lsl; 1488 Shift = ARM_AM::lsr; 1491 Shift = ARM_AM::asr; 1494 Shift = ARM_AM::ror; 1498 if (Shift == ARM_AM::ror && imm == 0) 1499 Shift = ARM_AM::rrx; 1521 ARM_AM::ShiftOpc Shift = ARM_AM [all...] |