Lines Matching refs:ARM_AM
459 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
852 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
862 ARM_AM::ShiftOpc ShiftTy;
872 ARM_AM::ShiftOpc ShiftTy;
879 ARM_AM::ShiftOpc ShiftTy;
1123 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1295 return (ARM_AM::getSOImmVal(Value) != -1 ||
1296 ARM_AM::getSOImmVal(-Value) != -1);
1313 return ARM_AM::getT2SOImmVal(Value) != -1;
1321 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1322 ARM_AM::getT2SOImmVal(~Value) != -1;
1331 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1332 ARM_AM::getT2SOImmVal(-Value) != -1;
1414 return ARM_AM::getSOImmVal(~Value) != -1;
1422 return ARM_AM::getSOImmVal(Value) == -1 &&
1423 ARM_AM::getSOImmVal(-Value) != -1;
1449 return isPostIdxRegShifted() && PostIdxReg.ShiftTy == ARM_AM::no_shift;
1615 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1684 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1691 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1708 if (Memory.ShiftType == ARM_AM::no_shift)
1710 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1719 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1885 if (shift == 0 && Memory.ShiftType != ARM_AM::no_shift)
1889 (Memory.ShiftType != ARM_AM::uxtw || Memory.ShiftImm != shift))
2253 return ARM_AM::isNEONi16splat(Value);
2263 return ARM_AM::isNEONi16splat(~Value & 0xffff);
2275 return ARM_AM::isNEONi32splat(Value);
2285 return ARM_AM::isNEONi32splat(~Value);
2551 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
2562 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
2622 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
2629 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
2678 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
2952 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2958 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2966 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2977 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2981 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
3005 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3011 Val = ARM_AM::getAM3Opc(AddSub, Val);
3019 ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
3028 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
3037 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3041 Val = ARM_AM::getAM3Opc(AddSub, Val);
3063 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3069 Val = ARM_AM::getAM5Opc(AddSub, Val);
3092 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
3098 Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
3208 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
3303 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
3304 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
3415 Value = ARM_AM::encodeNEONi16splat(Value);
3424 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
3433 Value = ARM_AM::encodeNEONi32splat(Value);
3442 Value = ARM_AM::encodeNEONi32splat(~Value);
3639 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3653 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
3804 ARM_AM::ShiftOpc ShiftType, unsigned ShiftImm, unsigned Alignment,
3821 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
3953 if (Memory.ShiftType != ARM_AM::no_shift) {
3954 OS << " shift-type:" << ARM_AM::getShiftOpcStr(Memory.ShiftType);
3964 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
3965 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
3987 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy) << " "
3992 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy) << " #"
4141 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
4142 .Case("asl", ARM_AM::lsl)
4143 .Case("lsl", ARM_AM::lsl)
4144 .Case("lsr", ARM_AM::lsr)
4145 .Case("asr", ARM_AM::asr)
4146 .Case("ror", ARM_AM::ror)
4147 .Case("rrx", ARM_AM::rrx)
4148 .Default(ARM_AM::no_shift);
4150 if (ShiftTy == ARM_AM::no_shift)
4167 if (ShiftTy == ARM_AM::rrx) {
4194 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
4195 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
4202 ShiftTy = ARM_AM::lsl;
4218 if (ShiftReg && ShiftTy != ARM_AM::rrx)
5471 int Enc = ARM_AM::getSOImmVal(Imm1);
5645 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
5727 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
5851 ARM_AM::no_shift, 0, 0, false,
5908 ARM_AM::no_shift, 0, Align,
5951 BaseRegNum, AdjustedOffset, 0, ARM_AM::no_shift, 0, 0, false, S, E));
5985 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
6017 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
6027 St = ARM_AM::lsl;
6029 St = ARM_AM::lsr;
6031 St = ARM_AM::asr;
6033 St = ARM_AM::ror;
6035 St = ARM_AM::rrx;
6037 St = ARM_AM::uxtw;
6044 if (St != ARM_AM::rrx) {
6064 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
6065 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
6069 St = ARM_AM::lsl;
6148 float RealVal = ARM_AM::getFPImmFloat(Val);
8743 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
8844 if (ARM_AM::getSOImmVal(Value) != -1) {
8845 Value = ARM_AM::getSOImmVal(Value);
8848 else if (ARM_AM::getSOImmVal(~Value) != -1) {
8849 Value = ARM_AM::getSOImmVal(~Value);
8863 ARM_AM::getT2SOImmVal(Value) != -1)
8866 ARM_AM::getT2SOImmVal(~Value) != -1) {
10013 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
10015 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
10016 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
10017 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
10018 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
10048 unsigned Shift = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10049 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
10052 if (Shift == ARM_AM::lsl && Amount == 0) {
10065 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
10066 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
10067 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
10068 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
10069 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
10094 ARM_AM::ShiftOpc ShiftTy;
10097 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
10098 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
10099 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
10100 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
10102 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
10119 ARM_AM::ShiftOpc ShiftTy;
10122 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
10123 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
10124 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
10125 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
10131 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
10133 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
10147 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
10233 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
10520 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
10522 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
10524 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
10545 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
10546 if (SOpc == ARM_AM::rrx) return false;
10558 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
10559 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {