Searched refs:SUnit (Results 1 - 25 of 40) sorted by relevance

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/freebsd-9.3-release/contrib/llvm/include/llvm/CodeGen/
H A DResourcePriorityQueue.h31 struct resource_sort : public std::binary_function<SUnit*, SUnit*, bool> {
35 bool operator()(const SUnit* left, const SUnit* right) const;
40 std::vector<SUnit> *SUnits;
49 std::vector<SUnit*> Queue;
71 std::vector<SUnit*> Packet;
86 void initNodes(std::vector<SUnit> &sunits);
88 void addNode(const SUnit *SU) {
92 void updateNode(const SUnit *S
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H A DLatencyPriorityQueue.h25 struct latency_sort : public std::binary_function<SUnit*, SUnit*, bool> {
29 bool operator()(const SUnit* left, const SUnit* right) const;
34 std::vector<SUnit> *SUnits;
43 std::vector<SUnit*> Queue;
52 void initNodes(std::vector<SUnit> &sunits) {
57 void addNode(const SUnit *SU) {
61 void updateNode(const SUnit *SU) {
80 virtual void push(SUnit *
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H A DScheduleDAGInstrs.h33 /// An individual mapping from virtual register number to SUnit.
36 SUnit *SU;
38 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {}
48 SUnit *SU;
52 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
114 /// scheduling region is mapped to an SUnit.
115 DenseMap<MachineInstr*, SUnit*> MISUnitMap;
138 std::vector<SUnit *> PendingLoads;
163 /// \brief Resolve and cache a resolved scheduling class for an SUnit.
164 const MCSchedClassDesc *getSchedClass(SUnit *S
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H A DMachineScheduler.h190 virtual SUnit *pickNode(bool &IsTopNode) = 0;
197 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
201 virtual void releaseTopNode(SUnit *SU) = 0;
204 virtual void releaseBottomNode(SUnit *SU) = 0;
209 /// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in.
216 std::vector<SUnit*> Queue;
226 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); }
234 typedef std::vector<SUnit*>::iterator iterator;
240 ArrayRef<SUnit*> element
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H A DScheduleHazardRecognizer.h20 class SUnit;
60 virtual HazardType getHazardType(SUnit *m, int Stalls = 0) {
71 virtual void EmitInstruction(SUnit *) {}
H A DScheduleDAG.h28 class SUnit;
74 /// Dep - A pointer to the depending/depended-on SUnit, and an enum
76 PointerIntPair<SUnit *, 2, Kind> Dep;
101 SDep(SUnit *S, Kind kind, unsigned Reg)
119 SDep(SUnit *S, OrderKind kind)
159 //// getSUnit - Return the SUnit to which this edge points.
160 SUnit *getSUnit() const {
164 //// setSUnit - Assign the SUnit to which this edge points.
165 void setSUnit(SUnit *SU) {
248 /// SUnit
249 class SUnit { class in namespace:llvm
311 SUnit(SDNode *node, unsigned nodenum) function
325 SUnit(MachineInstr *instr, unsigned nodenum) function
338 SUnit() function
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H A DDFAPacketizer.h41 class SUnit;
107 std::map<MachineInstr*, SUnit*> MIToSUnit;
154 virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) {
160 virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
H A DScoreboardHazardRecognizer.h28 class SUnit;
117 virtual HazardType getHazardType(SUnit *SU, int Stalls);
119 virtual void EmitInstruction(SUnit *SU);
/freebsd-9.3-release/contrib/llvm/lib/Target/R600/
H A DR600MachineScheduler.h54 std::vector<SUnit *> Available[IDLast], Pending[IDLast];
55 std::vector<SUnit *> AvailableAlus[AluLast];
56 std::vector<SUnit *> PhysicalRegCopy;
78 virtual SUnit *pickNode(bool &IsTopNode);
79 virtual void schedNode(SUnit *SU, bool IsTopNode);
80 virtual void releaseTopNode(SUnit *SU);
81 virtual void releaseBottomNode(SUnit *SU);
87 int getInstKind(SUnit *SU);
89 AluKind getAluKind(SUnit *SU) const;
92 SUnit *AttemptFillSlo
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H A DR600MachineScheduler.cpp45 void R600SchedStrategy::MoveUnits(std::vector<SUnit *> &QSrc,
46 std::vector<SUnit *> &QDst)
58 SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) {
59 SUnit *SU = 0;
131 const SUnit &S = DAG->SUnits[i];
141 void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
189 void R600SchedStrategy::releaseTopNode(SUnit *SU) {
193 void R600SchedStrategy::releaseBottomNode(SUnit *SU) {
219 R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const {
293 int R600SchedStrategy::getInstKind(SUnit* S
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/
H A DLatencyPriorityQueue.cpp22 bool latency_sort::operator()(const SUnit *LHS, const SUnit *RHS) const {
55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) {
56 SUnit *OnlyAvailablePred = 0;
57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
59 SUnit &Pred = *I->getSUnit();
72 void LatencyPriorityQueue::push(SUnit *SU) {
76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
91 void LatencyPriorityQueue::scheduledNode(SUnit *S
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H A DScheduleDAGPrinter.cpp44 static bool isNodeHidden(const SUnit *Node) {
48 static bool hasNodeAddressLabel(const SUnit *Node,
55 static std::string getEdgeAttributes(const SUnit *Node,
66 std::string getNodeLabel(const SUnit *Node, const ScheduleDAG *Graph);
67 static std::string getNodeAttributes(const SUnit *N,
79 std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
H A DScheduleDAG.cpp52 EntrySU = SUnit();
53 ExitSU = SUnit();
65 bool SUnit::addPred(const SDep &D, bool Required) {
76 SUnit *PredSU = I->getSUnit();
95 SUnit *N = D.getSUnit();
133 void SUnit::removePred(const SDep &D) {
141 SUnit *N = D.getSUnit();
178 void SUnit::setDepthDirty() {
180 SmallVector<SUnit*, 8> WorkList;
183 SUnit *S
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H A DScheduleDAGInstrs.cpp243 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
255 SUnit *UseSU = I->SU;
284 /// this SUnit to following instructions in the same scheduling region that
286 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
302 SUnit *DefSU = I->SU;
324 // Push this SUnit on the use list.
359 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
365 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
386 SUnit *DefSU = DefI->SU;
398 /// defines the virtual register used at OperIdx is mapped to an SUnit
564 iterateChainSucc(AliasAnalysis *AA, const MachineFrameInfo *MFI, SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth, SmallPtrSet<const SUnit*, 16> &Visited) argument
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H A DMachineScheduler.cpp371 bool ScheduleDAGMI::canAddEdge(SUnit *SuccSU, SUnit *PredSU) {
375 bool ScheduleDAGMI::addEdge(SUnit *SuccSU, const SDep &PredDep) {
392 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) {
393 SUnit *SuccSU = SuccEdge->getSUnit();
415 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) {
416 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
426 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) {
427 SUnit *PredSU = PredEdge->getSUnit();
449 void ScheduleDAGMI::releasePredecessors(SUnit *S
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/freebsd-9.3-release/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.h30 /// nodes into a single SUnit so that they are scheduled together.
42 /// The schedule. Null SUnit*'s represent noop instructions.
43 std::vector<SUnit*> Sequence;
73 /// NewSUnit - Creates a new SUnit and return a ptr to it.
75 SUnit *newSUnit(SDNode *N);
77 /// Clone - Creates a clone of the specified SUnit. It does not copy the
80 SUnit *Clone(SUnit *N);
82 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we
83 /// are input. This SUnit grap
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H A DScheduleDAGVLIW.cpp60 std::vector<SUnit*> PendingQueue;
86 void releaseSucc(SUnit *SU, const SDep &D);
87 void releaseSuccessors(SUnit *SU);
88 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
115 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
116 SUnit *SuccSU = D.getSUnit();
139 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) {
141 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
153 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
185 std::vector<SUnit*> NotRead
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H A DResourcePriorityQueue.cpp71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
73 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
78 SUnit *PredSU = I->getSUnit();
108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
116 SUnit *SuccSU = I->getSUnit();
146 static unsigned numberCtrlDepsInSU(SUnit *SU) {
148 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
156 static unsigned numberCtrlPredInSU(SUnit *SU) {
158 for (SUnit
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H A DScheduleDAGFast.cpp48 SmallVector<SUnit *, 16> Queue;
52 void push(SUnit *U) {
56 SUnit *pop() {
58 SUnit *V = Queue.back();
76 std::vector<SUnit*> LiveRegDefs;
85 /// AddPred - adds a predecessor edge to SUnit SU.
87 void AddPred(SUnit *SU, const SDep &D) {
91 /// RemovePred - removes a predecessor edge from SUnit SU.
93 void RemovePred(SUnit *SU, const SDep &D) {
98 void ReleasePred(SUnit *S
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H A DScheduleDAGRRList.cpp124 std::vector<SUnit*> PendingQueue;
143 std::vector<SUnit*> LiveRegDefs;
144 std::vector<SUnit*> LiveRegGens;
147 // Each interference is an SUnit and set of physical registers.
148 SmallVector<SUnit*, 4> Interferences;
149 typedef DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMapT;
158 DenseMap<SUnit*, SUnit*> CallSeqEndForStart;
185 bool IsReachable(const SUnit *SU, const SUnit *TargetS
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/freebsd-9.3-release/contrib/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.h52 std::vector<SUnit*> Packet;
88 bool isResourceAvailable(SUnit *SU);
89 bool reserveResources(SUnit *SU);
114 // The best SUnit candidate.
115 SUnit *SU;
176 bool checkHazard(SUnit *SU);
178 void releaseNode(SUnit *SU, unsigned ReadyCycle);
182 void bumpNode(SUnit *SU);
186 void removeReady(SUnit *SU);
188 SUnit *pickOnlyChoic
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H A DHexagonMachineScheduler.cpp25 SUnit* LastSequentialCall = NULL;
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) {
68 for (SUnit::const_succ_iterator I = Packet[i]->Succs.begin(),
83 bool VLIWResourceModel::reserveResources(SUnit *SU) {
156 SmallVector<SUnit*, 8> TopRoots, BotRoots;
164 // FIXME: SUnit::dumpAll always recompute depth and height now. The max
182 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) {
220 void ConvergingVLIWScheduler::releaseTopNode(SUnit *SU) {
224 for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end();
237 void ConvergingVLIWScheduler::releaseBottomNode(SUnit *S
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/freebsd-9.3-release/contrib/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.h40 virtual HazardType getHazardType(SUnit *SU, int Stalls);
42 virtual void EmitInstruction(SUnit *SU);
/freebsd-9.3-release/contrib/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.h33 virtual HazardType getHazardType(SUnit *SU, int Stalls);
34 virtual void EmitInstruction(SUnit *SU);
68 virtual HazardType getHazardType(SUnit *SU, int Stalls);
69 virtual void EmitInstruction(SUnit *SU);
/freebsd-9.3-release/contrib/llvm/include/llvm/Target/
H A DTargetSubtargetInfo.h25 class SUnit;
89 virtual void adjustSchedDependency(SUnit *def, SUnit *use,

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