Lines Matching refs:SUnit

243 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) {
255 SUnit *UseSU = I->SU;
284 /// this SUnit to following instructions in the same scheduling region that
286 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) {
302 SUnit *DefSU = I->SU;
324 // Push this SUnit on the use list.
359 /// addVRegDefDeps - Add register output and data dependencies from this SUnit
365 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
386 SUnit *DefSU = DefI->SU;
398 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add a
399 /// register antidependency from this SUnit to instructions that occur later in
403 void ScheduleDAGInstrs::addVRegUseDeps(SUnit *SU, unsigned OperIdx) {
427 SUnit *DefSU = getSUnit(Def);
565 SUnit *SUa, SUnit *SUb, SUnit *ExitSU, unsigned *Depth,
566 SmallPtrSet<const SUnit*, 16> &Visited) {
598 for (SUnit::const_succ_iterator I = SUb->Succs.begin(), E = SUb->Succs.end();
610 SUnit *SU, SUnit *ExitSU, std::set<SUnit *> &CheckList,
615 SmallPtrSet<const SUnit*, 16> Visited;
618 for (std::set<SUnit *>::iterator I = CheckList.begin(), IE = CheckList.end();
629 for (SUnit::const_succ_iterator J = (*I)->Succs.begin(),
641 SUnit *SUa, SUnit *SUb,
642 std::set<SUnit *> &RejectList,
661 /// Create an SUnit for each real instruction, numbered in top-down toplological
664 /// Map each real instruction to its SUnit.
667 /// hang onto SUnit pointers. We may relax this in the future by using SUnit IDs
673 // We'll be allocating one SUnit for each real instruction in the region,
682 SUnit *SU = newSUnit(MI);
707 // Create an SUnit for each real instruction.
717 SUnit *BarrierChain = 0, *AliasChain = 0;
723 MapVector<const Value *, SUnit *> AliasMemDefs, NonAliasMemDefs;
724 MapVector<const Value *, std::vector<SUnit *> > AliasMemUses, NonAliasMemUses;
725 std::set<SUnit*> RejectMemNodes;
760 SUnit *SU = MISUnitMap[MI];
761 assert(SU && "No SUnit mapped to this MI");
818 for (MapVector<const Value *, SUnit *>::iterator I =
822 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
856 for (MapVector<const Value *, SUnit *>::iterator I = AliasMemDefs.begin(),
859 for (MapVector<const Value *, std::vector<SUnit *> >::iterator I =
890 MapVector<const Value *, SUnit *>::iterator I =
892 MapVector<const Value *, SUnit *>::iterator IE =
905 MapVector<const Value *, std::vector<SUnit *> >::iterator J =
907 MapVector<const Value *, std::vector<SUnit *> >::iterator JE =
952 for (MapVector<const Value *, SUnit *>::iterator I =
971 MapVector<const Value *, SUnit *>::iterator I =
973 MapVector<const Value *, SUnit *>::iterator IE =
1002 void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
1008 std::string ScheduleDAGInstrs::getGraphNodeLabel(const SUnit *SU) const {
1038 std::vector<std::pair<const SUnit*, const SUnit*> > ConnectionPairs;
1063 bool isVisited(const SUnit *SU) const {
1070 void visitPreorder(const SUnit *SU) {
1078 void visitPostorderNode(const SUnit *SU) {
1091 for (SUnit::const_pred_iterator
1121 void visitPostorderEdge(const SDep &PredDep, const SUnit *Succ) {
1128 void visitCrossEdge(const SDep &PredDep, const SUnit *Succ) {
1158 for (std::vector<std::pair<const SUnit*, const SUnit*> >::const_iterator
1174 bool joinPredSubtree(const SDep &PredDep, const SUnit *Succ,
1179 const SUnit *PredSU = PredDep.getSUnit();
1187 for (SUnit::const_succ_iterator SI = PredSU->Succs.begin(),
1226 std::vector<std::pair<const SUnit*, SUnit::const_pred_iterator> > DFSStack;
1230 void follow(const SUnit *SU) {
1240 const SUnit *getCurr() const { return DFSStack.back().first; }
1242 SUnit::const_pred_iterator getPred() const { return DFSStack.back().second; }
1244 SUnit::const_pred_iterator getPredEnd() const {
1250 static bool hasDataSucc(const SUnit *SU) {
1251 for (SUnit::const_succ_iterator
1261 void SchedDFSResult::compute(ArrayRef<SUnit> SUnits) {
1266 for (ArrayRef<SUnit>::const_iterator
1268 const SUnit *SU = &*SI;
1294 const SUnit *Child = DFS.getCurr();