/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/ |
H A D | CallingConvLower.cpp | 86 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 89 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 90 MVT VT = Outs[i].VT; 91 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 100 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 103 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 104 MVT VT = Outs[i].VT; 105 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 118 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 120 unsigned NumOps = Outs [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/ |
H A D | HexagonCallingConvLower.cpp | 94 Hexagon_CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, argument 116 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 117 EVT VT = Outs[i].VT; 118 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 132 &Outs, 136 unsigned NumOps = Outs.size(); 147 EVT ArgVT = Outs[i].VT; 148 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 131 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, Hexagon_CCAssignFn Fn, int NonVarArgsParams, unsigned SretValueSize) argument
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H A D | HexagonCallingConvLower.h | 85 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 90 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | HexagonISelLowering.h | 77 SmallVectorImpl<ISD::OutputArg> &Outs, 118 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | HexagonISelLowering.cpp | 293 const SmallVectorImpl<ISD::OutputArg> &Outs, 305 CCInfo.AnalyzeReturn(Outs, RetCC_Hexagon); 377 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local 386 bool IsStructRet = (Outs.empty()) ? false : Outs[0].Flags.isSRet(); 412 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon_VarArg); 414 CCInfo.AnalyzeCallOperands(Outs, CC_Hexagon); 423 Outs, OutVals, Ins, DAG); 451 ISD::ArgFlagsTy Flags = Outs[ 291 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument 1589 IsEligibleForTailCallOptimization( SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg, bool isCalleeStructRet, bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MSP430/ |
H A D | MSP430ISelLowering.h | 128 const SmallVectorImpl<ISD::OutputArg> &Outs, 161 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | MSP430ISelLowering.cpp | 273 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local 291 Outs, OutVals, Ins, dl, DAG, InVals); 385 const SmallVectorImpl<ISD::OutputArg> &Outs, 393 if (CallConv == CallingConv::MSP430_INTR && !Outs.empty()) 401 CCInfo.AnalyzeReturn(Outs, RetCC_MSP430); 444 &Outs, 454 CCInfo.AnalyzeCallOperands(Outs, CC_MSP430); 383 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument 440 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Sparc/ |
H A D | SparcISelLowering.h | 85 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | SparcISelLowering.cpp | 82 const SmallVectorImpl<ISD::OutputArg> &Outs, 96 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 352 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local 368 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 380 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 381 ISD::ArgFlagsTy Flags = Outs[i].Flags; 414 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 80 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/NVPTX/ |
H A D | NVPTXISelLowering.cpp | 284 const SmallVectorImpl<ISD::OutputArg> &Outs, 381 if (Outs[i].Flags.isByVal() == false) { 404 unsigned align = Outs[i].Flags.getByValAlign(); 446 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local 463 assert((Outs.size() == Args.size()) && 468 for (unsigned i=0, e=Outs.size(); i!=e; ++i) { 469 EVT VT = Outs[i].VT; 471 if (Outs[i].Flags.isByVal() == false) { 497 if (Outs[ 282 getPrototype(Type *retTy, const ArgListTy &Args, const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment) const argument 1074 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument [all...] |
H A D | NVPTXISelLowering.h | 117 const SmallVectorImpl<ISD::OutputArg> &Outs,
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/PowerPC/ |
H A D | PPCISelLowering.h | 459 const SmallVectorImpl<ISD::OutputArg> &Outs, 465 const SmallVectorImpl<ISD::OutputArg> &Outs, 486 const SmallVectorImpl<ISD::OutputArg> &Outs, 494 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | PPCISelLowering.cpp | 2338 &Outs, 2345 unsigned NumOps = Outs.size(); 2356 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2357 EVT ArgVT = Outs[i].VT; 2977 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local 2992 isTailCall, Outs, OutVals, Ins, 2996 isTailCall, Outs, OutVals, Ins, 3004 const SmallVectorImpl<ISD::OutputArg> &Outs, 3044 unsigned NumArgs = Outs 2333 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, bool isPPC64, bool isVarArg, unsigned CC, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, unsigned &nAltivecParamsAtEnd) argument 3001 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3214 LowerCall_Darwin_Or_64SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 3648 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument 3659 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 202 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, 213 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/XCore/ |
H A D | XCoreISelLowering.h | 120 const SmallVectorImpl<ISD::OutputArg> &Outs, 183 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | XCoreISelLowering.cpp | 881 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local 901 Outs, OutVals, Ins, dl, DAG, InVals); 913 const SmallVectorImpl<ISD::OutputArg> &Outs, 928 CCInfo.AnalyzeCallOperands(Outs, CC_XCore); 1209 const SmallVectorImpl<ISD::OutputArg> &Outs, 1213 return CCInfo.CheckReturn(Outs, RetCC_XCore); 1219 const SmallVectorImpl<ISD::OutputArg> &Outs, 1232 CCInfo.AnalyzeReturn(Outs, RetCC_XCore); 910 LowerCCCCallTo(SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg, bool isTailCall, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<ISD::InputArg> &Ins, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const argument 1207 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, LLVMContext &Context) const argument 1217 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/CellSPU/ |
H A D | SPUISelLowering.h | 167 const SmallVectorImpl<ISD::OutputArg> &Outs,
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.h | 141 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | MBlazeISelLowering.cpp | 688 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local 712 CCInfo.AnalyzeCallOperands(Outs, CC_MBlaze); 1016 const SmallVectorImpl<ISD::OutputArg> &Outs, 1028 CCInfo.AnalyzeReturn(Outs, RetCC_MBlaze); 1015 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument
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/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/ |
H A D | FunctionLoweringInfo.cpp | 68 SmallVector<ISD::OutputArg, 4> Outs; local 70 Fn->getAttributes().getRetAttributes(), Outs, TLI); 73 Outs, Fn->getContext());
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/ |
H A D | X86ISelLowering.h | 752 const SmallVectorImpl<ISD::OutputArg> &Outs, 836 const SmallVectorImpl<ISD::OutputArg> &Outs, 851 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | X86FastISel.cpp | 742 SmallVector<ISD::OutputArg, 4> Outs; local 744 Outs, TLI); 750 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 783 if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) 789 if (Outs[0].Flags.isSExt()) 794 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : 1583 SmallVector<ISD::OutputArg, 4> Outs; 1585 Outs, TLI); 1588 Outs, FT [all...] |
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/ |
H A D | ARMISelLowering.h | 494 const SmallVectorImpl<ISD::OutputArg> &Outs, 501 const SmallVectorImpl<ISD::OutputArg> &Outs,
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Mips/ |
H A D | MipsISelLowering.h | 222 const SmallVectorImpl<ISD::OutputArg> &Outs,
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H A D | MipsISelLowering.cpp | 2650 const SmallVectorImpl<ISD::OutputArg> &Outs) { 2651 unsigned NumOps = Outs.size(); 2653 MVT ArgVT = Outs[i].VT; 2654 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; 2657 if (Outs[i].IsFixed) 2875 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; local 2899 CCInfo.AnalyzeCallOperands(Outs, CC_Mips_FastCC); 2901 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 2903 AnalyzeMips64CallOperands(CCInfo, Outs); 2649 AnalyzeMips64CallOperands(CCState &CCInfo, const SmallVectorImpl<ISD::OutputArg> &Outs) argument 3442 LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<SDValue> &OutVals, DebugLoc dl, SelectionDAG &DAG) const argument [all...] |