Searched refs:NumOps (Results 1 - 25 of 48) sorted by relevance

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/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/
H A DConstant.h47 Constant(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps) argument
48 : User(ty, vty, Ops, NumOps) {}
H A DInlineAsm.h234 static unsigned getFlagWord(unsigned Kind, unsigned NumOps) { argument
235 assert(((NumOps << 3) & ~0xffff) == 0 && "Too many inline asm operands!");
237 return Kind | (NumOps << 3);
H A DUser.h52 User(Type *ty, unsigned vty, Use *OpList, unsigned NumOps) argument
53 : Value(ty, vty), OperandList(OpList), NumOperands(NumOps) {}
H A DGlobalValue.h59 GlobalValue(Type *ty, ValueTy vty, Use *Ops, unsigned NumOps, argument
61 : Constant(ty, vty, Ops, NumOps), Linkage(linkage),
H A DInstruction.h386 Instruction(Type *Ty, unsigned iType, Use *Ops, unsigned NumOps,
388 Instruction(Type *Ty, unsigned iType, Use *Ops, unsigned NumOps,
H A DInstrTypes.h38 Use *Ops, unsigned NumOps,
40 : Instruction(Ty, iType, Ops, NumOps, InsertBefore) {}
43 Use *Ops, unsigned NumOps, BasicBlock *InsertAtEnd)
44 : Instruction(Ty, iType, Ops, NumOps, InsertAtEnd) {}
37 TerminatorInst(Type *Ty, Instruction::TermOps iType, Use *Ops, unsigned NumOps, Instruction *InsertBefore = 0) argument
42 TerminatorInst(Type *Ty, Instruction::TermOps iType, Use *Ops, unsigned NumOps, BasicBlock *InsertAtEnd) argument
/macosx-10.9.5/llvmCore-3425.0.33/include/llvm/CodeGen/
H A DSelectionDAG.h569 const SDUse *Ops, unsigned NumOps);
571 const SDValue *Ops, unsigned NumOps);
574 const SDValue *Ops, unsigned NumOps);
576 const SDValue *Ops, unsigned NumOps);
578 const SDValue *Ops, unsigned NumOps);
679 const SDValue *Ops, unsigned NumOps,
685 const SDValue *Ops, unsigned NumOps,
691 const SDValue *Ops, unsigned NumOps,
695 SDValue getMergeValues(const SDValue *Ops, unsigned NumOps, DebugLoc dl);
766 const SDValue *Ops, unsigned NumOps);
[all...]
H A DSelectionDAGNodes.h683 unsigned NumOps)
686 OperandList(NumOps ? new SDUse[NumOps] : 0),
688 NumOperands(NumOps), NumValues(VTs.NumVTs),
690 for (unsigned i = 0; i != NumOps; ++i) {
906 unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO);
1085 const SDValue *Ops, unsigned NumOps,
1087 : MemSDNode(Opc, dl, VTs, Ops, NumOps, MemoryVT, MMO) {
1567 unsigned NumOps, ISD::CvtCode Code)
1568 : SDNode(ISD::CONVERT_RNDSAT, dl, getSDVTList(VT), Ops, NumOps),
1084 MemIntrinsicSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops, unsigned NumOps, EVT MemoryVT, MachineMemOperand *MMO) argument
1566 CvtRndSatSDNode(EVT VT, DebugLoc dl, const SDValue *Ops, unsigned NumOps, ISD::CvtCode Code) argument
[all...]
H A DSelectionDAGISel.h247 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/
H A DCallingConvLower.cpp120 unsigned NumOps = Outs.size(); local
121 for (unsigned i = 0; i != NumOps; ++i) {
139 unsigned NumOps = ArgVTs.size(); local
140 for (unsigned i = 0; i != NumOps; ++i) {
H A DMachineInstr.cpp988 unsigned NumOps;
990 i += NumOps) {
995 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
996 if (i + NumOps > OpIdx) {
1223 unsigned NumOps;
1225 i += NumOps) {
1230 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1232 if (OpIdx > i && OpIdx < i + NumOps)
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/Hexagon/
H A DHexagonCallingConvLower.cpp136 unsigned NumOps = Outs.size(); local
146 for (; i != NumOps; ++i) {
164 unsigned NumOps = ArgVTs.size(); local
165 for (unsigned i = 0; i != NumOps; ++i) {
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/
H A DX86CodeEmitter.cpp169 unsigned NumOps = Desc.getNumOperands(); local
170 if (NumOps) {
171 bool isTwoAddr = NumOps > 1 &&
176 for (unsigned e = NumOps; i != e; ++i) {
194 for (unsigned e = NumOps; i != e; ++i) {
206 for (; i != NumOps; ++i) {
223 if (NumOps > e && X86InstrInfo::isX86_64ExtendedReg(MI.getOperand(e)))
240 for (unsigned e = NumOps; i != e; ++i) {
925 unsigned NumOps = Desc->getNumOperands();
927 if (NumOps >
[all...]
H A DX86FloatingPoint.cpp985 unsigned NumOps = MI->getDesc().getNumOperands();
986 assert((NumOps == X86::AddrNumOperands + 1 || NumOps == 1) &&
990 unsigned Reg = getFPReg(MI->getOperand(NumOps-1));
1022 MI->RemoveOperand(NumOps-1); // Remove explicit ST(0) operand
1050 unsigned NumOps = MI->getDesc().getNumOperands();
1051 assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
1472 unsigned NumOps = 0;
1474 i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) {
1476 NumOps
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp564 unsigned NumOps = Desc.getNumOperands(); local
566 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
568 else if (NumOps > 3 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0) {
569 assert(Desc.getOperandConstraint(NumOps - 1, MCOI::TIED_TO) == 1);
726 unsigned NumOps = MI.getNumOperands(); local
728 bool isTwoAddr = NumOps > 1 &&
733 for (; i != NumOps; ++i) {
751 for (; i != NumOps; ++i) {
763 for (; i != NumOps; ++i) {
780 if (NumOps >
969 unsigned NumOps = Desc.getNumOperands(); local
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp354 const SDValue *Ops, unsigned NumOps) {
355 for (; NumOps; --NumOps, ++Ops) {
364 const SDUse *Ops, unsigned NumOps) {
365 for (; NumOps; --NumOps, ++Ops) {
789 const SDValue *Ops,unsigned NumOps,
795 AddNodeIDNode(ID, N->getOpcode(), N->getVTList(), Ops, NumOps);
4126 SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, argument
4128 if (NumOps
353 AddNodeIDOperands(FoldingSetNodeID &ID, const SDValue *Ops, unsigned NumOps) argument
363 AddNodeIDOperands(FoldingSetNodeID &ID, const SDUse *Ops, unsigned NumOps) argument
788 FindModifiedNodeSlot(SDNode *N, const SDValue *Ops,unsigned NumOps, void *&InsertPos) argument
4140 getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, const EVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align, bool Vol, bool ReadMem, bool WriteMem) argument
4152 getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, EVT MemVT, MachinePointerInfo PtrInfo, unsigned Align, bool Vol, bool ReadMem, bool WriteMem) argument
4175 getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, EVT MemVT, MachineMemOperand *MMO) argument
4517 getNode(unsigned Opcode, DebugLoc DL, EVT VT, const SDUse *Ops, unsigned NumOps) argument
4533 getNode(unsigned Opcode, DebugLoc DL, EVT VT, const SDValue *Ops, unsigned NumOps) argument
4588 getNode(unsigned Opcode, DebugLoc DL, const std::vector<EVT> &ResultTys, const SDValue *Ops, unsigned NumOps) argument
4595 getNode(unsigned Opcode, DebugLoc DL, const EVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps) argument
4603 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, const SDValue *Ops, unsigned NumOps) argument
4863 UpdateNodeOperands(SDNode *N, const SDValue *Ops, unsigned NumOps) argument
4942 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, const SDValue *Ops, unsigned NumOps) argument
4949 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, const SDValue *Ops, unsigned NumOps) argument
4962 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps) argument
4969 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps) argument
5010 SelectNodeTo(SDNode *N, unsigned MachineOpc, SDVTList VTs, const SDValue *Ops, unsigned NumOps) argument
5045 MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, const SDValue *Ops, unsigned NumOps) argument
5160 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT, const SDValue *Ops, unsigned NumOps) argument
5198 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, const SDValue *Ops, unsigned NumOps) argument
5224 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps) argument
5232 getMachineNode(unsigned Opcode, DebugLoc dl, EVT VT1, EVT VT2, EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps) argument
5240 getMachineNode(unsigned Opcode, DebugLoc dl, const std::vector<EVT> &ResultTys, const SDValue *Ops, unsigned NumOps) argument
5248 getMachineNode(unsigned Opcode, DebugLoc DL, SDVTList VTs, const SDValue *Ops, unsigned NumOps) argument
5311 getNodeIfExists(unsigned Opcode, SDVTList VTList, const SDValue *Ops, unsigned NumOps) argument
5793 MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops, unsigned NumOps, EVT memvt, MachineMemOperand *mmo) argument
[all...]
H A DLegalizeTypes.cpp415 for (unsigned i = 0, NumOps = I->getNumOperands(); i < NumOps; ++i)
1047 unsigned NumOps = N->getNumOperands(); local
1049 if (NumOps == 0) {
1051 } else if (NumOps == 1) {
1054 } else if (NumOps == 2) {
1058 SmallVector<SDValue, 8> Ops(NumOps);
1059 for (unsigned i = 0; i < NumOps; ++i)
1062 return MakeLibCall(LC, N->getValueType(0), &Ops[0], NumOps, isSigned, dl);
1068 const SDValue *Ops, unsigned NumOps,
1067 MakeLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, DebugLoc dl) argument
[all...]
H A DScheduleDAGFast.cpp477 unsigned NumOps = Node->getNumOperands(); local
478 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
479 --NumOps; // Ignore the glue operand.
481 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
H A DInstrEmitter.cpp601 unsigned NumOps = Node->getNumOperands();
602 assert((NumOps & 1) == 1 &&
605 for (unsigned i = 1; i != NumOps; ++i) {
887 unsigned NumOps = Node->getNumOperands();
888 if (Node->getOperand(NumOps-1).getValueType() == MVT::Glue)
889 --NumOps; // Ignore the glue operand.
911 for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DThumb2SizeReduction.cpp658 unsigned NumOps = MCID.getNumOperands(); local
659 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
660 if (HasCC && MI->getOperand(NumOps-1).isDead())
684 unsigned NumOps = MCID.getNumOperands(); local
686 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
749 unsigned NumOps = MCID.getNumOperands(); local
750 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
751 if (HasCC && MI->getOperand(NumOps-1).isDead())
775 unsigned NumOps = MCID.getNumOperands(); local
777 if (i < NumOps
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/lib/VMCore/
H A DInstruction.cpp23 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps, argument
25 : User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) {
37 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps, argument
39 : User(ty, Value::InstructionVal + it, Ops, NumOps), Parent(0) {
H A DInstructions.cpp143 unsigned NumOps = e + e / 2; local
144 if (NumOps < 2) NumOps = 2; // 2 op PHI nodes are VERY common.
149 ReservedSpace = NumOps;
3211 unsigned NumOps = getNumOperands(); local
3215 if (2 + (idx + 1) * 2 != NumOps) {
3216 OL[2 + idx * 2] = OL[NumOps - 2];
3217 OL[2 + idx * 2 + 1] = OL[NumOps - 1];
3221 OL[NumOps-2].set(0);
3222 OL[NumOps
3241 unsigned NumOps = e*3; local
3284 unsigned NumOps = e*2; local
[all...]
/macosx-10.9.5/llvmCore-3425.0.33/utils/TableGen/
H A DAsmWriterEmitter.cpp403 unsigned NumOps = NumInstOpsHandled[InstIdxs[i]];
404 assert(NumOps <= Inst->Operands.size() &&
407 Inst->Operands.begin()+NumOps);
738 unsigned NumOps = 0;
742 ++NumOps;
746 return NumOps;
750 unsigned NumOps = 0;
762 ++NumOps;
767 return NumOps;
H A DCodeGenInstruction.cpp71 unsigned NumOps = 1; local
92 NumOps = NumArgs;
117 OperandType, MIOperandNo, NumOps,
119 MIOperandNo += NumOps;
H A DDAGISelMatcherEmitter.cpp647 unsigned NumOps = P.getNumOperands(); local
650 ++NumOps; // Get the chained node too.
653 OS << " Result.resize(NextRes+" << NumOps << ");\n"; local
668 for (unsigned i = 0; i != NumOps; ++i)

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