Searched refs:CPSR (Results 1 - 16 of 16) sorted by relevance

/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/
H A DThumb2SizeReduction.cpp51 // 2 - Always set CPSR.
80 // FIXME: tMOVi8 and tMVN also partially update CPSR but they are less
194 if (*Regs == ARM::CPSR)
200 /// the 's' 16-bit instruction partially update CPSR. Abort the
201 /// transformation to avoid adding false dependency on last CPSR setting
205 /// last instruction that defines the CPSR and the current instruction. If there
207 /// before the CPSR setting instruction anyway.
234 if (Reg == 0 || Reg == ARM::CPSR)
259 // Not predicated, must set CPSR.
261 // Original instruction was not setting CPSR, bu
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H A DARMMCInstLower.cpp71 // Ignore all non-CPSR implicit register operands.
72 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
H A DThumb2ITBlockPass.cpp86 if (Reg == ARM::CPSR)
124 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
H A DARMBaseInstrInfo.cpp514 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
515 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
1580 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1610 // predicated instructions which will be reading CPSR.
1643 // 4: CPSR use.
1684 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1703 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1706 /// This will go away once we can teach tblgen how to set the optional CPSR def
2066 // There are two possible candidates which can be changed to set CPSR:
2085 // Check that CPSR is
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H A DARMFastISel.cpp221 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
234 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
235 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { argument
239 // Look to see if our OptionalDef is defining CPSR or CCR.
243 if (MO.getReg() == ARM::CPSR)
244 *CPSR = true;
267 // CPSR defs that need to be added before the remaining operands. See s_cc_out
280 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
281 bool CPSR local
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H A DARMBaseInstrInfo.h332 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
376 /// CPSR def operand.
H A DARMISelLowering.cpp2929 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
2939 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3051 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3083 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3103 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3446 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
3480 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
5425 .addMBB(exitMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5441 .addMBB(loop1MBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
5545 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
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H A DARMAsmPrinter.cpp1783 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1808 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1828 TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
H A DARMCodeEmitter.cpp778 // Encode S bit if MI modifies CPSR.
803 // Encode S bit if MI modifies CPSR.
996 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
1013 // Encode S bit if MI modifies CPSR.
1314 // Encode S bit if MI modifies CPSR.
H A DARMConstantIslandPass.cpp1789 // If the conditional branch doesn't kill CPSR, then CPSR can be liveout
1791 if (!Br.MI->killsRegister(ARM::CPSR))
H A DARMExpandPseudoInsts.cpp835 .addReg(ARM::CPSR, RegState::Define);
H A DARMLoadStoreOptimizer.cpp520 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
521 // If the instruction has live CPSR def, then it's not safe to fold it
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp1406 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
3437 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
5053 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
6774 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6825 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6832 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6862 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6870 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7057 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7202 Inst.getOperand(4).getReg() == ARM::CPSR) ||
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/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp632 // implicitly set CPSR. Since it's not represented in the encoding, the
633 // auto-generated decoder won't inject the CPSR operand. We need to fix
643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
648 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
712 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
722 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
748 I->setReg(ARM::CPSR);
1107 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1114 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp234 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or
236 return MI.getOperand(Op).getReg() == ARM::CPSR;
560 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) {
/macosx-10.9.5/llvmCore-3425.0.33/lib/Target/ARM/InstPrinter/
H A DARMInstPrinter.cpp717 O << "CPSR";
748 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
749 "Expect ARM CPSR register!");

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