| /macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 24 UsedPhysRegs.resize(TRI.getNumRegs());
25 UsedPhysRegMask.resize(TRI.getNumRegs());
28 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()];
29 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs());
59 if (NewRC->getNumRegs() < MinNumRegs)
309 assert(ReservedRegs.size() == TRI->getNumRegs() &&
|
| H A D | RegisterClassInfo.cpp | 52 CSRNum.resize(TRI->getNumRegs(), 0);
79 unsigned NumRegs = RC->getNumRegs();
|
| H A D | CriticalAntiDepBreaker.cpp | 36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)),
37 KillIndices(TRI->getNumRegs(), 0),
38 DefIndices(TRI->getNumRegs(), 0),
39 KeepRegs(TRI->getNumRegs(), false) {}
46 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) {
116 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
241 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i)
441 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
495 std::vector<unsigned> LastNewReg(TRI->getNumRegs(), 0);
|
| H A D | RegisterScavenging.cpp | 80 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) &&
90 NumPhysRegs = TRI->getNumRegs();
244 BitVector Mask(TRI->getNumRegs());
|
| H A D | ExecutionDepsFix.cpp | 149 : MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
650 assert(NumRegs == RC->getNumRegs() && "Bad regclass");
670 AliasMap.resize(TRI->getNumRegs(), -1);
671 for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
|
| H A D | AggressiveAntiDepBreaker.cpp | 149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
220 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
511 BitVector BV(TRI->getNumRegs(), false);
762 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
|
| H A D | CallingConvLower.cpp | 36 UsedRegs.resize((TRI.getNumRegs()+31)/32);
|
| H A D | PostRASchedulerList.cpp | 202 LiveRegs(TRI->getNumRegs())
492 BitVector killedRegs(TRI->getNumRegs());
|
| H A D | RegAllocPBQP.cpp | 204 for (unsigned Reg = 1, e = tri->getNumRegs(); Reg != e; ++Reg) {
219 BitVector regMaskOverlaps(tri->getNumRegs());
|
| H A D | InterferenceCache.cpp | 33 PhysRegEntries.assign(TRI->getNumRegs(), 0);
|
| H A D | VirtRegMap.cpp | 349 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg)
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/MC/ |
| H A D | MCRegisterInfo.cpp | 39 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/AsmParser/ |
| H A D | MBlazeAsmLexer.cpp | 41 unsigned numRegs = info->getNumRegs();
|
| /macosx-10.10.1/llvmCore-3425.0.34/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 54 /// getNumRegs - Return the number of registers in this class.
56 unsigned getNumRegs() const { return RegsSize; } function in class:llvm::MCRegisterClass
61 assert(i < getNumRegs() && "Register number out of range!");
330 /// getNumRegs - Return the number of registers this target has (useful for
332 unsigned getNumRegs() const {
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmLexer.cpp | 43 unsigned numRegs = info->getNumRegs();
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ |
| H A D | TargetRegisterInfo.cpp | 39 else if (TRI && Reg < TRI->getNumRegs())
128 BitVector Allocatable(getNumRegs());
|
| /macosx-10.10.1/llvmCore-3425.0.34/include/llvm/Target/ |
| H A D | TargetRegisterInfo.h | 63 /// getNumRegs - Return the number of registers in this class.
65 unsigned getNumRegs() const { return MC->getNumRegs(); } function in class:llvm::TargetRegisterClass
194 return OrderFunc ? OrderFunc(MF) : makeArrayRef(begin(), getNumRegs());
418 /// The mask is an array containing (TRI::getNumRegs()+31)/32 entries.
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/ |
| H A D | MBlazeRegisterInfo.cpp | 72 BitVector Reserved(getNumRegs());
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/ |
| H A D | MipsRegisterInfo.cpp | 91 BitVector Reserved(getNumRegs());
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Sparc/ |
| H A D | SparcRegisterInfo.cpp | 43 BitVector Reserved(getNumRegs());
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/ |
| H A D | HexagonCallingConvLower.cpp | 35 UsedRegs.resize((TRI.getNumRegs()+31)/32);
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/ |
| H A D | MSP430RegisterInfo.cpp | 78 BitVector Reserved(getNumRegs());
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/ |
| H A D | NVPTXRegisterInfo.cpp | 274 BitVector Reserved(getNumRegs());
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGFast.cpp | 115 LiveRegDefs.resize(TRI->getNumRegs(), NULL);
116 LiveRegCycles.resize(TRI->getNumRegs(), 0);
|
| /macosx-10.10.1/llvmCore-3425.0.34/lib/MC/MCDisassembler/ |
| H A D | EDDisassembler.cpp | 255 unsigned numRegisters = registerInfo.getNumRegs();
|