1//===-- MSP430RegisterInfo.cpp - MSP430 Register Information --------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the MSP430 implementation of the TargetRegisterInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#define DEBUG_TYPE "msp430-reg-info" 15 16#include "MSP430RegisterInfo.h" 17#include "MSP430.h" 18#include "MSP430MachineFunctionInfo.h" 19#include "MSP430TargetMachine.h" 20#include "llvm/Function.h" 21#include "llvm/CodeGen/MachineFrameInfo.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/Target/TargetMachine.h" 25#include "llvm/Target/TargetOptions.h" 26#include "llvm/ADT/BitVector.h" 27#include "llvm/Support/ErrorHandling.h" 28 29#define GET_REGINFO_TARGET_DESC 30#include "MSP430GenRegisterInfo.inc" 31 32using namespace llvm; 33 34// FIXME: Provide proper call frame setup / destroy opcodes. 35MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm, 36 const TargetInstrInfo &tii) 37 : MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) { 38 StackAlign = TM.getFrameLowering()->getStackAlignment(); 39} 40 41const uint16_t* 42MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { 43 const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering(); 44 const Function* F = MF->getFunction(); 45 static const uint16_t CalleeSavedRegs[] = { 46 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, 47 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, 48 0 49 }; 50 static const uint16_t CalleeSavedRegsFP[] = { 51 MSP430::R5W, MSP430::R6W, MSP430::R7W, 52 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, 53 0 54 }; 55 static const uint16_t CalleeSavedRegsIntr[] = { 56 MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, 57 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, 58 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W, 59 0 60 }; 61 static const uint16_t CalleeSavedRegsIntrFP[] = { 62 MSP430::R5W, MSP430::R6W, MSP430::R7W, 63 MSP430::R8W, MSP430::R9W, MSP430::R10W, MSP430::R11W, 64 MSP430::R12W, MSP430::R13W, MSP430::R14W, MSP430::R15W, 65 0 66 }; 67 68 if (TFI->hasFP(*MF)) 69 return (F->getCallingConv() == CallingConv::MSP430_INTR ? 70 CalleeSavedRegsIntrFP : CalleeSavedRegsFP); 71 else 72 return (F->getCallingConv() == CallingConv::MSP430_INTR ? 73 CalleeSavedRegsIntr : CalleeSavedRegs); 74 75} 76 77BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 78 BitVector Reserved(getNumRegs()); 79 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 80 81 // Mark 4 special registers with subregisters as reserved. 82 Reserved.set(MSP430::PCB); 83 Reserved.set(MSP430::SPB); 84 Reserved.set(MSP430::SRB); 85 Reserved.set(MSP430::CGB); 86 Reserved.set(MSP430::PCW); 87 Reserved.set(MSP430::SPW); 88 Reserved.set(MSP430::SRW); 89 Reserved.set(MSP430::CGW); 90 91 // Mark frame pointer as reserved if needed. 92 if (TFI->hasFP(MF)) 93 Reserved.set(MSP430::FPW); 94 95 return Reserved; 96} 97 98const TargetRegisterClass * 99MSP430RegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind) 100 const { 101 return &MSP430::GR16RegClass; 102} 103 104void MSP430RegisterInfo:: 105eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 106 MachineBasicBlock::iterator I) const { 107 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 108 109 if (!TFI->hasReservedCallFrame(MF)) { 110 // If the stack pointer can be changed after prologue, turn the 111 // adjcallstackup instruction into a 'sub SPW, <amt>' and the 112 // adjcallstackdown instruction into 'add SPW, <amt>' 113 // TODO: consider using push / pop instead of sub + store / add 114 MachineInstr *Old = I; 115 uint64_t Amount = Old->getOperand(0).getImm(); 116 if (Amount != 0) { 117 // We need to keep the stack aligned properly. To do this, we round the 118 // amount of space needed for the outgoing arguments up to the next 119 // alignment boundary. 120 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign; 121 122 MachineInstr *New = 0; 123 if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) { 124 New = BuildMI(MF, Old->getDebugLoc(), 125 TII.get(MSP430::SUB16ri), MSP430::SPW) 126 .addReg(MSP430::SPW).addImm(Amount); 127 } else { 128 assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode()); 129 // factor out the amount the callee already popped. 130 uint64_t CalleeAmt = Old->getOperand(1).getImm(); 131 Amount -= CalleeAmt; 132 if (Amount) 133 New = BuildMI(MF, Old->getDebugLoc(), 134 TII.get(MSP430::ADD16ri), MSP430::SPW) 135 .addReg(MSP430::SPW).addImm(Amount); 136 } 137 138 if (New) { 139 // The SRW implicit def is dead. 140 New->getOperand(3).setIsDead(); 141 142 // Replace the pseudo instruction with a new instruction... 143 MBB.insert(I, New); 144 } 145 } 146 } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) { 147 // If we are performing frame pointer elimination and if the callee pops 148 // something off the stack pointer, add it back. 149 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) { 150 MachineInstr *Old = I; 151 MachineInstr *New = 152 BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri), 153 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt); 154 // The SRW implicit def is dead. 155 New->getOperand(3).setIsDead(); 156 157 MBB.insert(I, New); 158 } 159 } 160 161 MBB.erase(I); 162} 163 164void 165MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, 166 int SPAdj, RegScavenger *RS) const { 167 assert(SPAdj == 0 && "Unexpected"); 168 169 unsigned i = 0; 170 MachineInstr &MI = *II; 171 MachineBasicBlock &MBB = *MI.getParent(); 172 MachineFunction &MF = *MBB.getParent(); 173 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 174 DebugLoc dl = MI.getDebugLoc(); 175 while (!MI.getOperand(i).isFI()) { 176 ++i; 177 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 178 } 179 180 int FrameIndex = MI.getOperand(i).getIndex(); 181 182 unsigned BasePtr = (TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW); 183 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 184 185 // Skip the saved PC 186 Offset += 2; 187 188 if (!TFI->hasFP(MF)) 189 Offset += MF.getFrameInfo()->getStackSize(); 190 else 191 Offset += 2; // Skip the saved FPW 192 193 // Fold imm into offset 194 Offset += MI.getOperand(i+1).getImm(); 195 196 if (MI.getOpcode() == MSP430::ADD16ri) { 197 // This is actually "load effective address" of the stack slot 198 // instruction. We have only two-address instructions, thus we need to 199 // expand it into mov + add 200 201 MI.setDesc(TII.get(MSP430::MOV16rr)); 202 MI.getOperand(i).ChangeToRegister(BasePtr, false); 203 204 if (Offset == 0) 205 return; 206 207 // We need to materialize the offset via add instruction. 208 unsigned DstReg = MI.getOperand(0).getReg(); 209 if (Offset < 0) 210 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) 211 .addReg(DstReg).addImm(-Offset); 212 else 213 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) 214 .addReg(DstReg).addImm(Offset); 215 216 return; 217 } 218 219 MI.getOperand(i).ChangeToRegister(BasePtr, false); 220 MI.getOperand(i+1).ChangeToImmediate(Offset); 221} 222 223void 224MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) 225 const { 226 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 227 228 // Create a frame entry for the FPW register that must be saved. 229 if (TFI->hasFP(MF)) { 230 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(2, -4, true); 231 (void)FrameIdx; 232 assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && 233 "Slot for FPW register must be last in order to be found!"); 234 } 235} 236 237unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const { 238 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); 239 240 return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW; 241} 242