/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/NVPTX/ |
H A D | NVPTXFrameLowering.cpp | 47 NVPTX::VRFrame).addReg(NVPTX::VRFrameLocal); 50 .addReg(NVPTX::VRDepot); 54 NVPTX::VRFrame).addReg(NVPTX::VRFrameLocal); 57 .addReg(NVPTX::VRDepot); 65 .addReg(NVPTX::VRDepot); 69 .addReg(NVPTX::VRDepot);
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H A D | NVPTXInstrInfo.cpp | 43 .addReg(SrcReg, getKillRegState(KillSrc)); 47 .addReg(SrcReg, getKillRegState(KillSrc)); 51 .addReg(SrcReg, getKillRegState(KillSrc)); 55 .addReg(SrcReg, getKillRegState(KillSrc)); 59 .addReg(SrcReg, getKillRegState(KillSrc)); 63 .addReg(SrcReg, getKillRegState(KillSrc)); 67 .addReg(SrcReg, getKillRegState(KillSrc)); 71 .addReg(SrcReg, getKillRegState(KillSrc)); 75 .addReg(SrcReg, getKillRegState(KillSrc)); 79 .addReg(SrcRe [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); 99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); 109 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); 117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) 118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); 127 MIB.addReg(A [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Hexagon/ |
H A D | HexagonExpandPredSpillCode.cpp | 94 .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); 96 HEXAGON_RESERVED_REG_2).addReg(SrcReg); 99 .addReg(HEXAGON_RESERVED_REG_1) 100 .addImm(0).addReg(HEXAGON_RESERVED_REG_2); 103 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); 105 HEXAGON_RESERVED_REG_2).addReg(SrcReg); 108 .addReg(HEXAGON_RESERVED_REG_1) 110 .addReg(HEXAGON_RESERVED_REG_2); 114 HEXAGON_RESERVED_REG_2).addReg(SrcRe [all...] |
H A D | HexagonSplitTFRCondSets.cpp | 107 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 111 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); 127 addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); 132 addReg(MI->getOperand(1).getReg()). 137 addReg(MI->getOperand(1).getReg()). 153 addReg(MI->getOperand(1).getReg()). 158 addReg(M [all...] |
H A D | HexagonRegisterInfo.cpp | 201 dstReg).addReg(FrameReg).addReg(dstReg); 205 dstReg).addReg(FrameReg).addImm(Offset); 230 resReg).addReg(FrameReg).addReg(resReg); 234 resReg).addReg(FrameReg).addImm(Offset); 250 resReg).addReg(FrameReg).addReg(resReg); 256 resReg).addReg(FrameReg).addImm(Offset); 266 dstReg).addReg(FrameRe [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Sparc/ |
H A D | SparcFrameLowering.cpp | 56 .addReg(SP::O6).addImm(NumBytes); 64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); 66 .addReg(SP::O6).addReg(SP::G1); 78 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) 79 .addReg(SP::G0);
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/CellSPU/ |
H A D | SPUFrameLowering.cpp | 126 .addReg(SPU::R1); 130 .addReg(SPU::R1); 132 BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) 139 .addReg(SPU::R1); 143 .addReg(SPU::R2) 144 .addReg(SPU::R1); 146 .addReg(SPU::R1) 147 .addReg(SPU::R2); 149 .addReg(SPU::R2) 152 .addReg(SP [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/ARM/ |
H A D | Thumb2RegisterInfo.cpp | 49 .addReg(DestReg, getDefRegState(true), SubIdx) 50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
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H A D | ARMExpandPseudoInsts.cpp | 391 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 393 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 395 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 397 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 466 MIB.addReg(D0, getUndefRegState(SrcIsUndef)); 468 MIB.addReg(D1, getUndefRegState(SrcIsUndef)); 470 MIB.addReg(D2, getUndefRegState(SrcIsUndef)); 472 MIB.addReg(D3, getUndefRegState(SrcIsUndef)); 522 MIB.addReg(D [all...] |
H A D | Thumb2InstrInfo.cpp | 121 .addReg(SrcReg, getKillRegState(KillSrc))); 143 .addReg(SrcReg, getKillRegState(isKill)) 195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 200 .addReg(DestReg) 202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 209 .addReg(BaseReg, RegState::Kill) 210 .addReg(DestReg, RegState::Kill) 211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 215 .addReg(DestRe [all...] |
H A D | ARMFrameLowering.cpp | 298 .addReg(ARM::SP, RegState::Kill) 308 .addReg(ARM::SP, RegState::Kill)); 311 .addReg(ARM::R4, RegState::Kill) 314 .addReg(ARM::R4, RegState::Kill)); 329 .addReg(ARM::SP) 330 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); 334 .addReg(ARM::SP)); 408 .addReg(ARM::R4)); 414 .addReg(FramePt [all...] |
H A D | ARMLoadStoreOptimizer.cpp | 339 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset) 340 .addImm(Pred).addReg(PredReg).addReg(0); 350 .addReg(Base, getKillRegState(BaseKill)) 351 .addImm(Pred).addReg(PredReg); 353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) 358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); 778 .addReg(Base, getDefRegState(true)) // WB base register 779 .addReg(Base, getKillRegState(BaseKill)) 780 .addImm(Pred).addReg(PredRe [all...] |
H A D | ARMFastISel.cpp | 308 .addReg(Op0, Op0IsKill * RegState::Kill)); 311 .addReg(Op0, Op0IsKill * RegState::Kill)); 314 .addReg(II.ImplicitDefs[0])); 328 .addReg(Op0, Op0IsKill * RegState::Kill) 329 .addReg(Op1, Op1IsKill * RegState::Kill)); 332 .addReg(Op0, Op0IsKill * RegState::Kill) 333 .addReg(Op1, Op1IsKill * RegState::Kill)); 336 .addReg(II.ImplicitDefs[0])); 351 .addReg(Op0, Op0IsKill * RegState::Kill) 352 .addReg(Op [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 138 .addReg(SrcReg) 142 .addReg(SrcReg, RegState::Kill) 147 .addReg(SrcReg) 151 .addReg(SrcReg, RegState::Kill) 156 .addReg(SrcReg) 160 .addReg(SrcReg, RegState::Kill) 164 .addReg(DstReg, RegState::Kill) 333 .addReg(PPC::X31) 335 .addReg(PPC::X1); 339 .addReg(PP [all...] |
H A D | PPCRegisterInfo.cpp | 245 .addReg(StackReg, RegState::Kill) 252 .addReg(TmpReg, RegState::Kill) 255 .addReg(StackReg, RegState::Kill) 256 .addReg(TmpReg); 329 .addReg(PPC::R31) 335 .addReg(PPC::X1); 339 .addReg(PPC::X1); 343 .addReg(PPC::R1); 351 .addReg(Reg, RegState::Kill) 352 .addReg(PP [all...] |
H A D | PPCInstrInfo.cpp | 183 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead)) 184 .addReg(Reg2, getKillRegState(Reg2IsKill)) 185 .addReg(Reg1, getKillRegState(Reg1IsKill)) 397 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 408 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB); 436 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); 438 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); 452 .addReg(SrcReg, 461 .addReg(PP [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/ |
H A D | MipsLongBranch.cpp | 233 MIB.addReg(MO.getReg()); 283 .addReg(Mips::SP).addImm(-8); 284 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 285 .addReg(Mips::SP).addImm(0); 293 .addReg(Mips::AT).addImm(Lo); 295 .addReg(Mips::RA).addReg(Mips::AT); 297 .addReg(Mips::SP).addImm(0); 298 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::JR)).addReg(Mips::AT); 300 .addReg(Mip [all...] |
H A D | Mips16InstrInfo.cpp | 73 MIB.addReg(DestReg, RegState::Define); 76 MIB.addReg(ZeroReg); 79 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 94 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
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H A D | MipsSEInstrInfo.cpp | 145 MIB.addReg(DestReg, RegState::Define); 148 MIB.addReg(ZeroReg); 151 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 177 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 261 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 265 BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg); 296 BuildMI(MBB, II, DL, get(Inst->Opc), ATReg).addReg(ZEROReg) 301 BuildMI(MBB, II, DL, get(Inst->Opc), ATReg).addReg(ATReg) 323 BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mip [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 230 .addReg(FrameReg) 231 .addReg(ScratchReg, RegState::Kill); 235 .addReg(Reg, getKillRegState(isKill)) 236 .addReg(FrameReg) 237 .addReg(ScratchReg, RegState::Kill); 241 .addReg(FrameReg) 242 .addReg(ScratchReg, RegState::Kill); 251 .addReg(FrameReg) 256 .addReg(Reg, getKillRegState(isKill)) 257 .addReg(FrameRe [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/ |
H A D | MSP430FrameLowering.cpp | 67 .addReg(MSP430::FPW, RegState::Kill); 71 .addReg(MSP430::SPW); 99 .addReg(MSP430::SPW).addImm(NumBytes); 157 TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW); 162 .addReg(MSP430::SPW).addImm(CSSize); 171 .addReg(MSP430::SPW).addImm(NumBytes); 200 .addReg(Reg, RegState::Kill);
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/ |
H A D | MBlazeISelLowering.cpp | 296 .addReg(MI->getOperand(2).getReg()) 301 .addReg(MI->getOperand(1).getReg()) 305 .addReg(IAMT) 311 .addReg(IVAL).addMBB(MBB) 312 .addReg(NDST).addMBB(loop); 317 .addReg(IAMT).addMBB(MBB) 318 .addReg(NAMT).addMBB(loop); 321 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST); 323 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DS [all...] |
H A D | MBlazeFrameLowering.cpp | 273 .addReg(MBlaze::RMSR); 280 .addReg(MBlaze::R11); 367 .addReg(MBlaze::R1).addImm(-StackSize); 372 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset); 378 .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset); 382 .addReg(MBlaze::R1).addReg(MBlaze::R0); 406 .addReg(MBlaz [all...] |
/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/SelectionDAG/ |
H A D | FastISel.cpp | 625 .addReg(Reg, RegState::Debug).addImm(Offset) 642 .addReg(0U).addImm(DI->getOffset()) 659 .addReg(Reg, RegState::Debug).addImm(DI->getOffset()) 765 ResultReg).addReg(Op0); 1181 .addReg(Op0, Op0IsKill * RegState::Kill); 1184 .addReg(Op0, Op0IsKill * RegState::Kill); 1186 ResultReg).addReg(II.ImplicitDefs[0]); 1201 .addReg(Op0, Op0IsKill * RegState::Kill) 1202 .addReg(Op1, Op1IsKill * RegState::Kill); 1205 .addReg(Op [all...] |