Lines Matching refs:addReg
339 .addReg(Base, getKillRegState(BaseKill)).addImm(Offset)
340 .addImm(Pred).addReg(PredReg).addReg(0);
350 .addReg(Base, getKillRegState(BaseKill))
351 .addImm(Pred).addReg(PredReg);
353 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef)
358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine);
778 .addReg(Base, getDefRegState(true)) // WB base register
779 .addReg(Base, getKillRegState(BaseKill))
780 .addImm(Pred).addReg(PredReg);
931 .addReg(Base, getDefRegState(true)) // WB base register
932 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
933 .addImm(Pred).addReg(PredReg)
934 .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
942 .addReg(Base, RegState::Define)
943 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
947 .addReg(Base, RegState::Define)
948 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
954 .addReg(Base, RegState::Define)
955 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
966 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
967 .addReg(Base).addReg(0).addImm(Offset).addImm(Pred).addReg(PredReg);
972 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
973 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
1084 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
1085 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1086 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1090 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
1091 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1092 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1140 .addReg(BaseReg, getKillRegState(BaseKill))
1141 .addImm(Pred).addReg(PredReg)
1142 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1143 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill));
1147 .addReg(BaseReg, getKillRegState(BaseKill))
1148 .addImm(Pred).addReg(PredReg)
1149 .addReg(EvenReg,
1151 .addReg(OddReg,
1745 .addReg(EvenReg, RegState::Define)
1746 .addReg(OddReg, RegState::Define)
1747 .addReg(BaseReg);
1752 MIB.addReg(0);
1753 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1759 .addReg(EvenReg)
1760 .addReg(OddReg)
1761 .addReg(BaseReg);
1766 MIB.addReg(0);
1767 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);