1//===-- PPCInstrInfo.cpp - PowerPC Instruction Information ----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPC.h"
16#include "PPCInstrBuilder.h"
17#include "PPCMachineFunctionInfo.h"
18#include "PPCTargetMachine.h"
19#include "PPCHazardRecognizers.h"
20#include "MCTargetDesc/PPCPredicates.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/MC/MCAsmInfo.h"
27#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/ErrorHandling.h"
29#include "llvm/Support/TargetRegistry.h"
30#include "llvm/Support/raw_ostream.h"
31#include "llvm/ADT/STLExtras.h"
32
33#define GET_INSTRINFO_CTOR
34#include "PPCGenInstrInfo.inc"
35
36namespace llvm {
37extern cl::opt<bool> DisablePPC32RS;
38extern cl::opt<bool> DisablePPC64RS;
39}
40
41using namespace llvm;
42
43static cl::
44opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
45            cl::desc("Disable analysis for CTR loops"));
46
47PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
48  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
49    TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
50
51/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
52/// this target when scheduling the DAG.
53ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetHazardRecognizer(
54  const TargetMachine *TM,
55  const ScheduleDAG *DAG) const {
56  unsigned Directive = TM->getSubtarget<PPCSubtarget>().getDarwinDirective();
57  if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 ||
58      Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) {
59    const InstrItineraryData *II = TM->getInstrItineraryData();
60    return new PPCScoreboardHazardRecognizer(II, DAG);
61  }
62
63  return TargetInstrInfoImpl::CreateTargetHazardRecognizer(TM, DAG);
64}
65
66/// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
67/// to use for this target when scheduling the DAG.
68ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
69  const InstrItineraryData *II,
70  const ScheduleDAG *DAG) const {
71  unsigned Directive = TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
72
73  // Most subtargets use a PPC970 recognizer.
74  if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
75      Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
76    const TargetInstrInfo *TII = TM.getInstrInfo();
77    assert(TII && "No InstrInfo?");
78
79    return new PPCHazardRecognizer970(*TII);
80  }
81
82  return new PPCScoreboardHazardRecognizer(II, DAG);
83}
84
85// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
86bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
87                                         unsigned &SrcReg, unsigned &DstReg,
88                                         unsigned &SubIdx) const {
89  switch (MI.getOpcode()) {
90  default: return false;
91  case PPC::EXTSW:
92  case PPC::EXTSW_32_64:
93    SrcReg = MI.getOperand(1).getReg();
94    DstReg = MI.getOperand(0).getReg();
95    SubIdx = PPC::sub_32;
96    return true;
97  }
98}
99
100unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
101                                           int &FrameIndex) const {
102  switch (MI->getOpcode()) {
103  default: break;
104  case PPC::LD:
105  case PPC::LWZ:
106  case PPC::LFS:
107  case PPC::LFD:
108    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
109        MI->getOperand(2).isFI()) {
110      FrameIndex = MI->getOperand(2).getIndex();
111      return MI->getOperand(0).getReg();
112    }
113    break;
114  }
115  return 0;
116}
117
118unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
119                                          int &FrameIndex) const {
120  switch (MI->getOpcode()) {
121  default: break;
122  case PPC::STD:
123  case PPC::STW:
124  case PPC::STFS:
125  case PPC::STFD:
126    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
127        MI->getOperand(2).isFI()) {
128      FrameIndex = MI->getOperand(2).getIndex();
129      return MI->getOperand(0).getReg();
130    }
131    break;
132  }
133  return 0;
134}
135
136// commuteInstruction - We can commute rlwimi instructions, but only if the
137// rotate amt is zero.  We also have to munge the immediates a bit.
138MachineInstr *
139PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
140  MachineFunction &MF = *MI->getParent()->getParent();
141
142  // Normal instructions can be commuted the obvious way.
143  if (MI->getOpcode() != PPC::RLWIMI)
144    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
145
146  // Cannot commute if it has a non-zero rotate count.
147  if (MI->getOperand(3).getImm() != 0)
148    return 0;
149
150  // If we have a zero rotate count, we have:
151  //   M = mask(MB,ME)
152  //   Op0 = (Op1 & ~M) | (Op2 & M)
153  // Change this to:
154  //   M = mask((ME+1)&31, (MB-1)&31)
155  //   Op0 = (Op2 & ~M) | (Op1 & M)
156
157  // Swap op1/op2
158  unsigned Reg0 = MI->getOperand(0).getReg();
159  unsigned Reg1 = MI->getOperand(1).getReg();
160  unsigned Reg2 = MI->getOperand(2).getReg();
161  bool Reg1IsKill = MI->getOperand(1).isKill();
162  bool Reg2IsKill = MI->getOperand(2).isKill();
163  bool ChangeReg0 = false;
164  // If machine instrs are no longer in two-address forms, update
165  // destination register as well.
166  if (Reg0 == Reg1) {
167    // Must be two address instruction!
168    assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) &&
169           "Expecting a two-address instruction!");
170    Reg2IsKill = false;
171    ChangeReg0 = true;
172  }
173
174  // Masks.
175  unsigned MB = MI->getOperand(4).getImm();
176  unsigned ME = MI->getOperand(5).getImm();
177
178  if (NewMI) {
179    // Create a new instruction.
180    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
181    bool Reg0IsDead = MI->getOperand(0).isDead();
182    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
183      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
184      .addReg(Reg2, getKillRegState(Reg2IsKill))
185      .addReg(Reg1, getKillRegState(Reg1IsKill))
186      .addImm((ME+1) & 31)
187      .addImm((MB-1) & 31);
188  }
189
190  if (ChangeReg0)
191    MI->getOperand(0).setReg(Reg2);
192  MI->getOperand(2).setReg(Reg1);
193  MI->getOperand(1).setReg(Reg2);
194  MI->getOperand(2).setIsKill(Reg1IsKill);
195  MI->getOperand(1).setIsKill(Reg2IsKill);
196
197  // Swap the mask around.
198  MI->getOperand(4).setImm((ME+1) & 31);
199  MI->getOperand(5).setImm((MB-1) & 31);
200  return MI;
201}
202
203void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
204                              MachineBasicBlock::iterator MI) const {
205  DebugLoc DL;
206  BuildMI(MBB, MI, DL, get(PPC::NOP));
207}
208
209
210// Branch analysis.
211// Note: If the condition register is set to CTR or CTR8 then this is a
212// BDNZ (imm == 1) or BDZ (imm == 0) branch.
213bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
214                                 MachineBasicBlock *&FBB,
215                                 SmallVectorImpl<MachineOperand> &Cond,
216                                 bool AllowModify) const {
217  bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
218
219  // If the block has no terminators, it just falls into the block after it.
220  MachineBasicBlock::iterator I = MBB.end();
221  if (I == MBB.begin())
222    return false;
223  --I;
224  while (I->isDebugValue()) {
225    if (I == MBB.begin())
226      return false;
227    --I;
228  }
229  if (!isUnpredicatedTerminator(I))
230    return false;
231
232  // Get the last instruction in the block.
233  MachineInstr *LastInst = I;
234
235  // If there is only one terminator instruction, process it.
236  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
237    if (LastInst->getOpcode() == PPC::B) {
238      if (!LastInst->getOperand(0).isMBB())
239        return true;
240      TBB = LastInst->getOperand(0).getMBB();
241      return false;
242    } else if (LastInst->getOpcode() == PPC::BCC) {
243      if (!LastInst->getOperand(2).isMBB())
244        return true;
245      // Block ends with fall-through condbranch.
246      TBB = LastInst->getOperand(2).getMBB();
247      Cond.push_back(LastInst->getOperand(0));
248      Cond.push_back(LastInst->getOperand(1));
249      return false;
250    } else if (LastInst->getOpcode() == PPC::BDNZ8 ||
251               LastInst->getOpcode() == PPC::BDNZ) {
252      if (!LastInst->getOperand(0).isMBB())
253        return true;
254      if (DisableCTRLoopAnal)
255        return true;
256      TBB = LastInst->getOperand(0).getMBB();
257      Cond.push_back(MachineOperand::CreateImm(1));
258      Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
259                                               true));
260      return false;
261    } else if (LastInst->getOpcode() == PPC::BDZ8 ||
262               LastInst->getOpcode() == PPC::BDZ) {
263      if (!LastInst->getOperand(0).isMBB())
264        return true;
265      if (DisableCTRLoopAnal)
266        return true;
267      TBB = LastInst->getOperand(0).getMBB();
268      Cond.push_back(MachineOperand::CreateImm(0));
269      Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
270                                               true));
271      return false;
272    }
273
274    // Otherwise, don't know what this is.
275    return true;
276  }
277
278  // Get the instruction before it if it's a terminator.
279  MachineInstr *SecondLastInst = I;
280
281  // If there are three terminators, we don't know what sort of block this is.
282  if (SecondLastInst && I != MBB.begin() &&
283      isUnpredicatedTerminator(--I))
284    return true;
285
286  // If the block ends with PPC::B and PPC:BCC, handle it.
287  if (SecondLastInst->getOpcode() == PPC::BCC &&
288      LastInst->getOpcode() == PPC::B) {
289    if (!SecondLastInst->getOperand(2).isMBB() ||
290        !LastInst->getOperand(0).isMBB())
291      return true;
292    TBB =  SecondLastInst->getOperand(2).getMBB();
293    Cond.push_back(SecondLastInst->getOperand(0));
294    Cond.push_back(SecondLastInst->getOperand(1));
295    FBB = LastInst->getOperand(0).getMBB();
296    return false;
297  } else if ((SecondLastInst->getOpcode() == PPC::BDNZ8 ||
298              SecondLastInst->getOpcode() == PPC::BDNZ) &&
299      LastInst->getOpcode() == PPC::B) {
300    if (!SecondLastInst->getOperand(0).isMBB() ||
301        !LastInst->getOperand(0).isMBB())
302      return true;
303    if (DisableCTRLoopAnal)
304      return true;
305    TBB = SecondLastInst->getOperand(0).getMBB();
306    Cond.push_back(MachineOperand::CreateImm(1));
307    Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
308                                             true));
309    FBB = LastInst->getOperand(0).getMBB();
310    return false;
311  } else if ((SecondLastInst->getOpcode() == PPC::BDZ8 ||
312              SecondLastInst->getOpcode() == PPC::BDZ) &&
313      LastInst->getOpcode() == PPC::B) {
314    if (!SecondLastInst->getOperand(0).isMBB() ||
315        !LastInst->getOperand(0).isMBB())
316      return true;
317    if (DisableCTRLoopAnal)
318      return true;
319    TBB = SecondLastInst->getOperand(0).getMBB();
320    Cond.push_back(MachineOperand::CreateImm(0));
321    Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
322                                             true));
323    FBB = LastInst->getOperand(0).getMBB();
324    return false;
325  }
326
327  // If the block ends with two PPC:Bs, handle it.  The second one is not
328  // executed, so remove it.
329  if (SecondLastInst->getOpcode() == PPC::B &&
330      LastInst->getOpcode() == PPC::B) {
331    if (!SecondLastInst->getOperand(0).isMBB())
332      return true;
333    TBB = SecondLastInst->getOperand(0).getMBB();
334    I = LastInst;
335    if (AllowModify)
336      I->eraseFromParent();
337    return false;
338  }
339
340  // Otherwise, can't handle this.
341  return true;
342}
343
344unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
345  MachineBasicBlock::iterator I = MBB.end();
346  if (I == MBB.begin()) return 0;
347  --I;
348  while (I->isDebugValue()) {
349    if (I == MBB.begin())
350      return 0;
351    --I;
352  }
353  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC &&
354      I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
355      I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
356    return 0;
357
358  // Remove the branch.
359  I->eraseFromParent();
360
361  I = MBB.end();
362
363  if (I == MBB.begin()) return 1;
364  --I;
365  if (I->getOpcode() != PPC::BCC &&
366      I->getOpcode() != PPC::BDNZ8 && I->getOpcode() != PPC::BDNZ &&
367      I->getOpcode() != PPC::BDZ8  && I->getOpcode() != PPC::BDZ)
368    return 1;
369
370  // Remove the branch.
371  I->eraseFromParent();
372  return 2;
373}
374
375unsigned
376PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
377                           MachineBasicBlock *FBB,
378                           const SmallVectorImpl<MachineOperand> &Cond,
379                           DebugLoc DL) const {
380  // Shouldn't be a fall through.
381  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
382  assert((Cond.size() == 2 || Cond.size() == 0) &&
383         "PPC branch conditions have two components!");
384
385  bool isPPC64 = TM.getSubtargetImpl()->isPPC64();
386
387  // One-way branch.
388  if (FBB == 0) {
389    if (Cond.empty())   // Unconditional branch
390      BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
391    else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
392      BuildMI(&MBB, DL, get(Cond[0].getImm() ?
393                              (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
394                              (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
395    else                // Conditional branch
396      BuildMI(&MBB, DL, get(PPC::BCC))
397        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
398    return 1;
399  }
400
401  // Two-way Conditional Branch.
402  if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
403    BuildMI(&MBB, DL, get(Cond[0].getImm() ?
404                            (isPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
405                            (isPPC64 ? PPC::BDZ8  : PPC::BDZ))).addMBB(TBB);
406  else
407    BuildMI(&MBB, DL, get(PPC::BCC))
408      .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
409  BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
410  return 2;
411}
412
413void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
414                               MachineBasicBlock::iterator I, DebugLoc DL,
415                               unsigned DestReg, unsigned SrcReg,
416                               bool KillSrc) const {
417  unsigned Opc;
418  if (PPC::GPRCRegClass.contains(DestReg, SrcReg))
419    Opc = PPC::OR;
420  else if (PPC::G8RCRegClass.contains(DestReg, SrcReg))
421    Opc = PPC::OR8;
422  else if (PPC::F4RCRegClass.contains(DestReg, SrcReg))
423    Opc = PPC::FMR;
424  else if (PPC::CRRCRegClass.contains(DestReg, SrcReg))
425    Opc = PPC::MCRF;
426  else if (PPC::VRRCRegClass.contains(DestReg, SrcReg))
427    Opc = PPC::VOR;
428  else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg))
429    Opc = PPC::CROR;
430  else
431    llvm_unreachable("Impossible reg-to-reg copy");
432
433  const MCInstrDesc &MCID = get(Opc);
434  if (MCID.getNumOperands() == 3)
435    BuildMI(MBB, I, DL, MCID, DestReg)
436      .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
437  else
438    BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
439}
440
441// This function returns true if a CR spill is necessary and false otherwise.
442bool
443PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
444                                  unsigned SrcReg, bool isKill,
445                                  int FrameIdx,
446                                  const TargetRegisterClass *RC,
447                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
448  DebugLoc DL;
449  if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
450    if (SrcReg != PPC::LR) {
451      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
452                                         .addReg(SrcReg,
453                                                 getKillRegState(isKill)),
454                                         FrameIdx));
455    } else {
456      // FIXME: this spills LR immediately to memory in one step.  To do this,
457      // we use R11, which we know cannot be used in the prolog/epilog.  This is
458      // a hack.
459      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
460      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
461                                         .addReg(PPC::R11,
462                                                 getKillRegState(isKill)),
463                                         FrameIdx));
464    }
465  } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
466    if (SrcReg != PPC::LR8) {
467      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
468                                         .addReg(SrcReg,
469                                                 getKillRegState(isKill)),
470                                         FrameIdx));
471    } else {
472      // FIXME: this spills LR immediately to memory in one step.  To do this,
473      // we use X11, which we know cannot be used in the prolog/epilog.  This is
474      // a hack.
475      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
476      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
477                                         .addReg(PPC::X11,
478                                                 getKillRegState(isKill)),
479                                         FrameIdx));
480    }
481  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
482    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
483                                       .addReg(SrcReg,
484                                               getKillRegState(isKill)),
485                                       FrameIdx));
486  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
487    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
488                                       .addReg(SrcReg,
489                                               getKillRegState(isKill)),
490                                       FrameIdx));
491  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
492    if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
493        (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
494      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
495                                         .addReg(SrcReg,
496                                                 getKillRegState(isKill)),
497                                         FrameIdx));
498      return true;
499    } else {
500      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
501      // it's possible for the stack frame to be so big the save location is
502      // out of range of immediate offsets, necessitating another register.
503      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
504      // at the moment.
505
506      bool is64Bit = TM.getSubtargetImpl()->isPPC64();
507      // We need to store the CR in the low 4-bits of the saved value.  First,
508      // issue a MFCR to save all of the CRBits.
509      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
510                              (is64Bit ? PPC::X2 : PPC::R2) :
511                              (is64Bit ? PPC::X0 : PPC::R0);
512      NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::MFCR8pseud :
513                                             PPC::MFCRpseud), ScratchReg)
514                               .addReg(SrcReg, getKillRegState(isKill)));
515
516      // If the saved register wasn't CR0, shift the bits left so that they are
517      // in CR0's slot.
518      if (SrcReg != PPC::CR0) {
519        unsigned ShiftBits = getPPCRegisterNumbering(SrcReg)*4;
520        // rlwinm scratch, scratch, ShiftBits, 0, 31.
521        NewMIs.push_back(BuildMI(MF, DL, get(is64Bit ? PPC::RLWINM8 :
522                           PPC::RLWINM), ScratchReg)
523                       .addReg(ScratchReg).addImm(ShiftBits)
524                       .addImm(0).addImm(31));
525      }
526
527      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(is64Bit ?
528                                           PPC::STW8 : PPC::STW))
529                                         .addReg(ScratchReg,
530                                                 getKillRegState(isKill)),
531                                         FrameIdx));
532    }
533  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
534    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
535    // backend currently only uses CR1EQ as an individual bit, this should
536    // not cause any bug. If we need other uses of CR bits, the following
537    // code may be invalid.
538    unsigned Reg = 0;
539    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
540        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
541      Reg = PPC::CR0;
542    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
543             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
544      Reg = PPC::CR1;
545    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
546             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
547      Reg = PPC::CR2;
548    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
549             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
550      Reg = PPC::CR3;
551    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
552             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
553      Reg = PPC::CR4;
554    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
555             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
556      Reg = PPC::CR5;
557    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
558             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
559      Reg = PPC::CR6;
560    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
561             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
562      Reg = PPC::CR7;
563
564    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
565                               &PPC::CRRCRegClass, NewMIs);
566
567  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
568    // We don't have indexed addressing for vector loads.  Emit:
569    // R0 = ADDI FI#
570    // STVX VAL, 0, R0
571    //
572    // FIXME: We use R0 here, because it isn't available for RA.
573    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
574                                       FrameIdx, 0, 0));
575    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
576                     .addReg(SrcReg, getKillRegState(isKill))
577                     .addReg(PPC::R0)
578                     .addReg(PPC::R0));
579  } else {
580    llvm_unreachable("Unknown regclass!");
581  }
582
583  return false;
584}
585
586void
587PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
588                                  MachineBasicBlock::iterator MI,
589                                  unsigned SrcReg, bool isKill, int FrameIdx,
590                                  const TargetRegisterClass *RC,
591                                  const TargetRegisterInfo *TRI) const {
592  MachineFunction &MF = *MBB.getParent();
593  SmallVector<MachineInstr*, 4> NewMIs;
594
595  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
596    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
597    FuncInfo->setSpillsCR();
598  }
599
600  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
601    MBB.insert(MI, NewMIs[i]);
602
603  const MachineFrameInfo &MFI = *MF.getFrameInfo();
604  MachineMemOperand *MMO =
605    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
606                            MachineMemOperand::MOStore,
607                            MFI.getObjectSize(FrameIdx),
608                            MFI.getObjectAlignment(FrameIdx));
609  NewMIs.back()->addMemOperand(MF, MMO);
610}
611
612bool
613PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
614                                   unsigned DestReg, int FrameIdx,
615                                   const TargetRegisterClass *RC,
616                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
617  if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
618    if (DestReg != PPC::LR) {
619      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
620                                                 DestReg), FrameIdx));
621    } else {
622      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
623                                                 PPC::R11), FrameIdx));
624      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
625    }
626  } else if (PPC::G8RCRegClass.hasSubClassEq(RC)) {
627    if (DestReg != PPC::LR8) {
628      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
629                                         FrameIdx));
630    } else {
631      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
632                                                 PPC::X11), FrameIdx));
633      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::X11));
634    }
635  } else if (PPC::F8RCRegClass.hasSubClassEq(RC)) {
636    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
637                                       FrameIdx));
638  } else if (PPC::F4RCRegClass.hasSubClassEq(RC)) {
639    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
640                                       FrameIdx));
641  } else if (PPC::CRRCRegClass.hasSubClassEq(RC)) {
642    if ((!DisablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
643        (!DisablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
644      NewMIs.push_back(addFrameReference(BuildMI(MF, DL,
645                                                 get(PPC::RESTORE_CR), DestReg)
646                                         , FrameIdx));
647      return true;
648    } else {
649      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
650      // it's possible for the stack frame to be so big the save location is
651      // out of range of immediate offsets, necessitating another register.
652      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
653      // at the moment.
654      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
655                                                            PPC::R2 : PPC::R0;
656      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
657                                         ScratchReg), FrameIdx));
658
659      // If the reloaded register isn't CR0, shift the bits right so that they are
660      // in the right CR's slot.
661      if (DestReg != PPC::CR0) {
662        unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
663        // rlwinm r11, r11, 32-ShiftBits, 0, 31.
664        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
665                      .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
666                      .addImm(31));
667      }
668
669      NewMIs.push_back(BuildMI(MF, DL, get(TM.getSubtargetImpl()->isPPC64() ?
670                         PPC::MTCRF8 : PPC::MTCRF), DestReg)
671                       .addReg(ScratchReg));
672    }
673  } else if (PPC::CRBITRCRegClass.hasSubClassEq(RC)) {
674
675    unsigned Reg = 0;
676    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
677        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
678      Reg = PPC::CR0;
679    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
680             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
681      Reg = PPC::CR1;
682    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
683             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
684      Reg = PPC::CR2;
685    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
686             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
687      Reg = PPC::CR3;
688    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
689             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
690      Reg = PPC::CR4;
691    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
692             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
693      Reg = PPC::CR5;
694    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
695             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
696      Reg = PPC::CR6;
697    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
698             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
699      Reg = PPC::CR7;
700
701    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
702                                &PPC::CRRCRegClass, NewMIs);
703
704  } else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
705    // We don't have indexed addressing for vector loads.  Emit:
706    // R0 = ADDI FI#
707    // Dest = LVX 0, R0
708    //
709    // FIXME: We use R0 here, because it isn't available for RA.
710    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
711                                       FrameIdx, 0, 0));
712    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
713                     .addReg(PPC::R0));
714  } else {
715    llvm_unreachable("Unknown regclass!");
716  }
717
718  return false;
719}
720
721void
722PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
723                                   MachineBasicBlock::iterator MI,
724                                   unsigned DestReg, int FrameIdx,
725                                   const TargetRegisterClass *RC,
726                                   const TargetRegisterInfo *TRI) const {
727  MachineFunction &MF = *MBB.getParent();
728  SmallVector<MachineInstr*, 4> NewMIs;
729  DebugLoc DL;
730  if (MI != MBB.end()) DL = MI->getDebugLoc();
731  if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs)) {
732    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
733    FuncInfo->setSpillsCR();
734  }
735  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
736    MBB.insert(MI, NewMIs[i]);
737
738  const MachineFrameInfo &MFI = *MF.getFrameInfo();
739  MachineMemOperand *MMO =
740    MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
741                            MachineMemOperand::MOLoad,
742                            MFI.getObjectSize(FrameIdx),
743                            MFI.getObjectAlignment(FrameIdx));
744  NewMIs.back()->addMemOperand(MF, MMO);
745}
746
747MachineInstr*
748PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
749                                       int FrameIx, uint64_t Offset,
750                                       const MDNode *MDPtr,
751                                       DebugLoc DL) const {
752  MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
753  addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
754  return &*MIB;
755}
756
757bool PPCInstrInfo::
758ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
759  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
760  if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
761    Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
762  else
763    // Leave the CR# the same, but invert the condition.
764    Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
765  return false;
766}
767
768/// GetInstSize - Return the number of bytes of code the specified
769/// instruction may be.  This returns the maximum number of bytes.
770///
771unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
772  switch (MI->getOpcode()) {
773  case PPC::INLINEASM: {       // Inline Asm: Variable size.
774    const MachineFunction *MF = MI->getParent()->getParent();
775    const char *AsmStr = MI->getOperand(0).getSymbolName();
776    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
777  }
778  case PPC::PROLOG_LABEL:
779  case PPC::EH_LABEL:
780  case PPC::GC_LABEL:
781  case PPC::DBG_VALUE:
782    return 0;
783  case PPC::BL8_NOP_ELF:
784  case PPC::BLA8_NOP_ELF:
785    return 8;
786  default:
787    return 4; // PowerPC instructions are all 4 bytes
788  }
789}
790