Searched refs:RS (Results 1 - 25 of 87) sorted by relevance

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/macosx-10.10.1/cxxfilt-11/cxxfilt/include/opcode/
H A Di960.h85 * RS: global, local, or (if target allows) special-function register only
109 #define RS OP( 0, 0, 0, SFR ) macro
232 { 0x30000000, "bbc", I_BASE, COBR, 3, { RL, RS, 0 } },
233 { 0x31000000, "cmpobg", I_BASE, COBR, 3, { RL, RS, 0 } },
234 { 0x32000000, "cmpobe", I_BASE, COBR, 3, { RL, RS, 0 } },
235 { 0x33000000, "cmpobge", I_BASE, COBR, 3, { RL, RS, 0 } },
236 { 0x34000000, "cmpobl", I_BASE, COBR, 3, { RL, RS, 0 } },
237 { 0x35000000, "cmpobne", I_BASE, COBR, 3, { RL, RS, 0 } },
238 { 0x36000000, "cmpoble", I_BASE, COBR, 3, { RL, RS, 0 } },
239 { 0x37000000, "bbs", I_BASE, COBR, 3, { RL, RS,
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/PowerPC/
H A DPPCRegisterInfo.h64 int SPAdj, RegScavenger *RS) const;
66 int SPAdj, RegScavenger *RS) const;
68 int SPAdj, RegScavenger *RS) const;
72 int SPAdj, RegScavenger *RS = NULL) const;
H A DPPCJITInfo.cpp27 #define BUILD_ADDIS(RD,RS,IMM16) \
28 ((15 << 26) | ((RD) << 21) | ((RS) << 16) | ((IMM16) & 65535))
29 #define BUILD_ORI(RD,RS,UIMM16) \
30 ((24 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
31 #define BUILD_ORIS(RD,RS,UIMM16) \
32 ((25 << 26) | ((RS) << 21) | ((RD) << 16) | ((UIMM16) & 65535))
33 #define BUILD_RLDICR(RD,RS,SH,ME) \
34 ((30 << 26) | ((RS) << 21) | ((RD) << 16) | (((SH) & 31) << 11) | \
36 #define BUILD_MTSPR(RS,SPR) \
37 ((31 << 26) | ((RS) << 2
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/macosx-10.10.1/ruby-106/ruby/lib/
H A DEnglish.rb28 # $RS:: $/
78 alias $RS $/
/macosx-10.10.1/cxxfilt-11/cxxfilt/opcodes/
H A Dppc-opc.c412 the RS field in the instruction. This is used for extended
417 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
420 #define RS RBS + 1
421 #define RT RS
425 /* The RS field of the DS form stq instruction, which has special
427 #define RSQ RS + 1
435 /* The RS field of the tlbwe instruction, which is optional. */
1364 the RS field in the instruction. This is used for extended
1402 /* The RS field of the DS form stq instruction, which has special
2086 { "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, R
418 #define RS macro
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H A Diq2000-opc.c260 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
272 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
284 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
296 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
308 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
320 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
332 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
344 { { MNEM, ' ', OP (RT), ',', OP (RS), ',', OP (LO16), 0 } },
356 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', OP (RT), 0 } },
368 { { MNEM, ' ', OP (RD), ',', OP (RS), ',', O
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H A Dxstormy16-opc.c226 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ')', 0 } },
232 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ')', 0 } },
238 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ')', 0 } },
244 { { MNEM, OP (WS2), ' ', '(', OP (RS), ')', ',', OP (RDM), 0 } },
250 { { MNEM, OP (WS2), ' ', '(', OP (RS), '+', '+', ')', ',', OP (RDM), 0 } },
256 { { MNEM, OP (WS2), ' ', '(', '-', '-', OP (RS), ')', ',', OP (RDM), 0 } },
262 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), ',', OP (IMM12), ')', 0 } },
268 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
274 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
280 { { MNEM, OP (WS2), ' ', '(', OP (RS), ',', O
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H A Dh8500-opc.h145 #define RS 39 macro
199 {6,'-','X','!','!',O_XCH|O_WORD,"xch.w",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}},
200 {7,'-','X','!','!',O_XCH|O_UNSZ,"xch",2,{RS,RD},2, {{0xa8,0xf8,RS },{0x90,0xf8,RD }}},
474 {44,'-','B','S','S',O_SCB_NE|O_UNSZ,"scb/ne",2,{RS,PCREL8},3, {{0x06,0xff,0 },{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}},
475 {45,'-','B','S','S',O_SCB_F|O_UNSZ,"scb/f",2,{RS,PCREL8},3, {{0x01,0xff,0 },{0xb8,0xf8,RS },{0x00,0x00,PCREL8 }}},
476 {46,'-','B','S','S',O_SCB_EQ|O_UNSZ,"scb/eq",2,{RS,PCREL
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/macosx-10.10.1/ntp-92/include/
H A Dascii.h71 #define RS 30 macro
/macosx-10.10.1/tcl-105/tcl_ext/tcllib/tcllib/modules/doctools2idx/
H A Dexport_nroff.tcl93 .RS
101 .RS
162 proc .RS {} {
164 text::+ .RS
/macosx-10.10.1/tcl-105/tcl_ext/tcllib/tcllib/modules/doctools2toc/
H A Dexport_nroff.tcl99 .RS
167 proc .RS {} {
169 text::+ .RS
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/CellSPU/
H A DSPUFrameLowering.h44 RegScavenger *RS = NULL) const;
H A DSPURegisterInfo.h80 RegScavenger *RS = NULL) const;
99 RegScavenger *RS,
H A DSPURegisterInfo.cpp256 RegScavenger *RS) const
300 unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj);
347 RegScavenger *RS,
351 assert(RS && "Register scavenging must be on");
352 unsigned Reg = RS->FindUnusedReg(RC);
354 Reg = RS->scavengeRegister(RC, II, SPAdj);
346 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) const argument
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MBlaze/
H A DMBlazeFrameLowering.h47 RegScavenger *RS) const;
H A DMBlazeRegisterInfo.h59 int SPAdj, RegScavenger *RS = NULL) const;
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/
H A DMips16FrameLowering.h43 RegScavenger *RS) const;
H A DMipsSEFrameLowering.h39 RegScavenger *RS) const;
H A DMipsRegisterInfo.h56 int SPAdj, RegScavenger *RS = NULL) const;
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Sparc/
H A DSparcRegisterInfo.h44 int SPAdj, RegScavenger *RS = NULL) const;
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/XCore/
H A DXCoreFrameLowering.h45 RegScavenger *RS = NULL) const;
/macosx-10.10.1/apache-793/httpd/build/
H A Dbuild-modules-c.awk16 RS = " "
/macosx-10.10.1/efax-38/efax/
H A Defaxmsg.h15 SYN, ETB, CAN, EM, SUB, ESC, FS, GS, RS, US } ; enumerator in enum:cchar
/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/MSP430/
H A DMSP430RegisterInfo.h50 int SPAdj, RegScavenger *RS = NULL) const;
/macosx-10.10.1/llvmCore-3425.0.34/lib/CodeGen/
H A DPrologEpilogInserter.cpp74 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
84 TFI->processFunctionBeforeCalleeSavedScan(Fn, RS);
131 delete RS;
561 if (RS && TFI.hasFP(Fn) && RegInfo->useFPForScavengingIndex(Fn) &&
563 int SFI = RS->getScavengingFrameIndex();
608 if (RS && (int)i == RS->getScavengingFrameIndex())
630 if (RS && (int)i == RS->getScavengingFrameIndex())
644 if (RS
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