1/* ppc-opc.c -- PowerPC opcode list 2 Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 3 2005, 2006, 2007 Free Software Foundation, Inc. 4 Written by Ian Lance Taylor, Cygnus Support 5 6 This file is part of GDB, GAS, and the GNU binutils. 7 8 GDB, GAS, and the GNU binutils are free software; you can redistribute 9 them and/or modify them under the terms of the GNU General Public 10 License as published by the Free Software Foundation; either version 11 2, or (at your option) any later version. 12 13 GDB, GAS, and the GNU binutils are distributed in the hope that they 14 will be useful, but WITHOUT ANY WARRANTY; without even the implied 15 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 16 the GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this file; see the file COPYING. If not, write to the Free 20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 21 02110-1301, USA. */ 22 23#include <stdio.h> 24#include "sysdep.h" 25#include "opcode/ppc.h" 26#include "opintl.h" 27 28/* This file holds the PowerPC opcode table. The opcode table 29 includes almost all of the extended instruction mnemonics. This 30 permits the disassembler to use them, and simplifies the assembler 31 logic, at the cost of increasing the table size. The table is 32 strictly constant data, so the compiler should be able to put it in 33 the .text section. 34 35 This file also holds the operand table. All knowledge about 36 inserting operands into instructions and vice-versa is kept in this 37 file. */ 38 39/* Local insertion and extraction functions. */ 40 41static unsigned long insert_bat (unsigned long, long, int, const char **); 42static long extract_bat (unsigned long, int, int *); 43static unsigned long insert_bba (unsigned long, long, int, const char **); 44static long extract_bba (unsigned long, int, int *); 45static unsigned long insert_bd (unsigned long, long, int, const char **); 46static long extract_bd (unsigned long, int, int *); 47static unsigned long insert_bdm (unsigned long, long, int, const char **); 48static long extract_bdm (unsigned long, int, int *); 49static unsigned long insert_bdp (unsigned long, long, int, const char **); 50static long extract_bdp (unsigned long, int, int *); 51static unsigned long insert_bo (unsigned long, long, int, const char **); 52static long extract_bo (unsigned long, int, int *); 53static unsigned long insert_boe (unsigned long, long, int, const char **); 54static long extract_boe (unsigned long, int, int *); 55static unsigned long insert_dq (unsigned long, long, int, const char **); 56static long extract_dq (unsigned long, int, int *); 57static unsigned long insert_ds (unsigned long, long, int, const char **); 58static long extract_ds (unsigned long, int, int *); 59static unsigned long insert_de (unsigned long, long, int, const char **); 60static long extract_de (unsigned long, int, int *); 61static unsigned long insert_des (unsigned long, long, int, const char **); 62static long extract_des (unsigned long, int, int *); 63static unsigned long insert_fxm (unsigned long, long, int, const char **); 64static long extract_fxm (unsigned long, int, int *); 65static unsigned long insert_li (unsigned long, long, int, const char **); 66static long extract_li (unsigned long, int, int *); 67static unsigned long insert_mbe (unsigned long, long, int, const char **); 68static long extract_mbe (unsigned long, int, int *); 69static unsigned long insert_mb6 (unsigned long, long, int, const char **); 70static long extract_mb6 (unsigned long, int, int *); 71static unsigned long insert_nb (unsigned long, long, int, const char **); 72static long extract_nb (unsigned long, int, int *); 73static unsigned long insert_nsi (unsigned long, long, int, const char **); 74static long extract_nsi (unsigned long, int, int *); 75static unsigned long insert_ral (unsigned long, long, int, const char **); 76static unsigned long insert_ram (unsigned long, long, int, const char **); 77static unsigned long insert_raq (unsigned long, long, int, const char **); 78static unsigned long insert_ras (unsigned long, long, int, const char **); 79static unsigned long insert_rbs (unsigned long, long, int, const char **); 80static long extract_rbs (unsigned long, int, int *); 81static unsigned long insert_rsq (unsigned long, long, int, const char **); 82static unsigned long insert_rtq (unsigned long, long, int, const char **); 83static unsigned long insert_sh6 (unsigned long, long, int, const char **); 84static long extract_sh6 (unsigned long, int, int *); 85static unsigned long insert_spr (unsigned long, long, int, const char **); 86static long extract_spr (unsigned long, int, int *); 87static unsigned long insert_sprg (unsigned long, long, int, const char **); 88static long extract_sprg (unsigned long, int, int *); 89static unsigned long insert_tbr (unsigned long, long, int, const char **); 90static long extract_tbr (unsigned long, int, int *); 91static unsigned long insert_ev2 (unsigned long, long, int, const char **); 92static long extract_ev2 (unsigned long, int, int *); 93static unsigned long insert_ev4 (unsigned long, long, int, const char **); 94static long extract_ev4 (unsigned long, int, int *); 95static unsigned long insert_ev8 (unsigned long, long, int, const char **); 96static long extract_ev8 (unsigned long, int, int *); 97 98/* The operands table. 99 100 The fields are bits, shift, insert, extract, flags. 101 102 We used to put parens around the various additions, like the one 103 for BA just below. However, that caused trouble with feeble 104 compilers with a limit on depth of a parenthesized expression, like 105 (reportedly) the compiler in Microsoft Developer Studio 5. So we 106 omit the parens, since the macros are never used in a context where 107 the addition will be ambiguous. */ 108 109const struct powerpc_operand powerpc_operands[] = 110{ 111 /* The zero index is used to indicate the end of the list of 112 operands. */ 113#define UNUSED 0 114 { 0, 0, NULL, NULL, 0 }, 115 116 /* The BA field in an XL form instruction. */ 117#define BA UNUSED + 1 118#define BA_MASK (0x1f << 16) 119 { 5, 16, NULL, NULL, PPC_OPERAND_CR }, 120 121 /* The BA field in an XL form instruction when it must be the same 122 as the BT field in the same instruction. */ 123#define BAT BA + 1 124 { 5, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE }, 125 126 /* The BB field in an XL form instruction. */ 127#define BB BAT + 1 128#define BB_MASK (0x1f << 11) 129 { 5, 11, NULL, NULL, PPC_OPERAND_CR }, 130 131 /* The BB field in an XL form instruction when it must be the same 132 as the BA field in the same instruction. */ 133#define BBA BB + 1 134 { 5, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE }, 135 136 /* The BD field in a B form instruction. The lower two bits are 137 forced to zero. */ 138#define BD BBA + 1 139 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 140 141 /* The BD field in a B form instruction when absolute addressing is 142 used. */ 143#define BDA BD + 1 144 { 16, 0, insert_bd, extract_bd, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 145 146 /* The BD field in a B form instruction when the - modifier is used. 147 This sets the y bit of the BO field appropriately. */ 148#define BDM BDA + 1 149 { 16, 0, insert_bdm, extract_bdm, 150 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 151 152 /* The BD field in a B form instruction when the - modifier is used 153 and absolute address is used. */ 154#define BDMA BDM + 1 155 { 16, 0, insert_bdm, extract_bdm, 156 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 157 158 /* The BD field in a B form instruction when the + modifier is used. 159 This sets the y bit of the BO field appropriately. */ 160#define BDP BDMA + 1 161 { 16, 0, insert_bdp, extract_bdp, 162 PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 163 164 /* The BD field in a B form instruction when the + modifier is used 165 and absolute addressing is used. */ 166#define BDPA BDP + 1 167 { 16, 0, insert_bdp, extract_bdp, 168 PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 169 170 /* The BF field in an X or XL form instruction. */ 171#define BF BDPA + 1 172 { 3, 23, NULL, NULL, PPC_OPERAND_CR }, 173 174 /* An optional BF field. This is used for comparison instructions, 175 in which an omitted BF field is taken as zero. */ 176#define OBF BF + 1 177 { 3, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 178 179 /* The BFA field in an X or XL form instruction. */ 180#define BFA OBF + 1 181 { 3, 18, NULL, NULL, PPC_OPERAND_CR }, 182 183 /* The BI field in a B form or XL form instruction. */ 184#define BI BFA + 1 185#define BI_MASK (0x1f << 16) 186 { 5, 16, NULL, NULL, PPC_OPERAND_CR }, 187 188 /* The BO field in a B form instruction. Certain values are 189 illegal. */ 190#define BO BI + 1 191#define BO_MASK (0x1f << 21) 192 { 5, 21, insert_bo, extract_bo, 0 }, 193 194 /* The BO field in a B form instruction when the + or - modifier is 195 used. This is like the BO field, but it must be even. */ 196#define BOE BO + 1 197 { 5, 21, insert_boe, extract_boe, 0 }, 198 199#define BH BOE + 1 200 { 2, 11, NULL, NULL, PPC_OPERAND_OPTIONAL }, 201 202 /* The BT field in an X or XL form instruction. */ 203#define BT BH + 1 204 { 5, 21, NULL, NULL, PPC_OPERAND_CR }, 205 206 /* The condition register number portion of the BI field in a B form 207 or XL form instruction. This is used for the extended 208 conditional branch mnemonics, which set the lower two bits of the 209 BI field. This field is optional. */ 210#define CR BT + 1 211 { 3, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, 212 213 /* The CRB field in an X form instruction. */ 214#define CRB CR + 1 215 { 5, 6, NULL, NULL, 0 }, 216 217 /* The CRFD field in an X form instruction. */ 218#define CRFD CRB + 1 219 { 3, 23, NULL, NULL, PPC_OPERAND_CR }, 220 221 /* The CRFS field in an X form instruction. */ 222#define CRFS CRFD + 1 223 { 3, 0, NULL, NULL, PPC_OPERAND_CR }, 224 225 /* The CT field in an X form instruction. */ 226#define CT CRFS + 1 227 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 228 229 /* The D field in a D form instruction. This is a displacement off 230 a register, and implies that the next operand is a register in 231 parentheses. */ 232#define D CT + 1 233 { 16, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 234 235 /* The DE field in a DE form instruction. This is like D, but is 12 236 bits only. */ 237#define DE D + 1 238 { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS }, 239 240 /* The DES field in a DES form instruction. This is like DS, but is 14 241 bits only (12 stored.) */ 242#define DES DE + 1 243 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, 244 245 /* The DQ field in a DQ form instruction. This is like D, but the 246 lower four bits are forced to zero. */ 247#define DQ DES + 1 248 { 16, 0, insert_dq, extract_dq, 249 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, 250 251 /* The DS field in a DS form instruction. This is like D, but the 252 lower two bits are forced to zero. */ 253#define DS DQ + 1 254 { 16, 0, insert_ds, extract_ds, 255 PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, 256 257 /* The E field in a wrteei instruction. */ 258#define E DS + 1 259 { 1, 15, NULL, NULL, 0 }, 260 261 /* The FL1 field in a POWER SC form instruction. */ 262#define FL1 E + 1 263 { 4, 12, NULL, NULL, 0 }, 264 265 /* The FL2 field in a POWER SC form instruction. */ 266#define FL2 FL1 + 1 267 { 3, 2, NULL, NULL, 0 }, 268 269 /* The FLM field in an XFL form instruction. */ 270#define FLM FL2 + 1 271 { 8, 17, NULL, NULL, 0 }, 272 273 /* The FRA field in an X or A form instruction. */ 274#define FRA FLM + 1 275#define FRA_MASK (0x1f << 16) 276 { 5, 16, NULL, NULL, PPC_OPERAND_FPR }, 277 278 /* The FRB field in an X or A form instruction. */ 279#define FRB FRA + 1 280#define FRB_MASK (0x1f << 11) 281 { 5, 11, NULL, NULL, PPC_OPERAND_FPR }, 282 283 /* The FRC field in an A form instruction. */ 284#define FRC FRB + 1 285#define FRC_MASK (0x1f << 6) 286 { 5, 6, NULL, NULL, PPC_OPERAND_FPR }, 287 288 /* The FRS field in an X form instruction or the FRT field in a D, X 289 or A form instruction. */ 290#define FRS FRC + 1 291#define FRT FRS 292 { 5, 21, NULL, NULL, PPC_OPERAND_FPR }, 293 294 /* The FXM field in an XFX instruction. */ 295#define FXM FRS + 1 296#define FXM_MASK (0xff << 12) 297 { 8, 12, insert_fxm, extract_fxm, 0 }, 298 299 /* Power4 version for mfcr. */ 300#define FXM4 FXM + 1 301 { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, 302 303 /* The L field in a D or X form instruction. */ 304#define L FXM4 + 1 305 { 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 306 307 /* The LEV field in a POWER SVC form instruction. */ 308#define SVC_LEV L + 1 309 { 7, 5, NULL, NULL, 0 }, 310 311 /* The LEV field in an SC form instruction. */ 312#define LEV SVC_LEV + 1 313 { 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL }, 314 315 /* The LI field in an I form instruction. The lower two bits are 316 forced to zero. */ 317#define LI LEV + 1 318 { 26, 0, insert_li, extract_li, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED }, 319 320 /* The LI field in an I form instruction when used as an absolute 321 address. */ 322#define LIA LI + 1 323 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, 324 325 /* The LS field in an X (sync) form instruction. */ 326#define LS LIA + 1 327 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 328 329 /* The MB field in an M form instruction. */ 330#define MB LS + 1 331#define MB_MASK (0x1f << 6) 332 { 5, 6, NULL, NULL, 0 }, 333 334 /* The ME field in an M form instruction. */ 335#define ME MB + 1 336#define ME_MASK (0x1f << 1) 337 { 5, 1, NULL, NULL, 0 }, 338 339 /* The MB and ME fields in an M form instruction expressed a single 340 operand which is a bitmask indicating which bits to select. This 341 is a two operand form using PPC_OPERAND_NEXT. See the 342 description in opcode/ppc.h for what this means. */ 343#define MBE ME + 1 344 { 5, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT }, 345 { 32, 0, insert_mbe, extract_mbe, 0 }, 346 347 /* The MB or ME field in an MD or MDS form instruction. The high 348 bit is wrapped to the low end. */ 349#define MB6 MBE + 2 350#define ME6 MB6 351#define MB6_MASK (0x3f << 5) 352 { 6, 5, insert_mb6, extract_mb6, 0 }, 353 354 /* The MO field in an mbar instruction. */ 355#define MO MB6 + 1 356 { 5, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 357 358 /* The NB field in an X form instruction. The value 32 is stored as 359 0. */ 360#define NB MO + 1 361 { 6, 11, insert_nb, extract_nb, 0 }, 362 363 /* The NSI field in a D form instruction. This is the same as the 364 SI field, only negated. */ 365#define NSI NB + 1 366 { 16, 0, insert_nsi, extract_nsi, 367 PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, 368 369 /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ 370#define RA NSI + 1 371#define RA_MASK (0x1f << 16) 372 { 5, 16, NULL, NULL, PPC_OPERAND_GPR }, 373 374 /* As above, but 0 in the RA field means zero, not r0. */ 375#define RA0 RA + 1 376 { 5, 16, NULL, NULL, PPC_OPERAND_GPR_0 }, 377 378 /* The RA field in the DQ form lq instruction, which has special 379 value restrictions. */ 380#define RAQ RA0 + 1 381 { 5, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 }, 382 383 /* The RA field in a D or X form instruction which is an updating 384 load, which means that the RA field may not be zero and may not 385 equal the RT field. */ 386#define RAL RAQ + 1 387 { 5, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 }, 388 389 /* The RA field in an lmw instruction, which has special value 390 restrictions. */ 391#define RAM RAL + 1 392 { 5, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 }, 393 394 /* The RA field in a D or X form instruction which is an updating 395 store or an updating floating point load, which means that the RA 396 field may not be zero. */ 397#define RAS RAM + 1 398 { 5, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 }, 399 400 /* The RA field of the tlbwe instruction, which is optional. */ 401#define RAOPT RAS + 1 402 { 5, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 403 404 /* The RB field in an X, XO, M, or MDS form instruction. */ 405#define RB RAOPT + 1 406#define RB_MASK (0x1f << 11) 407 { 5, 11, NULL, NULL, PPC_OPERAND_GPR }, 408 409 /* The RB field in an X form instruction when it must be the same as 410 the RS field in the instruction. This is used for extended 411 mnemonics like mr. */ 412#define RBS RB + 1 413 { 5, 1, insert_rbs, extract_rbs, PPC_OPERAND_FAKE }, 414 415 /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form 416 instruction or the RT field in a D, DS, X, XFX or XO form 417 instruction. */ 418#define RS RBS + 1 419#define RT RS 420#define RT_MASK (0x1f << 21) 421 { 5, 21, NULL, NULL, PPC_OPERAND_GPR }, 422 423 /* The RS field of the DS form stq instruction, which has special 424 value restrictions. */ 425#define RSQ RS + 1 426 { 5, 21, insert_rsq, NULL, PPC_OPERAND_GPR_0 }, 427 428 /* The RT field of the DQ form lq instruction, which has special 429 value restrictions. */ 430#define RTQ RSQ + 1 431 { 5, 21, insert_rtq, NULL, PPC_OPERAND_GPR_0 }, 432 433 /* The RS field of the tlbwe instruction, which is optional. */ 434#define RSO RTQ + 1 435#define RTO RSO 436 { 5, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, 437 438 /* The SH field in an X or M form instruction. */ 439#define SH RSO + 1 440#define SH_MASK (0x1f << 11) 441 { 5, 11, NULL, NULL, 0 }, 442 443 /* The SH field in an MD form instruction. This is split. */ 444#define SH6 SH + 1 445#define SH6_MASK ((0x1f << 11) | (1 << 1)) 446 { 6, 1, insert_sh6, extract_sh6, 0 }, 447 448 /* The SH field of the tlbwe instruction, which is optional. */ 449#define SHO SH6 + 1 450 { 5, 11,NULL, NULL, PPC_OPERAND_OPTIONAL }, 451 452 /* The SI field in a D form instruction. */ 453#define SI SHO + 1 454 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED }, 455 456 /* The SI field in a D form instruction when we accept a wide range 457 of positive values. */ 458#define SISIGNOPT SI + 1 459 { 16, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT }, 460 461 /* The SPR field in an XFX form instruction. This is flipped--the 462 lower 5 bits are stored in the upper 5 and vice- versa. */ 463#define SPR SISIGNOPT + 1 464#define PMR SPR 465#define SPR_MASK (0x3ff << 11) 466 { 10, 11, insert_spr, extract_spr, 0 }, 467 468 /* The BAT index number in an XFX form m[ft]ibat[lu] instruction. */ 469#define SPRBAT SPR + 1 470#define SPRBAT_MASK (0x3 << 17) 471 { 2, 17, NULL, NULL, 0 }, 472 473 /* The SPRG register number in an XFX form m[ft]sprg instruction. */ 474#define SPRG SPRBAT + 1 475 { 5, 16, insert_sprg, extract_sprg, 0 }, 476 477 /* The SR field in an X form instruction. */ 478#define SR SPRG + 1 479 { 4, 16, NULL, NULL, 0 }, 480 481 /* The STRM field in an X AltiVec form instruction. */ 482#define STRM SR + 1 483#define STRM_MASK (0x3 << 21) 484 { 2, 21, NULL, NULL, 0 }, 485 486 /* The SV field in a POWER SC form instruction. */ 487#define SV STRM + 1 488 { 14, 2, NULL, NULL, 0 }, 489 490 /* The TBR field in an XFX form instruction. This is like the SPR 491 field, but it is optional. */ 492#define TBR SV + 1 493 { 10, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL }, 494 495 /* The TO field in a D or X form instruction. */ 496#define TO TBR + 1 497#define TO_MASK (0x1f << 21) 498 { 5, 21, NULL, NULL, 0 }, 499 500 /* The U field in an X form instruction. */ 501#define U TO + 1 502 { 4, 12, NULL, NULL, 0 }, 503 504 /* The UI field in a D form instruction. */ 505#define UI U + 1 506 { 16, 0, NULL, NULL, 0 }, 507 508 /* The VA field in a VA, VX or VXR form instruction. */ 509#define VA UI + 1 510#define VA_MASK (0x1f << 16) 511 { 5, 16, NULL, NULL, PPC_OPERAND_VR }, 512 513 /* The VB field in a VA, VX or VXR form instruction. */ 514#define VB VA + 1 515#define VB_MASK (0x1f << 11) 516 { 5, 11, NULL, NULL, PPC_OPERAND_VR }, 517 518 /* The VC field in a VA form instruction. */ 519#define VC VB + 1 520#define VC_MASK (0x1f << 6) 521 { 5, 6, NULL, NULL, PPC_OPERAND_VR }, 522 523 /* The VD or VS field in a VA, VX, VXR or X form instruction. */ 524#define VD VC + 1 525#define VS VD 526#define VD_MASK (0x1f << 21) 527 { 5, 21, NULL, NULL, PPC_OPERAND_VR }, 528 529 /* The SIMM field in a VX form instruction. */ 530#define SIMM VD + 1 531 { 5, 16, NULL, NULL, PPC_OPERAND_SIGNED}, 532 533 /* The UIMM field in a VX form instruction. */ 534#define UIMM SIMM + 1 535 { 5, 16, NULL, NULL, 0 }, 536 537 /* The SHB field in a VA form instruction. */ 538#define SHB UIMM + 1 539 { 4, 6, NULL, NULL, 0 }, 540 541 /* The other UIMM field in a EVX form instruction. */ 542#define EVUIMM SHB + 1 543 { 5, 11, NULL, NULL, 0 }, 544 545 /* The other UIMM field in a half word EVX form instruction. */ 546#define EVUIMM_2 EVUIMM + 1 547 { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS }, 548 549 /* The other UIMM field in a word EVX form instruction. */ 550#define EVUIMM_4 EVUIMM_2 + 1 551 { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS }, 552 553 /* The other UIMM field in a double EVX form instruction. */ 554#define EVUIMM_8 EVUIMM_4 + 1 555 { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS }, 556 557 /* The WS field. */ 558#define WS EVUIMM_8 + 1 559#define WS_MASK (0x7 << 11) 560 { 3, 11, NULL, NULL, 0 }, 561 562 /* The L field in an mtmsrd or A form instruction. */ 563#define MTMSRD_L WS + 1 564#define A_L MTMSRD_L 565 { 1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL }, 566 567 /* The DCM field in a Z form instruction. */ 568#define DCM MTMSRD_L + 1 569 { 6, 16, NULL, NULL, 0 }, 570 571 /* Likewise, the DGM field in a Z form instruction. */ 572#define DGM DCM + 1 573 { 6, 16, NULL, NULL, 0 }, 574 575#define TE DGM + 1 576 { 5, 11, NULL, NULL, 0 }, 577 578#define RMC TE + 1 579 { 2, 21, NULL, NULL, 0 }, 580 581#define R RMC + 1 582 { 1, 15, NULL, NULL, 0 }, 583 584#define SP R + 1 585 { 2, 11, NULL, NULL, 0 }, 586 587#define S SP + 1 588 { 1, 11, NULL, NULL, 0 }, 589 590 /* SH field starting at bit position 16. */ 591#define SH16 S + 1 592 { 6, 10, NULL, NULL, 0 }, 593 594 /* The L field in an X form with the RT field fixed instruction. */ 595#define XRT_L SH16 + 1 596 { 2, 21, NULL, NULL, PPC_OPERAND_OPTIONAL }, 597 598 /* The EH field in larx instruction. */ 599#define EH XRT_L + 1 600 { 1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL }, 601}; 602 603/* The functions used to insert and extract complicated operands. */ 604 605/* The BA field in an XL form instruction when it must be the same as 606 the BT field in the same instruction. This operand is marked FAKE. 607 The insertion function just copies the BT field into the BA field, 608 and the extraction function just checks that the fields are the 609 same. */ 610 611static unsigned long 612insert_bat (unsigned long insn, 613 long value ATTRIBUTE_UNUSED, 614 int dialect ATTRIBUTE_UNUSED, 615 const char **errmsg ATTRIBUTE_UNUSED) 616{ 617 return insn | (((insn >> 21) & 0x1f) << 16); 618} 619 620static long 621extract_bat (unsigned long insn, 622 int dialect ATTRIBUTE_UNUSED, 623 int *invalid) 624{ 625 if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) 626 *invalid = 1; 627 return 0; 628} 629 630/* The BB field in an XL form instruction when it must be the same as 631 the BA field in the same instruction. This operand is marked FAKE. 632 The insertion function just copies the BA field into the BB field, 633 and the extraction function just checks that the fields are the 634 same. */ 635 636static unsigned long 637insert_bba (unsigned long insn, 638 long value ATTRIBUTE_UNUSED, 639 int dialect ATTRIBUTE_UNUSED, 640 const char **errmsg ATTRIBUTE_UNUSED) 641{ 642 return insn | (((insn >> 16) & 0x1f) << 11); 643} 644 645static long 646extract_bba (unsigned long insn, 647 int dialect ATTRIBUTE_UNUSED, 648 int *invalid) 649{ 650 if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) 651 *invalid = 1; 652 return 0; 653} 654 655/* The BD field in a B form instruction. The lower two bits are 656 forced to zero. */ 657 658static unsigned long 659insert_bd (unsigned long insn, 660 long value, 661 int dialect ATTRIBUTE_UNUSED, 662 const char **errmsg ATTRIBUTE_UNUSED) 663{ 664 return insn | (value & 0xfffc); 665} 666 667static long 668extract_bd (unsigned long insn, 669 int dialect ATTRIBUTE_UNUSED, 670 int *invalid ATTRIBUTE_UNUSED) 671{ 672 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 673} 674 675/* The BD field in a B form instruction when the - modifier is used. 676 This modifier means that the branch is not expected to be taken. 677 For chips built to versions of the architecture prior to version 2 678 (ie. not Power4 compatible), we set the y bit of the BO field to 1 679 if the offset is negative. When extracting, we require that the y 680 bit be 1 and that the offset be positive, since if the y bit is 0 681 we just want to print the normal form of the instruction. 682 Power4 compatible targets use two bits, "a", and "t", instead of 683 the "y" bit. "at" == 00 => no hint, "at" == 01 => unpredictable, 684 "at" == 10 => not taken, "at" == 11 => taken. The "t" bit is 00001 685 in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 686 for branch on CTR. We only handle the taken/not-taken hint here. 687 Note that we don't relax the conditions tested here when 688 disassembling with -Many because insns using extract_bdm and 689 extract_bdp always occur in pairs. One or the other will always 690 be valid. */ 691 692static unsigned long 693insert_bdm (unsigned long insn, 694 long value, 695 int dialect, 696 const char **errmsg ATTRIBUTE_UNUSED) 697{ 698 if ((dialect & PPC_OPCODE_POWER4) == 0) 699 { 700 if ((value & 0x8000) != 0) 701 insn |= 1 << 21; 702 } 703 else 704 { 705 if ((insn & (0x14 << 21)) == (0x04 << 21)) 706 insn |= 0x02 << 21; 707 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 708 insn |= 0x08 << 21; 709 } 710 return insn | (value & 0xfffc); 711} 712 713static long 714extract_bdm (unsigned long insn, 715 int dialect, 716 int *invalid) 717{ 718 if ((dialect & PPC_OPCODE_POWER4) == 0) 719 { 720 if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) 721 *invalid = 1; 722 } 723 else 724 { 725 if ((insn & (0x17 << 21)) != (0x06 << 21) 726 && (insn & (0x1d << 21)) != (0x18 << 21)) 727 *invalid = 1; 728 } 729 730 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 731} 732 733/* The BD field in a B form instruction when the + modifier is used. 734 This is like BDM, above, except that the branch is expected to be 735 taken. */ 736 737static unsigned long 738insert_bdp (unsigned long insn, 739 long value, 740 int dialect, 741 const char **errmsg ATTRIBUTE_UNUSED) 742{ 743 if ((dialect & PPC_OPCODE_POWER4) == 0) 744 { 745 if ((value & 0x8000) == 0) 746 insn |= 1 << 21; 747 } 748 else 749 { 750 if ((insn & (0x14 << 21)) == (0x04 << 21)) 751 insn |= 0x03 << 21; 752 else if ((insn & (0x14 << 21)) == (0x10 << 21)) 753 insn |= 0x09 << 21; 754 } 755 return insn | (value & 0xfffc); 756} 757 758static long 759extract_bdp (unsigned long insn, 760 int dialect, 761 int *invalid) 762{ 763 if ((dialect & PPC_OPCODE_POWER4) == 0) 764 { 765 if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) 766 *invalid = 1; 767 } 768 else 769 { 770 if ((insn & (0x17 << 21)) != (0x07 << 21) 771 && (insn & (0x1d << 21)) != (0x19 << 21)) 772 *invalid = 1; 773 } 774 775 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 776} 777 778/* Check for legal values of a BO field. */ 779 780static int 781valid_bo (long value, int dialect, int extract) 782{ 783 if ((dialect & PPC_OPCODE_POWER4) == 0) 784 { 785 int valid; 786 /* Certain encodings have bits that are required to be zero. 787 These are (z must be zero, y may be anything): 788 001zy 789 011zy 790 1z00y 791 1z01y 792 1z1zz 793 */ 794 switch (value & 0x14) 795 { 796 default: 797 case 0: 798 valid = 1; 799 break; 800 case 0x4: 801 valid = (value & 0x2) == 0; 802 break; 803 case 0x10: 804 valid = (value & 0x8) == 0; 805 break; 806 case 0x14: 807 valid = value == 0x14; 808 break; 809 } 810 /* When disassembling with -Many, accept power4 encodings too. */ 811 if (valid 812 || (dialect & PPC_OPCODE_ANY) == 0 813 || !extract) 814 return valid; 815 } 816 817 /* Certain encodings have bits that are required to be zero. 818 These are (z must be zero, a & t may be anything): 819 0000z 820 0001z 821 0100z 822 0101z 823 001at 824 011at 825 1a00t 826 1a01t 827 1z1zz 828 */ 829 if ((value & 0x14) == 0) 830 return (value & 0x1) == 0; 831 else if ((value & 0x14) == 0x14) 832 return value == 0x14; 833 else 834 return 1; 835} 836 837/* The BO field in a B form instruction. Warn about attempts to set 838 the field to an illegal value. */ 839 840static unsigned long 841insert_bo (unsigned long insn, 842 long value, 843 int dialect, 844 const char **errmsg) 845{ 846 if (!valid_bo (value, dialect, 0)) 847 *errmsg = _("invalid conditional option"); 848 return insn | ((value & 0x1f) << 21); 849} 850 851static long 852extract_bo (unsigned long insn, 853 int dialect, 854 int *invalid) 855{ 856 long value; 857 858 value = (insn >> 21) & 0x1f; 859 if (!valid_bo (value, dialect, 1)) 860 *invalid = 1; 861 return value; 862} 863 864/* The BO field in a B form instruction when the + or - modifier is 865 used. This is like the BO field, but it must be even. When 866 extracting it, we force it to be even. */ 867 868static unsigned long 869insert_boe (unsigned long insn, 870 long value, 871 int dialect, 872 const char **errmsg) 873{ 874 if (!valid_bo (value, dialect, 0)) 875 *errmsg = _("invalid conditional option"); 876 else if ((value & 1) != 0) 877 *errmsg = _("attempt to set y bit when using + or - modifier"); 878 879 return insn | ((value & 0x1f) << 21); 880} 881 882static long 883extract_boe (unsigned long insn, 884 int dialect, 885 int *invalid) 886{ 887 long value; 888 889 value = (insn >> 21) & 0x1f; 890 if (!valid_bo (value, dialect, 1)) 891 *invalid = 1; 892 return value & 0x1e; 893} 894 895/* The DQ field in a DQ form instruction. This is like D, but the 896 lower four bits are forced to zero. */ 897 898static unsigned long 899insert_dq (unsigned long insn, 900 long value, 901 int dialect ATTRIBUTE_UNUSED, 902 const char **errmsg) 903{ 904 if ((value & 0xf) != 0) 905 *errmsg = _("offset not a multiple of 16"); 906 return insn | (value & 0xfff0); 907} 908 909static long 910extract_dq (unsigned long insn, 911 int dialect ATTRIBUTE_UNUSED, 912 int *invalid ATTRIBUTE_UNUSED) 913{ 914 return ((insn & 0xfff0) ^ 0x8000) - 0x8000; 915} 916 917static unsigned long 918insert_ev2 (unsigned long insn, 919 long value, 920 int dialect ATTRIBUTE_UNUSED, 921 const char **errmsg) 922{ 923 if ((value & 1) != 0) 924 *errmsg = _("offset not a multiple of 2"); 925 if ((value > 62) != 0) 926 *errmsg = _("offset greater than 62"); 927 return insn | ((value & 0x3e) << 10); 928} 929 930static long 931extract_ev2 (unsigned long insn, 932 int dialect ATTRIBUTE_UNUSED, 933 int *invalid ATTRIBUTE_UNUSED) 934{ 935 return (insn >> 10) & 0x3e; 936} 937 938static unsigned long 939insert_ev4 (unsigned long insn, 940 long value, 941 int dialect ATTRIBUTE_UNUSED, 942 const char **errmsg) 943{ 944 if ((value & 3) != 0) 945 *errmsg = _("offset not a multiple of 4"); 946 if ((value > 124) != 0) 947 *errmsg = _("offset greater than 124"); 948 return insn | ((value & 0x7c) << 9); 949} 950 951static long 952extract_ev4 (unsigned long insn, 953 int dialect ATTRIBUTE_UNUSED, 954 int *invalid ATTRIBUTE_UNUSED) 955{ 956 return (insn >> 9) & 0x7c; 957} 958 959static unsigned long 960insert_ev8 (unsigned long insn, 961 long value, 962 int dialect ATTRIBUTE_UNUSED, 963 const char **errmsg) 964{ 965 if ((value & 7) != 0) 966 *errmsg = _("offset not a multiple of 8"); 967 if ((value > 248) != 0) 968 *errmsg = _("offset greater than 248"); 969 return insn | ((value & 0xf8) << 8); 970} 971 972static long 973extract_ev8 (unsigned long insn, 974 int dialect ATTRIBUTE_UNUSED, 975 int *invalid ATTRIBUTE_UNUSED) 976{ 977 return (insn >> 8) & 0xf8; 978} 979 980/* The DS field in a DS form instruction. This is like D, but the 981 lower two bits are forced to zero. */ 982 983static unsigned long 984insert_ds (unsigned long insn, 985 long value, 986 int dialect ATTRIBUTE_UNUSED, 987 const char **errmsg) 988{ 989 if ((value & 3) != 0) 990 *errmsg = _("offset not a multiple of 4"); 991 return insn | (value & 0xfffc); 992} 993 994static long 995extract_ds (unsigned long insn, 996 int dialect ATTRIBUTE_UNUSED, 997 int *invalid ATTRIBUTE_UNUSED) 998{ 999 return ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1000} 1001 1002/* The DE field in a DE form instruction. */ 1003 1004static unsigned long 1005insert_de (unsigned long insn, 1006 long value, 1007 int dialect ATTRIBUTE_UNUSED, 1008 const char **errmsg) 1009{ 1010 if (value > 2047 || value < -2048) 1011 *errmsg = _("offset not between -2048 and 2047"); 1012 return insn | ((value << 4) & 0xfff0); 1013} 1014 1015static long 1016extract_de (unsigned long insn, 1017 int dialect ATTRIBUTE_UNUSED, 1018 int *invalid ATTRIBUTE_UNUSED) 1019{ 1020 return (insn & 0xfff0) >> 4; 1021} 1022 1023/* The DES field in a DES form instruction. */ 1024 1025static unsigned long 1026insert_des (unsigned long insn, 1027 long value, 1028 int dialect ATTRIBUTE_UNUSED, 1029 const char **errmsg) 1030{ 1031 if (value > 8191 || value < -8192) 1032 *errmsg = _("offset not between -8192 and 8191"); 1033 else if ((value & 3) != 0) 1034 *errmsg = _("offset not a multiple of 4"); 1035 return insn | ((value << 2) & 0xfff0); 1036} 1037 1038static long 1039extract_des (unsigned long insn, 1040 int dialect ATTRIBUTE_UNUSED, 1041 int *invalid ATTRIBUTE_UNUSED) 1042{ 1043 return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000; 1044} 1045 1046/* FXM mask in mfcr and mtcrf instructions. */ 1047 1048static unsigned long 1049insert_fxm (unsigned long insn, 1050 long value, 1051 int dialect, 1052 const char **errmsg) 1053{ 1054 /* If we're handling the mfocrf and mtocrf insns ensure that exactly 1055 one bit of the mask field is set. */ 1056 if ((insn & (1 << 20)) != 0) 1057 { 1058 if (value == 0 || (value & -value) != value) 1059 { 1060 *errmsg = _("invalid mask field"); 1061 value = 0; 1062 } 1063 } 1064 1065 /* If the optional field on mfcr is missing that means we want to use 1066 the old form of the instruction that moves the whole cr. In that 1067 case we'll have VALUE zero. There doesn't seem to be a way to 1068 distinguish this from the case where someone writes mfcr %r3,0. */ 1069 else if (value == 0) 1070 ; 1071 1072 /* If only one bit of the FXM field is set, we can use the new form 1073 of the instruction, which is faster. Unlike the Power4 branch hint 1074 encoding, this is not backward compatible. Do not generate the 1075 new form unless -mpower4 has been given, or -many and the two 1076 operand form of mfcr was used. */ 1077 else if ((value & -value) == value 1078 && ((dialect & PPC_OPCODE_POWER4) != 0 1079 || ((dialect & PPC_OPCODE_ANY) != 0 1080 && (insn & (0x3ff << 1)) == 19 << 1))) 1081 insn |= 1 << 20; 1082 1083 /* Any other value on mfcr is an error. */ 1084 else if ((insn & (0x3ff << 1)) == 19 << 1) 1085 { 1086 *errmsg = _("ignoring invalid mfcr mask"); 1087 value = 0; 1088 } 1089 1090 return insn | ((value & 0xff) << 12); 1091} 1092 1093static long 1094extract_fxm (unsigned long insn, 1095 int dialect ATTRIBUTE_UNUSED, 1096 int *invalid) 1097{ 1098 long mask = (insn >> 12) & 0xff; 1099 1100 /* Is this a Power4 insn? */ 1101 if ((insn & (1 << 20)) != 0) 1102 { 1103 /* Exactly one bit of MASK should be set. */ 1104 if (mask == 0 || (mask & -mask) != mask) 1105 *invalid = 1; 1106 } 1107 1108 /* Check that non-power4 form of mfcr has a zero MASK. */ 1109 else if ((insn & (0x3ff << 1)) == 19 << 1) 1110 { 1111 if (mask != 0) 1112 *invalid = 1; 1113 } 1114 1115 return mask; 1116} 1117 1118/* The LI field in an I form instruction. The lower two bits are 1119 forced to zero. */ 1120 1121static unsigned long 1122insert_li (unsigned long insn, 1123 long value, 1124 int dialect ATTRIBUTE_UNUSED, 1125 const char **errmsg) 1126{ 1127 if ((value & 3) != 0) 1128 *errmsg = _("ignoring least significant bits in branch offset"); 1129 return insn | (value & 0x3fffffc); 1130} 1131 1132static long 1133extract_li (unsigned long insn, 1134 int dialect ATTRIBUTE_UNUSED, 1135 int *invalid ATTRIBUTE_UNUSED) 1136{ 1137 return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000; 1138} 1139 1140/* The MB and ME fields in an M form instruction expressed as a single 1141 operand which is itself a bitmask. The extraction function always 1142 marks it as invalid, since we never want to recognize an 1143 instruction which uses a field of this type. */ 1144 1145static unsigned long 1146insert_mbe (unsigned long insn, 1147 long value, 1148 int dialect ATTRIBUTE_UNUSED, 1149 const char **errmsg) 1150{ 1151 unsigned long uval, mask; 1152 int mb, me, mx, count, last; 1153 1154 uval = value; 1155 1156 if (uval == 0) 1157 { 1158 *errmsg = _("illegal bitmask"); 1159 return insn; 1160 } 1161 1162 mb = 0; 1163 me = 32; 1164 if ((uval & 1) != 0) 1165 last = 1; 1166 else 1167 last = 0; 1168 count = 0; 1169 1170 /* mb: location of last 0->1 transition */ 1171 /* me: location of last 1->0 transition */ 1172 /* count: # transitions */ 1173 1174 for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) 1175 { 1176 if ((uval & mask) && !last) 1177 { 1178 ++count; 1179 mb = mx; 1180 last = 1; 1181 } 1182 else if (!(uval & mask) && last) 1183 { 1184 ++count; 1185 me = mx; 1186 last = 0; 1187 } 1188 } 1189 if (me == 0) 1190 me = 32; 1191 1192 if (count != 2 && (count != 0 || ! last)) 1193 *errmsg = _("illegal bitmask"); 1194 1195 return insn | (mb << 6) | ((me - 1) << 1); 1196} 1197 1198static long 1199extract_mbe (unsigned long insn, 1200 int dialect ATTRIBUTE_UNUSED, 1201 int *invalid) 1202{ 1203 long ret; 1204 int mb, me; 1205 int i; 1206 1207 *invalid = 1; 1208 1209 mb = (insn >> 6) & 0x1f; 1210 me = (insn >> 1) & 0x1f; 1211 if (mb < me + 1) 1212 { 1213 ret = 0; 1214 for (i = mb; i <= me; i++) 1215 ret |= 1L << (31 - i); 1216 } 1217 else if (mb == me + 1) 1218 ret = ~0; 1219 else /* (mb > me + 1) */ 1220 { 1221 ret = ~0; 1222 for (i = me + 1; i < mb; i++) 1223 ret &= ~(1L << (31 - i)); 1224 } 1225 return ret; 1226} 1227 1228/* The MB or ME field in an MD or MDS form instruction. The high bit 1229 is wrapped to the low end. */ 1230 1231static unsigned long 1232insert_mb6 (unsigned long insn, 1233 long value, 1234 int dialect ATTRIBUTE_UNUSED, 1235 const char **errmsg ATTRIBUTE_UNUSED) 1236{ 1237 return insn | ((value & 0x1f) << 6) | (value & 0x20); 1238} 1239 1240static long 1241extract_mb6 (unsigned long insn, 1242 int dialect ATTRIBUTE_UNUSED, 1243 int *invalid ATTRIBUTE_UNUSED) 1244{ 1245 return ((insn >> 6) & 0x1f) | (insn & 0x20); 1246} 1247 1248/* The NB field in an X form instruction. The value 32 is stored as 1249 0. */ 1250 1251static unsigned long 1252insert_nb (unsigned long insn, 1253 long value, 1254 int dialect ATTRIBUTE_UNUSED, 1255 const char **errmsg) 1256{ 1257 if (value < 0 || value > 32) 1258 *errmsg = _("value out of range"); 1259 if (value == 32) 1260 value = 0; 1261 return insn | ((value & 0x1f) << 11); 1262} 1263 1264static long 1265extract_nb (unsigned long insn, 1266 int dialect ATTRIBUTE_UNUSED, 1267 int *invalid ATTRIBUTE_UNUSED) 1268{ 1269 long ret; 1270 1271 ret = (insn >> 11) & 0x1f; 1272 if (ret == 0) 1273 ret = 32; 1274 return ret; 1275} 1276 1277/* The NSI field in a D form instruction. This is the same as the SI 1278 field, only negated. The extraction function always marks it as 1279 invalid, since we never want to recognize an instruction which uses 1280 a field of this type. */ 1281 1282static unsigned long 1283insert_nsi (unsigned long insn, 1284 long value, 1285 int dialect ATTRIBUTE_UNUSED, 1286 const char **errmsg ATTRIBUTE_UNUSED) 1287{ 1288 return insn | (-value & 0xffff); 1289} 1290 1291static long 1292extract_nsi (unsigned long insn, 1293 int dialect ATTRIBUTE_UNUSED, 1294 int *invalid) 1295{ 1296 *invalid = 1; 1297 return -(((insn & 0xffff) ^ 0x8000) - 0x8000); 1298} 1299 1300/* The RA field in a D or X form instruction which is an updating 1301 load, which means that the RA field may not be zero and may not 1302 equal the RT field. */ 1303 1304static unsigned long 1305insert_ral (unsigned long insn, 1306 long value, 1307 int dialect ATTRIBUTE_UNUSED, 1308 const char **errmsg) 1309{ 1310 if (value == 0 1311 || (unsigned long) value == ((insn >> 21) & 0x1f)) 1312 *errmsg = "invalid register operand when updating"; 1313 return insn | ((value & 0x1f) << 16); 1314} 1315 1316/* The RA field in an lmw instruction, which has special value 1317 restrictions. */ 1318 1319static unsigned long 1320insert_ram (unsigned long insn, 1321 long value, 1322 int dialect ATTRIBUTE_UNUSED, 1323 const char **errmsg) 1324{ 1325 if ((unsigned long) value >= ((insn >> 21) & 0x1f)) 1326 *errmsg = _("index register in load range"); 1327 return insn | ((value & 0x1f) << 16); 1328} 1329 1330/* The RA field in the DQ form lq instruction, which has special 1331 value restrictions. */ 1332 1333static unsigned long 1334insert_raq (unsigned long insn, 1335 long value, 1336 int dialect ATTRIBUTE_UNUSED, 1337 const char **errmsg) 1338{ 1339 long rtvalue = (insn & RT_MASK) >> 21; 1340 1341 if (value == rtvalue) 1342 *errmsg = _("source and target register operands must be different"); 1343 return insn | ((value & 0x1f) << 16); 1344} 1345 1346/* The RA field in a D or X form instruction which is an updating 1347 store or an updating floating point load, which means that the RA 1348 field may not be zero. */ 1349 1350static unsigned long 1351insert_ras (unsigned long insn, 1352 long value, 1353 int dialect ATTRIBUTE_UNUSED, 1354 const char **errmsg) 1355{ 1356 if (value == 0) 1357 *errmsg = _("invalid register operand when updating"); 1358 return insn | ((value & 0x1f) << 16); 1359} 1360 1361/* The RB field in an X form instruction when it must be the same as 1362 the RS field in the instruction. This is used for extended 1363 mnemonics like mr. This operand is marked FAKE. The insertion 1364 function just copies the BT field into the BA field, and the 1365 extraction function just checks that the fields are the same. */ 1366 1367static unsigned long 1368insert_rbs (unsigned long insn, 1369 long value ATTRIBUTE_UNUSED, 1370 int dialect ATTRIBUTE_UNUSED, 1371 const char **errmsg ATTRIBUTE_UNUSED) 1372{ 1373 return insn | (((insn >> 21) & 0x1f) << 11); 1374} 1375 1376static long 1377extract_rbs (unsigned long insn, 1378 int dialect ATTRIBUTE_UNUSED, 1379 int *invalid) 1380{ 1381 if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) 1382 *invalid = 1; 1383 return 0; 1384} 1385 1386/* The RT field of the DQ form lq instruction, which has special 1387 value restrictions. */ 1388 1389static unsigned long 1390insert_rtq (unsigned long insn, 1391 long value, 1392 int dialect ATTRIBUTE_UNUSED, 1393 const char **errmsg) 1394{ 1395 if ((value & 1) != 0) 1396 *errmsg = _("target register operand must be even"); 1397 return insn | ((value & 0x1f) << 21); 1398} 1399 1400/* The RS field of the DS form stq instruction, which has special 1401 value restrictions. */ 1402 1403static unsigned long 1404insert_rsq (unsigned long insn, 1405 long value ATTRIBUTE_UNUSED, 1406 int dialect ATTRIBUTE_UNUSED, 1407 const char **errmsg) 1408{ 1409 if ((value & 1) != 0) 1410 *errmsg = _("source register operand must be even"); 1411 return insn | ((value & 0x1f) << 21); 1412} 1413 1414/* The SH field in an MD form instruction. This is split. */ 1415 1416static unsigned long 1417insert_sh6 (unsigned long insn, 1418 long value, 1419 int dialect ATTRIBUTE_UNUSED, 1420 const char **errmsg ATTRIBUTE_UNUSED) 1421{ 1422 return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); 1423} 1424 1425static long 1426extract_sh6 (unsigned long insn, 1427 int dialect ATTRIBUTE_UNUSED, 1428 int *invalid ATTRIBUTE_UNUSED) 1429{ 1430 return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); 1431} 1432 1433/* The SPR field in an XFX form instruction. This is flipped--the 1434 lower 5 bits are stored in the upper 5 and vice- versa. */ 1435 1436static unsigned long 1437insert_spr (unsigned long insn, 1438 long value, 1439 int dialect ATTRIBUTE_UNUSED, 1440 const char **errmsg ATTRIBUTE_UNUSED) 1441{ 1442 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1443} 1444 1445static long 1446extract_spr (unsigned long insn, 1447 int dialect ATTRIBUTE_UNUSED, 1448 int *invalid ATTRIBUTE_UNUSED) 1449{ 1450 return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1451} 1452 1453/* Some dialects have 8 SPRG registers instead of the standard 4. */ 1454 1455static unsigned long 1456insert_sprg (unsigned long insn, 1457 long value, 1458 int dialect, 1459 const char **errmsg) 1460{ 1461 /* This check uses PPC_OPCODE_403 because PPC405 is later defined 1462 as a synonym. If ever a 405 specific dialect is added this 1463 check should use that instead. */ 1464 if (value > 7 1465 || (value > 3 1466 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) 1467 *errmsg = _("invalid sprg number"); 1468 1469 /* If this is mfsprg4..7 then use spr 260..263 which can be read in 1470 user mode. Anything else must use spr 272..279. */ 1471 if (value <= 3 || (insn & 0x100) != 0) 1472 value |= 0x10; 1473 1474 return insn | ((value & 0x17) << 16); 1475} 1476 1477static long 1478extract_sprg (unsigned long insn, 1479 int dialect, 1480 int *invalid) 1481{ 1482 unsigned long val = (insn >> 16) & 0x1f; 1483 1484 /* mfsprg can use 260..263 and 272..279. mtsprg only uses spr 272..279 1485 If not BOOKE or 405, then both use only 272..275. */ 1486 if (val <= 3 1487 || (val < 0x10 && (insn & 0x100) != 0) 1488 || (val - 0x10 > 3 1489 && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0)) 1490 *invalid = 1; 1491 return val & 7; 1492} 1493 1494/* The TBR field in an XFX instruction. This is just like SPR, but it 1495 is optional. When TBR is omitted, it must be inserted as 268 (the 1496 magic number of the TB register). These functions treat 0 1497 (indicating an omitted optional operand) as 268. This means that 1498 ``mftb 4,0'' is not handled correctly. This does not matter very 1499 much, since the architecture manual does not define mftb as 1500 accepting any values other than 268 or 269. */ 1501 1502#define TB (268) 1503 1504static unsigned long 1505insert_tbr (unsigned long insn, 1506 long value, 1507 int dialect ATTRIBUTE_UNUSED, 1508 const char **errmsg ATTRIBUTE_UNUSED) 1509{ 1510 if (value == 0) 1511 value = TB; 1512 return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); 1513} 1514 1515static long 1516extract_tbr (unsigned long insn, 1517 int dialect ATTRIBUTE_UNUSED, 1518 int *invalid ATTRIBUTE_UNUSED) 1519{ 1520 long ret; 1521 1522 ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); 1523 if (ret == TB) 1524 ret = 0; 1525 return ret; 1526} 1527 1528/* Macros used to form opcodes. */ 1529 1530/* The main opcode. */ 1531#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26) 1532#define OP_MASK OP (0x3f) 1533 1534/* The main opcode combined with a trap code in the TO field of a D 1535 form instruction. Used for extended mnemonics for the trap 1536 instructions. */ 1537#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21)) 1538#define OPTO_MASK (OP_MASK | TO_MASK) 1539 1540/* The main opcode combined with a comparison size bit in the L field 1541 of a D form or X form instruction. Used for extended mnemonics for 1542 the comparison instructions. */ 1543#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21)) 1544#define OPL_MASK OPL (0x3f,1) 1545 1546/* An A form instruction. */ 1547#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1)) 1548#define A_MASK A (0x3f, 0x1f, 1) 1549 1550/* An A_MASK with the FRB field fixed. */ 1551#define AFRB_MASK (A_MASK | FRB_MASK) 1552 1553/* An A_MASK with the FRC field fixed. */ 1554#define AFRC_MASK (A_MASK | FRC_MASK) 1555 1556/* An A_MASK with the FRA and FRC fields fixed. */ 1557#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK) 1558 1559/* An AFRAFRC_MASK, but with L bit clear. */ 1560#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16)) 1561 1562/* A B form instruction. */ 1563#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1)) 1564#define B_MASK B (0x3f, 1, 1) 1565 1566/* A B form instruction setting the BO field. */ 1567#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 1568#define BBO_MASK BBO (0x3f, 0x1f, 1, 1) 1569 1570/* A BBO_MASK with the y bit of the BO field removed. This permits 1571 matching a conditional branch regardless of the setting of the y 1572 bit. Similarly for the 'at' bits used for power4 branch hints. */ 1573#define Y_MASK (((unsigned long) 1) << 21) 1574#define AT1_MASK (((unsigned long) 3) << 21) 1575#define AT2_MASK (((unsigned long) 9) << 21) 1576#define BBOY_MASK (BBO_MASK &~ Y_MASK) 1577#define BBOAT_MASK (BBO_MASK &~ AT1_MASK) 1578 1579/* A B form instruction setting the BO field and the condition bits of 1580 the BI field. */ 1581#define BBOCB(op, bo, cb, aa, lk) \ 1582 (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16)) 1583#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1) 1584 1585/* A BBOCB_MASK with the y bit of the BO field removed. */ 1586#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) 1587#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) 1588#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) 1589 1590/* A BBOYCB_MASK in which the BI field is fixed. */ 1591#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) 1592#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) 1593 1594/* An Context form instruction. */ 1595#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) 1596#define CTX_MASK CTX(0x3f, 0x7) 1597 1598/* An User Context form instruction. */ 1599#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 1600#define UCTX_MASK UCTX(0x3f, 0x1f) 1601 1602/* The main opcode mask with the RA field clear. */ 1603#define DRA_MASK (OP_MASK | RA_MASK) 1604 1605/* A DS form instruction. */ 1606#define DSO(op, xop) (OP (op) | ((xop) & 0x3)) 1607#define DS_MASK DSO (0x3f, 3) 1608 1609/* A DE form instruction. */ 1610#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) 1611#define DE_MASK DEO (0x3e, 0xf) 1612 1613/* An EVSEL form instruction. */ 1614#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) 1615#define EVSEL_MASK EVSEL(0x3f, 0xff) 1616 1617/* An M form instruction. */ 1618#define M(op, rc) (OP (op) | ((rc) & 1)) 1619#define M_MASK M (0x3f, 1) 1620 1621/* An M form instruction with the ME field specified. */ 1622#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1)) 1623 1624/* An M_MASK with the MB and ME fields fixed. */ 1625#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK) 1626 1627/* An M_MASK with the SH and ME fields fixed. */ 1628#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK) 1629 1630/* An MD form instruction. */ 1631#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1)) 1632#define MD_MASK MD (0x3f, 0x7, 1) 1633 1634/* An MD_MASK with the MB field fixed. */ 1635#define MDMB_MASK (MD_MASK | MB6_MASK) 1636 1637/* An MD_MASK with the SH field fixed. */ 1638#define MDSH_MASK (MD_MASK | SH6_MASK) 1639 1640/* An MDS form instruction. */ 1641#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1)) 1642#define MDS_MASK MDS (0x3f, 0xf, 1) 1643 1644/* An MDS_MASK with the MB field fixed. */ 1645#define MDSMB_MASK (MDS_MASK | MB6_MASK) 1646 1647/* An SC form instruction. */ 1648#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) 1649#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) 1650 1651/* An VX form instruction. */ 1652#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) 1653 1654/* The mask for an VX form instruction. */ 1655#define VX_MASK VX(0x3f, 0x7ff) 1656 1657/* An VA form instruction. */ 1658#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) 1659 1660/* The mask for an VA form instruction. */ 1661#define VXA_MASK VXA(0x3f, 0x3f) 1662 1663/* An VXR form instruction. */ 1664#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) 1665 1666/* The mask for a VXR form instruction. */ 1667#define VXR_MASK VXR(0x3f, 0x3ff, 1) 1668 1669/* An X form instruction. */ 1670#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1671 1672/* A Z form instruction. */ 1673#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1)) 1674 1675/* An X form instruction with the RC bit specified. */ 1676#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1)) 1677 1678/* A Z form instruction with the RC bit specified. */ 1679#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1)) 1680 1681/* The mask for an X form instruction. */ 1682#define X_MASK XRC (0x3f, 0x3ff, 1) 1683 1684/* The mask for a Z form instruction. */ 1685#define Z_MASK ZRC (0x3f, 0x1ff, 1) 1686 1687/* An X_MASK with the RA field fixed. */ 1688#define XRA_MASK (X_MASK | RA_MASK) 1689 1690/* An X_MASK with the RB field fixed. */ 1691#define XRB_MASK (X_MASK | RB_MASK) 1692 1693/* An X_MASK with the RT field fixed. */ 1694#define XRT_MASK (X_MASK | RT_MASK) 1695 1696/* An XRT_MASK mask with the L bits clear. */ 1697#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21)) 1698 1699/* An X_MASK with the RA and RB fields fixed. */ 1700#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) 1701 1702/* An XRARB_MASK, but with the L bit clear. */ 1703#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) 1704 1705/* An X_MASK with the RT and RA fields fixed. */ 1706#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK) 1707 1708/* An XRTRA_MASK, but with L bit clear. */ 1709#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21)) 1710 1711/* An X form instruction with the L bit specified. */ 1712#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21)) 1713 1714/* The mask for an X form comparison instruction. */ 1715#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22)) 1716 1717/* The mask for an X form comparison instruction with the L field 1718 fixed. */ 1719#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21)) 1720 1721/* An X form trap instruction with the TO field specified. */ 1722#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21)) 1723#define XTO_MASK (X_MASK | TO_MASK) 1724 1725/* An X form tlb instruction with the SH field specified. */ 1726#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) 1727#define XTLB_MASK (X_MASK | SH_MASK) 1728 1729/* An X form sync instruction. */ 1730#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) 1731 1732/* An X form sync instruction with everything filled in except the LS field. */ 1733#define XSYNC_MASK (0xff9fffff) 1734 1735/* An X_MASK, but with the EH bit clear. */ 1736#define XEH_MASK (X_MASK & ~((unsigned long )1)) 1737 1738/* An X form AltiVec dss instruction. */ 1739#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) 1740#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) 1741 1742/* An XFL form instruction. */ 1743#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) 1744#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) 1745 1746/* An X form isel instruction. */ 1747#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) 1748#define XISEL_MASK XISEL(0x3f, 0x1f) 1749 1750/* An XL form instruction with the LK field set to 0. */ 1751#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) 1752 1753/* An XL form instruction which uses the LK field. */ 1754#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1)) 1755 1756/* The mask for an XL form instruction. */ 1757#define XL_MASK XLLK (0x3f, 0x3ff, 1) 1758 1759/* An XL form instruction which explicitly sets the BO field. */ 1760#define XLO(op, bo, xop, lk) \ 1761 (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21)) 1762#define XLO_MASK (XL_MASK | BO_MASK) 1763 1764/* An XL form instruction which explicitly sets the y bit of the BO 1765 field. */ 1766#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21)) 1767#define XLYLK_MASK (XL_MASK | Y_MASK) 1768 1769/* An XL form instruction which sets the BO field and the condition 1770 bits of the BI field. */ 1771#define XLOCB(op, bo, cb, xop, lk) \ 1772 (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16)) 1773#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1) 1774 1775/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed. */ 1776#define XLBB_MASK (XL_MASK | BB_MASK) 1777#define XLYBB_MASK (XLYLK_MASK | BB_MASK) 1778#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK) 1779 1780/* A mask for branch instructions using the BH field. */ 1781#define XLBH_MASK (XL_MASK | (0x1c << 11)) 1782 1783/* An XL_MASK with the BO and BB fields fixed. */ 1784#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK) 1785 1786/* An XL_MASK with the BO, BI and BB fields fixed. */ 1787#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK) 1788 1789/* An XO form instruction. */ 1790#define XO(op, xop, oe, rc) \ 1791 (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1)) 1792#define XO_MASK XO (0x3f, 0x1ff, 1, 1) 1793 1794/* An XO_MASK with the RB field fixed. */ 1795#define XORB_MASK (XO_MASK | RB_MASK) 1796 1797/* An XS form instruction. */ 1798#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1)) 1799#define XS_MASK XS (0x3f, 0x1ff, 1) 1800 1801/* A mask for the FXM version of an XFX form instruction. */ 1802#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20)) 1803 1804/* An XFX form instruction with the FXM field filled in. */ 1805#define XFXM(op, xop, fxm, p4) \ 1806 (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \ 1807 | ((unsigned long)(p4) << 20)) 1808 1809/* An XFX form instruction with the SPR field filled in. */ 1810#define XSPR(op, xop, spr) \ 1811 (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6)) 1812#define XSPR_MASK (X_MASK | SPR_MASK) 1813 1814/* An XFX form instruction with the SPR field filled in except for the 1815 SPRBAT field. */ 1816#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK) 1817 1818/* An XFX form instruction with the SPR field filled in except for the 1819 SPRG field. */ 1820#define XSPRG_MASK (XSPR_MASK & ~(0x17 << 16)) 1821 1822/* An X form instruction with everything filled in except the E field. */ 1823#define XE_MASK (0xffff7fff) 1824 1825/* An X form user context instruction. */ 1826#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) 1827#define XUC_MASK XUC(0x3f, 0x1f) 1828 1829/* The BO encodings used in extended conditional branch mnemonics. */ 1830#define BODNZF (0x0) 1831#define BODNZFP (0x1) 1832#define BODZF (0x2) 1833#define BODZFP (0x3) 1834#define BODNZT (0x8) 1835#define BODNZTP (0x9) 1836#define BODZT (0xa) 1837#define BODZTP (0xb) 1838 1839#define BOF (0x4) 1840#define BOFP (0x5) 1841#define BOFM4 (0x6) 1842#define BOFP4 (0x7) 1843#define BOT (0xc) 1844#define BOTP (0xd) 1845#define BOTM4 (0xe) 1846#define BOTP4 (0xf) 1847 1848#define BODNZ (0x10) 1849#define BODNZP (0x11) 1850#define BODZ (0x12) 1851#define BODZP (0x13) 1852#define BODNZM4 (0x18) 1853#define BODNZP4 (0x19) 1854#define BODZM4 (0x1a) 1855#define BODZP4 (0x1b) 1856 1857#define BOU (0x14) 1858 1859/* The BI condition bit encodings used in extended conditional branch 1860 mnemonics. */ 1861#define CBLT (0) 1862#define CBGT (1) 1863#define CBEQ (2) 1864#define CBSO (3) 1865 1866/* The TO encodings used in extended trap mnemonics. */ 1867#define TOLGT (0x1) 1868#define TOLLT (0x2) 1869#define TOEQ (0x4) 1870#define TOLGE (0x5) 1871#define TOLNL (0x5) 1872#define TOLLE (0x6) 1873#define TOLNG (0x6) 1874#define TOGT (0x8) 1875#define TOGE (0xc) 1876#define TONL (0xc) 1877#define TOLT (0x10) 1878#define TOLE (0x14) 1879#define TONG (0x14) 1880#define TONE (0x18) 1881#define TOU (0x1f) 1882 1883/* Smaller names for the flags so each entry in the opcodes table will 1884 fit on a single line. */ 1885#undef PPC 1886#define PPC PPC_OPCODE_PPC 1887#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON 1888#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM 1889#define POWER4 PPC_OPCODE_POWER4 1890#define POWER5 PPC_OPCODE_POWER5 1891#define POWER6 PPC_OPCODE_POWER6 1892#define CELL PPC_OPCODE_CELL 1893#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC 1894#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC 1895#define PPC403 PPC_OPCODE_403 1896#define PPC405 PPC403 1897#define PPC440 PPC_OPCODE_440 1898#define PPC750 PPC 1899#define PPC860 PPC 1900#define PPCVEC PPC_OPCODE_ALTIVEC 1901#define POWER PPC_OPCODE_POWER 1902#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1903#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 1904#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 1905#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON 1906#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 1907#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 1908#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON 1909#define MFDEC1 PPC_OPCODE_POWER 1910#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE 1911#define BOOKE PPC_OPCODE_BOOKE 1912#define BOOKE64 PPC_OPCODE_BOOKE64 1913#define CLASSIC PPC_OPCODE_CLASSIC 1914#define PPCE300 PPC_OPCODE_E300 1915#define PPCSPE PPC_OPCODE_SPE 1916#define PPCISEL PPC_OPCODE_ISEL 1917#define PPCEFS PPC_OPCODE_EFS 1918#define PPCBRLK PPC_OPCODE_BRLOCK 1919#define PPCPMR PPC_OPCODE_PMR 1920#define PPCCHLK PPC_OPCODE_CACHELCK 1921#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 1922#define PPCRFMCI PPC_OPCODE_RFMCI 1923 1924/* The opcode table. 1925 1926 The format of the opcode table is: 1927 1928 NAME OPCODE MASK FLAGS { OPERANDS } 1929 1930 NAME is the name of the instruction. 1931 OPCODE is the instruction opcode. 1932 MASK is the opcode mask; this is used to tell the disassembler 1933 which bits in the actual opcode must match OPCODE. 1934 FLAGS are flags indicated what processors support the instruction. 1935 OPERANDS is the list of operands. 1936 1937 The disassembler reads the table in order and prints the first 1938 instruction which matches, so this table is sorted to put more 1939 specific instructions before more general instructions. It is also 1940 sorted by major opcode. */ 1941 1942const struct powerpc_opcode powerpc_opcodes[] = { 1943{ "attn", X(0,256), X_MASK, POWER4, { 0 } }, 1944{ "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, 1945{ "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, 1946{ "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, 1947{ "tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, { RA, SI } }, 1948{ "tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, { RA, SI } }, 1949{ "tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, { RA, SI } }, 1950{ "tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, { RA, SI } }, 1951{ "tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, { RA, SI } }, 1952{ "tdgei", OPTO(2,TOGE), OPTO_MASK, PPC64, { RA, SI } }, 1953{ "tdnli", OPTO(2,TONL), OPTO_MASK, PPC64, { RA, SI } }, 1954{ "tdlti", OPTO(2,TOLT), OPTO_MASK, PPC64, { RA, SI } }, 1955{ "tdlei", OPTO(2,TOLE), OPTO_MASK, PPC64, { RA, SI } }, 1956{ "tdngi", OPTO(2,TONG), OPTO_MASK, PPC64, { RA, SI } }, 1957{ "tdnei", OPTO(2,TONE), OPTO_MASK, PPC64, { RA, SI } }, 1958{ "tdi", OP(2), OP_MASK, PPC64, { TO, RA, SI } }, 1959 1960{ "twlgti", OPTO(3,TOLGT), OPTO_MASK, PPCCOM, { RA, SI } }, 1961{ "tlgti", OPTO(3,TOLGT), OPTO_MASK, PWRCOM, { RA, SI } }, 1962{ "twllti", OPTO(3,TOLLT), OPTO_MASK, PPCCOM, { RA, SI } }, 1963{ "tllti", OPTO(3,TOLLT), OPTO_MASK, PWRCOM, { RA, SI } }, 1964{ "tweqi", OPTO(3,TOEQ), OPTO_MASK, PPCCOM, { RA, SI } }, 1965{ "teqi", OPTO(3,TOEQ), OPTO_MASK, PWRCOM, { RA, SI } }, 1966{ "twlgei", OPTO(3,TOLGE), OPTO_MASK, PPCCOM, { RA, SI } }, 1967{ "tlgei", OPTO(3,TOLGE), OPTO_MASK, PWRCOM, { RA, SI } }, 1968{ "twlnli", OPTO(3,TOLNL), OPTO_MASK, PPCCOM, { RA, SI } }, 1969{ "tlnli", OPTO(3,TOLNL), OPTO_MASK, PWRCOM, { RA, SI } }, 1970{ "twllei", OPTO(3,TOLLE), OPTO_MASK, PPCCOM, { RA, SI } }, 1971{ "tllei", OPTO(3,TOLLE), OPTO_MASK, PWRCOM, { RA, SI } }, 1972{ "twlngi", OPTO(3,TOLNG), OPTO_MASK, PPCCOM, { RA, SI } }, 1973{ "tlngi", OPTO(3,TOLNG), OPTO_MASK, PWRCOM, { RA, SI } }, 1974{ "twgti", OPTO(3,TOGT), OPTO_MASK, PPCCOM, { RA, SI } }, 1975{ "tgti", OPTO(3,TOGT), OPTO_MASK, PWRCOM, { RA, SI } }, 1976{ "twgei", OPTO(3,TOGE), OPTO_MASK, PPCCOM, { RA, SI } }, 1977{ "tgei", OPTO(3,TOGE), OPTO_MASK, PWRCOM, { RA, SI } }, 1978{ "twnli", OPTO(3,TONL), OPTO_MASK, PPCCOM, { RA, SI } }, 1979{ "tnli", OPTO(3,TONL), OPTO_MASK, PWRCOM, { RA, SI } }, 1980{ "twlti", OPTO(3,TOLT), OPTO_MASK, PPCCOM, { RA, SI } }, 1981{ "tlti", OPTO(3,TOLT), OPTO_MASK, PWRCOM, { RA, SI } }, 1982{ "twlei", OPTO(3,TOLE), OPTO_MASK, PPCCOM, { RA, SI } }, 1983{ "tlei", OPTO(3,TOLE), OPTO_MASK, PWRCOM, { RA, SI } }, 1984{ "twngi", OPTO(3,TONG), OPTO_MASK, PPCCOM, { RA, SI } }, 1985{ "tngi", OPTO(3,TONG), OPTO_MASK, PWRCOM, { RA, SI } }, 1986{ "twnei", OPTO(3,TONE), OPTO_MASK, PPCCOM, { RA, SI } }, 1987{ "tnei", OPTO(3,TONE), OPTO_MASK, PWRCOM, { RA, SI } }, 1988{ "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, 1989{ "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, 1990 1991{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1992{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1993{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1994{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1995{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1996{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1997{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1998{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 1999{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2000{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2001{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2002{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2003{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2004{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2005{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2006{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2007{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2008{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2009{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2010{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2011{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2012{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2013{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2014{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2015{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2016{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2017{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2018{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2019{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2020{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2021{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2022{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2023{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2024{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2025{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2026{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2027{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2028{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2029{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2030{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2031{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2032{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2033{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2034{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2035{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2036{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2037{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2038{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2039{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2040{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2041{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2042{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2043{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2044{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2045{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2046{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2047{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2048{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2049{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2050{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, 2051{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2052{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2053{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2054{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2055{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2056{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2057{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2058{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2059{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2060{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2061{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2062{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2063{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2064{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2065{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2066{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2067{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2068{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2069{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2070{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2071{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2072{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2073{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2074{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, 2075{ "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, 2076{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, 2077 2078 /* Double-precision opcodes. */ 2079 /* Some of these conflict with AltiVec, so move them before, since 2080 PPCVEC includes the PPC_OPCODE_PPC set. */ 2081{ "efscfd", VX(4, 719), VX_MASK, PPCEFS, { RS, RB } }, 2082{ "efdabs", VX(4, 740), VX_MASK, PPCEFS, { RS, RA } }, 2083{ "efdnabs", VX(4, 741), VX_MASK, PPCEFS, { RS, RA } }, 2084{ "efdneg", VX(4, 742), VX_MASK, PPCEFS, { RS, RA } }, 2085{ "efdadd", VX(4, 736), VX_MASK, PPCEFS, { RS, RA, RB } }, 2086{ "efdsub", VX(4, 737), VX_MASK, PPCEFS, { RS, RA, RB } }, 2087{ "efdmul", VX(4, 744), VX_MASK, PPCEFS, { RS, RA, RB } }, 2088{ "efddiv", VX(4, 745), VX_MASK, PPCEFS, { RS, RA, RB } }, 2089{ "efdcmpgt", VX(4, 748), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2090{ "efdcmplt", VX(4, 749), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2091{ "efdcmpeq", VX(4, 750), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2092{ "efdtstgt", VX(4, 764), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2093{ "efdtstlt", VX(4, 765), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2094{ "efdtsteq", VX(4, 766), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2095{ "efdcfsi", VX(4, 753), VX_MASK, PPCEFS, { RS, RB } }, 2096{ "efdcfsid", VX(4, 739), VX_MASK, PPCEFS, { RS, RB } }, 2097{ "efdcfui", VX(4, 752), VX_MASK, PPCEFS, { RS, RB } }, 2098{ "efdcfuid", VX(4, 738), VX_MASK, PPCEFS, { RS, RB } }, 2099{ "efdcfsf", VX(4, 755), VX_MASK, PPCEFS, { RS, RB } }, 2100{ "efdcfuf", VX(4, 754), VX_MASK, PPCEFS, { RS, RB } }, 2101{ "efdctsi", VX(4, 757), VX_MASK, PPCEFS, { RS, RB } }, 2102{ "efdctsidz",VX(4, 747), VX_MASK, PPCEFS, { RS, RB } }, 2103{ "efdctsiz", VX(4, 762), VX_MASK, PPCEFS, { RS, RB } }, 2104{ "efdctui", VX(4, 756), VX_MASK, PPCEFS, { RS, RB } }, 2105{ "efdctuidz",VX(4, 746), VX_MASK, PPCEFS, { RS, RB } }, 2106{ "efdctuiz", VX(4, 760), VX_MASK, PPCEFS, { RS, RB } }, 2107{ "efdctsf", VX(4, 759), VX_MASK, PPCEFS, { RS, RB } }, 2108{ "efdctuf", VX(4, 758), VX_MASK, PPCEFS, { RS, RB } }, 2109{ "efdcfs", VX(4, 751), VX_MASK, PPCEFS, { RS, RB } }, 2110 /* End of double-precision opcodes. */ 2111 2112{ "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, 2113{ "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, 2114{ "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, 2115{ "vaddshs", VX(4, 832), VX_MASK, PPCVEC, { VD, VA, VB } }, 2116{ "vaddsws", VX(4, 896), VX_MASK, PPCVEC, { VD, VA, VB } }, 2117{ "vaddubm", VX(4, 0), VX_MASK, PPCVEC, { VD, VA, VB } }, 2118{ "vaddubs", VX(4, 512), VX_MASK, PPCVEC, { VD, VA, VB } }, 2119{ "vadduhm", VX(4, 64), VX_MASK, PPCVEC, { VD, VA, VB } }, 2120{ "vadduhs", VX(4, 576), VX_MASK, PPCVEC, { VD, VA, VB } }, 2121{ "vadduwm", VX(4, 128), VX_MASK, PPCVEC, { VD, VA, VB } }, 2122{ "vadduws", VX(4, 640), VX_MASK, PPCVEC, { VD, VA, VB } }, 2123{ "vand", VX(4, 1028), VX_MASK, PPCVEC, { VD, VA, VB } }, 2124{ "vandc", VX(4, 1092), VX_MASK, PPCVEC, { VD, VA, VB } }, 2125{ "vavgsb", VX(4, 1282), VX_MASK, PPCVEC, { VD, VA, VB } }, 2126{ "vavgsh", VX(4, 1346), VX_MASK, PPCVEC, { VD, VA, VB } }, 2127{ "vavgsw", VX(4, 1410), VX_MASK, PPCVEC, { VD, VA, VB } }, 2128{ "vavgub", VX(4, 1026), VX_MASK, PPCVEC, { VD, VA, VB } }, 2129{ "vavguh", VX(4, 1090), VX_MASK, PPCVEC, { VD, VA, VB } }, 2130{ "vavguw", VX(4, 1154), VX_MASK, PPCVEC, { VD, VA, VB } }, 2131{ "vcfsx", VX(4, 842), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2132{ "vcfux", VX(4, 778), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2133{ "vcmpbfp", VXR(4, 966, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2134{ "vcmpbfp.", VXR(4, 966, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2135{ "vcmpeqfp", VXR(4, 198, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2136{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2137{ "vcmpequb", VXR(4, 6, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2138{ "vcmpequb.", VXR(4, 6, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2139{ "vcmpequh", VXR(4, 70, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2140{ "vcmpequh.", VXR(4, 70, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2141{ "vcmpequw", VXR(4, 134, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2142{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2143{ "vcmpgefp", VXR(4, 454, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2144{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2145{ "vcmpgtfp", VXR(4, 710, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2146{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2147{ "vcmpgtsb", VXR(4, 774, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2148{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2149{ "vcmpgtsh", VXR(4, 838, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2150{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2151{ "vcmpgtsw", VXR(4, 902, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2152{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2153{ "vcmpgtub", VXR(4, 518, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2154{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2155{ "vcmpgtuh", VXR(4, 582, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2156{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2157{ "vcmpgtuw", VXR(4, 646, 0), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2158{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC, { VD, VA, VB } }, 2159{ "vctsxs", VX(4, 970), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2160{ "vctuxs", VX(4, 906), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2161{ "vexptefp", VX(4, 394), VX_MASK, PPCVEC, { VD, VB } }, 2162{ "vlogefp", VX(4, 458), VX_MASK, PPCVEC, { VD, VB } }, 2163{ "vmaddfp", VXA(4, 46), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 2164{ "vmaxfp", VX(4, 1034), VX_MASK, PPCVEC, { VD, VA, VB } }, 2165{ "vmaxsb", VX(4, 258), VX_MASK, PPCVEC, { VD, VA, VB } }, 2166{ "vmaxsh", VX(4, 322), VX_MASK, PPCVEC, { VD, VA, VB } }, 2167{ "vmaxsw", VX(4, 386), VX_MASK, PPCVEC, { VD, VA, VB } }, 2168{ "vmaxub", VX(4, 2), VX_MASK, PPCVEC, { VD, VA, VB } }, 2169{ "vmaxuh", VX(4, 66), VX_MASK, PPCVEC, { VD, VA, VB } }, 2170{ "vmaxuw", VX(4, 130), VX_MASK, PPCVEC, { VD, VA, VB } }, 2171{ "vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2172{ "vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2173{ "vminfp", VX(4, 1098), VX_MASK, PPCVEC, { VD, VA, VB } }, 2174{ "vminsb", VX(4, 770), VX_MASK, PPCVEC, { VD, VA, VB } }, 2175{ "vminsh", VX(4, 834), VX_MASK, PPCVEC, { VD, VA, VB } }, 2176{ "vminsw", VX(4, 898), VX_MASK, PPCVEC, { VD, VA, VB } }, 2177{ "vminub", VX(4, 514), VX_MASK, PPCVEC, { VD, VA, VB } }, 2178{ "vminuh", VX(4, 578), VX_MASK, PPCVEC, { VD, VA, VB } }, 2179{ "vminuw", VX(4, 642), VX_MASK, PPCVEC, { VD, VA, VB } }, 2180{ "vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2181{ "vmrghb", VX(4, 12), VX_MASK, PPCVEC, { VD, VA, VB } }, 2182{ "vmrghh", VX(4, 76), VX_MASK, PPCVEC, { VD, VA, VB } }, 2183{ "vmrghw", VX(4, 140), VX_MASK, PPCVEC, { VD, VA, VB } }, 2184{ "vmrglb", VX(4, 268), VX_MASK, PPCVEC, { VD, VA, VB } }, 2185{ "vmrglh", VX(4, 332), VX_MASK, PPCVEC, { VD, VA, VB } }, 2186{ "vmrglw", VX(4, 396), VX_MASK, PPCVEC, { VD, VA, VB } }, 2187{ "vmsummbm", VXA(4, 37), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2188{ "vmsumshm", VXA(4, 40), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2189{ "vmsumshs", VXA(4, 41), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2190{ "vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2191{ "vmsumuhm", VXA(4, 38), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2192{ "vmsumuhs", VXA(4, 39), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2193{ "vmulesb", VX(4, 776), VX_MASK, PPCVEC, { VD, VA, VB } }, 2194{ "vmulesh", VX(4, 840), VX_MASK, PPCVEC, { VD, VA, VB } }, 2195{ "vmuleub", VX(4, 520), VX_MASK, PPCVEC, { VD, VA, VB } }, 2196{ "vmuleuh", VX(4, 584), VX_MASK, PPCVEC, { VD, VA, VB } }, 2197{ "vmulosb", VX(4, 264), VX_MASK, PPCVEC, { VD, VA, VB } }, 2198{ "vmulosh", VX(4, 328), VX_MASK, PPCVEC, { VD, VA, VB } }, 2199{ "vmuloub", VX(4, 8), VX_MASK, PPCVEC, { VD, VA, VB } }, 2200{ "vmulouh", VX(4, 72), VX_MASK, PPCVEC, { VD, VA, VB } }, 2201{ "vnmsubfp", VXA(4, 47), VXA_MASK, PPCVEC, { VD, VA, VC, VB } }, 2202{ "vnor", VX(4, 1284), VX_MASK, PPCVEC, { VD, VA, VB } }, 2203{ "vor", VX(4, 1156), VX_MASK, PPCVEC, { VD, VA, VB } }, 2204{ "vperm", VXA(4, 43), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2205{ "vpkpx", VX(4, 782), VX_MASK, PPCVEC, { VD, VA, VB } }, 2206{ "vpkshss", VX(4, 398), VX_MASK, PPCVEC, { VD, VA, VB } }, 2207{ "vpkshus", VX(4, 270), VX_MASK, PPCVEC, { VD, VA, VB } }, 2208{ "vpkswss", VX(4, 462), VX_MASK, PPCVEC, { VD, VA, VB } }, 2209{ "vpkswus", VX(4, 334), VX_MASK, PPCVEC, { VD, VA, VB } }, 2210{ "vpkuhum", VX(4, 14), VX_MASK, PPCVEC, { VD, VA, VB } }, 2211{ "vpkuhus", VX(4, 142), VX_MASK, PPCVEC, { VD, VA, VB } }, 2212{ "vpkuwum", VX(4, 78), VX_MASK, PPCVEC, { VD, VA, VB } }, 2213{ "vpkuwus", VX(4, 206), VX_MASK, PPCVEC, { VD, VA, VB } }, 2214{ "vrefp", VX(4, 266), VX_MASK, PPCVEC, { VD, VB } }, 2215{ "vrfim", VX(4, 714), VX_MASK, PPCVEC, { VD, VB } }, 2216{ "vrfin", VX(4, 522), VX_MASK, PPCVEC, { VD, VB } }, 2217{ "vrfip", VX(4, 650), VX_MASK, PPCVEC, { VD, VB } }, 2218{ "vrfiz", VX(4, 586), VX_MASK, PPCVEC, { VD, VB } }, 2219{ "vrlb", VX(4, 4), VX_MASK, PPCVEC, { VD, VA, VB } }, 2220{ "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, 2221{ "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, 2222{ "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, 2223{ "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, 2224{ "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, 2225{ "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, 2226{ "vsldoi", VXA(4, 44), VXA_MASK, PPCVEC, { VD, VA, VB, SHB } }, 2227{ "vslh", VX(4, 324), VX_MASK, PPCVEC, { VD, VA, VB } }, 2228{ "vslo", VX(4, 1036), VX_MASK, PPCVEC, { VD, VA, VB } }, 2229{ "vslw", VX(4, 388), VX_MASK, PPCVEC, { VD, VA, VB } }, 2230{ "vspltb", VX(4, 524), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2231{ "vsplth", VX(4, 588), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2232{ "vspltisb", VX(4, 780), VX_MASK, PPCVEC, { VD, SIMM } }, 2233{ "vspltish", VX(4, 844), VX_MASK, PPCVEC, { VD, SIMM } }, 2234{ "vspltisw", VX(4, 908), VX_MASK, PPCVEC, { VD, SIMM } }, 2235{ "vspltw", VX(4, 652), VX_MASK, PPCVEC, { VD, VB, UIMM } }, 2236{ "vsr", VX(4, 708), VX_MASK, PPCVEC, { VD, VA, VB } }, 2237{ "vsrab", VX(4, 772), VX_MASK, PPCVEC, { VD, VA, VB } }, 2238{ "vsrah", VX(4, 836), VX_MASK, PPCVEC, { VD, VA, VB } }, 2239{ "vsraw", VX(4, 900), VX_MASK, PPCVEC, { VD, VA, VB } }, 2240{ "vsrb", VX(4, 516), VX_MASK, PPCVEC, { VD, VA, VB } }, 2241{ "vsrh", VX(4, 580), VX_MASK, PPCVEC, { VD, VA, VB } }, 2242{ "vsro", VX(4, 1100), VX_MASK, PPCVEC, { VD, VA, VB } }, 2243{ "vsrw", VX(4, 644), VX_MASK, PPCVEC, { VD, VA, VB } }, 2244{ "vsubcuw", VX(4, 1408), VX_MASK, PPCVEC, { VD, VA, VB } }, 2245{ "vsubfp", VX(4, 74), VX_MASK, PPCVEC, { VD, VA, VB } }, 2246{ "vsubsbs", VX(4, 1792), VX_MASK, PPCVEC, { VD, VA, VB } }, 2247{ "vsubshs", VX(4, 1856), VX_MASK, PPCVEC, { VD, VA, VB } }, 2248{ "vsubsws", VX(4, 1920), VX_MASK, PPCVEC, { VD, VA, VB } }, 2249{ "vsububm", VX(4, 1024), VX_MASK, PPCVEC, { VD, VA, VB } }, 2250{ "vsububs", VX(4, 1536), VX_MASK, PPCVEC, { VD, VA, VB } }, 2251{ "vsubuhm", VX(4, 1088), VX_MASK, PPCVEC, { VD, VA, VB } }, 2252{ "vsubuhs", VX(4, 1600), VX_MASK, PPCVEC, { VD, VA, VB } }, 2253{ "vsubuwm", VX(4, 1152), VX_MASK, PPCVEC, { VD, VA, VB } }, 2254{ "vsubuws", VX(4, 1664), VX_MASK, PPCVEC, { VD, VA, VB } }, 2255{ "vsumsws", VX(4, 1928), VX_MASK, PPCVEC, { VD, VA, VB } }, 2256{ "vsum2sws", VX(4, 1672), VX_MASK, PPCVEC, { VD, VA, VB } }, 2257{ "vsum4sbs", VX(4, 1800), VX_MASK, PPCVEC, { VD, VA, VB } }, 2258{ "vsum4shs", VX(4, 1608), VX_MASK, PPCVEC, { VD, VA, VB } }, 2259{ "vsum4ubs", VX(4, 1544), VX_MASK, PPCVEC, { VD, VA, VB } }, 2260{ "vupkhpx", VX(4, 846), VX_MASK, PPCVEC, { VD, VB } }, 2261{ "vupkhsb", VX(4, 526), VX_MASK, PPCVEC, { VD, VB } }, 2262{ "vupkhsh", VX(4, 590), VX_MASK, PPCVEC, { VD, VB } }, 2263{ "vupklpx", VX(4, 974), VX_MASK, PPCVEC, { VD, VB } }, 2264{ "vupklsb", VX(4, 654), VX_MASK, PPCVEC, { VD, VB } }, 2265{ "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, 2266{ "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, 2267 2268{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, 2269{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 2270{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, 2271{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, 2272{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, 2273{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, 2274{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, 2275{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, 2276{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, 2277{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, 2278{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, 2279{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, 2280{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, 2281 2282{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, 2283 2284{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, 2285{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, 2286{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, 2287{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, 2288{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, 2289{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, 2290{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, 2291{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, 2292{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, 2293{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, 2294 2295{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, 2296{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2297{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, 2298{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2299{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, 2300{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, 2301{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2302{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, 2303{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, 2304{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, 2305{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, 2306{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, 2307{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, 2308{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, 2309 2310{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2311{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2312{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2313{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2314{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2315{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, 2316 2317{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2318{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, 2319{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2320{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, 2321{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2322{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, 2323{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2324{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, 2325{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2326{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, 2327{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2328{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, 2329{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2330{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, 2331{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2332{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, 2333{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 2334{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, 2335{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 2336{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, 2337{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, 2338{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, 2339 2340{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2341{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, 2342{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2343{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, 2344{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, 2345{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, 2346{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2347{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, 2348{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2349{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, 2350{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2351{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, 2352{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, 2353{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, 2354 2355{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, 2356{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, 2357{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, 2358{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, 2359{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, 2360{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, 2361{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, 2362{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2363{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2364{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2365{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2366{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2367{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, 2368{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, 2369{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, 2370{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, 2371{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, 2372{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, 2373{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, 2374{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, 2375{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, 2376{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, 2377{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, 2378 2379{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, 2380{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, 2381{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, 2382{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, 2383{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, 2384{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, 2385{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, 2386{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2387{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2388{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2389{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2390{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2391{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, 2392{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, 2393{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, 2394{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, 2395{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, 2396{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, 2397{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, 2398{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, 2399{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, 2400{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, 2401{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, 2402 2403{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, 2404{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, 2405{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, 2406{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, 2407{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, 2408{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, 2409{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, 2410{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, 2411{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, 2412{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, 2413{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, 2414{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, 2415{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, 2416{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, 2417{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, 2418{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, 2419 2420{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, 2421{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, 2422{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, 2423{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, 2424{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, 2425{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, 2426{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, 2427{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, 2428{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, 2429{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, 2430{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, 2431{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, 2432 2433{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, 2434{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, 2435{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, 2436{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, 2437{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, 2438{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, 2439{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, 2440{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, 2441{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, 2442{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, 2443{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, 2444{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, 2445 2446{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, 2447{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, 2448{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, 2449{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, 2450{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, 2451{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, 2452 2453{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, 2454{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, 2455{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, 2456{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, 2457{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, 2458{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, 2459 2460{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, 2461{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, 2462{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, 2463{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, 2464{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, 2465{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, 2466{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, 2467{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, 2468 2469{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, 2470{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, 2471 2472{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, 2473{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, 2474{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, 2475{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, 2476 2477{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, 2478{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, 2479{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, 2480{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, 2481 2482{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, 2483{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, 2484{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, 2485{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, 2486{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, 2487{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, 2488{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, 2489{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, 2490 2491{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, 2492{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, 2493{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, 2494{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, 2495 2496{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, 2497{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, 2498{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, 2499{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, 2500 2501{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, 2502{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, 2503{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, 2504{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, 2505 2506{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, 2507{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, 2508{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, 2509{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, 2510 2511{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, 2512 2513{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, 2514{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, 2515 2516{ "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, 2517{ "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, 2518 2519{ "subfic", OP(8), OP_MASK, PPCCOM, { RT, RA, SI } }, 2520{ "sfi", OP(8), OP_MASK, PWRCOM, { RT, RA, SI } }, 2521 2522{ "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, 2523 2524{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, 2525{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, 2526{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, 2527{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, 2528 2529{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, 2530{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, 2531{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, 2532{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, 2533 2534{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, 2535{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, 2536{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, 2537{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, 2538 2539{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, 2540{ "ai", OP(12), OP_MASK, PWRCOM, { RT, RA, SI } }, 2541{ "subic", OP(12), OP_MASK, PPCCOM, { RT, RA, NSI } }, 2542 2543{ "addic.", OP(13), OP_MASK, PPCCOM, { RT, RA, SI } }, 2544{ "ai.", OP(13), OP_MASK, PWRCOM, { RT, RA, SI } }, 2545{ "subic.", OP(13), OP_MASK, PPCCOM, { RT, RA, NSI } }, 2546 2547{ "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, 2548{ "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, 2549{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, 2550{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, 2551{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 2552{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, 2553 2554{ "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, 2555{ "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, 2556{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, 2557{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, 2558{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, 2559 2560{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 2561{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 2562{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, 2563{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, 2564{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 2565{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 2566{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, 2567{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, 2568{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 2569{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 2570{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, 2571{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, 2572{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 2573{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 2574{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, 2575{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, 2576{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, 2577{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, 2578{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, 2579{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, 2580{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, 2581{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, 2582{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, 2583{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, 2584{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, 2585{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, 2586{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, 2587{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, 2588{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2589{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2590{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2591{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2592{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2593{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2594{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2595{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2596{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2597{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2598{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2599{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2600{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2601{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2602{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2603{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2604{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2605{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2606{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2607{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2608{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2609{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2610{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2611{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2612{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2613{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2614{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2615{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2616{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2617{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2618{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2619{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2620{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2621{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2622{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2623{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2624{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2625{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2626{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2627{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2628{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2629{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2630{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2631{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2632{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2633{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2634{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2635{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2636{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2637{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2638{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2639{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2640{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2641{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2642{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2643{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2644{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2645{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2646{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2647{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2648{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2649{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2650{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2651{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2652{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2653{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2654{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2655{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2656{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2657{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2658{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2659{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2660{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2661{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2662{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2663{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2664{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2665{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2666{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2667{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2668{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2669{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2670{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2671{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2672{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2673{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2674{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2675{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2676{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2677{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2678{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2679{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2680{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2681{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2682{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2683{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2684{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2685{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2686{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2687{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2688{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2689{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2690{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2691{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2692{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2693{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2694{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2695{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2696{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2697{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2698{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2699{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2700{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2701{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2702{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2703{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2704{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2705{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2706{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2707{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2708{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2709{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2710{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, 2711{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2712{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2713{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, 2714{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2715{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2716{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, 2717{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2718{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2719{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, 2720{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2721{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2722{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2723{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, 2724{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, 2725{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, 2726{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2727{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2728{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2729{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, 2730{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, 2731{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, 2732{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2733{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2734{ "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2735{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2736{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2737{ "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2738{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2739{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2740{ "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2741{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2742{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2743{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2744{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2745{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2746{ "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2747{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2748{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2749{ "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2750{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2751{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2752{ "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2753{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2754{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2755{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2756{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2757{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2758{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 2759{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 2760{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2761{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2762{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 2763{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 2764{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2765{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2766{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2767{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2768{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2769{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2770{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2771{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2772{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2773{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2774{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, 2775{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, 2776{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, 2777{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, 2778{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, 2779{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, 2780{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2781{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2782{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2783{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2784{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, 2785{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, 2786{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, 2787{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, 2788{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2789{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2790{ "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2791{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2792{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2793{ "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2794{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2795{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2796{ "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2797{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2798{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2799{ "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2800{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2801{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2802{ "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, 2803{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDM } }, 2804{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4, { BI, BDP } }, 2805{ "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, 2806{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2807{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2808{ "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, 2809{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDMA } }, 2810{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4, { BI, BDPA } }, 2811{ "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, 2812{ "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, 2813{ "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, 2814{ "bc", B(16,0,0), B_MASK, COM, { BO, BI, BD } }, 2815{ "bcl-", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDM } }, 2816{ "bcl+", B(16,0,1), B_MASK, PPCCOM, { BOE, BI, BDP } }, 2817{ "bcl", B(16,0,1), B_MASK, COM, { BO, BI, BD } }, 2818{ "bca-", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 2819{ "bca+", B(16,1,0), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 2820{ "bca", B(16,1,0), B_MASK, COM, { BO, BI, BDA } }, 2821{ "bcla-", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDMA } }, 2822{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } }, 2823{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } }, 2824 2825{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } }, 2826{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, 2827{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } }, 2828{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, 2829{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, 2830 2831{ "b", B(18,0,0), B_MASK, COM, { LI } }, 2832{ "bl", B(18,0,1), B_MASK, COM, { LI } }, 2833{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, 2834{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, 2835 2836{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, 2837 2838{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2839{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, 2840{ "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2841{ "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, 2842{ "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2843{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2844{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2845{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2846{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2847{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2848{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2849{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2850{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2851{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2852{ "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2853{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2854{ "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2855{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2856{ "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, 2857{ "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, 2858{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2859{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2860{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, 2861{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, 2862{ "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2863{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2864{ "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2865{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2866{ "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2867{ "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2868{ "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2869{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2870{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2871{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2872{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2873{ "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2874{ "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2875{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2876{ "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2877{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2878{ "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2879{ "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2880{ "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2881{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2882{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2883{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2884{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2885{ "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2886{ "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2887{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2888{ "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2889{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2890{ "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2891{ "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2892{ "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2893{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2894{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2895{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2896{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2897{ "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2898{ "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2899{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2900{ "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2901{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2902{ "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2903{ "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2904{ "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2905{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2906{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2907{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2908{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2909{ "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2910{ "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2911{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2912{ "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2913{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2914{ "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2915{ "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2916{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2917{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2918{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2919{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2920{ "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2921{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2922{ "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2923{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2924{ "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2925{ "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2926{ "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2927{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2928{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2929{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2930{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2931{ "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2932{ "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2933{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2934{ "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2935{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2936{ "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2937{ "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2938{ "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2939{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2940{ "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2941{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2942{ "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2943{ "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2944{ "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2945{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2946{ "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2947{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2948{ "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2949{ "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2950{ "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2951{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2952{ "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2953{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2954{ "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2955{ "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2956{ "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2957{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2958{ "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2959{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2960{ "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2961{ "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2962{ "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2963{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2964{ "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2965{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2966{ "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2967{ "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2968{ "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2969{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2970{ "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2971{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2972{ "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2973{ "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2974{ "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2975{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2976{ "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2977{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2978{ "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2979{ "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2980{ "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2981{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2982{ "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2983{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2984{ "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2985{ "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, 2986{ "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2987{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2988{ "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2989{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2990{ "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 2991{ "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, 2992{ "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 2993{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2994{ "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2995{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2996{ "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, 2997{ "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 2998{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 2999{ "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3000{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3001{ "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, 3002{ "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3003{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3004{ "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 3005{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3006{ "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 3007{ "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 3008{ "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3009{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3010{ "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 3011{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3012{ "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 3013{ "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 3014{ "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3015{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3016{ "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, 3017{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3018{ "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, 3019{ "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, 3020{ "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3021{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3022{ "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, 3023{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3024{ "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, 3025{ "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, 3026{ "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3027{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3028{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3029{ "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3030{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3031{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3032{ "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3033{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3034{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3035{ "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3036{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3037{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3038{ "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3039{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3040{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3041{ "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3042{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3043{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3044{ "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, 3045{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3046{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3047{ "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, 3048{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3049{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3050{ "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3051{ "bclrl+", XLYLK(19,16,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3052{ "bclr-", XLYLK(19,16,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3053{ "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3054{ "bclr", XLLK(19,16,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 3055{ "bclrl", XLLK(19,16,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 3056{ "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, 3057{ "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, 3058{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, 3059{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, 3060 3061{ "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, 3062 3063{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, 3064{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, 3065{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, 3066 3067{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, 3068{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, 3069 3070{ "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, 3071 3072{ "crandc", XL(19,129), XL_MASK, COM, { BT, BA, BB } }, 3073 3074{ "isync", XL(19,150), 0xffffffff, PPCCOM, { 0 } }, 3075{ "ics", XL(19,150), 0xffffffff, PWRCOM, { 0 } }, 3076 3077{ "crclr", XL(19,193), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 3078{ "crxor", XL(19,193), XL_MASK, COM, { BT, BA, BB } }, 3079 3080{ "crnand", XL(19,225), XL_MASK, COM, { BT, BA, BB } }, 3081 3082{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } }, 3083 3084{ "hrfid", XL(19,274), 0xffffffff, POWER5 | CELL, { 0 } }, 3085 3086{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } }, 3087{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } }, 3088 3089{ "doze", XL(19,402), 0xffffffff, POWER6, { 0 } }, 3090 3091{ "crorc", XL(19,417), XL_MASK, COM, { BT, BA, BB } }, 3092 3093{ "nap", XL(19,434), 0xffffffff, POWER6, { 0 } }, 3094 3095{ "crmove", XL(19,449), XL_MASK, PPCCOM, { BT, BA, BBA } }, 3096{ "cror", XL(19,449), XL_MASK, COM, { BT, BA, BB } }, 3097 3098{ "sleep", XL(19,466), 0xffffffff, POWER6, { 0 } }, 3099{ "rvwinkle", XL(19,498), 0xffffffff, POWER6, { 0 } }, 3100 3101{ "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, 3102{ "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, 3103{ "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3104{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3105{ "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3106{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3107{ "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3108{ "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3109{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3110{ "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3111{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3112{ "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3113{ "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3114{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3115{ "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3116{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3117{ "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3118{ "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3119{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3120{ "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3121{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3122{ "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3123{ "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3124{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3125{ "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3126{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3127{ "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3128{ "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3129{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3130{ "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3131{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3132{ "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3133{ "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3134{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3135{ "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3136{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3137{ "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3138{ "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3139{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3140{ "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3141{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3142{ "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3143{ "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3144{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3145{ "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3146{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3147{ "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3148{ "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3149{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3150{ "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3151{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3152{ "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3153{ "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3154{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3155{ "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3156{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3157{ "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3158{ "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3159{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3160{ "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3161{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3162{ "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3163{ "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3164{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3165{ "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3166{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3167{ "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3168{ "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3169{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3170{ "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3171{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3172{ "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3173{ "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3174{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3175{ "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3176{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3177{ "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3178{ "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3179{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3180{ "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3181{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3182{ "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3183{ "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3184{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3185{ "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3186{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3187{ "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3188{ "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3189{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3190{ "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3191{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3192{ "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3193{ "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3194{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3195{ "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3196{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3197{ "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3198{ "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3199{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3200{ "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3201{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3202{ "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3203{ "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3204{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3205{ "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3206{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3207{ "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3208{ "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3209{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3210{ "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3211{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3212{ "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3213{ "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, 3214{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3215{ "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3216{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3217{ "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, 3218{ "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, 3219{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3220{ "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3221{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, 3222{ "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, 3223{ "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 3224{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3225{ "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3226{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3227{ "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3228{ "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 3229{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3230{ "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3231{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3232{ "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3233{ "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, 3234{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3235{ "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3236{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, 3237{ "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, 3238{ "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, 3239{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3240{ "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3241{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, 3242{ "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, 3243{ "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3244{ "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3245{ "bcctrl-", XLYLK(19,528,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3246{ "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, 3247{ "bcctr", XLLK(19,528,0), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 3248{ "bcctrl", XLLK(19,528,1), XLBH_MASK, PPCCOM, { BO, BI, BH } }, 3249{ "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, 3250{ "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, 3251{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } }, 3252{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } }, 3253 3254{ "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3255{ "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3256 3257{ "rlwimi.", M(20,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3258{ "rlimi.", M(20,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3259 3260{ "rotlwi", MME(21,31,0), MMBME_MASK, PPCCOM, { RA, RS, SH } }, 3261{ "clrlwi", MME(21,31,0), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3262{ "rlwinm", M(21,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3263{ "rlinm", M(21,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3264{ "rotlwi.", MME(21,31,1), MMBME_MASK, PPCCOM, { RA,RS,SH } }, 3265{ "clrlwi.", MME(21,31,1), MSHME_MASK, PPCCOM, { RA, RS, MB } }, 3266{ "rlwinm.", M(21,1), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, 3267{ "rlinm.", M(21,1), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, 3268 3269{ "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 3270{ "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, 3271 3272{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, 3273{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, 3274{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, 3275{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, 3276 3277{ "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 3278{ "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 3279{ "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 3280{ "rotlw.", MME(23,31,1), MMBME_MASK, PPCCOM, { RA, RS, RB } }, 3281{ "rlwnm.", M(23,1), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, 3282{ "rlnm.", M(23,1), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, 3283 3284{ "nop", OP(24), 0xffffffff, PPCCOM, { 0 } }, 3285{ "ori", OP(24), OP_MASK, PPCCOM, { RA, RS, UI } }, 3286{ "oril", OP(24), OP_MASK, PWRCOM, { RA, RS, UI } }, 3287 3288{ "oris", OP(25), OP_MASK, PPCCOM, { RA, RS, UI } }, 3289{ "oriu", OP(25), OP_MASK, PWRCOM, { RA, RS, UI } }, 3290 3291{ "xori", OP(26), OP_MASK, PPCCOM, { RA, RS, UI } }, 3292{ "xoril", OP(26), OP_MASK, PWRCOM, { RA, RS, UI } }, 3293 3294{ "xoris", OP(27), OP_MASK, PPCCOM, { RA, RS, UI } }, 3295{ "xoriu", OP(27), OP_MASK, PWRCOM, { RA, RS, UI } }, 3296 3297{ "andi.", OP(28), OP_MASK, PPCCOM, { RA, RS, UI } }, 3298{ "andil.", OP(28), OP_MASK, PWRCOM, { RA, RS, UI } }, 3299 3300{ "andis.", OP(29), OP_MASK, PPCCOM, { RA, RS, UI } }, 3301{ "andiu.", OP(29), OP_MASK, PWRCOM, { RA, RS, UI } }, 3302 3303{ "rotldi", MD(30,0,0), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 3304{ "clrldi", MD(30,0,0), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 3305{ "rldicl", MD(30,0,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3306{ "rotldi.", MD(30,0,1), MDMB_MASK, PPC64, { RA, RS, SH6 } }, 3307{ "clrldi.", MD(30,0,1), MDSH_MASK, PPC64, { RA, RS, MB6 } }, 3308{ "rldicl.", MD(30,0,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3309 3310{ "rldicr", MD(30,1,0), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 3311{ "rldicr.", MD(30,1,1), MD_MASK, PPC64, { RA, RS, SH6, ME6 } }, 3312 3313{ "rldic", MD(30,2,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3314{ "rldic.", MD(30,2,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3315 3316{ "rldimi", MD(30,3,0), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3317{ "rldimi.", MD(30,3,1), MD_MASK, PPC64, { RA, RS, SH6, MB6 } }, 3318 3319{ "rotld", MDS(30,8,0), MDSMB_MASK, PPC64, { RA, RS, RB } }, 3320{ "rldcl", MDS(30,8,0), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 3321{ "rotld.", MDS(30,8,1), MDSMB_MASK, PPC64, { RA, RS, RB } }, 3322{ "rldcl.", MDS(30,8,1), MDS_MASK, PPC64, { RA, RS, RB, MB6 } }, 3323 3324{ "rldcr", MDS(30,9,0), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 3325{ "rldcr.", MDS(30,9,1), MDS_MASK, PPC64, { RA, RS, RB, ME6 } }, 3326 3327{ "cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 3328{ "cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 3329{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, 3330{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 3331 3332{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, 3333{ "tlgt", XTO(31,4,TOLGT), XTO_MASK, PWRCOM, { RA, RB } }, 3334{ "twllt", XTO(31,4,TOLLT), XTO_MASK, PPCCOM, { RA, RB } }, 3335{ "tllt", XTO(31,4,TOLLT), XTO_MASK, PWRCOM, { RA, RB } }, 3336{ "tweq", XTO(31,4,TOEQ), XTO_MASK, PPCCOM, { RA, RB } }, 3337{ "teq", XTO(31,4,TOEQ), XTO_MASK, PWRCOM, { RA, RB } }, 3338{ "twlge", XTO(31,4,TOLGE), XTO_MASK, PPCCOM, { RA, RB } }, 3339{ "tlge", XTO(31,4,TOLGE), XTO_MASK, PWRCOM, { RA, RB } }, 3340{ "twlnl", XTO(31,4,TOLNL), XTO_MASK, PPCCOM, { RA, RB } }, 3341{ "tlnl", XTO(31,4,TOLNL), XTO_MASK, PWRCOM, { RA, RB } }, 3342{ "twlle", XTO(31,4,TOLLE), XTO_MASK, PPCCOM, { RA, RB } }, 3343{ "tlle", XTO(31,4,TOLLE), XTO_MASK, PWRCOM, { RA, RB } }, 3344{ "twlng", XTO(31,4,TOLNG), XTO_MASK, PPCCOM, { RA, RB } }, 3345{ "tlng", XTO(31,4,TOLNG), XTO_MASK, PWRCOM, { RA, RB } }, 3346{ "twgt", XTO(31,4,TOGT), XTO_MASK, PPCCOM, { RA, RB } }, 3347{ "tgt", XTO(31,4,TOGT), XTO_MASK, PWRCOM, { RA, RB } }, 3348{ "twge", XTO(31,4,TOGE), XTO_MASK, PPCCOM, { RA, RB } }, 3349{ "tge", XTO(31,4,TOGE), XTO_MASK, PWRCOM, { RA, RB } }, 3350{ "twnl", XTO(31,4,TONL), XTO_MASK, PPCCOM, { RA, RB } }, 3351{ "tnl", XTO(31,4,TONL), XTO_MASK, PWRCOM, { RA, RB } }, 3352{ "twlt", XTO(31,4,TOLT), XTO_MASK, PPCCOM, { RA, RB } }, 3353{ "tlt", XTO(31,4,TOLT), XTO_MASK, PWRCOM, { RA, RB } }, 3354{ "twle", XTO(31,4,TOLE), XTO_MASK, PPCCOM, { RA, RB } }, 3355{ "tle", XTO(31,4,TOLE), XTO_MASK, PWRCOM, { RA, RB } }, 3356{ "twng", XTO(31,4,TONG), XTO_MASK, PPCCOM, { RA, RB } }, 3357{ "tng", XTO(31,4,TONG), XTO_MASK, PWRCOM, { RA, RB } }, 3358{ "twne", XTO(31,4,TONE), XTO_MASK, PPCCOM, { RA, RB } }, 3359{ "tne", XTO(31,4,TONE), XTO_MASK, PWRCOM, { RA, RB } }, 3360{ "trap", XTO(31,4,TOU), 0xffffffff, PPCCOM, { 0 } }, 3361{ "tw", X(31,4), X_MASK, PPCCOM, { TO, RA, RB } }, 3362{ "t", X(31,4), X_MASK, PWRCOM, { TO, RA, RB } }, 3363 3364{ "subfc", XO(31,8,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3365{ "sf", XO(31,8,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3366{ "subc", XO(31,8,0,0), XO_MASK, PPC, { RT, RB, RA } }, 3367{ "subfc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3368{ "sf.", XO(31,8,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3369{ "subc.", XO(31,8,0,1), XO_MASK, PPCCOM, { RT, RB, RA } }, 3370{ "subfco", XO(31,8,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3371{ "sfo", XO(31,8,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3372{ "subco", XO(31,8,1,0), XO_MASK, PPC, { RT, RB, RA } }, 3373{ "subfco.", XO(31,8,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3374{ "sfo.", XO(31,8,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3375{ "subco.", XO(31,8,1,1), XO_MASK, PPC, { RT, RB, RA } }, 3376 3377{ "mulhdu", XO(31,9,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3378{ "mulhdu.", XO(31,9,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3379 3380{ "addc", XO(31,10,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3381{ "a", XO(31,10,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3382{ "addc.", XO(31,10,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3383{ "a.", XO(31,10,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3384{ "addco", XO(31,10,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3385{ "ao", XO(31,10,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3386{ "addco.", XO(31,10,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3387{ "ao.", XO(31,10,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3388 3389{ "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3390{ "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3391 3392{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, 3393{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, 3394{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, 3395{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, 3396 3397{ "mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, { RT, FXM } }, 3398{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4 | COM, { RT } }, 3399{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, 3400 3401{ "lwarx", X(31,20), XEH_MASK, PPC, { RT, RA0, RB, EH } }, 3402 3403{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, 3404 3405{ "icbt", X(31,22), X_MASK, BOOKE|PPCE300, { CT, RA, RB } }, 3406{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, 3407 3408{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, 3409{ "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, 3410 3411{ "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, 3412{ "sl", XRC(31,24,0), X_MASK, PWRCOM, { RA, RS, RB } }, 3413{ "slw.", XRC(31,24,1), X_MASK, PPCCOM, { RA, RS, RB } }, 3414{ "sl.", XRC(31,24,1), X_MASK, PWRCOM, { RA, RS, RB } }, 3415 3416{ "cntlzw", XRC(31,26,0), XRB_MASK, PPCCOM, { RA, RS } }, 3417{ "cntlz", XRC(31,26,0), XRB_MASK, PWRCOM, { RA, RS } }, 3418{ "cntlzw.", XRC(31,26,1), XRB_MASK, PPCCOM, { RA, RS } }, 3419{ "cntlz.", XRC(31,26,1), XRB_MASK, PWRCOM, { RA, RS } }, 3420 3421{ "sld", XRC(31,27,0), X_MASK, PPC64, { RA, RS, RB } }, 3422{ "sld.", XRC(31,27,1), X_MASK, PPC64, { RA, RS, RB } }, 3423 3424{ "and", XRC(31,28,0), X_MASK, COM, { RA, RS, RB } }, 3425{ "and.", XRC(31,28,1), X_MASK, COM, { RA, RS, RB } }, 3426 3427{ "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, 3428{ "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, 3429 3430{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, 3431 3432{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, 3433 3434{ "cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, 3435{ "cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, 3436{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, 3437{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, 3438 3439{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3440{ "sub", XO(31,40,0,0), XO_MASK, PPC, { RT, RB, RA } }, 3441{ "subf.", XO(31,40,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3442{ "sub.", XO(31,40,0,1), XO_MASK, PPC, { RT, RB, RA } }, 3443{ "subfo", XO(31,40,1,0), XO_MASK, PPC, { RT, RA, RB } }, 3444{ "subo", XO(31,40,1,0), XO_MASK, PPC, { RT, RB, RA } }, 3445{ "subfo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RA, RB } }, 3446{ "subo.", XO(31,40,1,1), XO_MASK, PPC, { RT, RB, RA } }, 3447 3448{ "ldux", X(31,53), X_MASK, PPC64, { RT, RAL, RB } }, 3449 3450{ "dcbst", X(31,54), XRT_MASK, PPC, { RA, RB } }, 3451 3452{ "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, 3453{ "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, 3454 3455{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, 3456 3457{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, 3458 3459{ "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, 3460{ "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, 3461 3462{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, 3463{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, 3464 3465{ "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, 3466{ "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, 3467{ "tdeq", XTO(31,68,TOEQ), XTO_MASK, PPC64, { RA, RB } }, 3468{ "tdlge", XTO(31,68,TOLGE), XTO_MASK, PPC64, { RA, RB } }, 3469{ "tdlnl", XTO(31,68,TOLNL), XTO_MASK, PPC64, { RA, RB } }, 3470{ "tdlle", XTO(31,68,TOLLE), XTO_MASK, PPC64, { RA, RB } }, 3471{ "tdlng", XTO(31,68,TOLNG), XTO_MASK, PPC64, { RA, RB } }, 3472{ "tdgt", XTO(31,68,TOGT), XTO_MASK, PPC64, { RA, RB } }, 3473{ "tdge", XTO(31,68,TOGE), XTO_MASK, PPC64, { RA, RB } }, 3474{ "tdnl", XTO(31,68,TONL), XTO_MASK, PPC64, { RA, RB } }, 3475{ "tdlt", XTO(31,68,TOLT), XTO_MASK, PPC64, { RA, RB } }, 3476{ "tdle", XTO(31,68,TOLE), XTO_MASK, PPC64, { RA, RB } }, 3477{ "tdng", XTO(31,68,TONG), XTO_MASK, PPC64, { RA, RB } }, 3478{ "tdne", XTO(31,68,TONE), XTO_MASK, PPC64, { RA, RB } }, 3479{ "td", X(31,68), X_MASK, PPC64, { TO, RA, RB } }, 3480 3481{ "mulhd", XO(31,73,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3482{ "mulhd.", XO(31,73,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3483 3484{ "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, 3485{ "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, 3486 3487{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, 3488{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, 3489 3490{ "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, 3491 3492{ "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, 3493 3494{ "ldarx", X(31,84), XEH_MASK, PPC64, { RT, RA0, RB, EH } }, 3495 3496{ "dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, { RA, RB } }, 3497{ "dcbf", X(31,86), XLRT_MASK, PPC, { RA, RB, XRT_L } }, 3498 3499{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, 3500 3501{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, 3502 3503{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, 3504 3505{ "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, 3506{ "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, 3507{ "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, 3508{ "nego.", XO(31,104,1,1), XORB_MASK, COM, { RT, RA } }, 3509 3510{ "mul", XO(31,107,0,0), XO_MASK, M601, { RT, RA, RB } }, 3511{ "mul.", XO(31,107,0,1), XO_MASK, M601, { RT, RA, RB } }, 3512{ "mulo", XO(31,107,1,0), XO_MASK, M601, { RT, RA, RB } }, 3513{ "mulo.", XO(31,107,1,1), XO_MASK, M601, { RT, RA, RB } }, 3514 3515{ "mtsrdin", X(31,114), XRA_MASK, PPC64, { RS, RB } }, 3516 3517{ "clf", X(31,118), XTO_MASK, POWER, { RA, RB } }, 3518 3519{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } }, 3520 3521{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } }, 3522 3523{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } }, 3524{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } }, 3525{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, 3526{ "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, 3527 3528{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, 3529 3530{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, 3531 3532{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, 3533 3534{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, 3535 3536{ "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3537{ "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3538{ "subfe.", XO(31,136,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3539{ "sfe.", XO(31,136,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3540{ "subfeo", XO(31,136,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3541{ "sfeo", XO(31,136,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3542{ "subfeo.", XO(31,136,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3543{ "sfeo.", XO(31,136,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3544 3545{ "adde", XO(31,138,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3546{ "ae", XO(31,138,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3547{ "adde.", XO(31,138,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3548{ "ae.", XO(31,138,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3549{ "addeo", XO(31,138,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3550{ "aeo", XO(31,138,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3551{ "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3552{ "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3553 3554{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, 3555 3556{ "mtocrf", XFXM(31,144,0,1), XFXFXM_MASK, COM, { FXM, RS } }, 3557{ "mtcr", XFXM(31,144,0xff,0), XRARB_MASK, COM, { RS }}, 3558{ "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, 3559 3560{ "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, 3561 3562{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, 3563 3564{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, 3565 3566{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, 3567{ "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, 3568 3569{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, 3570 3571{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, 3572 3573{ "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, 3574{ "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, 3575 3576{ "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, 3577{ "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, 3578 3579{ "prtyw", X(31,154), XRB_MASK, POWER6, { RA, RS } }, 3580 3581{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, 3582 3583{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, 3584{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, 3585 3586{ "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } }, 3587 3588{ "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, 3589 3590{ "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, 3591{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } }, 3592 3593{ "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, 3594{ "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, 3595 3596{ "prtyd", X(31,186), XRB_MASK, POWER6, { RA, RS } }, 3597 3598{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, 3599 3600{ "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3601{ "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3602{ "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3603{ "sfze.", XO(31,200,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3604{ "subfzeo", XO(31,200,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3605{ "sfzeo", XO(31,200,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3606{ "subfzeo.",XO(31,200,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3607{ "sfzeo.", XO(31,200,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3608 3609{ "addze", XO(31,202,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3610{ "aze", XO(31,202,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3611{ "addze.", XO(31,202,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3612{ "aze.", XO(31,202,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3613{ "addzeo", XO(31,202,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3614{ "azeo", XO(31,202,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3615{ "addzeo.", XO(31,202,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3616{ "azeo.", XO(31,202,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3617 3618{ "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, 3619 3620{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, 3621 3622{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } }, 3623 3624{ "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, 3625{ "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, 3626 3627{ "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, 3628{ "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, 3629 3630{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, 3631 3632{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, 3633 3634{ "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3635{ "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3636{ "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3637{ "sfme.", XO(31,232,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3638{ "subfmeo", XO(31,232,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3639{ "sfmeo", XO(31,232,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3640{ "subfmeo.",XO(31,232,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3641{ "sfmeo.", XO(31,232,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3642 3643{ "mulld", XO(31,233,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 3644{ "mulld.", XO(31,233,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 3645{ "mulldo", XO(31,233,1,0), XO_MASK, PPC64, { RT, RA, RB } }, 3646{ "mulldo.", XO(31,233,1,1), XO_MASK, PPC64, { RT, RA, RB } }, 3647 3648{ "addme", XO(31,234,0,0), XORB_MASK, PPCCOM, { RT, RA } }, 3649{ "ame", XO(31,234,0,0), XORB_MASK, PWRCOM, { RT, RA } }, 3650{ "addme.", XO(31,234,0,1), XORB_MASK, PPCCOM, { RT, RA } }, 3651{ "ame.", XO(31,234,0,1), XORB_MASK, PWRCOM, { RT, RA } }, 3652{ "addmeo", XO(31,234,1,0), XORB_MASK, PPCCOM, { RT, RA } }, 3653{ "ameo", XO(31,234,1,0), XORB_MASK, PWRCOM, { RT, RA } }, 3654{ "addmeo.", XO(31,234,1,1), XORB_MASK, PPCCOM, { RT, RA } }, 3655{ "ameo.", XO(31,234,1,1), XORB_MASK, PWRCOM, { RT, RA } }, 3656 3657{ "mullw", XO(31,235,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3658{ "muls", XO(31,235,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3659{ "mullw.", XO(31,235,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3660{ "muls.", XO(31,235,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3661{ "mullwo", XO(31,235,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3662{ "mulso", XO(31,235,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3663{ "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3664{ "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3665 3666{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, 3667{ "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, 3668{ "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, 3669 3670{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, 3671 3672{ "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, 3673 3674{ "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, 3675{ "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, 3676 3677{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } }, 3678 3679{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } }, 3680 3681{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, 3682 3683{ "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, 3684{ "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, 3685{ "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, 3686{ "dozo.", XO(31,264,1,1), XO_MASK, M601, { RT, RA, RB } }, 3687 3688{ "add", XO(31,266,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3689{ "cax", XO(31,266,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3690{ "add.", XO(31,266,0,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3691{ "cax.", XO(31,266,0,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3692{ "addo", XO(31,266,1,0), XO_MASK, PPCCOM, { RT, RA, RB } }, 3693{ "caxo", XO(31,266,1,0), XO_MASK, PWRCOM, { RT, RA, RB } }, 3694{ "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, 3695{ "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, 3696 3697{ "tlbiel", X(31,274), XRTLRA_MASK, POWER4, { RB, L } }, 3698 3699{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, 3700 3701{ "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, 3702{ "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, 3703 3704{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, 3705 3706{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, 3707 3708{ "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, 3709{ "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, 3710 3711{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, 3712 3713{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } }, 3714 3715{ "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, 3716{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } }, 3717 3718{ "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, 3719 3720{ "lhzux", X(31,311), X_MASK, COM, { RT, RAL, RB } }, 3721 3722{ "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, 3723{ "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, 3724 3725{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, 3726 3727{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, 3728{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, 3729{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, 3730{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, 3731{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, 3732{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, 3733{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, 3734{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, 3735{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, 3736{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, 3737{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, 3738{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, 3739{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, 3740{ "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, 3741{ "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, 3742{ "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, 3743{ "mfdmasa0", XSPR(31,323,195), XSPR_MASK, PPC403, { RT } }, 3744{ "mfdmacc0", XSPR(31,323,196), XSPR_MASK, PPC403, { RT } }, 3745{ "mfdmacr1", XSPR(31,323,200), XSPR_MASK, PPC403, { RT } }, 3746{ "mfdmact1", XSPR(31,323,201), XSPR_MASK, PPC403, { RT } }, 3747{ "mfdmada1", XSPR(31,323,202), XSPR_MASK, PPC403, { RT } }, 3748{ "mfdmasa1", XSPR(31,323,203), XSPR_MASK, PPC403, { RT } }, 3749{ "mfdmacc1", XSPR(31,323,204), XSPR_MASK, PPC403, { RT } }, 3750{ "mfdmacr2", XSPR(31,323,208), XSPR_MASK, PPC403, { RT } }, 3751{ "mfdmact2", XSPR(31,323,209), XSPR_MASK, PPC403, { RT } }, 3752{ "mfdmada2", XSPR(31,323,210), XSPR_MASK, PPC403, { RT } }, 3753{ "mfdmasa2", XSPR(31,323,211), XSPR_MASK, PPC403, { RT } }, 3754{ "mfdmacc2", XSPR(31,323,212), XSPR_MASK, PPC403, { RT } }, 3755{ "mfdmacr3", XSPR(31,323,216), XSPR_MASK, PPC403, { RT } }, 3756{ "mfdmact3", XSPR(31,323,217), XSPR_MASK, PPC403, { RT } }, 3757{ "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, 3758{ "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, 3759{ "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, 3760{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, 3761{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } }, 3762 3763{ "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, 3764{ "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, 3765{ "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, 3766{ "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, 3767 3768{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }}, 3769 3770{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, 3771{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, 3772{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, 3773{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, 3774{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, 3775{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, 3776{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, 3777{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, 3778{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, 3779{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, 3780{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, 3781{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, 3782{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, 3783{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, 3784{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, 3785{ "mfcfar", XSPR(31,339,28), XSPR_MASK, POWER6, { RT } }, 3786{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, 3787{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, 3788{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, 3789{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } }, 3790{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } }, 3791{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, 3792{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } }, 3793{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, 3794{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } }, 3795{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, 3796{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, 3797{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, 3798{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, 3799{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, 3800{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, 3801{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, 3802{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, 3803{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, 3804{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, 3805{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, 3806{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, 3807{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, 3808{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, 3809{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, 3810{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, 3811{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, 3812{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } }, 3813{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, 3814{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, 3815{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, 3816{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, 3817{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, 3818{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, 3819{ "mfsprg", XSPR(31,339,256), XSPRG_MASK, PPC, { RT, SPRG } }, 3820{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, 3821{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, 3822{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, 3823{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, 3824{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405 | BOOKE, { RT } }, 3825{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405 | BOOKE, { RT } }, 3826{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405 | BOOKE, { RT } }, 3827{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405 | BOOKE, { RT } }, 3828{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, 3829{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, 3830{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, 3831{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, 3832{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } }, 3833{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, 3834{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } }, 3835{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, 3836{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } }, 3837{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, 3838{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } }, 3839{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } }, 3840{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, 3841{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } }, 3842{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, 3843{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } }, 3844{ "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, 3845{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } }, 3846{ "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, 3847{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } }, 3848{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, 3849{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } }, 3850{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, 3851{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } }, 3852{ "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, 3853{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } }, 3854{ "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, 3855{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } }, 3856{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, 3857{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } }, 3858{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, 3859{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } }, 3860{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } }, 3861{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } }, 3862{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } }, 3863{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } }, 3864{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } }, 3865{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } }, 3866{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } }, 3867{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } }, 3868{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } }, 3869{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } }, 3870{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } }, 3871{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } }, 3872{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } }, 3873{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } }, 3874{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } }, 3875{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, 3876{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, 3877{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, 3878{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } }, 3879{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } }, 3880{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } }, 3881{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } }, 3882{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3883{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3884{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3885{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, 3886{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, 3887{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, 3888{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, 3889{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, 3890{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, 3891{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, 3892{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, 3893{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, 3894{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, 3895{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, 3896{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, 3897{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, 3898{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, 3899{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, 3900{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, 3901{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, 3902{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, 3903{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, 3904{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, 3905{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, 3906{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, 3907{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, 3908{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, 3909{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, 3910{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, 3911{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, 3912{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, 3913{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, 3914{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, 3915{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, 3916{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, 3917{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, 3918{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, 3919{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, 3920{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, 3921{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, 3922{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, 3923{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, 3924{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, 3925{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, 3926{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, 3927{ "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, 3928{ "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, 3929{ "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, 3930{ "mfpmc2", XSPR(31,339,954), XSPR_MASK, PPC750, { RT } }, 3931{ "mfdcwr", XSPR(31,339,954), XSPR_MASK, PPC403, { RT } }, 3932{ "mfsia", XSPR(31,339,955), XSPR_MASK, PPC750, { RT } }, 3933{ "mfsler", XSPR(31,339,955), XSPR_MASK, PPC405, { RT } }, 3934{ "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, 3935{ "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, 3936{ "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, 3937{ "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, 3938{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, 3939{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, 3940{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, 3941{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, 3942{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, 3943{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, 3944{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, 3945{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, 3946{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, 3947{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, 3948{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, 3949{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, 3950{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, 3951{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, 3952{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, 3953{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, 3954{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, 3955{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, 3956{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, 3957{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, 3958 3959{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } }, 3960 3961{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3962{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3963 3964{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } }, 3965 3966{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } }, 3967 3968{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3969{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, 3970 3971{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } }, 3972 3973{ "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, 3974{ "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, 3975{ "abso", XO(31,360,1,0), XORB_MASK, M601, { RT, RA } }, 3976{ "abso.", XO(31,360,1,1), XORB_MASK, M601, { RT, RA } }, 3977 3978{ "divs", XO(31,363,0,0), XO_MASK, M601, { RT, RA, RB } }, 3979{ "divs.", XO(31,363,0,1), XO_MASK, M601, { RT, RA, RB } }, 3980{ "divso", XO(31,363,1,0), XO_MASK, M601, { RT, RA, RB } }, 3981{ "divso.", XO(31,363,1,1), XO_MASK, M601, { RT, RA, RB } }, 3982 3983{ "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, 3984 3985{ "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, 3986 3987{ "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, 3988 3989{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } }, 3990 3991{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, 3992 3993{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }}, 3994 3995{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 3996{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 3997 3998{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 3999{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, 4000 4001{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }}, 4002 4003{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, 4004 4005{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } }, 4006 4007{ "cmpb", X(31,508), X_MASK, POWER6, { RA, RS, RB } }, 4008 4009{ "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, 4010 4011{ "lfdpx", X(31,791), X_MASK, POWER6, { FRT, RA, RB } }, 4012 4013{ "lfqux", X(31,823), X_MASK, POWER2, { FRT, RA, RB } }, 4014 4015{ "stfqx", X(31,919), X_MASK, POWER2, { FRS, RA, RB } }, 4016 4017{ "stfdpx", X(31,919), X_MASK, POWER6, { FRS, RA, RB } }, 4018 4019{ "stfqux", X(31,951), X_MASK, POWER2, { FRS, RA, RB } }, 4020 4021{ "orc", XRC(31,412,0), X_MASK, COM, { RA, RS, RB } }, 4022{ "orc.", XRC(31,412,1), X_MASK, COM, { RA, RS, RB } }, 4023 4024{ "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, 4025{ "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, 4026 4027{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } }, 4028 4029{ "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, 4030 4031{ "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, 4032 4033{ "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, 4034 4035{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, 4036 4037{ "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, 4038{ "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, 4039{ "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, 4040{ "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, 4041 4042{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } }, 4043{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } }, 4044{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } }, 4045{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } }, 4046{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } }, 4047{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } }, 4048{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } }, 4049{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } }, 4050{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } }, 4051{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } }, 4052{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } }, 4053{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } }, 4054{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } }, 4055{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } }, 4056{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } }, 4057{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } }, 4058{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } }, 4059{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } }, 4060{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } }, 4061{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } }, 4062{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } }, 4063{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } }, 4064{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } }, 4065{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } }, 4066{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } }, 4067{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } }, 4068{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } }, 4069{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } }, 4070{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } }, 4071{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } }, 4072{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } }, 4073{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } }, 4074{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } }, 4075{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } }, 4076{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } }, 4077 4078{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4079{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4080 4081{ "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 4082{ "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 4083{ "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, 4084{ "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, 4085 4086{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4087{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4088 4089{ "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4090{ "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, 4091{ "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, 4092{ "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, 4093 4094{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, 4095{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, 4096{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, 4097{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, 4098{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, 4099{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, 4100{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, 4101{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, 4102{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, 4103{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, 4104{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, 4105{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, 4106{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, 4107{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, 4108{ "mtcfar", XSPR(31,467,28), XSPR_MASK, POWER6, { RS } }, 4109{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, 4110{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, 4111{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, 4112{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } }, 4113{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } }, 4114{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } }, 4115{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } }, 4116{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } }, 4117{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } }, 4118{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } }, 4119{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } }, 4120{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } }, 4121{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } }, 4122{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } }, 4123{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } }, 4124{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } }, 4125{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } }, 4126{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } }, 4127{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } }, 4128{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } }, 4129{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } }, 4130{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } }, 4131{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } }, 4132{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } }, 4133{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } }, 4134{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, 4135{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, 4136{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, 4137{ "mtsprg", XSPR(31,467,256), XSPRG_MASK,PPC, { SPRG, RS } }, 4138{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, 4139{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, 4140{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, 4141{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } }, 4142{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } }, 4143{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } }, 4144{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } }, 4145{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } }, 4146{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, 4147{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, 4148{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, 4149{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, 4150{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } }, 4151{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } }, 4152{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } }, 4153{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } }, 4154{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } }, 4155{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } }, 4156{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } }, 4157{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } }, 4158{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } }, 4159{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } }, 4160{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } }, 4161{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } }, 4162{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } }, 4163{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } }, 4164{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } }, 4165{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } }, 4166{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } }, 4167{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } }, 4168{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } }, 4169{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } }, 4170{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } }, 4171{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } }, 4172{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } }, 4173{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } }, 4174{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } }, 4175{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } }, 4176{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } }, 4177{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } }, 4178{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } }, 4179{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } }, 4180{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } }, 4181{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } }, 4182{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } }, 4183{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } }, 4184{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } }, 4185{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } }, 4186{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } }, 4187{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } }, 4188{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } }, 4189{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } }, 4190{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } }, 4191{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } }, 4192{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } }, 4193{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, 4194{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, 4195{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, 4196{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } }, 4197{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } }, 4198{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } }, 4199{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } }, 4200{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4201{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4202{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4203{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, 4204{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, 4205{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, 4206{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } }, 4207{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } }, 4208{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } }, 4209{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } }, 4210{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } }, 4211{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } }, 4212{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } }, 4213{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } }, 4214{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } }, 4215{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } }, 4216{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } }, 4217{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } }, 4218{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } }, 4219{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } }, 4220{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } }, 4221{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } }, 4222{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } }, 4223{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } }, 4224{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } }, 4225{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } }, 4226{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } }, 4227{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } }, 4228{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } }, 4229{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } }, 4230{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } }, 4231{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } }, 4232{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } }, 4233{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } }, 4234{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } }, 4235{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } }, 4236{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } }, 4237{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } }, 4238{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } }, 4239{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } }, 4240{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } }, 4241{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } }, 4242{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } }, 4243{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } }, 4244{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } }, 4245{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } }, 4246{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, 4247 4248{ "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, 4249 4250{ "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, 4251{ "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, 4252 4253{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, 4254 4255{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }}, 4256 4257{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }}, 4258 4259{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }}, 4260 4261{ "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, 4262{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4263{ "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, 4264{ "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, 4265{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4266{ "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, 4267 4268{ "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, 4269{ "divd.", XO(31,489,0,1), XO_MASK, PPC64, { RT, RA, RB } }, 4270{ "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, 4271{ "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, 4272 4273{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } }, 4274{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } }, 4275 4276{ "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, 4277{ "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, 4278{ "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, 4279{ "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, 4280 4281{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, 4282 4283{ "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, 4284 4285{ "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, 4286 4287{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, 4288 4289{ "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, 4290 4291{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, 4292{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } }, 4293 4294{ "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, 4295 4296{ "ldbrx", X(31,532), X_MASK, CELL, { RT, RA0, RB } }, 4297 4298{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, 4299{ "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, 4300 4301{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, 4302{ "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, 4303 4304{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, 4305 4306{ "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4307{ "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4308{ "srw.", XRC(31,536,1), X_MASK, PPCCOM, { RA, RS, RB } }, 4309{ "sr.", XRC(31,536,1), X_MASK, PWRCOM, { RA, RS, RB } }, 4310 4311{ "rrib", XRC(31,537,0), X_MASK, M601, { RA, RS, RB } }, 4312{ "rrib.", XRC(31,537,1), X_MASK, M601, { RA, RS, RB } }, 4313 4314{ "srd", XRC(31,539,0), X_MASK, PPC64, { RA, RS, RB } }, 4315{ "srd.", XRC(31,539,1), X_MASK, PPC64, { RA, RS, RB } }, 4316 4317{ "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, 4318{ "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, 4319 4320{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, 4321 4322{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, 4323 4324{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, 4325 4326{ "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, 4327 4328{ "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, 4329 4330{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, 4331 4332{ "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, 4333 4334{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, 4335{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } }, 4336 4337{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, 4338{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, 4339{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } }, 4340{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, 4341{ "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, 4342 4343{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } }, 4344 4345{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, 4346 4347{ "mffgpr", XRC(31,607,0), XRA_MASK, POWER6, { FRT, RB } }, 4348 4349{ "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, 4350 4351{ "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, 4352 4353{ "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, 4354 4355{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, 4356 4357{ "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, 4358 4359{ "stdbrx", X(31,660), X_MASK, CELL, { RS, RA0, RB } }, 4360 4361{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, 4362{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, 4363 4364{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, 4365{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } }, 4366 4367{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } }, 4368 4369{ "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, 4370{ "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, 4371 4372{ "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, 4373{ "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, 4374 4375{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, 4376 4377{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4378 4379{ "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, 4380 4381{ "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, 4382{ "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, 4383 4384{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, 4385 4386{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, 4387{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } }, 4388 4389{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } }, 4390 4391{ "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, 4392{ "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, 4393 4394{ "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, 4395{ "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, 4396 4397{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4398 4399{ "mftgpr", XRC(31,735,0), XRA_MASK, POWER6, { RT, FRB } }, 4400 4401{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, 4402 4403{ "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, 4404 4405{ "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, 4406{ "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, 4407 4408{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, 4409 4410{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, 4411 4412{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, 4413{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, 4414 4415{ "lwzcix", X(31,789), X_MASK, POWER6, { RT, RA0, RB } }, 4416 4417{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, 4418 4419{ "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, 4420{ "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, 4421{ "sraw.", XRC(31,792,1), X_MASK, PPCCOM, { RA, RS, RB } }, 4422{ "sra.", XRC(31,792,1), X_MASK, PWRCOM, { RA, RS, RB } }, 4423 4424{ "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, 4425{ "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, 4426 4427{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, 4428 4429{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, 4430{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, 4431 4432{ "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, 4433 4434{ "lhzcix", X(31,821), X_MASK, POWER6, { RT, RA0, RB } }, 4435 4436{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, 4437{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { 0 } }, 4438 4439{ "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, 4440{ "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, 4441{ "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, 4442{ "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, 4443 4444{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, 4445 4446{ "lbzcix", X(31,853), X_MASK, POWER6, { RT, RA0, RB } }, 4447 4448{ "mbar", X(31,854), X_MASK, BOOKE, { MO } }, 4449{ "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, 4450 4451{ "lfiwax", X(31,855), X_MASK, POWER6, { FRT, RA0, RB } }, 4452 4453{ "ldcix", X(31,885), X_MASK, POWER6, { RT, RA0, RB } }, 4454 4455{ "tlbsx", XRC(31,914,0), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, 4456{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403|BOOKE, { RTO, RA, RB } }, 4457{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } }, 4458{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } }, 4459 4460{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, 4461 4462{ "stwcix", X(31,917), X_MASK, POWER6, { RS, RA0, RB } }, 4463 4464{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, 4465 4466{ "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, 4467{ "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, 4468 4469{ "srea", XRC(31,921,0), X_MASK, M601, { RA, RS, RB } }, 4470{ "srea.", XRC(31,921,1), X_MASK, M601, { RA, RS, RB } }, 4471 4472{ "extsh", XRC(31,922,0), XRB_MASK, PPCCOM, { RA, RS } }, 4473{ "exts", XRC(31,922,0), XRB_MASK, PWRCOM, { RA, RS } }, 4474{ "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, 4475{ "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, 4476 4477{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, 4478 4479{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, 4480 4481{ "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, 4482{ "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, 4483{ "tlbre", X(31,946), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, 4484 4485{ "sthcix", X(31,949), X_MASK, POWER6, { RS, RA0, RB } }, 4486 4487{ "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, 4488{ "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, 4489 4490{ "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, 4491{ "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, 4492 4493{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, 4494 4495{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, 4496 4497{ "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, 4498{ "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, 4499{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, 4500{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, 4501 4502{ "stbcix", X(31,981), X_MASK, POWER6, { RS, RA0, RB } }, 4503 4504{ "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, 4505 4506{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, 4507 4508{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, 4509{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, 4510 4511{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, 4512 4513{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, 4514{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } }, 4515 4516{ "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, 4517 4518{ "stdcix", X(31,1013), X_MASK, POWER6, { RS, RA0, RB } }, 4519 4520{ "dcbzl", XOPL(31,1014,1), XRT_MASK,POWER4, { RA, RB } }, 4521{ "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4522{ "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, 4523 4524{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, 4525 4526{ "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, 4527{ "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, 4528{ "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, 4529{ "lvsl", X(31, 6), X_MASK, PPCVEC, { VD, RA, RB } }, 4530{ "lvsr", X(31, 38), X_MASK, PPCVEC, { VD, RA, RB } }, 4531{ "lvx", X(31, 103), X_MASK, PPCVEC, { VD, RA, RB } }, 4532{ "lvxl", X(31, 359), X_MASK, PPCVEC, { VD, RA, RB } }, 4533{ "stvebx", X(31, 135), X_MASK, PPCVEC, { VS, RA, RB } }, 4534{ "stvehx", X(31, 167), X_MASK, PPCVEC, { VS, RA, RB } }, 4535{ "stvewx", X(31, 199), X_MASK, PPCVEC, { VS, RA, RB } }, 4536{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, 4537{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, 4538 4539/* New load/store left/right index vector instructions that are in the Cell only. */ 4540{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } }, 4541{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } }, 4542{ "lvrx", X(31, 551), X_MASK, CELL, { VD, RA0, RB } }, 4543{ "lvrxl", X(31, 807), X_MASK, CELL, { VD, RA0, RB } }, 4544{ "stvlx", X(31, 647), X_MASK, CELL, { VS, RA0, RB } }, 4545{ "stvlxl", X(31, 903), X_MASK, CELL, { VS, RA0, RB } }, 4546{ "stvrx", X(31, 679), X_MASK, CELL, { VS, RA0, RB } }, 4547{ "stvrxl", X(31, 935), X_MASK, CELL, { VS, RA0, RB } }, 4548 4549{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, 4550{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4551 4552{ "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, 4553{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4554 4555{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } }, 4556 4557{ "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, 4558 4559{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, 4560{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, 4561 4562{ "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, 4563{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } }, 4564 4565{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } }, 4566 4567{ "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, 4568 4569{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } }, 4570 4571{ "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, 4572 4573{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } }, 4574 4575{ "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, 4576 4577{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } }, 4578 4579{ "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, 4580 4581{ "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, 4582{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } }, 4583 4584{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, 4585{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } }, 4586 4587{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, 4588 4589{ "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, 4590 4591{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, 4592 4593{ "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, 4594 4595{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } }, 4596 4597{ "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, 4598 4599{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } }, 4600 4601{ "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, 4602 4603{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, 4604 4605{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, 4606 4607{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, 4608 4609{ "lfdp", OP(57), OP_MASK, POWER6, { FRT, D, RA0 } }, 4610 4611{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4612{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4613{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4614{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4615{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4616{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4617{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } }, 4618{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, 4619{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } }, 4620{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4621{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } }, 4622{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4623{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } }, 4624{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, 4625 4626{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, 4627 4628{ "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, 4629 4630{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, 4631 4632{ "dadd", XRC(59,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4633{ "dadd.", XRC(59,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4634 4635{ "dqua", ZRC(59,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4636{ "dqua.", ZRC(59,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4637 4638{ "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4639{ "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4640 4641{ "fsubs", A(59,20,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4642{ "fsubs.", A(59,20,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4643 4644{ "fadds", A(59,21,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4645{ "fadds.", A(59,21,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, 4646 4647{ "fsqrts", A(59,22,0), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4648{ "fsqrts.", A(59,22,1), AFRAFRC_MASK, PPC, { FRT, FRB } }, 4649 4650{ "fres", A(59,24,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 4651{ "fres.", A(59,24,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 4652 4653{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4654{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } }, 4655 4656{ "frsqrtes", A(59,26,0), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, 4657{ "frsqrtes.",A(59,26,1), AFRALFRC_MASK,POWER5, { FRT, FRB, A_L } }, 4658 4659{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4660{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4661 4662{ "fmadds", A(59,29,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4663{ "fmadds.", A(59,29,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4664 4665{ "fnmsubs", A(59,30,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4666{ "fnmsubs.",A(59,30,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4667 4668{ "fnmadds", A(59,31,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4669{ "fnmadds.",A(59,31,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4670 4671{ "dmul", XRC(59,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4672{ "dmul.", XRC(59,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4673 4674{ "drrnd", ZRC(59,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4675{ "drrnd.", ZRC(59,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4676 4677{ "dscli", ZRC(59,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4678{ "dscli.", ZRC(59,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4679 4680{ "dquai", ZRC(59,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4681{ "dquai.", ZRC(59,67,1), Z_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4682 4683{ "dscri", ZRC(59,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4684{ "dscri.", ZRC(59,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4685 4686{ "drintx", ZRC(59,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 4687{ "drintx.", ZRC(59,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 4688 4689{ "dcmpo", X(59,130), X_MASK, POWER6, { BF, FRA, FRB } }, 4690 4691{ "dtstex", X(59,162), X_MASK, POWER6, { BF, FRA, FRB } }, 4692{ "dtstdc", Z(59,194), Z_MASK, POWER6, { BF, FRA, DCM } }, 4693{ "dtstdg", Z(59,226), Z_MASK, POWER6, { BF, FRA, DGM } }, 4694 4695{ "drintn", ZRC(59,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 4696{ "drintn.", ZRC(59,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 4697 4698{ "dctdp", XRC(59,258,0), X_MASK, POWER6, { FRT, FRB } }, 4699{ "dctdp.", XRC(59,258,1), X_MASK, POWER6, { FRT, FRB } }, 4700 4701{ "dctfix", XRC(59,290,0), X_MASK, POWER6, { FRT, FRB } }, 4702{ "dctfix.", XRC(59,290,1), X_MASK, POWER6, { FRT, FRB } }, 4703 4704{ "ddedpd", XRC(59,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, 4705{ "ddedpd.", XRC(59,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, 4706 4707{ "dxex", XRC(59,354,0), X_MASK, POWER6, { FRT, FRB } }, 4708{ "dxex.", XRC(59,354,1), X_MASK, POWER6, { FRT, FRB } }, 4709 4710{ "dsub", XRC(59,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4711{ "dsub.", XRC(59,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4712 4713{ "ddiv", XRC(59,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4714{ "ddiv.", XRC(59,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4715 4716{ "dcmpu", X(59,642), X_MASK, POWER6, { BF, FRA, FRB } }, 4717 4718{ "dtstsf", X(59,674), X_MASK, POWER6, { BF, FRA, FRB } }, 4719 4720{ "drsp", XRC(59,770,0), X_MASK, POWER6, { FRT, FRB } }, 4721{ "drsp.", XRC(59,770,1), X_MASK, POWER6, { FRT, FRB } }, 4722 4723{ "dcffix", XRC(59,802,0), X_MASK, POWER6, { FRT, FRB } }, 4724{ "dcffix.", XRC(59,802,1), X_MASK, POWER6, { FRT, FRB } }, 4725 4726{ "denbcd", XRC(59,834,0), X_MASK, POWER6, { S, FRT, FRB } }, 4727{ "denbcd.", XRC(59,834,1), X_MASK, POWER6, { S, FRT, FRB } }, 4728 4729{ "diex", XRC(59,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4730{ "diex.", XRC(59,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4731 4732{ "stfq", OP(60), OP_MASK, POWER2, { FRS, D, RA } }, 4733 4734{ "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, 4735 4736{ "stfdp", OP(61), OP_MASK, POWER6, { FRT, D, RA0 } }, 4737 4738{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 4739{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, 4740{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, 4741{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, 4742{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, 4743{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, 4744{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } }, 4745{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, 4746{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, 4747{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, 4748{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, 4749{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, 4750 4751{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, 4752 4753{ "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, 4754 4755{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, 4756 4757{ "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4758 4759{ "daddq", XRC(63,2,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4760{ "daddq.", XRC(63,2,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4761 4762{ "dquaq", ZRC(63,3,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4763{ "dquaq.", ZRC(63,3,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4764 4765{ "fcpsgn", XRC(63,8,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4766{ "fcpsgn.", XRC(63,8,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4767 4768{ "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, 4769{ "frsp.", XRC(63,12,1), XRA_MASK, COM, { FRT, FRB } }, 4770 4771{ "fctiw", XRC(63,14,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 4772{ "fcir", XRC(63,14,0), XRA_MASK, POWER2, { FRT, FRB } }, 4773{ "fctiw.", XRC(63,14,1), XRA_MASK, PPCCOM, { FRT, FRB } }, 4774{ "fcir.", XRC(63,14,1), XRA_MASK, POWER2, { FRT, FRB } }, 4775 4776{ "fctiwz", XRC(63,15,0), XRA_MASK, PPCCOM, { FRT, FRB } }, 4777{ "fcirz", XRC(63,15,0), XRA_MASK, POWER2, { FRT, FRB } }, 4778{ "fctiwz.", XRC(63,15,1), XRA_MASK, PPCCOM, { FRT, FRB } }, 4779{ "fcirz.", XRC(63,15,1), XRA_MASK, POWER2, { FRT, FRB } }, 4780 4781{ "fdiv", A(63,18,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4782{ "fd", A(63,18,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4783{ "fdiv.", A(63,18,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4784{ "fd.", A(63,18,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4785 4786{ "fsub", A(63,20,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4787{ "fs", A(63,20,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4788{ "fsub.", A(63,20,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4789{ "fs.", A(63,20,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4790 4791{ "fadd", A(63,21,0), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4792{ "fa", A(63,21,0), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4793{ "fadd.", A(63,21,1), AFRC_MASK, PPCCOM, { FRT, FRA, FRB } }, 4794{ "fa.", A(63,21,1), AFRC_MASK, PWRCOM, { FRT, FRA, FRB } }, 4795 4796{ "fsqrt", A(63,22,0), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, 4797{ "fsqrt.", A(63,22,1), AFRAFRC_MASK, PPCPWR2, { FRT, FRB } }, 4798 4799{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4800{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } }, 4801 4802{ "fre", A(63,24,0), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, 4803{ "fre.", A(63,24,1), AFRALFRC_MASK, POWER5, { FRT, FRB, A_L } }, 4804 4805{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4806{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4807{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } }, 4808{ "fm.", A(63,25,1), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } }, 4809 4810{ "frsqrte", A(63,26,0), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 4811{ "frsqrte.",A(63,26,1), AFRALFRC_MASK, PPC, { FRT, FRB, A_L } }, 4812 4813{ "fmsub", A(63,28,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4814{ "fms", A(63,28,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4815{ "fmsub.", A(63,28,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4816{ "fms.", A(63,28,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4817 4818{ "fmadd", A(63,29,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4819{ "fma", A(63,29,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4820{ "fmadd.", A(63,29,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4821{ "fma.", A(63,29,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4822 4823{ "fnmsub", A(63,30,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4824{ "fnms", A(63,30,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4825{ "fnmsub.", A(63,30,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4826{ "fnms.", A(63,30,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4827 4828{ "fnmadd", A(63,31,0), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4829{ "fnma", A(63,31,0), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4830{ "fnmadd.", A(63,31,1), A_MASK, PPCCOM, { FRT,FRA,FRC,FRB } }, 4831{ "fnma.", A(63,31,1), A_MASK, PWRCOM, { FRT,FRA,FRC,FRB } }, 4832 4833{ "fcmpo", X(63,32), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, 4834 4835{ "dmulq", XRC(63,34,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4836{ "dmulq.", XRC(63,34,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4837 4838{ "drrndq", ZRC(63,35,0), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4839{ "drrndq.", ZRC(63,35,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4840 4841{ "mtfsb1", XRC(63,38,0), XRARB_MASK, COM, { BT } }, 4842{ "mtfsb1.", XRC(63,38,1), XRARB_MASK, COM, { BT } }, 4843 4844{ "fneg", XRC(63,40,0), XRA_MASK, COM, { FRT, FRB } }, 4845{ "fneg.", XRC(63,40,1), XRA_MASK, COM, { FRT, FRB } }, 4846 4847{ "mcrfs", X(63,64), XRB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, 4848 4849{ "dscliq", ZRC(63,66,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4850{ "dscliq.", ZRC(63,66,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4851 4852{ "dquaiq", ZRC(63,67,0), Z_MASK, POWER6, { TE, FRT, FRB, RMC } }, 4853{ "dquaiq.", ZRC(63,67,1), Z_MASK, POWER6, { FRT, FRA, FRB, RMC } }, 4854 4855{ "mtfsb0", XRC(63,70,0), XRARB_MASK, COM, { BT } }, 4856{ "mtfsb0.", XRC(63,70,1), XRARB_MASK, COM, { BT } }, 4857 4858{ "fmr", XRC(63,72,0), XRA_MASK, COM, { FRT, FRB } }, 4859{ "fmr.", XRC(63,72,1), XRA_MASK, COM, { FRT, FRB } }, 4860 4861{ "dscriq", ZRC(63,98,0), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4862{ "dscriq.", ZRC(63,98,1), Z_MASK, POWER6, { FRT, FRA, SH16 } }, 4863 4864{ "drintxq", ZRC(63,99,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 4865{ "drintxq.",ZRC(63,99,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 4866 4867{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } }, 4868 4869{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, 4870{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } }, 4871 4872{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } }, 4873{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } }, 4874 4875{ "dtstexq", X(63,162), X_MASK, POWER6, { BF, FRA, FRB } }, 4876{ "dtstdcq", Z(63,194), Z_MASK, POWER6, { BF, FRA, DCM } }, 4877{ "dtstdgq", Z(63,226), Z_MASK, POWER6, { BF, FRA, DGM } }, 4878 4879{ "drintnq", ZRC(63,227,0), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 4880{ "drintnq.",ZRC(63,227,1), Z_MASK, POWER6, { R, FRT, FRB, RMC } }, 4881 4882{ "dctqpq", XRC(63,258,0), X_MASK, POWER6, { FRT, FRB } }, 4883{ "dctqpq.", XRC(63,258,1), X_MASK, POWER6, { FRT, FRB } }, 4884 4885{ "fabs", XRC(63,264,0), XRA_MASK, COM, { FRT, FRB } }, 4886{ "fabs.", XRC(63,264,1), XRA_MASK, COM, { FRT, FRB } }, 4887 4888{ "dctfixq", XRC(63,290,0), X_MASK, POWER6, { FRT, FRB } }, 4889{ "dctfixq.",XRC(63,290,1), X_MASK, POWER6, { FRT, FRB } }, 4890 4891{ "ddedpdq", XRC(63,322,0), X_MASK, POWER6, { SP, FRT, FRB } }, 4892{ "ddedpdq.",XRC(63,322,1), X_MASK, POWER6, { SP, FRT, FRB } }, 4893 4894{ "dxexq", XRC(63,354,0), X_MASK, POWER6, { FRT, FRB } }, 4895{ "dxexq.", XRC(63,354,1), X_MASK, POWER6, { FRT, FRB } }, 4896 4897{ "frin", XRC(63,392,0), XRA_MASK, POWER5, { FRT, FRB } }, 4898{ "frin.", XRC(63,392,1), XRA_MASK, POWER5, { FRT, FRB } }, 4899{ "friz", XRC(63,424,0), XRA_MASK, POWER5, { FRT, FRB } }, 4900{ "friz.", XRC(63,424,1), XRA_MASK, POWER5, { FRT, FRB } }, 4901{ "frip", XRC(63,456,0), XRA_MASK, POWER5, { FRT, FRB } }, 4902{ "frip.", XRC(63,456,1), XRA_MASK, POWER5, { FRT, FRB } }, 4903{ "frim", XRC(63,488,0), XRA_MASK, POWER5, { FRT, FRB } }, 4904{ "frim.", XRC(63,488,1), XRA_MASK, POWER5, { FRT, FRB } }, 4905 4906{ "dsubq", XRC(63,514,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4907{ "dsubq.", XRC(63,514,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4908 4909{ "ddivq", XRC(63,546,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4910{ "ddivq.", XRC(63,546,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4911 4912{ "mffs", XRC(63,583,0), XRARB_MASK, COM, { FRT } }, 4913{ "mffs.", XRC(63,583,1), XRARB_MASK, COM, { FRT } }, 4914 4915{ "dcmpuq", X(63,642), X_MASK, POWER6, { BF, FRA, FRB } }, 4916 4917{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } }, 4918 4919{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } }, 4920{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } }, 4921 4922{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } }, 4923{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } }, 4924 4925{ "dcffixq", XRC(63,802,0), X_MASK, POWER6, { FRT, FRB } }, 4926{ "dcffixq.",XRC(63,802,1), X_MASK, POWER6, { FRT, FRB } }, 4927 4928{ "fctid", XRC(63,814,0), XRA_MASK, PPC64, { FRT, FRB } }, 4929{ "fctid.", XRC(63,814,1), XRA_MASK, PPC64, { FRT, FRB } }, 4930 4931{ "fctidz", XRC(63,815,0), XRA_MASK, PPC64, { FRT, FRB } }, 4932{ "fctidz.", XRC(63,815,1), XRA_MASK, PPC64, { FRT, FRB } }, 4933 4934{ "denbcdq", XRC(63,834,0), X_MASK, POWER6, { S, FRT, FRB } }, 4935{ "denbcdq.",XRC(63,834,1), X_MASK, POWER6, { S, FRT, FRB } }, 4936 4937{ "fcfid", XRC(63,846,0), XRA_MASK, PPC64, { FRT, FRB } }, 4938{ "fcfid.", XRC(63,846,1), XRA_MASK, PPC64, { FRT, FRB } }, 4939 4940{ "diexq", XRC(63,866,0), X_MASK, POWER6, { FRT, FRA, FRB } }, 4941{ "diexq.", XRC(63,866,1), X_MASK, POWER6, { FRT, FRA, FRB } }, 4942 4943}; 4944 4945const int powerpc_num_opcodes = 4946 sizeof (powerpc_opcodes) / sizeof (powerpc_opcodes[0]); 4947 4948/* The macro table. This is only used by the assembler. */ 4949 4950/* The expressions of the form (-x ! 31) & (x | 31) have the value 0 4951 when x=0; 32-x when x is between 1 and 31; are negative if x is 4952 negative; and are 32 or more otherwise. This is what you want 4953 when, for instance, you are emulating a right shift by a 4954 rotate-left-and-mask, because the underlying instructions support 4955 shifts of size 0 but not shifts of size 32. By comparison, when 4956 extracting x bits from some word you want to use just 32-x, because 4957 the underlying instructions don't support extracting 0 bits but do 4958 support extracting the whole word (32 bits in this case). */ 4959 4960const struct powerpc_macro powerpc_macros[] = { 4961{ "extldi", 4, PPC64, "rldicr %0,%1,%3,(%2)-1" }, 4962{ "extldi.", 4, PPC64, "rldicr. %0,%1,%3,(%2)-1" }, 4963{ "extrdi", 4, PPC64, "rldicl %0,%1,(%2)+(%3),64-(%2)" }, 4964{ "extrdi.", 4, PPC64, "rldicl. %0,%1,(%2)+(%3),64-(%2)" }, 4965{ "insrdi", 4, PPC64, "rldimi %0,%1,64-((%2)+(%3)),%3" }, 4966{ "insrdi.", 4, PPC64, "rldimi. %0,%1,64-((%2)+(%3)),%3" }, 4967{ "rotrdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),0" }, 4968{ "rotrdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),0" }, 4969{ "sldi", 3, PPC64, "rldicr %0,%1,%2,63-(%2)" }, 4970{ "sldi.", 3, PPC64, "rldicr. %0,%1,%2,63-(%2)" }, 4971{ "srdi", 3, PPC64, "rldicl %0,%1,(-(%2)!63)&((%2)|63),%2" }, 4972{ "srdi.", 3, PPC64, "rldicl. %0,%1,(-(%2)!63)&((%2)|63),%2" }, 4973{ "clrrdi", 3, PPC64, "rldicr %0,%1,0,63-(%2)" }, 4974{ "clrrdi.", 3, PPC64, "rldicr. %0,%1,0,63-(%2)" }, 4975{ "clrlsldi",4, PPC64, "rldic %0,%1,%3,(%2)-(%3)" }, 4976{ "clrlsldi.",4, PPC64, "rldic. %0,%1,%3,(%2)-(%3)" }, 4977 4978{ "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, 4979{ "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, 4980{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 4981{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, 4982{ "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, 4983{ "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, 4984{ "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, 4985{ "insrwi.", 4, PPCCOM, "rlwimi. %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1"}, 4986{ "rotrwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 4987{ "rotrwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),0,31" }, 4988{ "slwi", 3, PPCCOM, "rlwinm %0,%1,%2,0,31-(%2)" }, 4989{ "sli", 3, PWRCOM, "rlinm %0,%1,%2,0,31-(%2)" }, 4990{ "slwi.", 3, PPCCOM, "rlwinm. %0,%1,%2,0,31-(%2)" }, 4991{ "sli.", 3, PWRCOM, "rlinm. %0,%1,%2,0,31-(%2)" }, 4992{ "srwi", 3, PPCCOM, "rlwinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 4993{ "sri", 3, PWRCOM, "rlinm %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 4994{ "srwi.", 3, PPCCOM, "rlwinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 4995{ "sri.", 3, PWRCOM, "rlinm. %0,%1,(-(%2)!31)&((%2)|31),%2,31" }, 4996{ "clrrwi", 3, PPCCOM, "rlwinm %0,%1,0,0,31-(%2)" }, 4997{ "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, 4998{ "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, 4999{ "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, 5000}; 5001 5002const int powerpc_num_macros = 5003 sizeof (powerpc_macros) / sizeof (powerpc_macros[0]); 5004