/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsBaseInfo.h | 11 // the Mips target useful for the compiler back-end and the MC libraries. 32 // Mips Specific MachineOperand flags. 93 // Mips instructions. 124 case Mips::ZERO: case Mips::ZERO_64: case Mips::F0: case Mips::D0_64: 125 case Mips::D0: case Mips::FCC0: case Mips [all...] |
H A D | MipsMCCodeEmitter.cpp | 1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===// 118 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) && !Binary) 151 MCFixupKind(Mips::fixup_Mips_PC16))); 170 MCFixupKind(Mips::fixup_Mips_26))); 203 Mips::Fixups FixupKind = Mips::Fixups(0); 209 FixupKind = Mips::fixup_Mips_GPOFF_HI; 212 FixupKind = Mips::fixup_Mips_GPOFF_LO; 215 FixupKind = Mips [all...] |
H A D | MipsAsmBackend.cpp | 1 //===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===// 39 case Mips::fixup_Mips_LO16: 40 case Mips::fixup_Mips_GPOFF_HI: 41 case Mips::fixup_Mips_GPOFF_LO: 42 case Mips::fixup_Mips_GOT_PAGE: 43 case Mips::fixup_Mips_GOT_OFST: 44 case Mips::fixup_Mips_GOT_DISP: 46 case Mips::fixup_Mips_PC16: 55 case Mips::fixup_Mips_26: 61 case Mips [all...] |
H A D | MipsELFObjectWriter.cpp | 1 //===-- MipsELFObjectWriter.cpp - Mips ELF Writer -------------------------===// 113 case Mips::fixup_Mips_GPREL16: 116 case Mips::fixup_Mips_26: 119 case Mips::fixup_Mips_CALL16: 122 case Mips::fixup_Mips_GOT_Global: 123 case Mips::fixup_Mips_GOT_Local: 126 case Mips::fixup_Mips_HI16: 129 case Mips::fixup_Mips_LO16: 132 case Mips::fixup_Mips_TLSGD: 135 case Mips [all...] |
H A D | MipsFixupKinds.h | 1 //===-- MipsFixupKinds.h - Mips Specific Fixup Entries ----------*- C++ -*-===// 16 namespace Mips { namespace in namespace:llvm 22 // MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] 123 } // namespace Mips
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/ |
H A D | MipsSEInstrInfo.cpp | 28 tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J), 46 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) || 47 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || 48 (Opc == Mips::LDC1) || (Opc == Mips [all...] |
H A D | MipsDirectObjLower.cpp | 1 //===-- MipsDirectObjLower.cpp - Mips LLVM direct object lowering -----===// 10 // This file contains code to lower Mips MCInst records that are normally 23 void Mips::LowerLargeShift(MCInst& Inst) { 44 case Mips::DSLL: 45 Inst.setOpcode(Mips::DSLL32); 47 case Mips::DSRL: 48 Inst.setOpcode(Mips::DSRL32); 50 case Mips::DSRA: 51 Inst.setOpcode(Mips::DSRA32); 57 void Mips [all...] |
H A D | MipsRegisterInfo.cpp | 17 #include "Mips.h" 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST) {} 48 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } 54 /// Mips Callee Saved Registers 84 Mips::ZERO, Mips::AT, Mips::K0, Mips::K1, Mips::SP 88 Mips [all...] |
H A D | MipsRelocations.h | 1 //===-- MipsRelocations.h - Mips Code Relocations ---------------*- C++ -*-===// 10 // This file defines the Mips target-specific relocation types 21 namespace Mips{ namespace in namespace:llvm
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H A D | MipsELFWriterInfo.cpp | 1 //===-- MipsELFWriterInfo.cpp - ELF Writer Info for the Mips backend ------===// 10 // This file implements ELF writer information for the Mips backend. 37 case Mips::reloc_mips_pc16: 39 case Mips::reloc_mips_hi: 41 case Mips::reloc_mips_lo: 43 case Mips::reloc_mips_26: 46 llvm_unreachable("unknown Mips machine relocation type"); 55 llvm_unreachable("unknown Mips relocation type"); 65 llvm_unreachable("unknown Mips relocation type"); 76 llvm_unreachable("unknown Mips relocatio [all...] |
H A D | MipsMachineFunction.cpp | 1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===// 38 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass; 41 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass : 42 (const TargetRegisterClass*)&Mips::CPURegsRegClass;
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H A D | MipsLongBranch.cpp | 21 #include "Mips.h" 74 return "Mips Long Branch"; 282 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) 283 .addReg(Mips::SP).addImm(-8); 284 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA) 285 .addReg(Mips::SP).addImm(0); 286 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB); 287 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips [all...] |
H A D | MipsDirectObjLower.h | 1 //===-- MipsDirectObjLower.h - Mips LLVM direct object lowering *- C++ -*--===// 19 namespace Mips { namespace in namespace:llvm
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H A D | MipsISelDAGToDAG.cpp | 1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===// 15 #include "Mips.h" 132 RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass; 134 RC = (const TargetRegisterClass*)&Mips::CPU16RegsRegClass; 136 RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass; 143 MF.getRegInfo().addLiveIn(Mips::T9_64); 144 MBB.addLiveIn(Mips::T9_64); 150 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) 152 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) 153 .addReg(Mips [all...] |
H A D | MipsSEFrameLowering.cpp | 40 unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP; 41 unsigned FP = STI.isABI_N64() ? Mips::FP_64 : Mips::FP; 42 unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 43 unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu; 87 if (Mips::AFGR64RegClass.contains(Reg)) { 90 MachineLocation SrcML0(RegInfo->getSubReg(Reg, Mips [all...] |
H A D | MipsSERegisterInfo.cpp | 16 #include "Mips.h" 56 if (I->getOpcode() == Mips::ADJCALLSTACKDOWN) 60 unsigned SP = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP; 95 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP; 118 unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu; 119 unsigned ATReg = Subtarget.isABI_N64() ? Mips::AT_64 : Mips [all...] |
H A D | MipsISelLowering.cpp | 1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 117 // Mips does not have i1 type, so use i32 for 123 addRegisterClass(MVT::i32, &Mips::CPURegsRegClass); 126 addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); 129 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); 136 addRegisterClass(VecTys[i], &Mips::DSPRegsRegClass); 149 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 154 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 156 addRegisterClass(MVT::f64, &Mips [all...] |
H A D | Mips16InstrInfo.cpp | 63 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. 64 if (Mips::CPURegsRegClass.contains(SrcReg)) 65 Opc = Mips::Move32R16; 91 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 92 Opc = Mips::SwRxSpImmX16; 108 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) 109 Opc = Mips::LwRxSpImmX16; 121 case Mips::RetRA16: 122 ExpandRetRA16(MBB, MI, Mips::JrRa16);
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H A D | Mips16FrameLowering.cpp | 43 BuildMI(MBB, MBBI, dl, TII.get(Mips::SaveRaF16)).addImm(StackSize); 61 BuildMI(MBB, MBBI, dl, TII.get(Mips::RestoreRaF16)).addImm(StackSize); 84 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA) 116 MF.getRegInfo().setPhysRegUsed(Mips::RA); 117 MF.getRegInfo().setPhysRegUsed(Mips::S0); 118 MF.getRegInfo().setPhysRegUsed(Mips::S1);
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H A D | MipsAnalyzeImmediate.cpp | 10 #include "Mips.h" 130 ADDiu = Mips::ADDiu; 131 ORi = Mips::ORi; 132 SLL = Mips::SLL; 133 LUi = Mips::LUi; 135 ADDiu = Mips::DADDiu; 136 ORi = Mips::ORi64; 137 SLL = Mips::DSLL; 138 LUi = Mips::LUi64;
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H A D | Makefile | 1 ##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===## 12 TARGET = Mips
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H A D | Mips16RegisterInfo.cpp | 15 #include "Mips.h" 80 FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/InstPrinter/ |
H A D | MipsInstPrinter.cpp | 1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===// 10 // This class prints an Mips MCInst to a .s file. 28 const char* Mips::MipsFCCToString(Mips::CondCode CC) { 75 case Mips::RDHWR: 76 case Mips::RDHWR64: 87 case Mips::RDHWR: 88 case Mips::RDHWR64: 198 O << MipsFCCToString((Mips::CondCode)MO.getImm());
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H A D | MipsInstPrinter.h | 1 //=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==// 10 // This class prints a Mips MCInst to a .s file. 22 namespace Mips { namespace in namespace:llvm 23 // Mips Branch Codes 32 // Mips Condition Codes 73 const char *MipsFCCToString(Mips::CondCode CC); 74 } // end namespace Mips
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/macosx-10.10.1/llvmCore-3425.0.34/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===// 76 return (STI.getFeatureBits() & Mips::FeatureMips64) != 0; 80 return (STI.getFeatureBits() & Mips::FeatureFP64Bit) != 0; 116 /// MipsOperand - Instances of this class represent a parsed Mips machine 301 .Case("zero", Mips::ZERO) 302 .Case("a0", Mips::A0) 303 .Case("a1", Mips::A1) 304 .Case("a2", Mips::A2) 305 .Case("a3", Mips::A3) 306 .Case("v0", Mips [all...] |