Lines Matching refs:Mips
1 //===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
15 #include "Mips.h"
132 RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
134 RC = (const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
136 RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
143 MF.getRegInfo().addLiveIn(Mips::T9_64);
144 MBB.addLiveIn(Mips::T9_64);
150 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
152 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
153 .addReg(Mips::T9_64);
154 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
160 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
162 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
164 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
165 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
175 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
177 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
182 MF.getRegInfo().addLiveIn(Mips::T9);
183 MBB.addLiveIn(Mips::T9);
190 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
192 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
193 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
214 // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
217 MF.getRegInfo().addLiveIn(Mips::V0);
218 MBB.addLiveIn(Mips::V0);
219 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
220 .addReg(Mips::V0).addReg(Mips::T9);
228 if ((MI.getOpcode() == Mips::ADDiu) &&
229 (MI.getOperand(1).getReg() == Mips::ZERO) &&
232 ZeroReg = Mips::ZERO;
233 } else if ((MI.getOpcode() == Mips::DADDiu) &&
234 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
237 ZeroReg = Mips::ZERO_64;
288 /// Used on Mips Load/Store instructions
375 Lo = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFLO : Mips::MFLO64, dl,
380 Hi = CurDAG->getMachineNode(Ty == MVT::i32 ? Mips::MFHI : Mips::MFHI64, dl,
423 MOp = Mips::ADDu;
426 MOp = Mips::SUBu;
435 SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
436 SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
447 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::MULTu : Mips::MULT);
449 MultOpc = (Opcode == ISD::UMUL_LOHI ? Mips::DMULTu : Mips::DMULT);
468 return SelectMULT(Node, NodeTy == MVT::i32 ? Mips::MULT : Mips::DMULT,
474 MultOpc = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT);
476 MultOpc = (Opcode == ISD::MULHU ? Mips::DMULTu : Mips::DMULT);
490 Mips::ZERO_64, MVT::i64);
491 return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
495 Mips::ZERO, MVT::i32);
496 return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,
524 if (Inst->Opc == Mips::LUi64)
529 CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
557 RdhwrOpc = Mips::RDHWR;
558 SrcReg = Mips::HWR29;
559 DestReg = Mips::V1;
561 RdhwrOpc = Mips::RDHWR64;
562 SrcReg = Mips::HWR29_64;
563 DestReg = Mips::V1_64;