/linux-master/drivers/clk/axs10x/ |
H A D | pll_clock.c | 219 struct axs10x_pll_clk *pll_clk; local 223 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); 224 if (!pll_clk) 227 pll_clk->base = devm_platform_ioremap_resource(pdev, 0); 228 if (IS_ERR(pll_clk->base)) 229 return PTR_ERR(pll_clk->base); 231 pll_clk->lock = devm_platform_ioremap_resource(pdev, 1); 232 if (IS_ERR(pll_clk->lock)) 233 return PTR_ERR(pll_clk 262 struct axs10x_pll_clk *pll_clk; local [all...] |
H A D | i2s_pll_clock.c | 170 struct i2s_pll_clk *pll_clk; local 173 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); 174 if (!pll_clk) 177 pll_clk->base = devm_platform_ioremap_resource(pdev, 0); 178 if (IS_ERR(pll_clk->base)) 179 return PTR_ERR(pll_clk->base); 188 pll_clk->hw.init = &init; 189 pll_clk->dev = dev; 191 clk = devm_clk_register(dev, &pll_clk [all...] |
/linux-master/drivers/clk/ |
H A D | clk-hsdk-pll.c | 308 struct hsdk_pll_clk *pll_clk; local 312 pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL); 313 if (!pll_clk) 316 pll_clk->regs = devm_platform_ioremap_resource(pdev, 0); 317 if (IS_ERR(pll_clk->regs)) 318 return PTR_ERR(pll_clk->regs); 331 pll_clk->hw.init = &init; 332 pll_clk->dev = dev; 333 pll_clk 355 struct hsdk_pll_clk *pll_clk; local [all...] |
H A D | clk-moxart.c | 59 struct clk *pll_clk; local 81 pll_clk = of_clk_get(node, 0); 82 if (IS_ERR(pll_clk)) {
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H A D | clk-vt8500.c | 677 struct clk_pll *pll_clk; local 690 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); 691 if (WARN_ON(!pll_clk)) 694 pll_clk->reg = pmc_base + reg; 695 pll_clk->lock = &_lock; 696 pll_clk->type = pll_type; 707 pll_clk->hw.init = &init; 709 hw = &pll_clk->hw; 710 rc = clk_hw_register(NULL, &pll_clk [all...] |
/linux-master/drivers/clk/socfpga/ |
H A D | clk-pll-s10.c | 194 struct socfpga_pll *pll_clk; local 199 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); 200 if (WARN_ON(!pll_clk)) 203 pll_clk->hw.reg = reg + clks->offset; 216 pll_clk->hw.hw.init = &init; 218 pll_clk->hw.bit_idx = SOCFPGA_PLL_POWER; 220 hw_clk = &pll_clk->hw.hw; 224 kfree(pll_clk); 234 struct socfpga_pll *pll_clk; local 273 struct socfpga_pll *pll_clk; local [all...] |
H A D | clk-pll.c | 78 struct socfpga_pll *pll_clk; local 87 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); 88 if (WARN_ON(!pll_clk)) 95 pll_clk->hw.reg = clk_mgr_base_addr + reg; 105 pll_clk->hw.hw.init = &init; 107 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; 109 hw_clk = &pll_clk->hw.hw; 129 kfree(pll_clk);
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H A D | clk-pll-a10.c | 71 struct socfpga_pll *pll_clk; local 81 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL); 82 if (WARN_ON(!pll_clk)) 89 pll_clk->hw.reg = clk_mgr_a10_base_addr + reg; 102 pll_clk->hw.hw.init = &init; 104 pll_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA; 105 hw_clk = &pll_clk->hw.hw; 125 kfree(pll_clk);
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/linux-master/drivers/clk/renesas/ |
H A D | rcar-gen3-cpg.c | 55 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); local 59 val = readl(pll_clk->pllcr_reg) & CPG_PLLnCR_STC_MASK; 62 return parent_rate * mult * pll_clk->fixed_mult; 68 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); local 72 prate = req->best_parent_rate * pll_clk->fixed_mult; 88 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); local 92 mult = DIV_ROUND_CLOSEST_ULL(rate, parent_rate * pll_clk->fixed_mult); 95 val = readl(pll_clk->pllcr_reg); 98 writel(val, pll_clk->pllcr_reg); 101 if (readl(pll_clk 124 struct cpg_pll_clk *pll_clk; local [all...] |
H A D | rcar-gen4-cpg.c | 73 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); local 76 mult = FIELD_GET(CPG_PLLxCR0_NI, readl(pll_clk->pllcr0_reg)) + 1; 103 struct cpg_pll_clk *pll_clk = to_pll_clk(hw); local 110 if (readl(pll_clk->pllcr0_reg) & CPG_PLLxCR0_KICK) 113 cpg_reg_modify(pll_clk->pllcr0_reg, CPG_PLLxCR0_NI, 120 cpg_reg_modify(pll_clk->pllcr0_reg, 0, CPG_PLLxCR0_KICK); 131 return readl_poll_timeout(pll_clk->pllecr_reg, val, 132 val & pll_clk->pllecr_pllst_mask, 0, 1000); 149 struct cpg_pll_clk *pll_clk; local 153 pll_clk [all...] |
H A D | rzg2l-cpg.c | 949 struct pll_clk { struct 957 #define to_pll(_hw) container_of(_hw, struct pll_clk, hw) 962 struct pll_clk *pll_clk = to_pll(hw); local 963 struct rzg2l_cpg_priv *priv = pll_clk->priv; 967 if (pll_clk->type != CLK_TYPE_SAM_PLL) 970 val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf)); 971 val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf)); 986 struct pll_clk *pll_clk local 1025 struct pll_clk *pll_clk; local [all...] |
/linux-master/arch/sh/kernel/cpu/sh2a/ |
H A D | clock-sh7269.c | 47 static struct clk pll_clk = { variable in typeref:struct:clk 64 .parent = &pll_clk, 79 .parent = &pll_clk, 86 &pll_clk, 106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 142 CLKDEV_CON_ID("pll_clk", &pll_clk),
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H A D | clock-sh7264.c | 51 static struct clk pll_clk = { variable in typeref:struct:clk 60 &pll_clk, 78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 108 CLKDEV_CON_ID("pll_clk", &pll_clk),
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/linux-master/arch/sh/kernel/cpu/sh4a/ |
H A D | clock-sh7722.c | 82 static struct clk pll_clk = { variable in typeref:struct:clk 91 &pll_clk, 109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 174 CLKDEV_CON_ID("pll_clk", &pll_clk), 226 pll_clk.parent = &dll_clk; 228 pll_clk.parent = &extal_clk;
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H A D | clock-sh7757.c | 37 static struct clk pll_clk = { variable in typeref:struct:clk 45 &pll_clk, 63 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags) 105 CLKDEV_CON_ID("pll_clk", &pll_clk),
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H A D | clock-shx3.c | 36 static struct clk pll_clk = { variable in typeref:struct:clk 44 &pll_clk, 62 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 103 CLKDEV_CON_ID("pll_clk", &pll_clk),
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H A D | clock-sh7343.c | 76 static struct clk pll_clk = { variable in typeref:struct:clk 85 &pll_clk, 106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 122 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 190 CLKDEV_CON_ID("pll_clk", &pll_clk), 258 pll_clk.parent = &dll_clk; 260 pll_clk.parent = &extal_clk;
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H A D | clock-sh7366.c | 79 static struct clk pll_clk = { variable in typeref:struct:clk 88 &pll_clk, 109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 125 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 188 CLKDEV_CON_ID("pll_clk", &pll_clk), 251 pll_clk.parent = &dll_clk; 253 pll_clk.parent = &extal_clk;
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H A D | clock-sh7785.c | 40 static struct clk pll_clk = { variable in typeref:struct:clk 48 &pll_clk, 67 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 119 CLKDEV_CON_ID("pll_clk", &pll_clk),
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H A D | clock-sh7786.c | 42 static struct clk pll_clk = { variable in typeref:struct:clk 50 &pll_clk, 68 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags) 128 CLKDEV_CON_ID("pll_clk", &pll_clk),
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H A D | clock-sh7724.c | 85 static struct clk pll_clk = { variable in typeref:struct:clk 102 .parent = &pll_clk, 119 &pll_clk, 151 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 264 CLKDEV_CON_ID("pll_clk", &pll_clk), 348 pll_clk.parent = &fll_clk; 350 pll_clk.parent = &extal_clk;
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H A D | clock-sh7723.c | 83 static struct clk pll_clk = { variable in typeref:struct:clk 92 &pll_clk, 112 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) 138 [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0), 199 CLKDEV_CON_ID("pll_clk", &pll_clk), 274 pll_clk.parent = &dll_clk; 276 pll_clk.parent = &extal_clk;
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/linux-master/drivers/spi/ |
H A D | spi-bcmbca-hsspi.c | 117 struct clk *pll_clk; member in struct:bcmbca_hsspi 440 struct clk *clk, *pll_clk = NULL; local 472 pll_clk = devm_clk_get(dev, "pll"); 474 if (IS_ERR(pll_clk)) { 475 ret = PTR_ERR(pll_clk); 479 ret = clk_prepare_enable(pll_clk); 483 rate = clk_get_rate(pll_clk); 499 bs->pll_clk = pll_clk; 573 clk_disable_unprepare(pll_clk); [all...] |
H A D | spi-bcm63xx-hsspi.c | 136 struct clk *pll_clk; member in struct:bcm63xx_hsspi 730 struct clk *clk, *pll_clk = NULL; local 764 pll_clk = devm_clk_get(dev, "pll"); 766 if (IS_ERR(pll_clk)) { 767 ret = PTR_ERR(pll_clk); 771 ret = clk_prepare_enable(pll_clk); 775 rate = clk_get_rate(pll_clk); 791 bs->pll_clk = pll_clk; 874 clk_disable_unprepare(pll_clk); [all...] |
/linux-master/drivers/clk/imx/ |
H A D | clk-fracn-gppll.c | 344 const struct imx_fracn_gppll_clk *pll_clk, 357 init.flags = pll_clk->flags; 364 pll->rate_table = pll_clk->rate_table; 365 pll->rate_count = pll_clk->rate_count; 381 const struct imx_fracn_gppll_clk *pll_clk) 383 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN); 389 const struct imx_fracn_gppll_clk *pll_clk) 391 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER); 342 _imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk, u32 pll_flags) argument 380 imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk) argument 387 imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk) argument
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