Searched refs:mmTPC3_QM_GLBL_CFG0 (Results 1 - 5 of 5) sorted by relevance

/linux-master/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dtpc3_qm_regs.h22 #define mmTPC3_QM_GLBL_CFG0 0xEC8000 macro
/linux-master/drivers/accel/habanalabs/include/gaudi/asic_reg/
H A Dtpc3_qm_regs.h22 #define mmTPC3_QM_GLBL_CFG0 0xEC8000 macro
/linux-master/drivers/accel/habanalabs/goya/
H A Dgoya_security.c1317 pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
1318 word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
1319 mask = 1 << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2);
H A Dgoya.c2086 WREG32(mmTPC3_QM_GLBL_CFG0, 0);
/linux-master/drivers/accel/habanalabs/gaudi/
H A Dgaudi_security.c10543 pb_addr = (mmTPC3_QM_GLBL_CFG0 & ~0xFFF) + PROT_BITS_OFFS;
10544 word_offset = ((mmTPC3_QM_GLBL_CFG0 & PROT_BITS_OFFS) >> 7) << 2;
10545 mask = 1U << ((mmTPC3_QM_GLBL_CFG0 & 0x7F) >> 2);

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