1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2018 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8/************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13#ifndef ASIC_REG_TPC3_QM_REGS_H_ 14#define ASIC_REG_TPC3_QM_REGS_H_ 15 16/* 17 ***************************************** 18 * TPC3_QM (Prototype: QMAN) 19 ***************************************** 20 */ 21 22#define mmTPC3_QM_GLBL_CFG0 0xEC8000 23 24#define mmTPC3_QM_GLBL_CFG1 0xEC8004 25 26#define mmTPC3_QM_GLBL_PROT 0xEC8008 27 28#define mmTPC3_QM_GLBL_ERR_CFG 0xEC800C 29 30#define mmTPC3_QM_GLBL_ERR_ADDR_LO 0xEC8010 31 32#define mmTPC3_QM_GLBL_ERR_ADDR_HI 0xEC8014 33 34#define mmTPC3_QM_GLBL_ERR_WDATA 0xEC8018 35 36#define mmTPC3_QM_GLBL_SECURE_PROPS 0xEC801C 37 38#define mmTPC3_QM_GLBL_NON_SECURE_PROPS 0xEC8020 39 40#define mmTPC3_QM_GLBL_STS0 0xEC8024 41 42#define mmTPC3_QM_GLBL_STS1 0xEC8028 43 44#define mmTPC3_QM_PQ_BASE_LO 0xEC8060 45 46#define mmTPC3_QM_PQ_BASE_HI 0xEC8064 47 48#define mmTPC3_QM_PQ_SIZE 0xEC8068 49 50#define mmTPC3_QM_PQ_PI 0xEC806C 51 52#define mmTPC3_QM_PQ_CI 0xEC8070 53 54#define mmTPC3_QM_PQ_CFG0 0xEC8074 55 56#define mmTPC3_QM_PQ_CFG1 0xEC8078 57 58#define mmTPC3_QM_PQ_ARUSER 0xEC807C 59 60#define mmTPC3_QM_PQ_PUSH0 0xEC8080 61 62#define mmTPC3_QM_PQ_PUSH1 0xEC8084 63 64#define mmTPC3_QM_PQ_PUSH2 0xEC8088 65 66#define mmTPC3_QM_PQ_PUSH3 0xEC808C 67 68#define mmTPC3_QM_PQ_STS0 0xEC8090 69 70#define mmTPC3_QM_PQ_STS1 0xEC8094 71 72#define mmTPC3_QM_PQ_RD_RATE_LIM_EN 0xEC80A0 73 74#define mmTPC3_QM_PQ_RD_RATE_LIM_RST_TOKEN 0xEC80A4 75 76#define mmTPC3_QM_PQ_RD_RATE_LIM_SAT 0xEC80A8 77 78#define mmTPC3_QM_PQ_RD_RATE_LIM_TOUT 0xEC80AC 79 80#define mmTPC3_QM_CQ_CFG0 0xEC80B0 81 82#define mmTPC3_QM_CQ_CFG1 0xEC80B4 83 84#define mmTPC3_QM_CQ_ARUSER 0xEC80B8 85 86#define mmTPC3_QM_CQ_PTR_LO 0xEC80C0 87 88#define mmTPC3_QM_CQ_PTR_HI 0xEC80C4 89 90#define mmTPC3_QM_CQ_TSIZE 0xEC80C8 91 92#define mmTPC3_QM_CQ_CTL 0xEC80CC 93 94#define mmTPC3_QM_CQ_PTR_LO_STS 0xEC80D4 95 96#define mmTPC3_QM_CQ_PTR_HI_STS 0xEC80D8 97 98#define mmTPC3_QM_CQ_TSIZE_STS 0xEC80DC 99 100#define mmTPC3_QM_CQ_CTL_STS 0xEC80E0 101 102#define mmTPC3_QM_CQ_STS0 0xEC80E4 103 104#define mmTPC3_QM_CQ_STS1 0xEC80E8 105 106#define mmTPC3_QM_CQ_RD_RATE_LIM_EN 0xEC80F0 107 108#define mmTPC3_QM_CQ_RD_RATE_LIM_RST_TOKEN 0xEC80F4 109 110#define mmTPC3_QM_CQ_RD_RATE_LIM_SAT 0xEC80F8 111 112#define mmTPC3_QM_CQ_RD_RATE_LIM_TOUT 0xEC80FC 113 114#define mmTPC3_QM_CQ_IFIFO_CNT 0xEC8108 115 116#define mmTPC3_QM_CP_MSG_BASE0_ADDR_LO 0xEC8120 117 118#define mmTPC3_QM_CP_MSG_BASE0_ADDR_HI 0xEC8124 119 120#define mmTPC3_QM_CP_MSG_BASE1_ADDR_LO 0xEC8128 121 122#define mmTPC3_QM_CP_MSG_BASE1_ADDR_HI 0xEC812C 123 124#define mmTPC3_QM_CP_MSG_BASE2_ADDR_LO 0xEC8130 125 126#define mmTPC3_QM_CP_MSG_BASE2_ADDR_HI 0xEC8134 127 128#define mmTPC3_QM_CP_MSG_BASE3_ADDR_LO 0xEC8138 129 130#define mmTPC3_QM_CP_MSG_BASE3_ADDR_HI 0xEC813C 131 132#define mmTPC3_QM_CP_LDMA_TSIZE_OFFSET 0xEC8140 133 134#define mmTPC3_QM_CP_LDMA_SRC_BASE_LO_OFFSET 0xEC8144 135 136#define mmTPC3_QM_CP_LDMA_SRC_BASE_HI_OFFSET 0xEC8148 137 138#define mmTPC3_QM_CP_LDMA_DST_BASE_LO_OFFSET 0xEC814C 139 140#define mmTPC3_QM_CP_LDMA_DST_BASE_HI_OFFSET 0xEC8150 141 142#define mmTPC3_QM_CP_LDMA_COMMIT_OFFSET 0xEC8154 143 144#define mmTPC3_QM_CP_FENCE0_RDATA 0xEC8158 145 146#define mmTPC3_QM_CP_FENCE1_RDATA 0xEC815C 147 148#define mmTPC3_QM_CP_FENCE2_RDATA 0xEC8160 149 150#define mmTPC3_QM_CP_FENCE3_RDATA 0xEC8164 151 152#define mmTPC3_QM_CP_FENCE0_CNT 0xEC8168 153 154#define mmTPC3_QM_CP_FENCE1_CNT 0xEC816C 155 156#define mmTPC3_QM_CP_FENCE2_CNT 0xEC8170 157 158#define mmTPC3_QM_CP_FENCE3_CNT 0xEC8174 159 160#define mmTPC3_QM_CP_STS 0xEC8178 161 162#define mmTPC3_QM_CP_CURRENT_INST_LO 0xEC817C 163 164#define mmTPC3_QM_CP_CURRENT_INST_HI 0xEC8180 165 166#define mmTPC3_QM_CP_BARRIER_CFG 0xEC8184 167 168#define mmTPC3_QM_CP_DBG_0 0xEC8188 169 170#define mmTPC3_QM_PQ_BUF_ADDR 0xEC8300 171 172#define mmTPC3_QM_PQ_BUF_RDATA 0xEC8304 173 174#define mmTPC3_QM_CQ_BUF_ADDR 0xEC8308 175 176#define mmTPC3_QM_CQ_BUF_RDATA 0xEC830C 177 178#endif /* ASIC_REG_TPC3_QM_REGS_H_ */ 179