Searched refs:lane_count (Results 1 - 25 of 79) sorted by relevance

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/linux-master/drivers/gpu/drm/i915/display/
H A Dintel_combo_phy.h18 int lane_count, bool lane_reversal);
H A Dintel_dp_link_training.c350 lane = min(lane, crtc_state->lane_count - 1);
353 for (lane = 0; lane < crtc_state->lane_count; lane++)
373 lane = min(lane, crtc_state->lane_count - 1);
378 for (lane = 0; lane < crtc_state->lane_count; lane++) {
446 crtc_state->lane_count,
453 crtc_state->lane_count,
487 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
488 len = crtc_state->lane_count + 1;
558 crtc_state->lane_count,
565 crtc_state->lane_count,
673 u8 lane_count = crtc_state->lane_count; local
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H A Dintel_dpio_phy.c315 for (lane = 0; lane < crtc_state->lane_count; lane++) {
324 for (lane = 0; lane < crtc_state->lane_count; lane++) {
339 for (lane = 0; lane < crtc_state->lane_count; lane++) {
598 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) argument
600 switch (lane_count) {
608 MISSING_CASE(lane_count);
737 if (crtc_state->lane_count > 2) {
750 if (crtc_state->lane_count > 2) {
758 for (i = 0; i < crtc_state->lane_count; i++) {
766 for (i = 0; i < crtc_state->lane_count;
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H A Dintel_dp.h57 int link_rate, int lane_count);
59 int link_rate, u8 lane_count);
140 u32 link_clock, u32 lane_count,
157 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) argument
159 return ~((1 << lane_count) - 1) & 0xf;
H A Dintel_combo_phy.c259 int lane_count, bool lane_reversal)
266 switch (lane_count) {
277 MISSING_CASE(lane_count);
284 switch (lane_count) {
294 MISSING_CASE(lane_count);
257 intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, enum phy phy, bool is_dsi, int lane_count, bool lane_reversal) argument
H A Dvlv_dsi.c53 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, argument
57 8 * 100), lane_count);
61 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, argument
64 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100),
1022 unsigned int lane_count = intel_dsi->lane_count; local
1074 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count,
1076 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count,
1078 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count,
1127 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count,
1223 unsigned int lane_count = intel_dsi->lane_count; local
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H A Dintel_dpio_phy.h40 u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
100 static inline u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count) argument
H A Dvlv_dsi_pll.c48 int lane_count)
55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count);
168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp);
183 intel_dsi->lane_count);
349 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp);
488 intel_dsi->lane_count);
47 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, int lane_count) argument
/linux-master/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.h39 uint8_t lane_count);
H A Dlink_dp_capability.c66 enum dc_lane_count lane_count; member in struct:dp_lt_fallback_entry
101 .lane_count = LANE_COUNT_ONE,
431 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) argument
433 return lane_count <= LANE_COUNT_ONE;
441 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) argument
443 switch (lane_count) {
490 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) argument
492 switch (lane_count) {
545 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count
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H A Dlink_dp_training_fixed_vs_pe_retimer.c75 uint8_t lane_count)
82 for (lane = 0; lane < lane_count; lane++) {
254 lt_settings->link_settings.lane_count;
295 lt_settings->link_settings.lane_count,
304 if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) {
325 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local
376 for (lane = 0; lane < lane_count; lane++) {
414 if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
447 status = dp_get_cr_failure(lane_count, dpcd_lane_statu
72 dp_fixed_vs_pe_set_retimer_lane_settings( struct dc_link *link, const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX], uint8_t lane_count) argument
455 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local
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H A Dlink_dp_training_8b_10b.c103 lt_settings->link_settings.lane_count = link_setting->lane_count;
163 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local
228 if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
267 return dp_get_cr_failure(lane_count, dpcd_lane_status);
279 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local
334 if (!dp_is_cr_done(lane_count, dpcd_lane_status))
340 if (dp_is_ch_eq_done(lane_count, dpcd_lane_statu
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H A Dlink_dp_training_dpia.c298 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local
403 if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
409 result = dp_get_cr_failure(lane_count, dpcd_lane_status);
468 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local
511 if (dp_is_cr_done(lane_count, dpcd_lane_status)) {
517 result = dp_get_cr_failure(lane_count, dpcd_lane_status);
623 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local
771 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; local
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H A Dlink_dp_training.c172 lt_settings->link_settings.lane_count,
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) {
463 (uint32_t)(lt_settings->link_settings.lane_count);
531 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
592 (uint32_t)(link_training_setting->link_settings.lane_count);
1048 lt_settings->link_settings.lane_count;
1094 lt_settings->link_settings.lane_count,
1104 lt_settings->link_settings.lane_count,
1129 link_training_setting->link_settings.lane_count);
1198 size_in_bytes = lt_settings->link_settings.lane_count *
1348 enum dc_lane_count lane_count = local
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H A Dlink_dp_irq_handler.c59 if (link->cur_link_settings.lane_count == 0)
65 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
269 pipes[i]->link_config.dp_link_settings.lane_count =
270 link->verified_link_cap.lane_count;
361 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
/linux-master/drivers/gpu/drm/msm/dp/
H A Ddp_panel.h84 * @lane_count: lane count requested by the sink
88 static inline bool is_lane_count_valid(u32 lane_count) argument
90 return (lane_count == 1 ||
91 lane_count == 2 ||
92 lane_count == 4);
H A Ddp_audio.h17 * @lane_count: number of lanes configured in current session
21 u32 lane_count; member in struct:dp_audio
/linux-master/drivers/gpu/drm/tests/
H A Ddrm_dp_mst_helper_test.c73 int lane_count; member in struct:drm_dp_mst_calc_pbn_div_test
86 * .expected = .link_rate * .lane_count * 0.9671 / 8 / 54 / 100
88 * .expected = .link_rate * .lane_count * 0.8000 / 8 / 54 / 100
94 .lane_count = 4,
99 .lane_count = 2,
104 .lane_count = 1,
109 .lane_count = 4,
114 .lane_count = 2,
119 .lane_count = 1,
124 .lane_count
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/linux-master/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c262 int lane, lane_count, pll_tries, retval; local
264 lane_count = dp->link_train.lane_count;
269 for (lane = 0; lane < lane_count; lane++)
274 analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
278 buf[1] = dp->link_train.lane_count;
290 for (lane = 0; lane < lane_count; lane++)
316 for (lane = 0; lane < lane_count; lane++)
321 lane_count);
336 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) argument
349 analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, int lane_count) argument
446 int lane, lane_count; local
469 int lane, lane_count, retval; local
541 int lane, lane_count, retval; local
628 analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, u8 *lane_count) argument
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/linux-master/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c262 uint8_t lane_count; member in struct:cdv_intel_dp
897 int lane_count, clock; local
910 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
912 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count);
916 intel_dp->lane_count = lane_count;
920 intel_dp->link_bw, intel_dp->lane_count,
928 intel_dp->lane_count
990 int lane_count = 4, bpp = 24; local
1314 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) argument
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/linux-master/drivers/gpu/drm/amd/display/include/
H A Daudio_types.h42 enum dc_lane_count lane_count; member in struct:audio_dp_link_info
/linux-master/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c54 u32 lane_count; member in struct:ps8622_bridge
184 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count);
490 &ps8622->lane_count)) {
491 ps8622->lane_count = ps8622->max_lane_count;
492 } else if (ps8622->lane_count > ps8622->max_lane_count) {
495 ps8622->lane_count = ps8622->max_lane_count;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_link_encoder.c63 if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO)
64 link_settings->lane_count = LANE_COUNT_TWO;
/linux-master/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dio_link_encoder.c475 dpia_control.lanenum = (uint8_t)link_settings->lane_count;
522 dpia_control.lanenum = (uint8_t)link_settings->lane_count;
658 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
680 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
/linux-master/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_hpo_fixed_vs_pe_retimer_dp.c107 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR)
114 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR)
196 if (link_settings->lane_count == LANE_COUNT_FOUR)

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