Searched refs:fence_context (Results 1 - 25 of 39) sorted by relevance

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/linux-master/drivers/gpu/drm/i915/gt/selftests/
H A Dmock_timeline.c14 timeline->fence_context = context;
/linux-master/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_ids.c231 u64 fence_context = adev->vm_manager.fence_context + ring->idx; local
240 array = dma_fence_array_create(i, fences, fence_context,
279 uint64_t fence_context = adev->fence_context + ring->idx; local
285 if ((*id)->owner != vm->immediate.fence_context ||
289 ((*id)->last_flush->context != fence_context &&
306 (*id)->owner != vm->immediate.fence_context) {
358 uint64_t fence_context = adev->fence_context local
[all...]
H A Damdgpu_fence.c171 adev->fence_context + ring->idx, seq);
177 adev->fence_context + ring->idx, seq);
/linux-master/drivers/gpu/drm/v3d/
H A Dv3d_fence.c18 v3d->queue[queue].fence_context, fence->seqno);
H A Dv3d_gem.c252 queue->fence_context = dma_fence_context_alloc(1);
H A Dv3d_drv.h57 u64 fence_context; member in struct:v3d_queue_state
/linux-master/drivers/gpu/drm/i915/gt/
H A Dintel_timeline_types.h22 u64 fence_context; member in struct:intel_timeline
H A Dintel_timeline.c101 timeline->fence_context = dma_fence_context_alloc(1);
212 tl->fence_context, tl->hwsp_offset);
429 tl->fence_context);
452 drm_printf(m, "Timeline %llx: { ", tl->fence_context);
H A Dintel_context_types.h276 * @fence_context: fence context composite fence when doing
279 u64 fence_context; member in struct:intel_context::__anon729
H A Dintel_context.h25 ce__->timeline->fence_context, \
H A Dselftest_timeline.c586 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
658 n, tl->fence_context, tl->hwsp_offset, *tl->hwsp_seqno);
1395 count, tl->fence_context,
H A Dintel_execlists_submission.c816 ce->timeline->fence_context,
825 ccid, ce->timeline->fence_context,
844 ce->timeline->fence_context,
859 ce->timeline->fence_context,
875 ce->timeline->fence_context,
884 ce->timeline->fence_context,
893 ce->timeline->fence_context,
2678 parent->parallel.fence_context = dma_fence_context_alloc(1);
/linux-master/include/drm/
H A Ddrm_writeback.h63 * @fence_context:
67 unsigned int fence_context; member in struct:drm_writeback_connector
71 * spinlock to protect the fences in the fence_context.
H A Ddrm_crtc.h1145 * @fence_context:
1149 unsigned int fence_context; member in struct:drm_crtc
1154 * spinlock to protect the fences in the fence_context.
H A Dgpu_scheduler.h167 * @fence_context:
170 * &drm_sched_fence.scheduled uses the fence_context but
171 * &drm_sched_fence.finished uses fence_context + 1.
173 uint64_t fence_context; member in struct:drm_sched_entity
/linux-master/drivers/gpu/drm/virtio/
H A Dvirtgpu_fence.c78 uint64_t fence_context = base_fence_ctx + ring_idx; local
96 fence_context, 0);
/linux-master/drivers/gpu/drm/scheduler/
H A Dsched_fence.c229 &fence->lock, entity->fence_context, seq);
231 &fence->lock, entity->fence_context + 1, seq);
H A Dsched_entity.c112 entity->fence_context = dma_fence_context_alloc(2);
413 if (fence->context == entity->fence_context ||
414 fence->context == entity->fence_context + 1) {
/linux-master/drivers/gpu/drm/lima/
H A Dlima_sched.h49 u64 fence_context; member in struct:lima_sched_pipe
H A Dlima_sched.c98 pipe->fence_context, ++pipe->fence_seqno);
519 pipe->fence_context = dma_fence_context_alloc(1);
/linux-master/drivers/gpu/drm/
H A Ddrm_writeback.c266 wb_connector->fence_context = dma_fence_context_alloc(1);
463 &wb_connector->fence_lock, wb_connector->fence_context,
H A Ddrm_crtc.c193 crtc->fence_context, ++crtc->fence_seqno);
276 crtc->fence_context = dma_fence_context_alloc(1);
/linux-master/drivers/gpu/drm/etnaviv/
H A Detnaviv_gpu.h138 u64 fence_context; member in struct:etnaviv_gpu
/linux-master/drivers/gpu/drm/i915/
H A Di915_active.c373 GEM_BUG_ON(node->timeline != engine->kernel_context->timeline->fence_context);
429 u64 idx = i915_request_timeline(rq)->fence_context;
878 u64 idx = engine->kernel_context->timeline->fence_context;
/linux-master/drivers/gpu/drm/panfrost/
H A Dpanfrost_job.c32 u64 fence_context; member in struct:panfrost_queue_state
101 js->queue[js_num].fence_context, fence->seqno);
870 js->queue[j].fence_context = dma_fence_context_alloc(1);

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