| /linux-master/drivers/clk/rockchip/ |
| H A D | clk-ddr.c | 21 int div_shift; member in struct:rockchip_ddrclk
94 int div_shift, int div_width,
129 ddrclk->div_shift = div_shift;
90 rockchip_clk_register_ddrclk(const char *name, int flags, const char *const *parent_names, u8 num_parents, int mux_offset, int mux_shift, int mux_width, int div_shift, int div_width, int ddr_flag, void __iomem *reg_base, spinlock_t *lock) argument
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| H A D | clk.h | 495 int div_shift, int div_width,
540 u8 div_shift; member in struct:rockchip_clk_branch
563 .div_shift = ds, \
585 .div_shift = ds, \
603 .div_shift = ds, \
621 .div_shift = ds, \
661 .div_shift = ds, \
680 .div_shift = ds, \
696 .div_shift = 16, \
713 .div_shift
[all...] |
| H A D | clk.c | 43 int div_offset, u8 div_shift, u8 div_width, u8 div_flags,
97 div->shift = div_shift;
492 list->div_shift, list->div_width,
499 list->div_shift, list->div_width,
516 list->mux_flags, list->div_shift,
536 list->div_shift, list->div_width,
546 list->div_shift
554 list->div_shift, list->div_flags, &ctx->lock);
560 list->div_shift, list->div_width,
569 list->mux_width, list->div_shift,
38 rockchip_clk_register_branch(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u32 *mux_table, int div_offset, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) argument
[all...] |
| H A D | clk-half-divider.c | 163 u8 div_shift, u8 div_width,
209 div->shift = div_shift;
158 rockchip_clk_register_halfdiv(const char *name, const char *const *parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u8 div_shift, u8 div_width, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) argument
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| /linux-master/drivers/clk/ |
| H A D | clk-loongson2.c | 39 u8 div_shift; member in struct:loongson2_clk_data
52 u8 div_shift; member in struct:loongson2_clk_board_info
66 .div_shift = _dshift, \
80 .div_shift = _dshift, \
92 .div_shift = _dshift, \
219 div = loongson2_rate_part(val, clk->div_shift, clk->div_width);
235 mult = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;
268 clk->div_shift = cld->div_shift;
325 p->div_shift,
[all...] |
| H A D | clk-en7523.c | 57 u8 div_shift; member in struct:en_clk_desc
91 .div_shift = 0,
104 .div_shift = 0,
117 .div_shift = 0,
131 .div_shift = 24,
143 .div_shift = 8,
157 .div_shift = 0,
199 val >>= desc->div_shift;
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| H A D | clk-sp7021.c | 52 int div_shift; member in struct:sp_pll
473 u32 fbdiv = ((reg >> clk->div_shift) & ((1 << clk->div_width) - 1)) + 1;
498 u32 mask = GENMASK(clk->div_shift + clk->div_width - 1, clk->div_shift);
501 reg |= ((fbdiv - 1) << clk->div_shift) & mask;
576 pll->div_shift = shift;
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| H A D | clk-bm1880.c | 120 s8 div_shift; member in struct:bm1880_composite_clock
152 .div_shift = _div_shift, \
168 .div_shift = -1, \
803 if (clks->div_shift >= 0) {
812 div_hws->div.shift = clks->div_shift;
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| H A D | clk-k210.c | 35 u8 div_shift; member in struct:k210_clk_cfg
55 .div_shift = (_shift), \
760 div_val = (reg >> cfg->div_shift) & GENMASK(cfg->div_width - 1, 0);
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| /linux-master/drivers/clk/x86/ |
| H A D | clk-cgu.h | 182 u8 div_shift; member in struct:lgm_clk_branch
232 .div_shift = _shift, \
272 .div_shift = _shift, \
292 .div_shift = _shift, \
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| H A D | clk-cgu.c | 30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift,
199 u8 shift = list->div_shift;
251 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift,
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| /linux-master/sound/soc/fsl/ |
| H A D | fsl_mqs.c | 43 * @div_shift: clock divider bit shift
55 int div_shift; member in struct:fsl_mqs_soc_data
95 (div - 1) << mqs_priv->soc->div_shift);
316 .div_shift = MQS_CLK_DIV_SHIFT,
329 .div_shift = IMX6SX_GPR2_MQS_CLK_DIV_SHIFT,
342 .div_shift = 8,
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| /linux-master/drivers/clk/imx/ |
| H A D | clk-pllv3.c | 39 * @div_shift: shift of divider bits
53 u32 div_shift; member in struct:clk_pllv3
115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask;
143 val &= ~(pll->div_mask << pll->div_shift);
144 val |= (div << pll->div_shift);
439 pll->div_shift = 1;
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mtk.h | 190 unsigned char div_shift; member in struct:mtk_clk_divider
201 .div_shift = _shift, \
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| H A D | clk-mt8167-apmixedsys.c | 82 .div_shift = _shift, \
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| H A D | clk-mt8167.c | 663 .div_shift = _shift, \
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| H A D | clk-mt8516.c | 474 .div_shift = _shift, \
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| H A D | clk-mt8365.c | 547 .div_shift = _shift, \
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| H A D | clk-mtk.c | 418 mcd->flags, base + mcd->div_reg, mcd->div_shift,
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| /linux-master/drivers/clk/at91/ |
| H A D | clk-sam9x60-pll.c | 346 (div << core->layout->div_shift) | ena_val);
367 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
513 cdiv = (val & core->layout->div_mask) >> core->layout->div_shift;
569 cdiv = (val & core.layout->div_mask) >> core.layout->div_shift;
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| H A D | pmc.h | 65 u8 div_shift; member in struct:clk_pll_layout
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| H A D | sam9x60.c | 56 .div_shift = 0,
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| H A D | sama7g5.c | 93 .div_shift = 0,
101 .div_shift = 12,
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| /linux-master/drivers/mfd/ |
| H A D | db8500-prcmu.c | 523 u32 div_shift; member in struct:dsiescclk
530 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
535 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
540 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
1534 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1899 val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
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| /linux-master/drivers/clk/tegra/ |
| H A D | clk-tegra-periph.c | 832 u8 div_shift; member in struct:pll_out_data
843 .div_shift = _div_shift,\
967 data->div_shift, 8, 1, data->lock);
|