| /linux-master/drivers/clk/ |
| H A D | clk-fractional-divider.h | 5 struct clk_hw;
9 void clk_fractional_divider_general_approximation(struct clk_hw *hw,
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| H A D | clk.h | 7 struct clk_hw;
12 struct clk_hw *of_clk_get_hw(struct device_node *np,
15 static inline struct clk_hw *of_clk_get_hw(struct device_node *np,
22 struct clk_hw *clk_find_hw(const char *dev_id, const char *con_id);
25 struct clk *clk_hw_create_clk(struct device *dev, struct clk_hw *hw,
31 clk_hw_create_clk(struct device *dev, struct clk_hw *hw, const char *dev_id,
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| H A D | clk-hi655x.c | 22 struct clk_hw clk_hw; member in struct:hi655x_clk
25 static unsigned long hi655x_clk_recalc_rate(struct clk_hw *hw,
31 static int hi655x_clk_enable(struct clk_hw *hw, bool enable)
34 container_of(hw, struct hi655x_clk, clk_hw);
42 static int hi655x_clk_prepare(struct clk_hw *hw)
47 static void hi655x_clk_unprepare(struct clk_hw *hw)
52 static int hi655x_clk_is_prepared(struct clk_hw *hw)
55 container_of(hw, struct hi655x_clk, clk_hw);
93 hi655x_clk->clk_hw
[all...] |
| H A D | clk-composite.c | 11 static u8 clk_composite_get_parent(struct clk_hw *hw)
15 struct clk_hw *mux_hw = composite->mux_hw;
22 static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
26 struct clk_hw *mux_hw = composite->mux_hw;
33 static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
38 struct clk_hw *rate_hw = composite->rate_hw;
45 static int clk_composite_determine_rate_for_parent(struct clk_hw *rate_hw,
47 struct clk_hw *parent_hw,
68 static int clk_composite_determine_rate(struct clk_hw *hw,
74 struct clk_hw *rate_h
[all...] |
| H A D | clk-gpio.c | 45 struct clk_hw hw;
51 static int clk_gpio_gate_enable(struct clk_hw *hw)
60 static void clk_gpio_gate_disable(struct clk_hw *hw)
67 static int clk_gpio_gate_is_enabled(struct clk_hw *hw)
80 static int clk_sleeping_gpio_gate_prepare(struct clk_hw *hw)
89 static void clk_sleeping_gpio_gate_unprepare(struct clk_hw *hw)
96 static int clk_sleeping_gpio_gate_is_prepared(struct clk_hw *hw)
117 static u8 clk_gpio_mux_get_parent(struct clk_hw *hw)
124 static int clk_gpio_mux_set_parent(struct clk_hw *hw, u8 index)
139 static struct clk_hw *clk_register_gpi
[all...] |
| /linux-master/drivers/clk/qcom/ |
| H A D | clk-regmap.h | 21 struct clk_hw hw;
28 static inline struct clk_regmap *to_clk_regmap(struct clk_hw *hw)
33 int clk_is_enabled_regmap(struct clk_hw *hw);
34 int clk_enable_regmap(struct clk_hw *hw);
35 void clk_disable_regmap(struct clk_hw *hw);
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| /linux-master/drivers/clk/meson/ |
| H A D | meson-clkc-utils.h | 13 struct clk_hw **hws;
17 struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk_hw_data);
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| /linux-master/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1.h | 10 struct clk_hw *ma35d1_reg_clk_pll(struct device *dev, u32 id, u8 u8mode, const char *name,
11 struct clk_hw *parent_hw, void __iomem *base);
13 struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
14 struct clk_hw *parent_hw, spinlock_t *lock,
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| /linux-master/drivers/clk/at91/ |
| H A D | pmc.h | 22 struct clk_hw **chws;
24 struct clk_hw **shws;
26 struct clk_hw **phws;
28 struct clk_hw **ghws;
30 struct clk_hw **pchws;
32 struct clk_hw *hwtable[];
129 struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);
131 struct clk_hw * __init
135 struct clk_hw * __init
139 struct clk_hw * __ini
[all...] |
| H A D | clk-utmi.c | 23 struct clk_hw hw;
40 static int clk_utmi_prepare(struct clk_hw *hw)
42 struct clk_hw *hw_parent;
95 static int clk_utmi_is_prepared(struct clk_hw *hw)
102 static void clk_utmi_unprepare(struct clk_hw *hw)
110 static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
117 static int clk_utmi_save_context(struct clk_hw *hw)
126 static void clk_utmi_restore_context(struct clk_hw *hw)
143 static struct clk_hw * __init
147 struct clk_hw *parent_h
[all...] |
| /linux-master/include/linux/ |
| H A D | clkdev.h | 15 struct clk_hw;
23 struct clk_hw *clk_hw; member in struct:clk_lookup
38 struct clk_lookup *clkdev_hw_create(struct clk_hw *hw, const char *con_id,
45 int clk_hw_register_clkdev(struct clk_hw *, const char *, const char *);
47 int devm_clk_hw_register_clkdev(struct device *dev, struct clk_hw *hw,
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| H A D | clk-provider.h | 37 struct clk_hw;
64 struct clk_hw *best_parent_hw;
67 void clk_hw_init_rate_request(const struct clk_hw *hw,
70 void clk_hw_forward_rate_request(const struct clk_hw *core,
72 const struct clk_hw *parent,
235 int (*prepare)(struct clk_hw *hw);
236 void (*unprepare)(struct clk_hw *hw);
237 int (*is_prepared)(struct clk_hw *hw);
238 void (*unprepare_unused)(struct clk_hw *hw);
239 int (*enable)(struct clk_hw *h
326 struct clk_hw { struct
[all...] |
| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-pll.h | 62 struct clk_hw hw;
82 static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
87 int mtk_pll_is_prepared(struct clk_hw *hw);
89 int mtk_pll_prepare(struct clk_hw *hw);
91 void mtk_pll_unprepare(struct clk_hw *hw);
93 unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate);
97 int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
99 long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
102 struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
106 struct clk_hw *mtk_clk_register_pl
[all...] |
| H A D | clk-gate.c | 18 struct clk_hw hw;
26 static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
31 static u32 mtk_get_clockgating(struct clk_hw *hw)
41 static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
46 static int mtk_cg_bit_is_set(struct clk_hw *hw)
51 static void mtk_cg_set_bit(struct clk_hw *hw)
58 static void mtk_cg_clr_bit(struct clk_hw *hw)
65 static void mtk_cg_set_bit_no_setclr(struct clk_hw *hw)
72 static void mtk_cg_clr_bit_no_setclr(struct clk_hw *hw)
79 static int mtk_cg_enable(struct clk_hw *h
[all...] |
| /linux-master/drivers/clk/ux500/ |
| H A D | clk.h | 16 struct clk_hw;
30 struct clk_hw *clk_reg_prcmu_scalable(const char *name,
36 struct clk_hw *clk_reg_prcmu_gate(const char *name,
41 struct clk_hw *clk_reg_prcmu_scalable_rate(const char *name,
47 struct clk_hw *clk_reg_prcmu_rate(const char *name,
52 struct clk_hw *clk_reg_prcmu_opp_gate(const char *name,
57 struct clk_hw *clk_reg_prcmu_opp_volt_scalable(const char *name,
63 struct clk_hw *clk_reg_prcmu_clkout(const char *name,
|
| /linux-master/drivers/clk/socfpga/ |
| H A D | stratix10-clk.h | 76 struct clk_hw *s10_register_pll(const struct stratix10_pll_clock *clks,
78 struct clk_hw *agilex_register_pll(const struct stratix10_pll_clock *clks,
80 struct clk_hw *n5x_register_pll(const struct stratix10_pll_clock *clks,
82 struct clk_hw *s10_register_periph(const struct stratix10_perip_c_clock *clks,
84 struct clk_hw *n5x_register_periph(const struct n5x_perip_c_clock *clks,
86 struct clk_hw *s10_register_cnt_periph(const struct stratix10_perip_cnt_clock *clks,
88 struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks,
90 struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks,
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| /linux-master/drivers/clk/imx/ |
| H A D | clk-scu.h | 30 struct clk_hw *imx_scu_of_clk_src_get(struct of_phandle_args *clkspec,
32 struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
36 struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
42 struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
45 void imx_clk_lpcg_scu_unregister(struct clk_hw *hw);
47 struct clk_hw *__imx_clk_gpr_scu(const char *name, const char * const *parent_name,
51 static inline struct clk_hw *imx_clk_scu(const char *name, u32 rsrc_id,
57 static inline struct clk_hw *imx_clk_scu2(const char *name, const char * const *parents,
63 static inline struct clk_hw *imx_clk_lpcg_scu_dev(struct device *dev, const char *name,
71 static inline struct clk_hw *imx_clk_lpcg_sc
[all...] |
| /linux-master/drivers/clk/ti/ |
| H A D | clock.h | 12 struct clk_hw hw;
27 struct clk_hw hw;
202 struct clk *of_ti_clk_register(struct device_node *node, struct clk_hw *hw,
205 struct clk_hw *hw, const char *con);
212 struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
223 int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
247 int omap2_init_clk_clkdm(struct clk_hw *hw);
248 int omap2_clkops_enable_clkdm(struct clk_hw *hw);
249 void omap2_clkops_disable_clkdm(struct clk_hw *hw);
251 int omap2_dflt_clk_enable(struct clk_hw *h
[all...] |
| H A D | interface.c | 34 struct clk_hw_omap *clk_hw; local
37 clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
38 if (!clk_hw)
41 clk_hw->hw.init = &init;
42 clk_hw->ops = ops;
43 memcpy(&clk_hw->enable_reg, reg, sizeof(*reg));
44 clk_hw->enable_bit = bit_idx;
53 clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
56 kfree(clk_hw);
[all...] |
| H A D | clockdomain.c | 24 * @hw: struct clk_hw * of the clock being enabled
34 int omap2_clkops_enable_clkdm(struct clk_hw *hw)
62 * @hw: struct clk_hw * of the clock being disabled
69 void omap2_clkops_disable_clkdm(struct clk_hw *hw)
98 int omap2_init_clk_clkdm(struct clk_hw *hw)
125 struct clk_hw *clk_hw; local
139 clk_hw = __clk_get_hw(clk);
140 if (!omap2_clk_is_hw_omap(clk_hw)) {
146 to_clk_hw_omap(clk_hw)
[all...] |
| H A D | apll.c | 32 static int dra7_apll_enable(struct clk_hw *hw)
83 static void dra7_apll_disable(struct clk_hw *hw)
100 static int dra7_apll_is_enabled(struct clk_hw *hw)
116 static u8 dra7_init_apll_parent(struct clk_hw *hw)
131 struct clk_hw *hw = user;
132 struct clk_hw_omap *clk_hw = to_clk_hw_omap(hw); local
133 struct dpll_data *ad = clk_hw->dpll_data;
136 const struct clk_init_data *init = clk_hw->hw.init;
163 clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);
172 kfree(clk_hw
181 struct clk_hw_omap *clk_hw = NULL; local
342 struct clk_hw_omap *clk_hw = NULL; local
[all...] |
| /linux-master/drivers/clk/samsung/ |
| H A D | clk.c | 100 struct clk_hw *clk_hw, unsigned int id)
103 ctx->clk_data.hws[id] = clk_hw;
111 struct clk_hw *clk_hw; local
121 clk_hw = ctx->clk_data.hws[list->id];
122 if (!clk_hw) {
128 ret = clk_hw_register_clkdev(clk_hw, list->alias,
141 struct clk_hw *clk_hw; local
99 samsung_clk_add_lookup(struct samsung_clk_provider *ctx, struct clk_hw *clk_hw, unsigned int id) argument
161 struct clk_hw *clk_hw; local
182 struct clk_hw *clk_hw; local
205 struct clk_hw *clk_hw; local
235 struct clk_hw *clk_hw; local
[all...] |
| /linux-master/drivers/phy/mediatek/ |
| H A D | phy-mtk-mipi-dsi.h | 33 struct clk_hw pll_hw;
36 struct mtk_mipi_tx *mtk_mipi_tx_from_clk_hw(struct clk_hw *hw);
37 int mtk_mipi_tx_pll_set_rate(struct clk_hw *hw, unsigned long rate,
39 unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
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| /linux-master/drivers/clk/actions/ |
| H A D | owl-composite.c | 16 static u8 owl_comp_get_parent(struct clk_hw *hw)
23 static int owl_comp_set_parent(struct clk_hw *hw, u8 index)
30 static void owl_comp_disable(struct clk_hw *hw)
38 static int owl_comp_enable(struct clk_hw *hw)
48 static int owl_comp_is_enabled(struct clk_hw *hw)
56 static int owl_comp_div_determine_rate(struct clk_hw *hw,
71 static unsigned long owl_comp_div_recalc_rate(struct clk_hw *hw,
80 static int owl_comp_div_set_rate(struct clk_hw *hw, unsigned long rate,
89 static int owl_comp_fact_determine_rate(struct clk_hw *hw,
105 static unsigned long owl_comp_fact_recalc_rate(struct clk_hw *h
[all...] |
| /linux-master/drivers/clk/zynqmp/ |
| H A D | clk-zynqmp.h | 70 struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
75 struct clk_hw *zynqmp_clk_register_gate(const char *name, u32 clk_id,
80 struct clk_hw *zynqmp_clk_register_divider(const char *name,
86 struct clk_hw *zynqmp_clk_register_mux(const char *name, u32 clk_id,
91 struct clk_hw *zynqmp_clk_register_fixed_factor(const char *name,
|