Searched refs:base_clk (Results 1 - 8 of 8) sorted by relevance
/linux-master/drivers/mmc/host/ |
H A D | sdhci-pic32.c | 48 struct clk *base_clk; member in struct:pic32_sdhci_priv 55 return clk_get_rate(sdhci_pdata->base_clk); 176 sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk"); 177 if (IS_ERR(sdhci_pdata->base_clk)) { 178 ret = PTR_ERR(sdhci_pdata->base_clk); 183 ret = clk_prepare_enable(sdhci_pdata->base_clk); 203 clk_disable_unprepare(sdhci_pdata->base_clk); 221 clk_disable_unprepare(sdhci_pdata->base_clk);
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H A D | sdhci-brcmstb.c | 36 struct clk *base_clk; member in struct:sdhci_brcmstb_priv 318 struct clk *base_clk = NULL; local 392 base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq"); 393 if (IS_ERR(base_clk)) { 398 res = clk_prepare_enable(base_clk); 403 clk_set_rate(base_clk, priv->base_freq_hz); 404 actual_clock_mhz = clk_get_rate(base_clk) / 1000000; 413 priv->base_clk = base_clk; 425 clk_disable_unprepare(base_clk); [all...] |
H A D | sdhci-sprd.c | 205 static inline u32 sdhci_sprd_calc_div(u32 base_clk, u32 clk) argument 210 if (base_clk <= clk * 2) 213 div = (u32) (base_clk / (clk * 2)); 215 if ((base_clk / div) > (clk * 2))
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/linux-master/drivers/clk/sunxi/ |
H A D | clk-a10-pll2.c | 42 struct clk **clks, *base_clk, *prediv_clk; local 95 base_clk = clk_register_composite(NULL, "pll2-base", 101 if (IS_ERR(base_clk)) { 106 parent = __clk_get_name(base_clk);
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/linux-master/drivers/media/rc/ |
H A D | sunxi-cir.c | 143 static unsigned int sunxi_ithr_to_usec(unsigned int base_clk, unsigned int ithr) argument 146 base_clk / (128 * 64)); 150 static unsigned int sunxi_usec_to_ithr(unsigned int base_clk, unsigned int usec) argument 153 return DIV_ROUND_UP((base_clk / (128 * 64)) * usec, USEC_PER_SEC) - 1; 159 unsigned int base_clk = clk_get_rate(ir->clk); local 161 unsigned int ithr = sunxi_usec_to_ithr(base_clk, timeout); 169 rc_dev->timeout = sunxi_ithr_to_usec(base_clk, ithr);
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/linux-master/drivers/pwm/ |
H A D | pwm-samsung.c | 76 * @base_clk: base clock used to drive the timers 87 struct clk *base_clk; member in struct:samsung_pwm_chip 172 rate = clk_get_rate(our_chip->base_clk); 575 our_chip->base_clk = devm_clk_get_enabled(&pdev->dev, "timers"); 576 if (IS_ERR(our_chip->base_clk)) 577 return dev_err_probe(dev, PTR_ERR(our_chip->base_clk), 594 dev_dbg(dev, "base_clk at %lu, tclk0 at %lu, tclk1 at %lu\n", 595 clk_get_rate(our_chip->base_clk),
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/linux-master/drivers/spi/ |
H A D | spi-pic32-sqi.c | 141 struct clk *base_clk; /* drives spi clock */ member in struct:pic32_sqi 169 /* div = base_clk / (2 * spi_clk) */ 170 div = clk_get_rate(sqi->base_clk) / (2 * sck); 603 sqi->base_clk = devm_clk_get_enabled(&pdev->dev, "spi_ck"); 604 if (IS_ERR(sqi->base_clk)) { 605 ret = PTR_ERR(sqi->base_clk); 632 host->max_speed_hz = clk_get_rate(sqi->base_clk);
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H A D | spi-bcm-qspi.c | 225 u32 base_clk; member in struct:bcm_qspi 653 qspi->base_clk = MSPI_BASE_FREQ; 657 qspi->base_clk = MSPI_BASE_FREQ * 4; 685 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2); 686 spbr = bcm_qspi_calc_spbr(qspi->base_clk, xp); 1591 qspi->base_clk = clk_get_rate(qspi->clk); 1593 qspi->base_clk = MSPI_BASE_FREQ; 1607 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
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