Searched refs:RGMII (Results 1 - 5 of 5) sorted by relevance
/linux-master/scripts/dtc/include-prefixes/dt-bindings/phy/ |
H A D | phy-lan966x-serdes.h | 10 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro 11 #define RGMII_MAX RGMII(2)
|
/linux-master/include/dt-bindings/phy/ |
H A D | phy-lan966x-serdes.h | 10 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro 11 #define RGMII_MAX RGMII(2)
|
/linux-master/drivers/phy/microchip/ |
H A D | lan966x_serdes.c | 101 SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG | 107 SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG | 113 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG | 119 SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG | 403 /* Configure RGMII */
|
/linux-master/drivers/net/dsa/realtek/ |
H A D | rtl8365mb.c | 10 * RGMII. The switch is configured via the Realtek Simple Management Interface 22 * CPU/PHY <-MII/RMII/RGMII---> Extension <---> Extension | 43 * NOTE: Currently, only the RGMII interface is implemented in this driver. 223 /* External interface RGMII TX/RX delay configuration registers 0~2 */ 530 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 542 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 553 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 555 PHY_INTF(RMII) | PHY_INTF(RGMII) }, 887 /* Set the RGMII TX/RX delay 903 * Only configure an RGMII T [all...] |
/linux-master/drivers/net/ethernet/cadence/ |
H A D | macb_main.c | 551 /* RGMII allows 50 ppm frequency error. Test and warn if this limit 4233 .rgmii = GEM_BIT(RGMII),
|
Completed in 487 milliseconds