| /linux-master/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 82 #define PCLK_PWM 67 macro
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| H A D | rk3036-cru.h | 71 #define PCLK_PWM 350 macro
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| H A D | exynos7-clk.h | 87 #define PCLK_PWM 10 macro
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| H A D | rk3128-cru.h | 112 #define PCLK_PWM 350 macro
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| H A D | rv1108-cru.h | 120 #define PCLK_PWM 269 macro
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| H A D | rk3228-cru.h | 111 #define PCLK_PWM 350 macro
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| H A D | rk3288-cru.h | 142 #define PCLK_PWM 350 macro
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| H A D | rk3328-cru.h | 145 #define PCLK_PWM 214 macro
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| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 82 #define PCLK_PWM 67 macro
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| H A D | rk3036-cru.h | 71 #define PCLK_PWM 350 macro
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| H A D | exynos7-clk.h | 87 #define PCLK_PWM 10 macro
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| H A D | rk3128-cru.h | 112 #define PCLK_PWM 350 macro
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| H A D | rv1108-cru.h | 120 #define PCLK_PWM 269 macro
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| H A D | rk3228-cru.h | 111 #define PCLK_PWM 350 macro
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| H A D | rk3288-cru.h | 142 #define PCLK_PWM 350 macro
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| H A D | rk3328-cru.h | 145 #define PCLK_PWM 214 macro
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| /linux-master/drivers/clk/samsung/ |
| H A D | clk-s3c64xx.c | 238 GATE_BUS(PCLK_PWM, "pclk_pwm", "pclk", PCLK_GATE, 7),
343 ALIAS(PCLK_PWM, NULL, "timers"),
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| H A D | clk-exynos7.c | 670 GATE(PCLK_PWM, "pclk_pwm", "mout_aclk_peric0_66_user",
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| /linux-master/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 414 GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
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| H A D | clk-rk3228.c | 608 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 7, GFLAGS),
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| H A D | clk-rk3128.c | 505 GATE(PCLK_PWM, "pclk_pwm", "pclk_peri", 0, RK2928_CLKGATE_CON(7), 10, GFLAGS),
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| H A D | clk-rk3288.c | 683 GATE(PCLK_PWM, "pclk_pwm", "pclk_cpu", 0, RK3288_CLKGATE_CON(10), 0, GFLAGS),
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| H A D | clk-rk3328.c | 778 GATE(PCLK_PWM, "pclk_rk_pwm", "pclk_bus", 0, RK3328_CLKGATE_CON(16), 6, GFLAGS),
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| H A D | clk-rv1108.c | 630 GATE(PCLK_PWM, "pclk_pwm", "pclk_bus_pre", 0,
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