Searched refs:CSR1 (Results 1 - 15 of 15) sorted by relevance
| /linux-master/drivers/media/pci/dt3155/ |
| H A D | dt3155.c | 163 pd->regs + CSR1);
183 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
248 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
253 ipd->regs + CSR1);
417 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
421 iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
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| H A D | dt3155.h | 36 #define CSR1 0x40 macro
69 /* CSR1 bit masks */
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| /linux-master/drivers/net/ethernet/dec/tulip/ |
| H A D | tulip.h | 107 CSR1 = 0x08, enumerator in enum:tulip_offsets
564 iowrite32(0, ioaddr + CSR1);
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| H A D | xircom_cb.c | 49 #define CSR1 0x08 macro
531 This is accomplished by writing to the CSR1 port. The documentation
539 xw32(CSR1, 0);
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| H A D | interrupt.c | 688 iowrite32(0, ioaddr + CSR1);
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| H A D | tulip_core.c | 694 iowrite32(0, tp->base_addr + CSR1);
1171 iowrite32(0, ioaddr + CSR1);
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| /linux-master/drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 63 #define CSR1 0x0100 /* - IADR[15:0] */ macro
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| H A D | sun3lance.c | 204 #define CSR1 1 /* init block addr (low) */ macro
497 REGA(CSR1) = dvma_vtob(&(MEM->init));
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| H A D | atarilance.c | 304 #define CSR1 1 /* init block addr (low) */ macro
653 REGA( CSR1 ) = 0;
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| /linux-master/drivers/net/wireless/ralink/rt2x00/ |
| H A D | rt2400pci.c | 878 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
882 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
884 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
887 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
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| H A D | rt2400pci.h | 58 * CSR1: System control register.
63 #define CSR1 0x0004 macro
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| H A D | rt2500pci.h | 69 * CSR1: System control register.
74 #define CSR1 0x0004 macro
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| H A D | rt2500pci.c | 1016 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
1020 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
1022 reg = rt2x00mmio_register_read(rt2x00dev, CSR1);
1025 rt2x00mmio_register_write(rt2x00dev, CSR1, reg);
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| /linux-master/drivers/net/ethernet/renesas/ |
| H A D | ravb.h | 211 CSR1 = 0x0804, enumerator in enum:ravb_reg
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| H A D | ravb_main.c | 482 ravb_write(ndev, CSR1_TIP4 | CSR1_TTCP4 | CSR1_TUDP4, CSR1);
2500 ret = ravb_endisable_csum_gbeth(ndev, CSR1, val, CSR0_TPE);
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