Searched refs:CLK_TOP_SCP_SEL (Results 1 - 24 of 24) sorted by relevance

/linux-master/include/dt-bindings/clock/
H A Dmt7629-clk.h102 #define CLK_TOP_SCP_SEL 92 macro
H A Dmt7622-clk.h87 #define CLK_TOP_SCP_SEL 75 macro
H A Dmt6765-clk.h134 #define CLK_TOP_SCP_SEL 99 macro
H A Dmt8173-clk.h113 #define CLK_TOP_SCP_SEL 103 macro
H A Dmediatek,mt6795-clk.h111 #define CLK_TOP_SCP_SEL 100 macro
H A Dmt2701-clk.h105 #define CLK_TOP_SCP_SEL 94 macro
H A Dmt8192-clk.h14 #define CLK_TOP_SCP_SEL 2 macro
H A Dmediatek,mt8365-clk.h74 #define CLK_TOP_SCP_SEL 64 macro
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt7629-clk.h102 #define CLK_TOP_SCP_SEL 92 macro
H A Dmt7622-clk.h87 #define CLK_TOP_SCP_SEL 75 macro
H A Dmt6765-clk.h134 #define CLK_TOP_SCP_SEL 99 macro
H A Dmt8173-clk.h113 #define CLK_TOP_SCP_SEL 103 macro
H A Dmediatek,mt6795-clk.h111 #define CLK_TOP_SCP_SEL 100 macro
H A Dmt2701-clk.h105 #define CLK_TOP_SCP_SEL 94 macro
H A Dmt8192-clk.h14 #define CLK_TOP_SCP_SEL 2 macro
H A Dmediatek,mt8365-clk.h74 #define CLK_TOP_SCP_SEL 64 macro
/linux-master/drivers/clk/mediatek/
H A Dclk-mt6795-topckgen.c483 TOP_MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x90, 8, 3, 15, 0),
H A Dclk-mt8173-topckgen.c568 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x0090, 8, 3, 15),
H A Dclk-mt7622.c432 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", ddrphycfg_parents,
H A Dclk-mt7629.c504 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
H A Dclk-mt8365.c417 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, 0x040,
H A Dclk-mt2701.c525 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
H A Dclk-mt6765.c379 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel", scp_parents, CLK_CFG_0,
H A Dclk-mt8192.c554 MUX_GATE_CLR_SET_UPD(CLK_TOP_SCP_SEL, "scp_sel",

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