Searched refs:CLK_TOP_AUD_ENGEN1_SEL (Results 1 - 13 of 13) sorted by relevance
| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 178 #define CLK_TOP_AUD_ENGEN1_SEL 146 macro
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| H A D | mt6765-clk.h | 149 #define CLK_TOP_AUD_ENGEN1_SEL 114 macro
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| H A D | mt8192-clk.h | 55 #define CLK_TOP_AUD_ENGEN1_SEL 43 macro
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| H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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| /linux-master/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 178 #define CLK_TOP_AUD_ENGEN1_SEL 146 macro
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| H A D | mt6765-clk.h | 149 #define CLK_TOP_AUD_ENGEN1_SEL 114 macro
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| H A D | mt8192-clk.h | 55 #define CLK_TOP_AUD_ENGEN1_SEL 43 macro
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| H A D | mediatek,mt8365-clk.h | 90 #define CLK_TOP_AUD_ENGEN1_SEL 80 macro
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt8167.c | 588 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
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| H A D | clk-mt8516.c | 399 MUX(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel", aud_engen1_parents,
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| H A D | clk-mt8365.c | 461 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
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| H A D | clk-mt6765.c | 428 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
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| H A D | clk-mt8192.c | 649 MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
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Completed in 285 milliseconds