Searched refs:CLK_TOP_ARMPLL_DIVIDER_PLL0 (Results 1 - 3 of 3) sorted by relevance

/linux-master/include/dt-bindings/clock/
H A Dmt6765-clk.h108 #define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 macro
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dmt6765-clk.h108 #define CLK_TOP_ARMPLL_DIVIDER_PLL0 73 macro
/linux-master/drivers/clk/mediatek/
H A Dclk-mt6765.c156 FACTOR(CLK_TOP_ARMPLL_DIVIDER_PLL0, "arm_div_pll0", "syspll_d2", 1, 1),

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