Searched refs:CLK_TOP_APLL12_DIV5 (Results 1 - 12 of 12) sorted by relevance
| /linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 157 #define CLK_TOP_APLL12_DIV5 125 macro
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| H A D | mt6779-clk.h | 144 #define CLK_TOP_APLL12_DIV5 134 macro
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| H A D | mt8192-clk.h | 160 #define CLK_TOP_APLL12_DIV5 148 macro
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| /linux-master/include/dt-bindings/clock/ |
| H A D | mt8516-clk.h | 157 #define CLK_TOP_APLL12_DIV5 125 macro
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| H A D | mt6779-clk.h | 144 #define CLK_TOP_APLL12_DIV5 134 macro
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| H A D | mt8192-clk.h | 160 #define CLK_TOP_APLL12_DIV5 148 macro
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| /linux-master/sound/soc/mediatek/mt8192/ |
| H A D | mt8192-afe-clk.h | 212 CLK_TOP_APLL12_DIV5, enumerator in enum:__anon408
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| H A D | mt8192-afe-clk.c | 55 [CLK_TOP_APLL12_DIV5] = "top_apll12_div5",
497 .div_clk_id = CLK_TOP_APLL12_DIV5,
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| /linux-master/drivers/clk/mediatek/ |
| H A D | clk-mt8167.c | 856 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
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| H A D | clk-mt8516.c | 638 GATE_TOP5(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll12_ck_div5", 6),
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| H A D | clk-mt8192.c | 706 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "apll_i2s5_m_sel", 0x320, 6, 0x334, 8, 16),
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| H A D | clk-mt6779.c | 839 DIV_GATE(CLK_TOP_APLL12_DIV5, "apll12_div5", "i2s5_m_ck_sel",
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