Searched refs:CLK_PWM (Results 1 - 21 of 21) sorted by relevance

/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dexynos5410.h49 #define CLK_PWM 279 macro
H A Dexynos5250.h115 #define CLK_PWM 311 macro
H A Dsophgo,cv1800.h71 #define CLK_PWM 60 macro
H A Ds5pv210.h155 #define CLK_PWM 137 macro
H A Dexynos5420.h88 #define CLK_PWM 279 macro
H A Dexynos3250.h208 #define CLK_PWM 202 macro
H A Dexynos4.h174 #define CLK_PWM 336 macro
/linux-master/include/dt-bindings/clock/
H A Dexynos5410.h49 #define CLK_PWM 279 macro
H A Dexynos5250.h115 #define CLK_PWM 311 macro
H A Dsophgo,cv1800.h71 #define CLK_PWM 60 macro
H A Ds5pv210.h155 #define CLK_PWM 137 macro
H A Dexynos3250.h208 #define CLK_PWM 202 macro
H A Dexynos5420.h88 #define CLK_PWM 279 macro
H A Dexynos4.h174 #define CLK_PWM 336 macro
/linux-master/drivers/clk/samsung/
H A Dclk-exynos5410.c213 GATE(CLK_PWM, "pwm", "aclk66", GATE_IP_PERIC, 24, 0, 0),
H A Dclk-s5pv210.c571 GATE(CLK_PWM, "pwm", "dout_pclkp", CLK_GATE_IP3, 23, 0, 0),
H A Dclk-exynos5250.c598 GATE(CLK_PWM, "pwm", "div_aclk66", GATE_IP_PERIC, 24, 0, 0),
H A Dclk-exynos3250.c655 GATE(CLK_PWM, "pwm", "div_aclk_100", GATE_IP_PERIL, 24, 0, 0),
H A Dclk-exynos4.c754 GATE(CLK_PWM, "pwm", "aclk100", GATE_IP_PERIL, 24, 0, 0),
H A Dclk-exynos5420.c1096 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
/linux-master/drivers/clk/sophgo/
H A Dclk-cv1800.c1089 [CLK_PWM] = &clk_pwm.common.hw,
1320 [CLK_PWM] = &clk_pwm.common.hw,

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