1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4 * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> 5 * 6 * Device Tree binding constants for Samsung S5PV210 clock controller. 7 */ 8 9#ifndef _DT_BINDINGS_CLOCK_S5PV210_H 10#define _DT_BINDINGS_CLOCK_S5PV210_H 11 12/* Core clocks. */ 13#define FIN_PLL 1 14#define FOUT_APLL 2 15#define FOUT_MPLL 3 16#define FOUT_EPLL 4 17#define FOUT_VPLL 5 18 19/* Muxes. */ 20#define MOUT_FLASH 6 21#define MOUT_PSYS 7 22#define MOUT_DSYS 8 23#define MOUT_MSYS 9 24#define MOUT_VPLL 10 25#define MOUT_EPLL 11 26#define MOUT_MPLL 12 27#define MOUT_APLL 13 28#define MOUT_VPLLSRC 14 29#define MOUT_CSIS 15 30#define MOUT_FIMD 16 31#define MOUT_CAM1 17 32#define MOUT_CAM0 18 33#define MOUT_DAC 19 34#define MOUT_MIXER 20 35#define MOUT_HDMI 21 36#define MOUT_G2D 22 37#define MOUT_MFC 23 38#define MOUT_G3D 24 39#define MOUT_FIMC2 25 40#define MOUT_FIMC1 26 41#define MOUT_FIMC0 27 42#define MOUT_UART3 28 43#define MOUT_UART2 29 44#define MOUT_UART1 30 45#define MOUT_UART0 31 46#define MOUT_MMC3 32 47#define MOUT_MMC2 33 48#define MOUT_MMC1 34 49#define MOUT_MMC0 35 50#define MOUT_PWM 36 51#define MOUT_SPI0 37 52#define MOUT_SPI1 38 53#define MOUT_DMC0 39 54#define MOUT_PWI 40 55#define MOUT_HPM 41 56#define MOUT_SPDIF 42 57#define MOUT_AUDIO2 43 58#define MOUT_AUDIO1 44 59#define MOUT_AUDIO0 45 60 61/* Dividers. */ 62#define DOUT_PCLKP 46 63#define DOUT_HCLKP 47 64#define DOUT_PCLKD 48 65#define DOUT_HCLKD 49 66#define DOUT_PCLKM 50 67#define DOUT_HCLKM 51 68#define DOUT_A2M 52 69#define DOUT_APLL 53 70#define DOUT_CSIS 54 71#define DOUT_FIMD 55 72#define DOUT_CAM1 56 73#define DOUT_CAM0 57 74#define DOUT_TBLK 58 75#define DOUT_G2D 59 76#define DOUT_MFC 60 77#define DOUT_G3D 61 78#define DOUT_FIMC2 62 79#define DOUT_FIMC1 63 80#define DOUT_FIMC0 64 81#define DOUT_UART3 65 82#define DOUT_UART2 66 83#define DOUT_UART1 67 84#define DOUT_UART0 68 85#define DOUT_MMC3 69 86#define DOUT_MMC2 70 87#define DOUT_MMC1 71 88#define DOUT_MMC0 72 89#define DOUT_PWM 73 90#define DOUT_SPI1 74 91#define DOUT_SPI0 75 92#define DOUT_DMC0 76 93#define DOUT_PWI 77 94#define DOUT_HPM 78 95#define DOUT_COPY 79 96#define DOUT_FLASH 80 97#define DOUT_AUDIO2 81 98#define DOUT_AUDIO1 82 99#define DOUT_AUDIO0 83 100#define DOUT_DPM 84 101#define DOUT_DVSEM 85 102 103/* Gates */ 104#define SCLK_FIMC 86 105#define CLK_CSIS 87 106#define CLK_ROTATOR 88 107#define CLK_FIMC2 89 108#define CLK_FIMC1 90 109#define CLK_FIMC0 91 110#define CLK_MFC 92 111#define CLK_G2D 93 112#define CLK_G3D 94 113#define CLK_IMEM 95 114#define CLK_PDMA1 96 115#define CLK_PDMA0 97 116#define CLK_MDMA 98 117#define CLK_DMC1 99 118#define CLK_DMC0 100 119#define CLK_NFCON 101 120#define CLK_SROMC 102 121#define CLK_CFCON 103 122#define CLK_NANDXL 104 123#define CLK_USB_HOST 105 124#define CLK_USB_OTG 106 125#define CLK_HDMI 107 126#define CLK_TVENC 108 127#define CLK_MIXER 109 128#define CLK_VP 110 129#define CLK_DSIM 111 130#define CLK_FIMD 112 131#define CLK_TZIC3 113 132#define CLK_TZIC2 114 133#define CLK_TZIC1 115 134#define CLK_TZIC0 116 135#define CLK_VIC3 117 136#define CLK_VIC2 118 137#define CLK_VIC1 119 138#define CLK_VIC0 120 139#define CLK_TSI 121 140#define CLK_HSMMC3 122 141#define CLK_HSMMC2 123 142#define CLK_HSMMC1 124 143#define CLK_HSMMC0 125 144#define CLK_JTAG 126 145#define CLK_MODEMIF 127 146#define CLK_CORESIGHT 128 147#define CLK_SDM 129 148#define CLK_SECSS 130 149#define CLK_PCM2 131 150#define CLK_PCM1 132 151#define CLK_PCM0 133 152#define CLK_SYSCON 134 153#define CLK_GPIO 135 154#define CLK_TSADC 136 155#define CLK_PWM 137 156#define CLK_WDT 138 157#define CLK_KEYIF 139 158#define CLK_UART3 140 159#define CLK_UART2 141 160#define CLK_UART1 142 161#define CLK_UART0 143 162#define CLK_SYSTIMER 144 163#define CLK_RTC 145 164#define CLK_SPI1 146 165#define CLK_SPI0 147 166#define CLK_I2C_HDMI_PHY 148 167#define CLK_I2C1 149 168#define CLK_I2C2 150 169#define CLK_I2C0 151 170#define CLK_I2S1 152 171#define CLK_I2S2 153 172#define CLK_I2S0 154 173#define CLK_AC97 155 174#define CLK_SPDIF 156 175#define CLK_TZPC3 157 176#define CLK_TZPC2 158 177#define CLK_TZPC1 159 178#define CLK_TZPC0 160 179#define CLK_SECKEY 161 180#define CLK_IEM_APC 162 181#define CLK_IEM_IEC 163 182#define CLK_CHIPID 164 183#define CLK_JPEG 163 184 185/* Special clocks*/ 186#define SCLK_PWI 164 187#define SCLK_SPDIF 165 188#define SCLK_AUDIO2 166 189#define SCLK_AUDIO1 167 190#define SCLK_AUDIO0 168 191#define SCLK_PWM 169 192#define SCLK_SPI1 170 193#define SCLK_SPI0 171 194#define SCLK_UART3 172 195#define SCLK_UART2 173 196#define SCLK_UART1 174 197#define SCLK_UART0 175 198#define SCLK_MMC3 176 199#define SCLK_MMC2 177 200#define SCLK_MMC1 178 201#define SCLK_MMC0 179 202#define SCLK_FINVPLL 180 203#define SCLK_CSIS 181 204#define SCLK_FIMD 182 205#define SCLK_CAM1 183 206#define SCLK_CAM0 184 207#define SCLK_DAC 185 208#define SCLK_MIXER 186 209#define SCLK_HDMI 187 210#define SCLK_FIMC2 188 211#define SCLK_FIMC1 189 212#define SCLK_FIMC0 190 213#define SCLK_HDMI27M 191 214#define SCLK_HDMIPHY 192 215#define SCLK_USBPHY0 193 216#define SCLK_USBPHY1 194 217 218/* S5P6442-specific clocks */ 219#define MOUT_D0SYNC 195 220#define MOUT_D1SYNC 196 221#define DOUT_MIXER 197 222#define CLK_ETB 198 223#define CLK_ETM 199 224 225/* CLKOUT */ 226#define FOUT_APLL_CLKOUT 200 227#define FOUT_MPLL_CLKOUT 201 228#define DOUT_APLL_CLKOUT 202 229#define MOUT_CLKSEL 203 230#define DOUT_CLKOUT 204 231#define MOUT_CLKOUT 205 232 233/* Total number of clocks. */ 234#define NR_CLKS 206 235 236#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */ 237