Searched refs:CLKID_MPLL0_DIV (Results 1 - 15 of 15) sorted by relevance

/linux-master/include/dt-bindings/clock/
H A Damlogic,s4-pll-clkc.h34 #define CLKID_MPLL0_DIV 24 macro
H A Daxg-clkc.h76 #define CLKID_MPLL0_DIV 65 macro
H A Dgxbb-clkc.h150 #define CLKID_MPLL0_DIV 142 macro
H A Dmeson8b-clkc.h103 #define CLKID_MPLL0_DIV 96 macro
H A Dg12a-clkc.h80 #define CLKID_MPLL0_DIV 69 macro
/linux-master/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Damlogic,s4-pll-clkc.h34 #define CLKID_MPLL0_DIV 24 macro
H A Daxg-clkc.h76 #define CLKID_MPLL0_DIV 65 macro
H A Dmeson8b-clkc.h103 #define CLKID_MPLL0_DIV 96 macro
H A Dgxbb-clkc.h150 #define CLKID_MPLL0_DIV 142 macro
H A Dg12a-clkc.h80 #define CLKID_MPLL0_DIV 69 macro
/linux-master/drivers/clk/meson/
H A Ds4-pll.c756 [CLKID_MPLL0_DIV] = &s4_mpll0_div.hw,
H A Dgxbb.c2875 [CLKID_MPLL0_DIV] = &gxbb_mpll0_div.hw,
3082 [CLKID_MPLL0_DIV] = &gxl_mpll0_div.hw,
H A Dmeson8b.c2872 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3076 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
3291 [CLKID_MPLL0_DIV] = &meson8b_mpll0_div.hw,
H A Dg12a.c4451 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4678 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
4946 [CLKID_MPLL0_DIV] = &g12a_mpll0_div.hw,
H A Daxg.c1961 [CLKID_MPLL0_DIV] = &axg_mpll0_div.hw,

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