1/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2/* 3 * Copyright (c) 2022-2023 Amlogic, Inc. All rights reserved. 4 * Author: Yu Tu <yu.tu@amlogic.com> 5 */ 6 7#ifndef _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H 8#define _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H 9 10#define CLKID_FIXED_PLL_DCO 0 11#define CLKID_FIXED_PLL 1 12#define CLKID_FCLK_DIV2_DIV 2 13#define CLKID_FCLK_DIV2 3 14#define CLKID_FCLK_DIV3_DIV 4 15#define CLKID_FCLK_DIV3 5 16#define CLKID_FCLK_DIV4_DIV 6 17#define CLKID_FCLK_DIV4 7 18#define CLKID_FCLK_DIV5_DIV 8 19#define CLKID_FCLK_DIV5 9 20#define CLKID_FCLK_DIV7_DIV 10 21#define CLKID_FCLK_DIV7 11 22#define CLKID_FCLK_DIV2P5_DIV 12 23#define CLKID_FCLK_DIV2P5 13 24#define CLKID_GP0_PLL_DCO 14 25#define CLKID_GP0_PLL 15 26#define CLKID_HIFI_PLL_DCO 16 27#define CLKID_HIFI_PLL 17 28#define CLKID_HDMI_PLL_DCO 18 29#define CLKID_HDMI_PLL_OD 19 30#define CLKID_HDMI_PLL 20 31#define CLKID_MPLL_50M_DIV 21 32#define CLKID_MPLL_50M 22 33#define CLKID_MPLL_PREDIV 23 34#define CLKID_MPLL0_DIV 24 35#define CLKID_MPLL0 25 36#define CLKID_MPLL1_DIV 26 37#define CLKID_MPLL1 27 38#define CLKID_MPLL2_DIV 28 39#define CLKID_MPLL2 29 40#define CLKID_MPLL3_DIV 30 41#define CLKID_MPLL3 31 42 43#endif /* _DT_BINDINGS_CLOCK_AMLOGIC_S4_PLL_CLKC_H */ 44