1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * GXBB clock tree IDs 4 */ 5 6#ifndef __GXBB_CLKC_H 7#define __GXBB_CLKC_H 8 9#define CLKID_SYS_PLL 0 10#define CLKID_HDMI_PLL 2 11#define CLKID_FIXED_PLL 3 12#define CLKID_FCLK_DIV2 4 13#define CLKID_FCLK_DIV3 5 14#define CLKID_FCLK_DIV4 6 15#define CLKID_FCLK_DIV5 7 16#define CLKID_FCLK_DIV7 8 17#define CLKID_GP0_PLL 9 18#define CLKID_MPEG_SEL 10 19#define CLKID_MPEG_DIV 11 20#define CLKID_CLK81 12 21#define CLKID_MPLL0 13 22#define CLKID_MPLL1 14 23#define CLKID_MPLL2 15 24#define CLKID_DDR 16 25#define CLKID_DOS 17 26#define CLKID_ISA 18 27#define CLKID_PL301 19 28#define CLKID_PERIPHS 20 29#define CLKID_SPICC 21 30#define CLKID_I2C 22 31#define CLKID_SAR_ADC 23 32#define CLKID_SMART_CARD 24 33#define CLKID_RNG0 25 34#define CLKID_UART0 26 35#define CLKID_SDHC 27 36#define CLKID_STREAM 28 37#define CLKID_ASYNC_FIFO 29 38#define CLKID_SDIO 30 39#define CLKID_ABUF 31 40#define CLKID_HIU_IFACE 32 41#define CLKID_ASSIST_MISC 33 42#define CLKID_SPI 34 43#define CLKID_ETH 36 44#define CLKID_I2S_SPDIF 35 45#define CLKID_DEMUX 37 46#define CLKID_AIU_GLUE 38 47#define CLKID_IEC958 39 48#define CLKID_I2S_OUT 40 49#define CLKID_AMCLK 41 50#define CLKID_AIFIFO2 42 51#define CLKID_MIXER 43 52#define CLKID_MIXER_IFACE 44 53#define CLKID_ADC 45 54#define CLKID_BLKMV 46 55#define CLKID_AIU 47 56#define CLKID_UART1 48 57#define CLKID_G2D 49 58#define CLKID_USB0 50 59#define CLKID_USB1 51 60#define CLKID_RESET 52 61#define CLKID_NAND 53 62#define CLKID_DOS_PARSER 54 63#define CLKID_USB 55 64#define CLKID_VDIN1 56 65#define CLKID_AHB_ARB0 57 66#define CLKID_EFUSE 58 67#define CLKID_BOOT_ROM 59 68#define CLKID_AHB_DATA_BUS 60 69#define CLKID_AHB_CTRL_BUS 61 70#define CLKID_HDMI_INTR_SYNC 62 71#define CLKID_HDMI_PCLK 63 72#define CLKID_USB1_DDR_BRIDGE 64 73#define CLKID_USB0_DDR_BRIDGE 65 74#define CLKID_MMC_PCLK 66 75#define CLKID_DVIN 67 76#define CLKID_UART2 68 77#define CLKID_SANA 69 78#define CLKID_VPU_INTR 70 79#define CLKID_SEC_AHB_AHB3_BRIDGE 71 80#define CLKID_CLK81_A53 72 81#define CLKID_VCLK2_VENCI0 73 82#define CLKID_VCLK2_VENCI1 74 83#define CLKID_VCLK2_VENCP0 75 84#define CLKID_VCLK2_VENCP1 76 85#define CLKID_GCLK_VENCI_INT0 77 86#define CLKID_GCLK_VENCI_INT 78 87#define CLKID_DAC_CLK 79 88#define CLKID_AOCLK_GATE 80 89#define CLKID_IEC958_GATE 81 90#define CLKID_ENC480P 82 91#define CLKID_RNG1 83 92#define CLKID_GCLK_VENCI_INT1 84 93#define CLKID_VCLK2_VENCLMCC 85 94#define CLKID_VCLK2_VENCL 86 95#define CLKID_VCLK_OTHER 87 96#define CLKID_EDP 88 97#define CLKID_AO_MEDIA_CPU 89 98#define CLKID_AO_AHB_SRAM 90 99#define CLKID_AO_AHB_BUS 91 100#define CLKID_AO_IFACE 92 101#define CLKID_AO_I2C 93 102#define CLKID_SD_EMMC_A 94 103#define CLKID_SD_EMMC_B 95 104#define CLKID_SD_EMMC_C 96 105#define CLKID_SAR_ADC_CLK 97 106#define CLKID_SAR_ADC_SEL 98 107#define CLKID_SAR_ADC_DIV 99 108#define CLKID_MALI_0_SEL 100 109#define CLKID_MALI_0_DIV 101 110#define CLKID_MALI_0 102 111#define CLKID_MALI_1_SEL 103 112#define CLKID_MALI_1_DIV 104 113#define CLKID_MALI_1 105 114#define CLKID_MALI 106 115#define CLKID_CTS_AMCLK 107 116#define CLKID_CTS_AMCLK_SEL 108 117#define CLKID_CTS_AMCLK_DIV 109 118#define CLKID_CTS_MCLK_I958 110 119#define CLKID_CTS_MCLK_I958_SEL 111 120#define CLKID_CTS_MCLK_I958_DIV 112 121#define CLKID_CTS_I958 113 122#define CLKID_32K_CLK 114 123#define CLKID_32K_CLK_SEL 115 124#define CLKID_32K_CLK_DIV 116 125#define CLKID_SD_EMMC_A_CLK0_SEL 117 126#define CLKID_SD_EMMC_A_CLK0_DIV 118 127#define CLKID_SD_EMMC_A_CLK0 119 128#define CLKID_SD_EMMC_B_CLK0_SEL 120 129#define CLKID_SD_EMMC_B_CLK0_DIV 121 130#define CLKID_SD_EMMC_B_CLK0 122 131#define CLKID_SD_EMMC_C_CLK0_SEL 123 132#define CLKID_SD_EMMC_C_CLK0_DIV 124 133#define CLKID_SD_EMMC_C_CLK0 125 134#define CLKID_VPU_0_SEL 126 135#define CLKID_VPU_0_DIV 127 136#define CLKID_VPU_0 128 137#define CLKID_VPU_1_SEL 129 138#define CLKID_VPU_1_DIV 130 139#define CLKID_VPU_1 131 140#define CLKID_VPU 132 141#define CLKID_VAPB_0_SEL 133 142#define CLKID_VAPB_0_DIV 134 143#define CLKID_VAPB_0 135 144#define CLKID_VAPB_1_SEL 136 145#define CLKID_VAPB_1_DIV 137 146#define CLKID_VAPB_1 138 147#define CLKID_VAPB_SEL 139 148#define CLKID_VAPB 140 149#define CLKID_HDMI_PLL_PRE_MULT 141 150#define CLKID_MPLL0_DIV 142 151#define CLKID_MPLL1_DIV 143 152#define CLKID_MPLL2_DIV 144 153#define CLKID_MPLL_PREDIV 145 154#define CLKID_FCLK_DIV2_DIV 146 155#define CLKID_FCLK_DIV3_DIV 147 156#define CLKID_FCLK_DIV4_DIV 148 157#define CLKID_FCLK_DIV5_DIV 149 158#define CLKID_FCLK_DIV7_DIV 150 159#define CLKID_VDEC_1_SEL 151 160#define CLKID_VDEC_1_DIV 152 161#define CLKID_VDEC_1 153 162#define CLKID_VDEC_HEVC_SEL 154 163#define CLKID_VDEC_HEVC_DIV 155 164#define CLKID_VDEC_HEVC 156 165#define CLKID_GEN_CLK_SEL 157 166#define CLKID_GEN_CLK_DIV 158 167#define CLKID_GEN_CLK 159 168#define CLKID_FIXED_PLL_DCO 160 169#define CLKID_HDMI_PLL_DCO 161 170#define CLKID_HDMI_PLL_OD 162 171#define CLKID_HDMI_PLL_OD2 163 172#define CLKID_SYS_PLL_DCO 164 173#define CLKID_GP0_PLL_DCO 165 174#define CLKID_VID_PLL 166 175#define CLKID_VID_PLL_SEL 167 176#define CLKID_VID_PLL_DIV 168 177#define CLKID_VCLK_SEL 169 178#define CLKID_VCLK2_SEL 170 179#define CLKID_VCLK_INPUT 171 180#define CLKID_VCLK2_INPUT 172 181#define CLKID_VCLK_DIV 173 182#define CLKID_VCLK2_DIV 174 183#define CLKID_VCLK 175 184#define CLKID_VCLK2 176 185#define CLKID_VCLK_DIV2_EN 177 186#define CLKID_VCLK_DIV4_EN 178 187#define CLKID_VCLK_DIV6_EN 179 188#define CLKID_VCLK_DIV12_EN 180 189#define CLKID_VCLK2_DIV2_EN 181 190#define CLKID_VCLK2_DIV4_EN 182 191#define CLKID_VCLK2_DIV6_EN 183 192#define CLKID_VCLK2_DIV12_EN 184 193#define CLKID_VCLK_DIV1 185 194#define CLKID_VCLK_DIV2 186 195#define CLKID_VCLK_DIV4 187 196#define CLKID_VCLK_DIV6 188 197#define CLKID_VCLK_DIV12 189 198#define CLKID_VCLK2_DIV1 190 199#define CLKID_VCLK2_DIV2 191 200#define CLKID_VCLK2_DIV4 192 201#define CLKID_VCLK2_DIV6 193 202#define CLKID_VCLK2_DIV12 194 203#define CLKID_CTS_ENCI_SEL 195 204#define CLKID_CTS_ENCP_SEL 196 205#define CLKID_CTS_VDAC_SEL 197 206#define CLKID_HDMI_TX_SEL 198 207#define CLKID_CTS_ENCI 199 208#define CLKID_CTS_ENCP 200 209#define CLKID_CTS_VDAC 201 210#define CLKID_HDMI_TX 202 211#define CLKID_HDMI_SEL 203 212#define CLKID_HDMI_DIV 204 213#define CLKID_HDMI 205 214#define CLKID_ACODEC 206 215 216#endif /* __GXBB_CLKC_H */ 217